JP2004325978A - Semiconductor integrated circuit device for driving liquid crystal - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data side driver IC for a liquid crystal display device which can shorten test time and is advantageous to EMI noise. <P>SOLUTION: The data side driver having a shift register 20 consisting of a plurality of flip flops 21 for receiving a start signal transferred by cascade connection and outputting data input control signals from respective stages and a data register circuit 30 consisting of a plurality of registers 31 for inputting data signals by the data input control signals comprises also a selector circuit 60 consisting of a plurality of selectors 61 in which the data signal output terminal of a pre-stage side flip flop 21 out of two adjacent flop flops 21 is connected to respective input terminals (a), the data signal input terminal of the post stage side flip flop 21 is connected to respective output terminals and the start signal input is connected to respective input terminals (b) in common. When data signals inputted to respective registers 31 are the same, the input terminals (b) of respective selectors 61 are selected and the data signals are simultaneously inputted to respective registers 31. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a liquid crystal driving semiconductor integrated circuit device used to drive data lines of a liquid crystal panel.
[0002]
[Prior art]
As a dot matrix type display device, the liquid crystal display device is used for various devices such as personal computers because of its features of thinness, light weight and low power, and it is particularly advantageous for controlling the image quality with high definition. Display devices dominate.
[0003]
Hereinafter, a conventional liquid crystal display device described in Patent Document 1 will be described with reference to FIG. This liquid crystal display device includes a liquid crystal panel (LCD panel) 11, a control circuit (hereinafter, referred to as a controller) 12 including a semiconductor integrated circuit device (hereinafter, referred to as an IC), and a plurality of scanning side drive circuits (hereinafter, referred to as an IC). , A scanning side driver) 13 and a data side driving circuit (hereinafter, referred to as a data side driver) 14. Although not shown in detail, the liquid crystal panel 11 has a semiconductor substrate on which a transparent pixel electrode and a thin film transistor (TFT) are arranged, a counter substrate on which one transparent electrode is formed over the entire surface, and these two substrates facing each other. A predetermined voltage is applied to each pixel electrode by controlling a TFT having a switching function, and the transmittance of the liquid crystal is determined by a potential difference between each pixel electrode and a counter substrate electrode. The image is displayed by changing it. On the semiconductor substrate, a data line for transmitting a gradation voltage to be applied to each pixel electrode and a scanning line for transmitting a switching control signal (scanning signal) for the TFT are wired.
[0004]
The controller 12 has an input side connected to a PC (personal computer) 15 and an output side connected to a scanning driver 13 and a data driver 14. The output sides of the scanning driver 13 and the data driver 14 are connected to the scanning lines and the data lines of the liquid crystal panel 11, respectively. The chip size of the scanning driver 13 and the data driver 14 is limited due to manufacturing restrictions. Therefore, the number of outputs corresponding to the scanning lines and data lines that can be output by one IC is also limited, and the size of the liquid crystal panel 11 is large. In this case, it is necessary to arrange a plurality of them on the outer periphery of the liquid crystal panel 11. For example, in the case of a liquid crystal panel of XGA (1024 × 768 pixels) color display, mounting of the drivers 13 and 14 on the module is as follows.
{Circle around (1)} The scanning driver 13 needs to drive 768 gate lines. For example, if it has a driving capability of 192 gates, four drivers are required. You.
{Circle around (2)} The data-side driver 14 needs three data lines for R (red), G (green), and B (blue) in order to display one pixel in color. It is necessary to drive the data lines. For example, when the data lines have a driving capability of 384 lines, eight cascade-connected (A, B,..., H) are arranged on the upper outer periphery of the liquid crystal panel 11 on one side.
[0005]
The image data is transmitted from the PC 15 to the controller 12 of the liquid crystal display module, the clock signal CLK and the like are transmitted from the controller 12 to the scanning driver 13 in parallel to each scanning driver 13, and a start signal STV for vertical synchronization is supplied to the first stage. , And sequentially transferred to the cascaded scanning driver 13 at the next and subsequent stages. In addition, a timing signal such as a clock signal CLK and a data signal DA of a predetermined bit indicating a gradation are sent from the controller 12 to the data side driver 14 in parallel to each data side driver 14, and a start signal STH for horizontal synchronization is sent to the data side driver 14. The data is sent to the data driver A in the first stage, and is sequentially transferred to the data drivers B, C,... Then, a pulse-like scanning signal is sent to each scanning line from the scanning side driver 13, and when the scanning signal applied to the scanning line is at a high level, all the TFTs connected to that scanning line are turned on, The gray scale voltage sent from the driver 14 to the data line is applied to the pixel electrode via the turned-on TFT. Then, when the scanning signal becomes low level and the TFT changes to the off state, the potential difference between the pixel electrode and the counter substrate electrode is held until the next gradation voltage is applied to the pixel electrode. Then, by sequentially transmitting a scanning signal to each scanning line, a predetermined gradation voltage is applied to all the pixel electrodes, and an image can be displayed by rewriting the gradation voltage in a frame cycle.
[0006]
Next, a conventional example of the data-side driver 14 will be described with reference to FIG. For the sake of simplicity, the description will be made assuming that 4 × 1 (R) pixels in the horizontal direction are driven. In the figure, reference numeral 20 denotes a shift register, which has four stages of flip-flops 21 connected in cascade. The data signal output terminal of each flip-flop 21 is connected to the data signal input terminal of the next succeeding flip-flop 21 and is cascaded. The clock input terminals of the flip-flops 21 are commonly connected to the clock signal input terminal 1. The data signal input terminal of the first stage flip-flop 21 is connected to the start signal input terminal 2, and the data signal output terminal of the last stage flip-flop 21 is connected to the start signal output terminal 3. Further, the data signal output terminal of each flip-flop 21 is connected to each of the four registers 31 of the data register circuit 30 corresponding to each flip-flop 21. Each register 31 has a data signal input terminal commonly connected to the data signal input terminal 4 and a data signal output terminal connected to each latch (not shown) of the latch circuit 40 corresponding to each register 31. The latch circuit 40 is connected to the latch signal input terminal 5 and has a data signal output terminal connected to the driver circuit 50. The driver circuit 50 includes a level shifter, a D / A converter, and an output amplifier (not shown) corresponding to each flip-flop 21, and a data signal output terminal is connected to the driver output terminal 6 corresponding to each flip-flop 21. Have been.
[0007]
The operation of the data-side driver having the above configuration will be described with reference to FIG. For simplicity of the following description, it is assumed that the number of pixels in the horizontal direction of the liquid crystal display panel is 4 × 1 (R), and the operation is performed by one data-side driver. A clock signal CLK synchronized with the transmission timing of the data signal DA at the terminal 4 is commonly input from the clock signal input terminal 1 to each flip-flop 21, and the start signal STH is supplied from the start signal input terminal 2 to the first stage at the timing of one horizontal drive period. When the start signal STH is input to the first flip-flop 21, the start signal STH is read at the rising edge of the clock signal CLK and transferred to each flip-flop 21. The data signal DA is output from the data signal output terminal of each flip-flop 21 to the corresponding register 31. Are sequentially output, and the start signal STH when the data side driver is cascaded from the last flip-flop 21 to the next stage is supplied to the start signal output terminal 3. Is output to At the rise of the data fetch control signals C1, C2, C3, and C4 input to the data register circuit 30, the data signals DA are sequentially fetched from the data signal input terminal 4 to the respective registers 31, and the output terminals R1, R2 of the respective registers 31 are output. , R3, R4. The data signal DA fetched by all the registers 31 is latched by the latch circuit 40 in synchronization with the latch signal STB given to the terminal 5 every one horizontal drive period (hereinafter, not shown in FIG. 6). Output to the circuit 50. The driver circuit 50 selects a gradation voltage from a gradation voltage generation circuit (not shown) corresponding to each data signal DA, and outputs the selected gradation voltage from each driver output terminal 6.
[0008]
[Patent Document 1]
Japanese Patent Application No. 2002-153854 (paragraph numbers “0002” to “0005”, FIG. 4)
[Patent Document 2]
Japanese Patent Application Laid-Open No. 10-214061 (paragraph numbers "0003" to "0004", FIGS. 6 and 7)
[0009]
[Problems to be solved by the invention]
By the way, when the size of the liquid crystal panel 11 is further increased from XGA to SXGA (1280 × 1024) and UXGA (1600 × 1200) and the number of pixels is increased, the number of data-side drivers to be cascade-connected becomes, , 8 and UXGA, if 10 are set, the number of outputs per data-side driver is 480, which is larger than the 384 outputs in the output example of XGA. To increase. In the data driver described above, the data capture control signals C1, C2, C3, and C4 are input by shifting the start signal STH from the start signal input terminal 2 to each register 31 by causing each flip-flop 21 to transfer the start signal STH. Therefore, if the number of data fetch control signals increases, the data fetch time increases accordingly if the clock signal period is the same. Further, in order to suppress an increase in the data fetch time, it is necessary to shorten the cycle of the clock signal. Therefore, the above-mentioned data driver has the following problem.
[0010]
{Circle around (1)} The above-mentioned data-side driver inputs a digital data signal DA to the data signal input terminal 4 as a functional test in the final stage of the wafer or the final stage of the product in the manufacturing process, and outputs the digital data signal from each driver output terminal 6. An analog gray scale voltage is measured by a tester to determine the quality. In this test, for example, in the case of a 64-gradation display, a 6-bit data signal DA indicating 64 gradations is supplied to each register 31 from the terminal 4 by one gradation at a time. The same data signal DA is taken in by C3 and C4, and the same gradation voltage is output from each terminal 6 at the same time. Therefore, there is a problem that if the number of data fetch control signals increases, the test time increases accordingly if the clock signal period is the same. Also, when you suppress an increase in test time, the period of the clock signal is shortened, EMI (E lectro M agnetic I nterference) noise problems.
[0011]
{Circle around (2)} When driving the liquid crystal panel 11 with the data side driver described above, if the number of pixels of the liquid crystal panel 11 increases, the length of one horizontal period decreases, and data for one horizontal period is taken in that time. In addition, the period of the clock signal is shortened, which causes a problem of EMI noise.
[0012]
Accordingly, an object of the present invention is to provide a liquid crystal driving semiconductor integrated circuit device which can shorten the test time and is advantageous against EMI noise.
[0013]
[Means for Solving the Problems]
A semiconductor integrated circuit device for driving a liquid crystal according to the present invention includes a shift register including a plurality of flip-flops each of which outputs a data capture control signal from a start signal transferred by cascade connection, and a data capture control signal. In a liquid crystal driving semiconductor integrated circuit device having a data register circuit composed of a plurality of registers for taking in signals, a data signal output terminal of each of two adjacent preceding flip-flops of the flip-flop is connected to one input terminal. And a selector circuit comprising a plurality of selectors, wherein a data signal input terminal of the subsequent flip-flop is connected to each output terminal, and a start signal input is commonly connected to each of the other input terminals. When the data signal taken in between the registers of each stage is the same, the other input terminal of each selector is selected. Is characterized by the data signal is taken into the register of each stage simultaneously.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
The data-side driver according to an embodiment of the present invention described below is used, for example, in a liquid crystal panel for color display of SXGA (1280 × 1024) or UXGA (1600 × 1200), and has a driving capability for 480 data lines. Have. For the sake of simplicity, the description will be made assuming that 4 × 1 (R) pixels in the horizontal direction are driven, and the same components as those in FIG. 5 are denoted by the same reference numerals and description thereof is omitted. 5 in that a selector circuit 60 is provided in addition to the shift register 20, the data register circuit 30, the latch circuit 40, and the driver circuit 50. Although the data signal input terminal 4 is shown as a single terminal in the drawing, the data signal input terminal 4 has terminals corresponding to the number of bits of the data signal input in parallel, and is connected to the wiring corresponding to the number of bits. . For example, when a data signal of 6 bits × R, G, B = 18 bits of 64 gradation display is input in parallel, it has 18 terminals and 18 wirings.
[0015]
The selector circuit 60 has a selector 61 in which the data signal output terminals of the flip-flops 21 except the last stage are connected to the respective a input terminals, and the data signal input terminals of the flip-flops 21 in the succeeding stage are connected to the respective output terminals. have. The b input terminal of each selector 61 is commonly connected to the start signal input terminal 2. The control signal input terminal of each selector 61 is connected to the control signal input terminal 7.
[0016]
The operation of the data-side driver having the above configuration will be described. For simplicity of the following description, it is assumed that the number of pixels in the horizontal direction of the liquid crystal display panel is 4 × 1 (R), and the operation is performed by one data-side driver. The case of 64-gradation display will be described as an example.
First, a digital data signal DA is input to the data signal input terminal 4 of the data-side driver, and an analog gray scale voltage output from each driver output terminal 6 is measured by a tester to determine whether the test is good or bad. This will be described with reference to FIG. At the time of the test, the terminal 7 to which the control signal SEL is input is fixed at the “H” level, and the input terminal b of each selector 61 is selected, and the data signal output terminal of each flip-flop 21 and the one subsequent stage The connection with the data signal input terminal of the flip-flop 21 is cut off, and the terminal 2 is commonly connected to the data signal input terminals of the second and subsequent flip-flops 21. To the terminal 4, a 6-bit data signal DA indicating 64 tones is input in the order of DA (1), (2), (3),..., (64).
[0017]
At time t1, the data signal DA (1) of the first gradation is input to the terminal 4. At this time, the “H” level of the start signal STH is commonly input to the flip-flops 21 from the terminal 2.
[0018]
At time t2, the “H” level of the start signal STH input to each flip-flop 21 is read at the rising edge of the clock signal CLK (1), and is read from the data signal output terminal of each flip-flop 21 to the corresponding register 31. Data capture control signals C1, C2, C3, and C4 for capturing data signal DA (1) are simultaneously output. Then, at the rise of the data fetch control signals C1, C2, C3, and C4 input to the data register circuit 30, the data signal DA (1) is simultaneously fetched from the data signal input terminal 4 to each of the registers 31. Are output simultaneously from the output terminals R1, R2, R3, and R4.
[0019]
At time t3, the “L” level of the start signal STH input to each flip-flop 21 is read at the rise of the clock signal CLK (2), and the data capture control signal from the data signal output terminal of each flip-flop 21 is read. C1, C2, C3, and C4 fall at the same time. Hereinafter, although not shown, after time t3, the data is latched by the latch circuit 40 in synchronization with the latch signal STB and output to the driver circuit 50. The driver circuit 50 selects a gray scale voltage from a gray scale voltage generation circuit (not shown) corresponding to the data signal DA (1), outputs the selected gray scale voltage from each driver output terminal 6, and measures the quality with a tester. .
[0020]
Hereinafter, similarly, the data signal DA is taken in from the terminal 4 as DA (2), (3),..., (64), the gradation voltage corresponding to each data signal is selected from the terminal 6, and each driver output terminal 6 and measured by a tester to determine the quality.
[0021]
Next, the operation when the data side driver drives the liquid crystal panel 11 will be described.
(1) When the data signals fetched between the registers of each stage of the data register circuit are not the same: When the data signals fetched between the registers 31 of each stage of the data register circuit 30 are not the same, the data signal is sent to the data side driver. The sending controller 12 determines in advance that the data signals are not the same, and sends the data signals as data signals DA (1), (2), (3) and (4). At this time, the "L" level of the control signal SEL is input to the terminal 7 at the same time, the input terminal a of each selector 61 is selected, and the data signal output terminal of each flip-flop 21 and the flip-flop 21 It is connected to the data signal input terminal and operates in the same manner as the data side driver shown in FIG.
[0022]
(2) When the data signal taken in between the registers of each stage of the data register circuit is the same: A description will be given with reference to FIG. At time t1, the data signal DA (1) is input to the terminal 4. When the data signals taken in between the registers 31 of the respective stages of the data register circuit 30 are the same, the controller 12 for sending the data signal to the data side driver determines in advance that the data signals are the same, Is compressed into one data and transmitted as a data signal DA (1). At this time, the "H" level of the control signal SEL is input to the terminal 7 at the same time, the input terminal b of each selector 61 is selected, and the data signal output terminal of each flip-flop 21 and the flip-flop 21 The connection with the data signal input terminal is disconnected, and the terminal 2 is commonly connected to the data signal input terminals of the flip-flops 21 of the second and subsequent stages. At this time, the “H” level of the start signal STH is commonly input to the flip-flops 21 from the terminal 2.
[0023]
At time t2, the “H” level of the start signal STH input to each flip-flop 21 is read at the rising edge of the clock signal CLK (1), and is read from the data signal output terminal of each flip-flop 21 to the corresponding register 31. Data capture control signals C1, C2, C3, and C4 for capturing data signal DA are simultaneously output. Then, at the rise of the data fetch control signals C1, C2, C3, and C4 input to the data register circuit 30, the data signal DA (1) is simultaneously fetched from the data signal input terminal 4 to each of the registers 31. Are output simultaneously from the output terminals R1, R2, R3, and R4.
[0024]
At time t3, the “L” level of the start signal STH input to each flip-flop 21 is read at the rising edge of the clock signal CLK (2), and the data capture control signal from the data signal output terminal of each flip-flop 21 is read. C1, C2, C3, and C4 fall at the same time. Then, at time t4 after the fall, the control signal SEL falls. Hereinafter, although not shown, the data is latched by the latch circuit 40 in synchronization with the latch signal STB and output to the driver circuit 50. The driver circuit 50 selects a gray scale voltage from a gray scale voltage generation circuit (not shown) corresponding to the data signal DA (1), and outputs the selected gray scale voltage from each driver output terminal 6.
[0025]
As described above, in the function test of the gradation of the data side driver, since the data signal is simultaneously taken into the register 31 by the data taking control signals C1, C2, C3, C4, the cycle of the clock signal is not shortened. However, the test time can be reduced.
When the liquid crystal panel 11 is driven by the data-side driver, when the data signals fetched between the registers 31 at the respective stages are the same, the data fetch control signals C1, C2, C3, and C4 simultaneously transmit the data signals to the register 31. Therefore, the data signal capturing time can be reduced without shortening the cycle of the clock signal.
[0026]
In the above embodiment, the selection signal SEL is supplied to the selector circuit 60 from the outside of the data side driver to select the cascade connection between the flip-flops 21 or the common connection to the start signal input terminal 2 of each flip-flop 21. In the case where the cascade connection between the flip-flops 21 is selected by supplying the selection signal SEL generated inside the data-side driver to the selector circuit 60 based on a binary signal from outside the data-side driver, When the start signal from the start signal input terminal 2 is used and the start signal is commonly input to each flip-flop 21, the start signal generated inside the data driver based on the binary signal from outside the data driver is used. May be used. Also, in the data side driver, an example has been described in which the register of the data register circuit corresponds to each flip-flop with one output, but a plurality of outputs, for example, three outputs of R, G, and B may be used. .
[0027]
【The invention's effect】
According to the present invention, in the function test of the gradation of the data side driver, the test time can be reduced without shortening the cycle of the clock signal. In addition, even when the liquid crystal panel is driven by the data-side driver, the time for capturing the data signal can be reduced.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a data side driver of a liquid crystal display device according to an embodiment of the present invention.
FIG. 2 is a waveform chart for explaining an operation in a function test of the data-side driver shown in FIG. 1;
FIG. 3 is a waveform diagram illustrating an operation when a data driver shown in FIG. 1 drives a liquid crystal panel.
FIG. 4 is a block diagram illustrating a configuration of a conventional liquid crystal display device.
5 is a circuit diagram of a conventional data-side driver used in the liquid crystal display device shown in FIG.
FIG. 6 is a waveform chart for explaining the operation of the data-side driver shown in FIG.
[Explanation of symbols]
Reference Signs List 20 shift register 21 flip-flop 30 data register circuit 31 register 60 selector circuit 61 selector

Claims (1)

A shift register composed of a plurality of flip-flops that output a data capture control signal from each stage by transferring a start signal by cascade connection, and a data register circuit composed of a plurality of registers that capture a data signal by the data capture control signal In the semiconductor integrated circuit device for driving liquid crystal having
The data signal output terminals of the two preceding flip-flops adjacent to each other of the flip-flop are connected to one input terminal, and the data signal input terminals of the subsequent flip-flop are connected to each output terminal. A start signal input having a selector circuit composed of a plurality of selectors commonly connected to the other input terminals,
A liquid crystal driving semiconductor integrated circuit, wherein when the data signal taken in between the registers in each stage is the same, the other input terminal of each selector is selected, and the data signal is taken into the register in each stage at the same time. Circuit device.

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