JP2004172602A - Capacitor and its manufacturing method, wiring board, decoupling circuit, and high frequency circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a capacitor of low ESL and high capacity in a simple inexpensive method. <P>SOLUTION: The capacitor 10 comprises a first capacitor 11 and a second capacitor 12 integrated each other in the direction of layers. The first capacitor 11 comprises multilayer dielectric layers 2, first conductive layers 3a, second conductive layers 4a opposed to the first conductive layers 3a across the dielectric layers 2, first through conductor 5a penetrating the first conductive layers 3 to connect one another, and second through conductor 6a penetrating the second conductive layers 4a to connect one another. The second capacitor 12 comprises multilayer dielectric layers 2, third conductive layers 3b, fourth conductive layers 4b opposed to the third conductive layers 3b across the dielectric layers 2, third through conductor 5b penetrating the third conductive layers to connect one another, fourth through conductor 6b penetrating the fourth conductive layers 4b to connect one another. The total number of first and second through conductors 5a and 6a is larger than that of third and fourth through 5b and 6b. <P>COPYRIGHT: (C)2004,JPO

Description

    The present invention relates to a capacitor, a wiring board, a decoupling circuit, and a high-frequency circuit, and particularly to a capacitor that can be advantageously applied in a high-frequency region, and a wiring board, a decoupling circuit, and a high-frequency circuit configured using the capacitor. It concerns the circuit.

  As a typical capacitor, a laminated capacitor will be described as an example.

In an equivalent circuit using a multilayer capacitor, when the capacitance of the capacitor is C and the equivalent series inductance (ESL) is L, the resonance frequency (f ₀ ) is f ₀ = 1 / [2π × (L × C) expressed in relation ^1/2], in the frequency region higher than the resonance frequency (f _0), it is known that the function of the capacitor is lost. That is, in order to maintain the capacitance (C) of a certain value or more, it is necessary to reduce ESL (L) as much as possible. That is, when the ESL is low, the resonance frequency (f ₀ ) is high, and it can be used in a higher frequency range. For this reason, in order to use the multilayer capacitor in the microwave region, a capacitor having a lower ESL is required.

Also, a multilayer capacitor which is used to supply power to an MPU chip of a micro processing unit (MPU) such as a workstation or a personal computer, and which is usually connected on a wiring board as a decoupling capacitor,
With the recent increase in speed and frequency of MPUs, lower ESL is required.

  Here, a conventional multilayer capacitor will be described with reference to FIGS. FIG. 4A is a cross-sectional view, and FIG. 4B is a schematic view showing an overlapping state of the first and second conductor layers.

  In the conventional multilayer capacitor 50 shown in the figure, a first conductor layer 53 is formed on one main surface of a dielectric layer 52, and a second conductor layer 54 is formed on the other main surface, and a plurality of these dielectric layers 52 are laminated. Further, in the thickness direction of these dielectric layers 52, first and second through conductors 55 and 56 for connecting the first and second conductor layers 53 and 54 to each other are formed, and the laminated body 51 is formed. Have been. Here, the first and second through conductors 55 and 56 are exposed on one outermost surface of the multilayer body 51 and connected to the first and second connection terminals 57 and 58, respectively, to configure the multilayer capacitor 50. ing. Further, first and second non-conductor formation regions 63 and 64 which are not connected to the second and first through conductors 56 and 55, respectively, are formed in the first and second conductor layers 53 and 54.

The first and second through conductors 55 and 56 are alternately dispersed in a grid pattern over the entire area of the first and second conductor layers 53 and 54 (see Patent Documents 1 to 4).
JP-A-7-201651 (page 3-5, FIG. 1-5) JP-A-11-204372 (page 4-6, FIG. 1-4) JP 2001-148324 A (page 4-7, FIG. 1-6) JP 2001-148325 A (page 5-7, FIG. 1-9)

  However, according to the multilayer capacitor 50, in order to reduce the ESL, it is conceivable to increase the number of the first and second through conductors 55 and 56 and reduce the distance between the centers. At this time, since the areas of the non-conductor formation regions 63 and 64 in the first and second conductor layers 53 and 54 increase, there is a problem that the capacitance of the multilayer capacitor 50 decreases.

  The present invention has been devised in view of the above-described problems, and an object of the present invention is to provide a capacitor which realizes low ESL and high capacitance by a simple and inexpensive manufacturing method, and a manufacturing method thereof.

  Another object of the present invention is to provide a wiring board, a decoupling circuit, or a high-frequency circuit configured using the above-described capacitor.

The present invention includes a plurality of stacked dielectric layers, a plurality of first conductor layers and a second conductor layer which are alternately arranged between the dielectric layers, and are opposed to each other, and penetrates in a thickness direction of the dielectric layers. A plurality of first through conductors that are separated by the second conductor layer and the second non-conductor formation region, and are connected by the first conductor layers, and are separated by the first conductor layer and the first non-conductor formation region; A first capacitor portion formed with a plurality of second through conductors connecting the second conductor layers,
A plurality of stacked dielectric layers, a plurality of third conductor layers and fourth conductor layers alternately arranged between the dielectric layers, and facing each other, and penetrating through the thickness direction of the dielectric layers; A capacitor formed by integrating a third through conductor for connecting conductor layers and a second capacitor portion formed with a fourth through conductor for connecting the fourth conductor layers in a stacking direction,
The total number of the first through conductors and the second through conductors is greater than the total number of the third through conductors and the fourth through conductors, and at least one of the first through conductors is the third through conductor. And at least one of the second through conductors is connected to the fourth through conductor.

  Also, at least a part of the first to fourth through conductors is connected to a connection electrode having a higher resistance value than the first to fourth conductor layers.

  Further, the distance between the centers of the first through conductor and the second through conductor that are adjacent to each other is P, and the center of the first through conductor and the second non-conductor formation region are located on a straight line connecting the centers. A capacitor that satisfies the relationship of P ≦ m1 + m2, where m2 is the distance from the periphery and m1 is the distance between the center of the second through conductor and the periphery of the first non-conductor formation region.

Further, a plurality of laminated dielectric layers, a plurality of first conductor layers and second conductor layers, which are alternately arranged between the respective dielectric layers and face each other, penetrate through the thickness direction of the dielectric layers, A plurality of first through conductors separated by a second conductor layer and a second non-conductor formation region and connecting the first conductor layers to each other; separated by the first conductor layer and the first non-conductor formation region; A first capacitor portion formed with a plurality of second through conductors connecting the two conductor layers,
A plurality of stacked dielectric layers, a plurality of third conductor layers and fourth conductor layers alternately arranged between the dielectric layers, and facing each other, and penetrating through the thickness direction of the dielectric layers; A method for manufacturing a capacitor, comprising: integrating a third through conductor for connecting conductor layers together and a second capacitor portion having a fourth through conductor for connecting the fourth conductor layers together in a laminating direction. hand,
A step of forming first and second through conductors penetrating only the first capacitor part, and, if necessary, a step of forming third and fourth penetrating conductors penetrating only the second capacitor part; A step of laminating first and second capacitor portions, and a step of electrically connecting the first and second capacitor portions to the first and third through conductors; Forming a through conductor.

  Further, the above-mentioned capacitor is formed on the wiring board. Further, the above-mentioned capacitor is used for a decoupling circuit. The above-mentioned capacitor is used for a high-frequency circuit. The present invention is also applicable to a wiring board provided with the above-described capacitor. Further, the capacitor according to the present invention is advantageously used as a decoupling capacitor connected to a power supply circuit for an MPU chip provided in the MPU. Further, the present invention can be applied to a high-frequency circuit including the above-described capacitor.

  As described above, according to the capacitor of the present invention, since the number of the first and second through conductors is increased in the first capacitor portion, the distance through which the current flows is shortened, and the current is induced by the current. Self-inductance and mutual inductance components caused by magnetic flux are reduced. Therefore, the equivalent series inductance (ESL) of the entire capacitor can be reduced. On the other hand, in the second capacitor portion, the number of the third and fourth through conductors can be reduced, so that the facing area between the third conductor layer and the fourth conductor layer can be increased. be able to. As a result, the equivalent series inductance (ESL) of the entire capacitor can be reduced, and a large-capacity capacitor can be realized.

In addition, these characteristics are particularly effective for a circuit board that includes a circuit that operates at high speed, a circuit that operates with a high-frequency signal, a decoupling circuit, or a high-frequency circuit.

  Further, a first through conductor and a third through conductor, a second through conductor and a fourth through conductor, which connect the first and second capacitor units to each other, and the first and second capacitor units are laminated. Later, since they are formed at once, the connection reliability between the first capacitor portion and the second capacitor portion is greatly improved.

  Hereinafter, a capacitor, a wiring board, a decoupling circuit, and a high-frequency circuit of the present invention will be described in detail with reference to the drawings.

  1A and 1B are diagrams showing a multilayer capacitor as an example of the capacitor according to the present invention, wherein FIG. 1A is a cross-sectional view, FIG. 1B is a schematic diagram showing an overlapping state of first and second conductor layers, and FIG. It is the schematic which shows the overlapping state of the 3rd, 4th conductor layer.

  In the figure, a multilayer capacitor 10 has first and second connection terminals 7 a and 8 a formed on one main surface of a multilayer body 1 and third and fourth connection terminals 7 b and 8 b on the other main surface of the multilayer body 1. Is formed. Furthermore, the multilayer body 1 integrates the first capacitor unit 11 and the second capacitor unit 12 in the stacking direction.

  The first capacitor unit 11 includes a plurality of stacked dielectric layers 2, a first conductor layer 3 a and a second conductor layer 4 a that are disposed between the dielectric layers 2 and face each other with the dielectric layer 2 interposed therebetween. A first through conductor 5a penetrating through the thickness direction of the dielectric layer 2 and connecting the first conductor layers 3a and a second through conductor 6a connecting the second conductor layers 4a are formed respectively. Further, the first and second through conductors 5a, 6a are exposed on one main surface of the multilayer body 1 and are connected to the first and second connection terminals 7a, 8a, respectively. In the first and second conductor layers 3a and 4a, first and second non-conductor formation regions 13a and 14a that are not connected to the second and first through conductors 6a and 5a, respectively, are formed.

  On the other hand, the second capacitor unit 12 includes a plurality of stacked dielectric layers 2, a third conductor layer 3 b and a fourth conductor layer 4 b that are disposed between the dielectric layers 2 and face each other with the dielectric layer 2 interposed therebetween. A third through conductor 5b penetrating through the thickness direction of the dielectric layer 2 and connecting the third conductor layers 3b and a fourth through conductor 6b connecting the fourth conductor layers 4b are formed. The third and fourth through conductors 5b and 6b are exposed on one main surface of the multilayer body 1 and are connected to the third and fourth connection terminals 7b and 8b, respectively. In the third and fourth conductor layers 3b and 4b, third and fourth non-conductor formation regions 13b and 14b that are not connected to the fourth and third through conductors 6b and 5b, respectively, are formed.

  Here, the total number of conductors of the first through conductor 5a and the second through conductor 6a of the first capacitor unit 11 is larger than the total number of conductors of the third through conductor 5b and the fourth through conductor 6b of the second capacitor unit 12. Is also increasing.

  Also, at least one of the first through conductors 5a of the first capacitor portion 11 is connected to the third through conductor 5b of the second capacitor portion, and similarly, at least one of the second through conductors 6a is connected to the fourth through conductor 4a. Connected to conductor 6b. Specifically, the first penetrating conductor 5a of the first capacitor portion 11 is connected to the first conductor layer 3a stacked in the thickness direction, and at the same time, connects the second non-conductor formation region 14a of the second conductor layer 4a. Since it penetrates, it does not conduct to the second conductor layer 4a. Similarly, the second through conductor 6a of the first capacitor portion 11 is connected to the second conductor layer 4a stacked in the thickness direction, and simultaneously penetrates the first non-conductor formation region 13a of the first conductor layer 3a. Does not conduct to the first conductor layer 3a. The same applies to the third through conductor 5b and the fourth through conductor 6b on the second capacitor section 12 side.

  In addition, in order to shorten the distance through which the current flows, and to cancel out the magnetic flux induced by the current, it is desirable that the first and second through conductors 5a and 6a are alternately formed in a lattice shape.

  The dielectric layer 2 is made of a non-reducing dielectric material containing barium titanate as a main component, and a dielectric material containing a glass component. Is configured. The shape, thickness, and number of layers of the dielectric layer 2 can be arbitrarily changed according to the capacitance value.

  The first to fourth conductor layers 3a to 4b are made of a material mainly containing Ni, Cu, or an alloy thereof, and have a thickness of 1 to 2 μm. The material of the first to fourth through conductors 5a to 6b is made of a material mainly containing Ni, Cu, or an alloy thereof.

  For the connection terminals 7a, 8a, 7b, 8b, solder bumps, ball solders or the like are used.

  Next, a method for manufacturing the multilayer capacitor 10 of the present invention will be described. Note that, in the drawings, each symbol is not distinguished before and after firing.

  First, conductive films 3a and 4a serving as first and second conductive layers are formed on a ceramic green sheet 2 serving as a dielectric layer of the first capacitor unit 11 by printing and drying a conductive paste. At this time, the first and second non-conductor formation regions 13a and 14a are also formed. On the other hand, conductive films 3b and 4b serving as third and fourth conductive layers are formed on the ceramic green sheet 2 serving as the dielectric layer of the second capacitor unit 12 by printing and drying a conductive paste. At this time, the third and fourth non-conductor formation regions 13b and 14b are also formed. The dielectric layer 2 may be made of another ceramic material having a perovskite structure or an organic ferroelectric material.

  Next, a required number of the ceramic green sheets 2 on which the conductor films 3a and 4a are formed are alternately stacked to form a large laminated body from which the first capacitor unit 11 is extracted. Similarly, the required number of ceramic green sheets 2 on which the conductor films 3b and 4b are formed are alternately stacked to form a large laminate from which the second capacitor unit 12 is extracted.

  Next, the conductor films 3a, 4a and the ceramic green sheet 2 are placed in the thickness direction on the main surface of the large laminated body from which the first capacitor portion 11 is extracted by laser irradiation, a punching method using micro drilling or punching, or the like. A through hole is formed. Further, by filling a conductive paste into the through holes, conductor portions 5a and 6a serving as first and second through conductors are formed. Here, the through hole serving as the first through conductor 5a of the first capacitor portion 11 passes through the second non-conductor forming region 14a of the first conductor layer 3a and the second conductor layer 4a, and serves as the second through conductor 6a. Are formed to penetrate the first non-conductor formation region 13a of the second conductor layer 4a and the first conductor layer 3a.

  Similarly, through holes are formed in the main surface of the large-sized laminate from which the second capacitor portion 12 is extracted, and penetrate through the conductor films 3b and 4b and the ceramic green sheet 2 in the thickness direction. Further, by filling the through holes with a conductive paste, conductor portions 5b and 6b serving as third and fourth through conductors are formed. Here, the through-hole serving as the third through conductor 5b of the second capacitor portion 12 penetrates through the third non-conductor forming region 14b of the third conductor layer 3b and the fourth conductor layer 4b, and serves as the fourth through conductor 6b. Are formed so as to penetrate the third non-conductor formation region 13b of the fourth conductor layer 4b and the third conductor layer 3b.

  Next, the large laminates from which the first capacitor unit 11 and the second capacitor unit 12 are extracted are stacked to form a large laminate from which the laminate 1 is extracted. At this time, one of the first through conductors 5 a formed in the first capacitor unit 11 is connected to the third through conductor 5 b formed in the second capacitor unit 12 and is formed in the first capacitor unit 11. One of the second through conductors 6a overlaps in the vertical direction so as to be connected to the fourth through conductor 6b formed in the second capacitor portion 12.

  The ceramic green sheet 2 serving as a dielectric layer is provided with through holes in advance by a punching method using a microdrill or punching, and the conductor layers 3a to 4b are formed on the ceramic green sheet 2 by a screen printing method. The conductor portions 5a to 6b serving as the first to fourth through conductors may be formed and then laminated by filling the through holes with a conductive paste at the same time as printing the conductor film.

  Next, the large-sized laminate is cut by a press-cutting blade process, a dicing method, or the like, to obtain a laminate 1 in an unfired state.

  Next, the unfired laminate 1 is fired after the binder removal process, and the first to fourth conductor layers 3a to 4b and the first to fourth through conductors 5a to 6b are formed therein. , At least one of the first through conductors 5a is electrically connected to the third through conductor 5b, and at least one of the second through conductors 6a is electrically connected to the fourth through conductor 6b. The laminated body 1 in which the first and second through conductors 5a and 6a are exposed on the surface and the third and fourth through conductors 5b and 6b are exposed on the other main surface is obtained.

  At this time, since the surfaces of the first to fourth through conductors 5a to 6b are oxidized, the oxide film is removed by surface polishing.

  Next, Ni plating and Sn plating are formed on the exposed portions of the first to fourth through conductors 5a to 6b. Here, Au or Cu plating may be used.

  Next, the solder to be the connection terminals 7a, 8a, 7b, 8b is formed by a method of screen printing a solder paste or a method of mounting a ball solder after applying a flux, and then a reflow process is performed. 7a, 8a, 7b and 8b are formed. The connection terminals 7b and 8b may be formed on the exposed portions of the third and fourth through conductors 5b and 6b also on the second capacitor portion 12 side.

  In each of the through conductors 5a, 5b, 6a, and 6b formed in the first capacitor portion 11 and the second capacitor portion 12, only the first and second through conductors 5a and 6a that penetrate only the first capacitor portion 11 are formed. In addition, if necessary, only the third and fourth through conductors 5b and 6b penetrating only the second capacitor portion 12 are formed, and after the first capacitor portion 11 and the second capacitor portion 12 are laminated, The first through-conductor 5a and the third through-conductor 6a that connect them may be formed, and the second through-conductor 5b and the fourth through-conductor 6b may be formed. The specific manufacturing method will be described in detail with reference to FIG.

  Thus, a multilayer capacitor 10 as shown in FIG. 1 is obtained.

  It should be noted that the present invention is not limited to the above embodiments, and various changes and improvements can be made without departing from the spirit of the present invention.

  2A and 2B are diagrams showing another embodiment of the multilayer capacitor of the present invention, wherein FIG. 2A is a cross-sectional view, FIG. 2B is a diagram in which a first through conductor 5a and a third through conductor 5b are connected, and FIG. FIG. 9 is a plan view showing an intermediate dielectric layer on which connection electrodes 3c and 4c for connecting a through conductor 6a and a fourth through conductor 6b are formed.

  According to the figure, the first and second capacitors are connected between the first capacitor unit 11 and the second capacitor unit 12 via the connection electrodes 3c and 4c of the intermediate dielectric layers 3c and 4c shown in FIG. The two through conductors 5a, 6a are connected to the third and fourth through conductors 5b, 6b. For example, the first through conductor 5a is connected to the third through conductor 5b via the connection electrode 3c, and similarly, the second through conductor 6a is connected to the fourth through conductor 6b via the connection electrode 4c. ing. By arranging the connection electrodes 3c and 4c between the first capacitor section 11 and the second capacitor section 12 in this manner, the arrangement of the third and fourth through conductors 5b and 6b becomes free, and at the same time, the both through conductors are formed. The connection reliability of the conductor is greatly improved. The connection electrodes 3c and 4c may be formed on both main surfaces, and the connection electrodes on the front and back may be connected between the main electrodes by via-hole conductors.

  At this time, the connection electrodes 3c and 4c each have a single layer, whereas the entirety of the first to fourth conductor layers 5a to 6b is a plurality of layers. Since the resistance value becomes higher than that of the whole of 5a to 6b and functions as a resistor (dump resistance), a resonance phenomenon can be reduced and a use frequency range can be expanded. Further, for example, when a Ni material is used for the first to fourth conductor layers 5a to 6b, the connection electrodes 3c and 4c are made of Ag, Ag alloy, or Ni— having a higher resistance value than the first to fourth conductor layers 5a to 6b. By using Cr, carbon film, metal gram, metal oxide material, etc., the effect of reducing this resonance phenomenon can be more effectively obtained.

  FIG. 5 is a frequency-impedance curve of the multilayer capacitor 50 of FIG. 1 (dotted line), the first and second capacitor portions 11 and 12 of FIG. 1 (solid line), and the multilayer capacitor 10 of FIG. As shown in the figure, the multilayer capacitor 10 of the present invention has a wide characteristic by utilizing both the characteristics of the first capacitor unit 11 having a low impedance in a high frequency part and the characteristics of the second capacitor unit 12 having a low impedance in a low frequency part. Low impedance can be realized in the frequency range. Further, as shown in FIG. 2, by connecting the first to fourth conductor layers 5a to 6b to the connection electrodes 3c and 4c, it is possible to reduce the resonance phenomenon and expand the frequency range of use. Understand.

  6A and 6B are views showing still another embodiment of the multilayer capacitor of the present invention, wherein FIG. 6A is a cross-sectional view, FIG. 6B is a schematic view showing an overlapping state of the first and second conductor layers, and FIG. () Is a schematic diagram showing an overlapping state of the third and fourth conductor layers. According to the figure, there is no region where capacitance occurs between the first through conductor 5a and the second through conductor 6a adjacent to each other. Specifically, the distance between the center of the adjacent first through conductor 5a and the center of the second through conductor 6a is P, and the radii of the first and second non-conductor forming regions 13a and 14a are m1 and m2 (general). Specifically, when m1 = m2), the relationship of P ≦ m1 + m2 is satisfied. Here, in order to prevent an increase in the equivalent series resistance (ESR), it is desirable to satisfy the relationship of r1 + r2 ≦ P when the radii of the first and second through conductors 3 and 4 are r1 and r2, respectively. . As a result, there is almost no current flowing from one of the first through conductors 5a to the other of the second through conductors 6a through the overlapping portion. As a result, the self-inductance component caused by the magnetic flux induced by the current becomes extremely low, and the ESL of the entire multilayer capacitor 10 can be further reduced. Further, since there is a region where the non-conductor formation regions 13a and 14a do not contribute to the formation of the capacitance, there is a region where the first to fourth conductor layers 3a to 4b relatively overlap when viewed from the entire multilayer capacitor 10. However, the capacitance of the multilayer capacitor 10 can be further increased.

  Here, the radii r1 and r2 of the first and second through conductors 5a and 6a and the radii m1 and m2 of the first and second non-conductor forming regions 13a and 14a may be equal to or different from each other.

  The cross-sectional shape of the first to fourth through conductors 5a to 6b or the shape of the first to fourth non-conductor forming regions 13a to 14b is not limited to a substantially circular shape, but may be any shape such as an elliptical shape or a polygonal shape. be able to.

  7A and 7B are diagrams showing a method for manufacturing a multilayer capacitor according to the present invention, and FIG. 7A shows a step of forming first and second through conductors 5a and 6a penetrating only the first capacitor portion 11. 7B shows a step of forming the second capacitor section 12, FIG. 7C shows a step of laminating the first and second capacitor sections 11 and 12, and FIG. And a step of forming a first through conductor 5a and a third through conductor 5b, and a second through conductor 6a and a fourth through conductor 6b penetrating both the first and second capacitor portions 11 and 12.

  By manufacturing in this manner, the connection between the first through conductor 5a and the third through conductor 5b, or the connection between the second through conductor 6a and the fourth through conductor 6b, which penetrates both the first and second capacitor portions 11 and 12, is established. And the equivalent series resistance (ESR) can be reduced.

  The third and fourth through conductors 5b and 6b are omitted since the second and third capacitor portions 12 in FIG. 7B do not have the third and fourth through conductors existing only in this capacitor portion. However, third and fourth through conductors that are present only in the second capacitor portion 12 and that are not connected to the through conductors 5a and 6a of the first capacitor portion 11 are formed in advance in the process of FIG. Need to be kept.

  FIG. 3 is a cross-sectional view showing a structural example of the MPU 20 using the multilayer capacitor 10 of the present invention as a decoupling capacitor.

  As shown in the figure, the MPU 20 has an MPU chip 30 mounted on a wiring board 21. The multilayer capacitor 10 (A) of the present invention is mounted on the wiring board 21, and the multilayer capacitor 10 (B) of the present invention is accommodated in the cavity of the wiring board 21. The multilayer capacitors 10 (A) and 10 (B) are both connected in parallel to the MPU chip 30 and function as decoupling capacitors.

  A power supply side conductor layer 23 and a ground side conductor layer 24 are formed inside the wiring board 21.

  The first connection terminal 7a of the multilayer capacitor 10 (A) is electrically connected to the power supply side conductor layer 23 via the power supply side through conductor 25, and the second connection terminal 8a of the multilayer capacitor 10 (A) is Are electrically connected to the MPU chip 30 through the ground-side through conductor 26. Here, the multilayer capacitor 10 (A) does not need to form the third and fourth connection terminals 7b and 8b. At this time, the oxide film on the surfaces of the third and fourth through conductors 5b and 6b must be removed. Thus, unnecessary conduction can be prevented.

  As described above, since the multilayer capacitor 10 of the present invention has a low ESL, even when used as a decoupling capacitor in the MPU 20, it can sufficiently cope with high-speed operation. Further, the present invention can be applied to a wiring board including the multilayer capacitor 10.

  The multilayer capacitor 10 of the present invention shown in FIG. 1 and the conventional multilayer capacitor 50 shown in FIG. 4 were prepared, and the capacitance C and the equivalent series inductance L were measured. Here, the dimensions of both the multilayer capacitors 10 and 50 are 3.2 mm × 3.2 mm, a total of 36 first and second through conductors 5 a and 6 a are arranged in a lattice, and third and fourth through conductors 5 b and 5 A total of two 6b were formed in the center portion. As a result of the measurement, the conventional multilayer capacitor 50 shown in FIG. 4 has C = 7.8 μF and L = 20 pH, whereas the multilayer capacitor 10 of the present invention shown in FIG. 1 has C = 15 μF and L = 8 pH. Was.

  From these results, in the multilayer capacitor 10 of the present invention, the total number of conductors of the first through conductor 5a and the second through conductor 6a is larger than the total number of conductors of the third through conductor 5b and the fourth through conductor 6b. Since one of the first through conductors 5a is connected to the third through conductor 5b and one of the second through conductors 6a is connected to the fourth through conductor 6b, low ESL and high capacity are realized. I knew I could do it.

  As described above, according to the capacitor of the present invention, a plurality of laminated dielectric layers, the first conductor layer and the second conductor layer disposed between the dielectric layers and facing each other with the dielectric layer interposed therebetween, A first through conductor that penetrates through the body layer in the thickness direction, is separated by the second conductor layer and the second non-conductor formation region, and is connected by the first conductor layer and the first non-conductor formation region; A first capacitor portion formed with a second through conductor for connecting the second conductor layers to each other; a plurality of stacked dielectric layers; and a plurality of dielectric layers arranged between the dielectric layers and opposed via the dielectric layers. A third conductor layer and a fourth conductor layer that are in contact with each other, a third through conductor that penetrates through the thickness direction of the dielectric layer and connects the first conductor layers, and a fourth through conductor that connects the fourth conductor layers are formed. A capacitor formed by integrating the formed second capacitor portions in the laminating direction. A capacitors, conductors total number of the first through conductor and the second through conductor is made larger than the conductor the total number of the third through conductor and the fourth through-conductors. One of the first and second through conductors is electrically connected to the third and fourth through conductors, respectively.

  That is, in the first capacitor portion, the total number of conductors of the first and second through conductors is larger than the total number of conductors with the third and fourth through conductors, so that the distance through which current flows becomes shorter. Therefore, the self-inductance and the mutual inductance component due to the magnetic flux induced by the current are reduced. For this reason, the first capacitor section serves as an equivalent series inductance controlling section in which the equivalent series inductance of the capacitor is substantially controlled, and the equivalent series inductance (ESL) of the entire capacitor can be reduced. On the other hand, in the second capacitor portion, the number of the third and fourth through conductors can be reduced, so that the facing area between the third conductor layer and the fourth conductor layer can be increased. Becomes a capacitance dominant portion where the capacitance is substantially controlled, and the entire capacitor can be increased in capacity. By combining these two capacitor sections, a capacitor having low ESL and high capacity can be provided. Further, since there is no need to largely change the conventional production line, the production method is simple and inexpensive.

  Further, since at least a part (except for all) of the first to fourth through conductors is connected to a connection electrode having a higher resistance value than the first to fourth conductor layers, a resonance phenomenon can be reduced, The operating frequency range can be expanded.

  Furthermore, since at least a part (except all) of the first to fourth through conductors has a higher resistance value than the other first to fourth through conductors, the resonance phenomenon can be reduced also by this, The operating frequency range can be expanded.

  The distance between the centers of the first through conductor and the second through conductor that are adjacent to each other is P, and the distance between the center of the first through conductor and the periphery of the second non-conductor formation region on a straight line connecting the centers. When the interval is m2, and the interval between the center of the second through conductor and the periphery of the first non-conductor formation region is m1, the relationship of P ≦ m1 + m2 is satisfied. Almost no flow to the conductor. As a result, the self-inductance component caused by the magnetic flux induced by the current becomes extremely low, and the ESL of the entire capacitor can be further reduced. Furthermore, since the non-conductor formation regions that do not contribute to the formation of the capacitance overlap each other, the capacitance region relatively increases from the viewpoint of the entire capacitor, and further higher capacitance of the capacitor can be realized.

  Further, in order to form a first through conductor and a third through conductor, or a second through conductor and a fourth through conductor that penetrate both the first and second capacitor portions after laminating the first and second capacitor portions, Each connection is improved, and the equivalent series resistance (ESR) can be reduced.

  These characteristics are particularly effective for a wiring board having a circuit operating at a high speed, a circuit operating with a high-frequency signal, a decoupling circuit or a high-frequency circuit, and the connection reliability between the first capacitor unit and the second capacitor unit. Become more likely.

It is a figure which shows the laminated capacitor of this invention, (a) is sectional drawing, (b) is the schematic which shows the overlap state of the 1st, 2nd conductor layer, (c) is the overlap of the 3rd, 4th conductor layer. It is a schematic diagram showing a state. It is a figure which shows other embodiment of the laminated capacitor of this invention, (a) is sectional drawing, (b) is a top view which shows a connection electrode. FIG. 3 is a cross-sectional view illustrating a structural example of an MPU using the multilayer capacitor of the present invention as a decoupling capacitor. It is a figure which shows the conventional multilayer capacitor, (a) is sectional drawing, (b) is the schematic which shows the overlapping state of the 1st, 2nd conductor layer. 3 is a frequency-impedance curve of the multilayer capacitor of FIG. 1 (dotted line), the first and second capacitor units of FIG. 1 (solid line), and the multilayer capacitor of FIG. It is a figure which shows other embodiment of the laminated capacitor of this invention, (a) is sectional drawing, (b) is the schematic which shows the overlap state of the 1st, 2nd conductor layer, (c) is 3rd. FIG. 9 is a schematic view showing an overlapping state of a fourth conductor layer. It is a figure which shows the manufacturing method of the multilayer capacitor of this invention, (a) The process of forming the 1st and 2nd penetrating conductor which penetrates only a 1st capacitor part, (b) The process of forming a 2nd capacitor part, c) a step of laminating the first and second capacitor portions, and (d) a first through conductor and a third through conductor, and a second through conductor and a fourth through conductor that penetrate both the first and second capacitor portions. This is the step of forming

Explanation of reference numerals

Reference Signs List 10 multilayer capacitor 11 first capacitor section 12 second capacitor section 2 dielectric layer 3a first conductor layer 4a second conductor layer 3b third conductor layer 4b fourth conductor layer 5a first through conductor 6a second through conductor 5b third Through conductor 6b Fourth through conductor 7a First connection terminal 8a Second connection terminal 7b Third connection terminal 8b Fourth connection terminal 13a First non-conductor formation region 14a Second non-conductor formation region 13b Third non-conductor formation region 14b 4 Non-conductor forming area 3c, 4c Connection electrode (resistor)

Claims (7)

A plurality of stacked dielectric layers, a plurality of first conductor layers and a plurality of second conductor layers, which are alternately arranged between the dielectric layers, and face each other; A plurality of first through conductors separated by a conductor layer and a second non-conductor formation region and connecting the first conductor layers to each other; and a plurality of first through conductors separated by the first conductor layer and the first non-conductor formation region. A first capacitor portion formed with a plurality of second through conductors connecting the layers,
A plurality of stacked dielectric layers, a plurality of third conductor layers and fourth conductor layers alternately arranged between the dielectric layers, and facing each other, and penetrating through the thickness direction of the dielectric layers; A capacitor formed by integrating a third through conductor for connecting conductor layers and a second capacitor portion formed with a fourth through conductor for connecting the fourth conductor layers in a stacking direction,
The total number of the first through conductors and the second through conductors is greater than the total number of the third through conductors and the fourth through conductors, and at least one of the first through conductors is the third through conductor. , And at least one of the second through conductors is connected to the fourth through conductor. The capacitor according to claim 1, wherein at least a part of the first to fourth through conductors is connected to a connection electrode having a higher resistance value than the first to fourth conductor layers. The distance between the centers of the first through conductor and the second through conductor that are adjacent to each other is P, and on a straight line connecting the centers, the center of the first through conductor and the periphery of the second non-conductor formation region 3. The relationship of P ≦ m1 + m2 is satisfied, where m2 is an interval of m2, and m1 is an interval between the center of the second through conductor and the periphery of the first non-conductor formation region. The capacitor according to any one of the above. A plurality of stacked dielectric layers, a plurality of first conductor layers and a plurality of second conductor layers, which are alternately arranged between the dielectric layers, and face each other; A plurality of first through conductors separated by a conductor layer and a second non-conductor formation region and connecting the first conductor layers to each other; and a plurality of first through conductors separated by the first conductor layer and the first non-conductor formation region. A first capacitor portion formed with a plurality of second through conductors connecting the layers,
A plurality of stacked dielectric layers, a plurality of third conductor layers and fourth conductor layers alternately arranged between the dielectric layers, and facing each other, and penetrating through the thickness direction of the dielectric layers; A method for manufacturing a capacitor, comprising: integrating a third through conductor for connecting conductor layers together and a second capacitor portion having a fourth through conductor for connecting the fourth conductor layers together in a laminating direction. hand,
Forming first and second through conductors penetrating only the first capacitor portion;
If necessary, forming third and fourth through conductors that penetrate only the second capacitor portion;
Laminating the first and second capacitor portions;
Forming the first through conductor, the third through conductor, the second through conductor, and the fourth through conductor that electrically connect the first and second capacitor units. Method of manufacturing a capacitor. A wiring board comprising the capacitor according to claim 1. A decoupling circuit comprising the capacitor according to claim 1. A high-frequency circuit comprising the capacitor according to claim 1.

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