JP2006191147A - Capacitor and wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a capacitor with low ESL and high capacity realized. <P>SOLUTION: A first capacitor part 11 having a first dielectric layer 2 and a second capacitor part 12 having a second dielectric layer 2', are integrated via a third dielectric layer 9 therebetween, that is thicker than those of the first and the second dielectric layers 2 and 2'. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

    The present invention relates to a capacitor and a wiring board, and more particularly to a capacitor and a wiring board that can be advantageously applied in a high frequency region.

  As a typical capacitor, a multilayer capacitor will be described as an example.

In an equivalent circuit using multilayer capacitors, when the capacitance of the capacitor is C and the equivalent series inductance (ESL) is L, the resonance frequency (f ₀ ) is f ₀ = 1 / [2π × (L × C). expressed in relation ^1/2], in the frequency region higher than the resonance frequency (f _0), it is known that the function of the capacitor is lost. That is, in order to maintain an electrostatic capacity (C) of a certain value or more, it is necessary to make ESL (L) as low as possible. That is, if the ESL is low, the resonance frequency (f ₀ ) is high and can be used in a higher frequency region. For this reason, in order to use the multilayer capacitor in the microwave region, it is necessary to further reduce the ESL.

  In addition, multilayer capacitors that are used to supply power to the MPU chip of a microprocessing unit (MPU) such as a workstation or personal computer and are usually connected on a wiring board as a decoupling capacitor are also used in recent MPU high speeds. As the frequency increases, there is a demand for lower ESL.

  Here, a conventional multilayer capacitor will be described with reference to FIGS. FIG. 4A is a cross-sectional view, and FIG. 4B is a schematic view showing an overlapping state of the first and second conductor layers.

  In the conventional multilayer capacitor 50 shown in the figure, a first conductor layer 53 is formed on one main surface of a dielectric layer 52, and a second conductor layer 54 is formed on the other main surface, and a plurality of these dielectric layers 52 are stacked. In addition, in the thickness direction of these dielectric layers 52, first and second through conductors 55 and 56 are formed to connect the first and second conductor layers 53 and 54, respectively. Has been. Here, the first and second through conductors 55 and 56 are exposed on one outermost surface of the multilayer body 51 and connected to the first and second connection terminals 57 and 58, respectively, so that the multilayer capacitor 50 is configured. ing. Further, first and second non-conductor forming regions 63 and 64 that are not connected to the second and first through conductors 56 and 55 are formed in the first and second conductor layers 53 and 54, respectively.

The first and second through conductors 55 and 56 are alternately distributed in a lattice pattern over the entire area of the first and second conductor layers 53 and 54 (see Patent Documents 1 to 4).
Japanese Patent Laid-Open No. 7-201651 (page 3-5, FIG. 1-5) Japanese Patent Laid-Open No. 11-204372 (page 4-6, FIG. 1-4) JP 2001-148324 A (page 4-7, FIG. 1-6) JP 2001-148325 A (page 5-7, FIG. 1-9)

  However, according to the multilayer capacitor 50, a method of increasing the number of the first and second through conductors 55 and 56 and reducing the distance between the centers can be considered in order to reduce the ESL. At this time, since the areas of the non-conductor formation regions 63 and 64 in the first and second conductor layers 53 and 54 are increased, the capacitance of the multilayer capacitor 50 is reduced.

  The present invention has been devised in view of the above-described problems, and an object thereof is to provide a capacitor that realizes a low ESL and a high capacity. Another object of the present invention is to provide a wiring board configured using the capacitor as described above.

  In the capacitor according to the present invention, a first capacitor portion having a first dielectric layer and a second capacitor portion having a second dielectric layer are interposed between the first and second dielectric layers. It is characterized by being integrated through a dielectric layer.

  In the capacitor of the present invention, the third dielectric layer is formed by laminating a plurality of dielectric layers.

  The capacitor of the present invention is characterized in that all through conductors that penetrate the first capacitor portion and the second capacitor portion in the thickness direction are formed.

  A wiring board according to the present invention includes the above-described capacitor.

  According to the capacitor of the present invention, the first and second capacitor portions are provided, and in the first capacitor portion, by increasing the number of conductors of the first and second through conductors, the distance through which the current flows is shortened. The self-inductance and mutual inductance components resulting from the induced magnetic flux are reduced. For this reason, the equivalent series inductance (ESL) of the whole capacitor can be reduced. On the other hand, if the number of the third and fourth through conductors is reduced in the second capacitor portion, the facing area between the third conductor layer and the fourth conductor layer can be increased, so that the capacitor portion has a large capacity. be able to. As a result, the equivalent series inductance (ESL) of the entire capacitor can be reduced, and a large-capacity capacitor can be realized.

  The wiring board provided with the capacitor described above is particularly effective in a circuit that operates at a high speed or a circuit that operates with a high-frequency signal.

  Hereinafter, a capacitor and a wiring board according to the present invention will be described in detail with reference to the drawings.

  1A and 1B are diagrams showing a multilayer capacitor as an example of a capacitor according to the present invention, in which FIG. 1A is a cross-sectional view, FIG. 1B is a schematic diagram showing an overlapping state of first and second conductor layers, and FIG. It is the schematic which shows the overlapping state of a 3rd, 4th conductor layer.

  In the figure, the multilayer capacitor 10 has first and second connection terminals 7a, 8a formed on one main surface of the multilayer body 1, and third and fourth connection terminals 7b, 8b on the other main surface of the multilayer body 1. Is formed. Furthermore, the multilayer body 1 integrates the first capacitor unit 11 and the second capacitor unit 12 in the stacking direction.

  The first capacitor unit 11 includes a plurality of stacked first dielectric layers 2 and a first conductor layer 3a disposed between the first dielectric layers 2 and facing each other with the first dielectric layer 2 therebetween. A first through conductor 5a passing through the second conductor layer 4a, passing through the thickness direction of the first dielectric layer 2 and connecting the first conductor layers 3a, and a second through conductor 6a connecting the second conductor layers 4a; Are formed respectively. Furthermore, the 1st and 2nd penetration conductors 5a and 6a are exposed to one main surface of the laminated body 1, and are connected to the 1st and 2nd connection terminals 7a and 8a, respectively. In the first and second conductor layers 3a and 4a, first and second non-conductor forming regions 13a and 14a that are not connected to the second and first through conductors 6a and 5a are formed.

  On the other hand, the second capacitor portion 12 is disposed between the second dielectric layer 2 ′ and the second dielectric layer 2 ′ that are stacked, and the third conductors face each other via the second dielectric layer 2 ′. The fourth through-layer 5b connecting the third conductor layer 4b and the third through-conductor 5b that connects the third conductor layer 3b through the thickness direction of the layer 3b and the fourth conductor layer 4b and the second dielectric layer 2 '. The through conductors 6b are formed respectively. Moreover, the 3rd and 4th penetration conductors 5b and 6b are exposed to one main surface of the laminated body 1, and are connected to the 3rd and 4th connection terminals 7b and 8b, respectively. And in the 3rd and 4th conductor layers 3b and 4b, the 3rd and 4th nonconductor formation area | regions 13b and 14b which are not connected with the 4th and 3rd penetration conductors 6b and 5b, respectively are formed.

  Here, the total number of conductors of the first through conductor 5a and the second through conductor 6a of the first capacitor unit 11 is based on the total number of conductors of the third through conductor 5b and the fourth through conductor 6b of the second capacitor unit 12. Has also increased.

  Further, at least one of the first through conductors 5a of the first capacitor unit 11 is connected to the third through conductor 5b of the second capacitor unit, and similarly, at least one of the second through conductors 6a is connected to the fourth through conductor. It is connected to the conductor 6b. A through conductor in which the through conductor formed in the first capacitor unit 11 and the through conductor formed in the second capacitor unit 12 are connected in this way is referred to as an “all through conductor”.

  Specifically, the first through conductor 5a of the first capacitor unit 11 is connected to the first conductor layer 3a laminated in the thickness direction, and at the same time, the second non-conductor formation region 14a of the second conductor layer 4a is connected. Since it penetrates, it does not conduct to the second conductor layer 4a. Similarly, the second through conductor 6a of the first capacitor portion 11 is connected to the second conductor layer 4a laminated in the thickness direction and simultaneously penetrates the first non-conductor formation region 13a of the first conductor layer 3a. The first conductor layer 3a is not conductive. The same applies to the third through conductor 5b and the fourth through conductor 6b on the second capacitor unit 12 side.

  Further, in order to shorten the distance through which the current flows and to cancel the magnetic fluxes induced by the current, it is desirable that the first and second through conductors 5a and 6a are alternately formed in a lattice shape.

  Here, a characteristic of the present invention is that, as shown in FIG. 1A, the first capacitor portion 11 and the second capacitor portion 12 are made to be thicker than the thicknesses of the first and second dielectric layers. It is integrated through the layer 9.

  The first and second dielectric layers 2, 2 ′ and the third dielectric layer 9 are made of a non-reducing dielectric material mainly composed of barium titanate and a dielectric material containing a glass component. One dielectric layer 2 is laminated in the upper direction in the figure to form a laminate 1. The shape, thickness, and number of layers of the first and second dielectric layers 2, 2 ′ and the third dielectric layer 9 can be arbitrarily changed according to the capacitance value, but the thickness of the third dielectric layer 9 is The first and second dielectric layers 2 and 2 'are formed thicker than the first and second dielectric layers 2 and 2'. The third dielectric layer 9 may be formed by laminating a plurality of dielectric layers with no conductor layer formed therebetween.

  The 1st-4th conductor layers 3a-4b are comprised from the material which has Ni, Cu, or these alloys as a main component, The thickness shall be 1-2 micrometers. Moreover, the material of the 1st-4th penetration conductors 5a-6b is comprised from the material which has Ni, Cu, or these alloys as a main component.

  For the connection terminals 7a, 8a, 7b, 8b, solder bumps, ball solder or the like is used.

  Next, a method for manufacturing the multilayer capacitor 10 of the present invention will be described. In the drawings, each symbol is not distinguished before and after firing.

  First, conductor films 3a and 4a serving as first and second conductor layers are formed on the ceramic green sheet 2 serving as a dielectric layer of the first capacitor unit 11 by printing and drying a conductive paste. At this time, the first and second non-conductor forming regions 13a and 14a are also formed. On the other hand, the conductor films 3b and 4b serving as the third and fourth conductor layers are formed on the ceramic green sheet 2 serving as the dielectric layer of the second capacitor unit 12 by printing and drying a conductive paste. At this time, third and fourth non-conductor forming regions 13b and 14b are also formed. As the first and second dielectric layers 2, 2 ′ and the third dielectric layer 9, other ceramic materials having a perovskite structure or organic ferroelectric materials may be used.

  Next, the required number of ceramic green sheets 2 on which the conductor films 3a and 4a are formed are alternately stacked to form a large laminate from which the first capacitor portion 11 is extracted. Similarly, the required number of ceramic green sheets 2 on which the conductor films 3b and 4b are formed are alternately stacked to form a large laminate from which the second capacitor unit 12 is extracted.

  Next, the conductor films 3a and 4a and the ceramic green sheet 2 are arranged in the thickness direction on the main surface of the large laminate from which the first capacitor portion 11 is extracted by laser irradiation or a punching method using micro drilling or punching. A penetrating through hole is formed. Further, by filling the through hole with a conductive paste, the conductor portions 5a and 6a serving as the first and second through conductors are formed. Here, the through-hole serving as the first through conductor 5a of the first capacitor unit 11 penetrates through the first conductor layer 3a and the second non-conductor formation region 14a of the second conductor layer 4a, and serves as the second through-conductor 6a. Are formed so as to penetrate the second conductor layer 4a and the first non-conductor formation region 13a of the first conductor layer 3a.

  Similarly, a through-hole penetrating the conductor films 3b and 4b and the ceramic green sheet 2 in the thickness direction is formed on the main surface of the large laminate from which the second capacitor portion 12 is extracted. Further, by filling the through hole with a conductive paste, conductor portions 5b and 6b serving as third and fourth through conductors are formed. Here, the through-hole serving as the third through conductor 5b of the second capacitor portion 12 penetrates through the third conductor layer 3b and the fourth non-conductor formation region 14b of the fourth conductor layer 4b and serves as the fourth through conductor 6b. Is formed so as to penetrate through the fourth conductor layer 4b and the third non-conductor formation region 13b of the third conductor layer 3b.

  Next, the large laminate from which the first capacitor portion 11 and the second capacitor portion 12 are extracted is stacked to form a large laminate from which the laminate 1 is extracted. At this time, one of the first through conductors 5 a formed in the first capacitor unit 11 is connected to the third through conductor 5 b formed in the second capacitor unit 12 and formed in the first capacitor unit 11. One of the second through conductors 6a overlaps in the vertical direction so as to be connected to the fourth through conductor 6b formed in the second capacitor unit 12.

  In addition, through holes are made in advance in the ceramic green sheet 2 to be a dielectric layer by a punching method using a micro drill or punching, and the conductor layers 3a to 4b are formed on the ceramic green sheet 2 by a screen printing method. At the same time as printing the conductor film, the conductive portions 5a to 6b to be the first to fourth through conductors may be formed and then stacked by filling the through holes with a conductive paste.

  Next, the large-sized laminate is cut by a press cutting process, a dicing method, or the like to obtain the unfired laminate 1.

  Next, the unfired laminate 1 is fired after the binder removal process, and the first to fourth conductor layers 3a to 4b and the first to fourth through conductors 5a to 6b are formed therein. , At least one of the first through conductors 5a is electrically connected to the third through conductor 5b, and at least one of the second through conductors 6a is electrically connected to the fourth through conductor 6b, The laminated body 1 is obtained in which the first and second through conductors 5a and 6a are exposed on the surface, and the third and fourth through conductors 5b and 6b are exposed on the other main surface.

  At this time, since the surfaces of the first to fourth through conductors 5a to 6b are oxidized, the oxide film is removed by surface polishing.

  Next, Ni plating and Sn plating are formed on the exposed portions of the first to fourth through conductors 5a to 6b. Here, Au or Cu plating may be used.

  Next, by forming a solder to be the connection terminals 7a, 8a, 7b, and 8b by a screen printing method of solder paste or a method of mounting ball solder after applying the flux, the connection terminals are subjected to a reflow process. 7a, 8a, 7b, 8b are formed. Note that the connection terminals 7b and 8b may be formed on the exposed portions of the third and fourth through conductors 5b and 6b also on the second capacitor portion 12 side.

  In addition, in each penetration conductor 5a, 5b, 6a, 6b formed in the 1st capacitor | condenser part 11 and the 2nd capacitor | condenser part 12, only the 1st and 2nd penetration conductors 5a and 6a penetrated only to the 1st capacitor | condenser part 11 are formed. In addition, if necessary, after forming only the third and fourth through conductors 5b and 6b penetrating only the second capacitor portion 12, and laminating the first capacitor portion 11 and the second capacitor portion 12, You may form the 1st penetration conductor 5a and the 3rd penetration conductor 6a which connect both, and the 2nd penetration conductor 5b and the 4th penetration conductor 6b. The specific manufacturing method will be described in detail with reference to FIG.

  Thus, the multilayer capacitor 10 as shown in FIG. 1 is obtained.

  In addition, this invention is not limited to the above embodiment, A various change and improvement can be added in the range which does not deviate from the summary of this invention.

  2A and 2B are diagrams showing another embodiment of the multilayer capacitor of the present invention, in which FIG. 2A is a cross-sectional view, FIG. 2B is a diagram illustrating a connection between a first through conductor 5a and a third through conductor 5b. It is a top view which shows the intermediate dielectric layer which formed the connection electrodes 3c and 4c which connect the penetration conductor 6a and the 4th penetration conductor 6b.

  According to the figure, the first and second capacitor portions 11 and 12 are connected between the first capacitor portion 11 and the second capacitor portion 12 via the connection electrodes 3c and 4c of the intermediate dielectric layers 3c and 4c shown in FIG. The two through conductors 5a and 6a are connected to the third and fourth through conductors 5b and 6b. For example, the first through conductor 5a is connected to the third through conductor 5b through the connection electrode 3c. Similarly, the second through conductor 6a is connected to the fourth through conductor 6b through the connection electrode 4c. ing. Thus, by arranging the connection electrodes 3c and 4c in the middle of the first capacitor part 11 and the second capacitor part 12, the arrangement of the third and fourth through conductors 5b and 6b becomes free, and at the same time, both through The connection reliability of the conductor is greatly improved. The connection electrodes 3c and 4c may be formed on both main surfaces, and the connection electrodes on the front and back sides may be connected with via hole conductors therebetween.

  At this time, since the connection electrodes 3c and 4c are each one layer, the entire first to fourth conductor layers 5a to 6b are a plurality of layers. Therefore, the connection electrodes 3c and 4c are the first to fourth conductor layers. Since the resistance value becomes higher than that of the whole 5a to 6b and functions as a resistor (dump resistor), the resonance phenomenon can be reduced and the operating frequency range can be expanded. Furthermore, for example, when Ni material is used for the first to fourth conductor layers 5a to 6b, the connection electrodes 3c and 4c have higher resistance values than those of the first to fourth conductor layers 5a to 6b, such as Ag, Ag alloy, Ni- The effect of reducing this resonance phenomenon can be obtained more effectively by using Cr, a carbon film, a metal grain, a metal oxide material, or the like.

  5 is a frequency-impedance curve of the multilayer capacitor 50 (dotted line) in FIG. 4, the first and second capacitor portions 11 and 12 (solid line) in FIG. 1, and the multilayer capacitor 10 (one-dot chain line) in FIG. As shown in the figure, the multilayer capacitor 10 of the present invention is wide by utilizing both the characteristics of the first capacitor section 11 having low impedance at the high frequency section and the characteristics of the second capacitor section 12 having low impedance at the low frequency section. Low impedance can be achieved in the frequency range. Further, as shown in FIG. 2, the first to fourth conductor layers 5a to 6b are connected to the connection electrodes 3c and 4c, so that the resonance phenomenon can be reduced and the usable frequency range can be expanded. Recognize.

  6A and 6B are diagrams showing still another embodiment of the multilayer capacitor of the present invention, in which FIG. 6A is a cross-sectional view, FIG. 6B is a schematic diagram showing an overlapping state of the first and second conductor layers, and FIG. ) Is a schematic view showing an overlapping state of the third and fourth conductor layers. According to the figure, there is no region where capacitance is generated between the first through conductor 5a and the second through conductor 6a adjacent to each other. Specifically, the interval between the center of the first through conductor 5a and the center of the second through conductor 6a adjacent to each other is P, and the radii of the first and second nonconductor forming regions 13a and 14a are m1 and m2 (general Specifically, the relationship of P ≦ m1 + m2 is satisfied when m1 = m2. Here, in order to prevent an increase in equivalent series resistance (ESR), it is desirable to satisfy the relationship r1 + r2 ≦ P when the radii of the first and second through conductors 3 and 4 are r1 and r2, respectively. . As a result, almost no current flows through the overlapping portion from one side, for example, the first through conductor 5a to the other side, for example, the second through conductor 6a. As a result, the self-inductance component caused by the magnetic flux induced by the current becomes extremely low, and the ESL of the entire multilayer capacitor 10 can be further reduced. In addition, since there is a region where the non-conductor formation regions 13a and 14a that do not contribute to the formation of capacitance overlap, the region where the first to fourth conductor layers 3a to 4b overlap relatively when viewed from the entire multilayer capacitor 10 increases. (Capacitance region is increased), and the multilayer capacitor 10 can be further increased in capacity.

  Here, the radii r1 and r2 of the first and second through conductors 5a and 6a and the radii m1 and m2 of the first and second non-conductor forming regions 13a and 14a may be equal or different.

  In addition, the cross-sectional shape of the first to fourth through conductors 5a to 6b or the shape of the first to fourth non-conductor forming regions 13a to 14b is an arbitrary shape such as an ellipse or a polygon in addition to a substantially circular shape. be able to.

  FIG. 7 is a view showing a method for manufacturing a multilayer capacitor according to the present invention, and FIG. 7A shows a process of forming first and second through conductors 5a and 6a penetrating only the first capacitor portion 11. FIG. 7B shows a step of forming the second capacitor unit 12, FIG. 7C shows a step of stacking the first and second capacitor units 11 and 12, and FIG. The process of forming the 1st penetration conductor 5a and the 3rd penetration conductor 5b which penetrates both the 1st and 2nd capacitor parts 11 and 12 and the 2nd penetration conductor 6a and the 4th penetration conductor 6b is shown.

  By manufacturing in this way, the connection between the first through conductor 5a and the third through conductor 5b or the second through conductor 6a and the fourth through conductor 6b penetrating both the first and second capacitor portions 11 and 12 is achieved. And the equivalent series resistance (ESR) can be reduced.

  The second capacitor portion 12 in FIG. 7B does not have the third and fourth through conductors that exist only in this capacitor portion, so the third and fourth through conductors 5b and 6b are omitted. The third and fourth through conductors that are present only in the second capacitor unit 12 and are not connected to the through conductors 5a and 6a of the first capacitor unit 11 are formed in advance in the process of FIG. 7B. It is necessary to keep.

  FIG. 3 is a cross-sectional view showing a structural example of the MPU 20 using the multilayer capacitor 10 of the present invention as a decoupling capacitor.

  As shown in the figure, the MPU 20 has an MPU chip 30 mounted on a wiring board 21. The multilayer capacitor 10 (A) of the present invention is mounted on the wiring board 21, and the multilayer capacitor 10 (B) of the present invention is accommodated in the cavity of the wiring board 21. The multilayer capacitors 10 (A) and 10 (B) are both connected in parallel to the MPU chip 30 and function as a decoupling capacitor.

  A power supply side conductor layer 23 and a ground side conductor layer 24 are formed inside the wiring board 21.

  The first connection terminal 7a of the multilayer capacitor 10 (A) is electrically connected to the power supply side conductor layer 23 via the power supply side through conductor 25, and the second connection terminal 8a of the multilayer capacitor 10 (A) is The MPU chip 30 is electrically connected via the ground side through conductor 26. Here, the multilayer capacitor 10 (A) does not have to form the third and fourth connection terminals 7b and 8b. At this time, the oxide film on the surfaces of the third and fourth through conductors 5b and 6b must be removed. Thus, unnecessary conduction can be prevented.

  Thus, since the multilayer capacitor 10 of the present invention has a low ESL, even when it is used as a decoupling capacitor in the MPU 20, it can sufficiently cope with high-speed operation. Further, the present invention can be applied to a wiring board provided with the multilayer capacitor 10.

  The multilayer capacitor 10 of the present invention shown in FIG. 1 and the conventional multilayer capacitor 50 shown in FIG. 4 were prepared, and the capacitance C and the equivalent series inductance L were measured. Here, both of the multilayer capacitors 10 and 50 have a size of 3.2 mm × 3.2 mm, a total of 36 first and second through conductors 5a and 6a in a lattice shape, the third and fourth through conductors 5b, A total of two 6b were formed in the central portion. As a result of the measurement, the conventional multilayer capacitor 50 shown in FIG. 4 has C = 7.8 μF and L = 20 pH, whereas the multilayer capacitor 10 of the present invention shown in FIG. 1 has C = 15 μF and L = 8 pH. It was.

  From these results, in the multilayer capacitor 10 of the present invention, the total number of conductors of the first through conductor 5a and the second through conductor 6a is larger than the total number of conductors of the third through conductor 5b and the fourth through conductor 6b. Since one of the first through conductors 5a is connected to the third through conductor 5b and one of the second through conductors 6a is connected to the fourth through conductor 6b, low ESL and high capacity are realized. I knew it was possible.

  As described above, according to the capacitor of the present invention, a plurality of laminated dielectric layers, the first conductor layer and the second conductor layer that are disposed between the dielectric layers and face each other with the dielectric layer interposed therebetween, and the dielectric The body layer passes through the thickness direction, is separated by the second conductor layer and the second non-conductor formation region, and is separated by the first through conductor connecting the first conductor layers, and the first conductor layer and the first non-conductor formation region. A first capacitor portion in which a second through conductor connecting the second conductor layers is formed, a plurality of laminated dielectric layers, and disposed between the dielectric layers, facing each other through the dielectric layers A third conductor layer and a fourth conductor layer, a third through conductor that connects the first conductor layers through the thickness direction of the dielectric layer, and a fourth through conductor that connects the fourth conductor layers. A capacitor formed by integrating the respective second capacitor portions formed in the stacking direction. A capacitors, conductors total number of the first through conductor and the second through conductor is made larger than the conductor the total number of the third through conductor and the fourth through-conductors. One of the first and second through conductors is electrically connected to the third and fourth through conductors, respectively.

  That is, in the first capacitor portion, the total number of conductors of the first and second through conductors is larger than the total number of conductors with the third and fourth through conductors, and therefore the current flowing distance is shortened. Therefore, the self-inductance and the mutual inductance component due to the magnetic flux induced by the current are reduced. For this reason, the 1st capacitor | condenser part turns into an equivalent series inductance control part by which the equivalent series inductance of a capacitor | condenser is roughly controlled, and can reduce the equivalent series inductance (ESL) of the whole capacitor | condenser. On the other hand, since the number of the third and fourth through conductors can be reduced in the second capacitor portion, the facing area between the third conductor layer and the fourth conductor layer can be increased. As a result, the entire capacitance of the capacitor can be increased. By combining these two capacitor portions, a capacitor realizing low ESL and high capacity can be provided. Further, since it is not necessary to greatly change the conventional production line, the production method is simple and inexpensive.

  In addition, since at least a part of the first to fourth through conductors (except for all) is connected to the connection electrode having a higher resistance value than the first to fourth conductor layers, the resonance phenomenon can be reduced. The operating frequency range can be expanded.

  Furthermore, since at least a part (excluding all) of the first to fourth through conductors has a higher resistance value than the other first to fourth through conductors, this can also reduce the resonance phenomenon. The operating frequency range can be expanded.

  Further, the interval between the centers of the first and second through conductors adjacent to each other is P, and on the straight line connecting the centers, the center of the first through conductor and the periphery of the second non-conductor forming region are When the interval is m2 and the interval between the center of the second through conductor and the periphery of the first non-conductor forming region is m1, the relationship from P ≦ m1 + m2 is satisfied, so that the first through conductor, for example, the second through There is almost no flow to the conductor. As a result, the self-inductance component due to the magnetic flux induced by the current becomes extremely low, and the ESL of the entire capacitor can be further reduced. Furthermore, since the non-conductor formation regions that do not contribute to the formation of the capacitance overlap, the capacitance region is relatively increased when viewed from the whole capacitor, and further increase in the capacitance of the capacitor can be realized.

  In addition, in order to form the first through conductor and the third through conductor, or the second through conductor and the fourth through conductor that pass through both the first and second capacitor sections after the first and second capacitor sections are stacked, Each connection is improved, and the equivalent series resistance (ESR) can be reduced.

  These characteristics make it particularly effective for a circuit that operates at a high speed, a circuit board that includes a circuit that operates with a high-frequency signal, a decoupling circuit, or a high-frequency circuit, and the connection reliability between the first capacitor unit and the second capacitor unit. The higher the nature.

BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows the multilayer capacitor of this invention, (a) is sectional drawing, (b) is the schematic which shows the overlapping state of the 1st, 2nd conductor layer, (c) is the overlap of the 3rd, 4th conductor layer It is the schematic which shows a state. It is a figure which shows other embodiment of the multilayer capacitor of this invention, (a) is sectional drawing, (b) is a top view which shows a connection electrode. It is sectional drawing which shows the structural example of MPU which used the multilayer capacitor of this invention as a decoupling capacitor. It is a figure which shows the conventional multilayer capacitor, (a) is sectional drawing, (b) is the schematic which shows the overlapping state of the 1st, 2nd conductor layer. 3 is a frequency-impedance curve of the multilayer capacitor in FIG. 1 (dotted line), the first and second capacitor portions in FIG. 1 (solid line), and the multilayer capacitor in FIG. It is a figure which shows other embodiment of the multilayer capacitor of this invention, (a) is sectional drawing, (b) is the schematic which shows the overlapping state of the 1st, 2nd conductor layer, (c) is 3rd. FIG. 5 is a schematic view showing an overlapping state of fourth conductor layers. It is a figure which shows the manufacturing method of the multilayer capacitor of this invention, (a) The process of forming the 1st and 2nd penetration conductor which penetrates only a 1st capacitor | condenser part, (b) The process of forming a 2nd capacitor | condenser part, c) a step of laminating the first and second capacitor parts; and (d) a first through conductor and a third through conductor penetrating both the first and second capacitor parts, and a second through conductor and a fourth through conductor. Is a step of forming.

Explanation of symbols

10 multilayer capacitor 11 first capacitor portion 12 second capacitor portion 2 dielectric layer 3a first conductor layer 4a second conductor layer 3b third conductor layer 4b fourth conductor layer 5a first through conductor 6a second through conductor 5b third Through conductor 6b Fourth through conductor 7a First connection terminal 8a Second connection terminal 7b Third connection terminal 8b Fourth connection terminal 13a First nonconductor formation region 14a Second nonconductor formation region 13b Third nonconductor formation region 14b 4 Non-conductor formation region 3c, 4c Connection electrode (resistor)

Claims (4)

A first capacitor part having a first dielectric layer and a second capacitor part having a second dielectric layer are interposed via a third dielectric layer that is thicker than the thickness of the first and second dielectric layers. An integrated capacitor. The capacitor according to claim 1, wherein the third dielectric layer is formed by stacking a plurality of dielectric layers. A capacitor, wherein all through conductors are formed so as to penetrate the first capacitor portion and the second capacitor portion in the thickness direction. A wiring board comprising the capacitor according to claim 1.

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