JP2004164641A5 - - Google Patents

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Publication number
JP2004164641A5
JP2004164641A5 JP2003379250A JP2003379250A JP2004164641A5 JP 2004164641 A5 JP2004164641 A5 JP 2004164641A5 JP 2003379250 A JP2003379250 A JP 2003379250A JP 2003379250 A JP2003379250 A JP 2003379250A JP 2004164641 A5 JP2004164641 A5 JP 2004164641A5
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JP
Japan
Prior art keywords
address
memory
banks
remainder
received
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2003379250A
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English (en)
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JP4771654B2 (ja
JP2004164641A (ja
Filing date
Publication date
Priority claimed from US10/292,144 external-priority patent/US6912616B2/en
Application filed filed Critical
Publication of JP2004164641A publication Critical patent/JP2004164641A/ja
Publication of JP2004164641A5 publication Critical patent/JP2004164641A5/ja
Application granted granted Critical
Publication of JP4771654B2 publication Critical patent/JP4771654B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Claims (3)

  1. 受信アドレスを複数のメモリバンクのメモリロケーションにマッピングするメモリコントローラであって、
    前記受信アドレスを前記複数のバンクの数に基づく除数によって除算した際の剰余を計算する回路と、
    前記剰余および前記受信アドレスの少なくとも１ビットに基づいて、前記複数のバンクのうちの特定のバンクを求める回路と、
    前記受信アドレスの少なくとも一部を使用して前記特定のバンク内の前記メモリロケーションを求める回路と、
    を有するメモリコントローラ。
  2. アドレスを複数のメモリバンクのうちの特定のバンクにマップする方法であって、
    前記アドレスを受け取るステップと、
    前記複数のバンクの数に基づく除数によって前記アドレスを除算するステップと、
    前記除算するステップの剰余および前記アドレスの少なくとも１ビットに基づいて、前記特定のバンクを求めるステップと、
    を含む方法。
  3. 複数のメモリバンクと、
    アドレスを含むメモリアクセス要求を受け取り、前記アドレスの少なくとも１ビットと、前記複数のメモリバンクの数に関連付けられる数によって前記アドレスを除算した剰余とに基づいて、前記アドレスを複数のメモリバンク内の特定のロケーションにマップする、メモリコントローラと、
    前記受け取ったアドレスの少なくとも一部を使用して、前記特定のロケーションにアクセスする回路と、
    を有するコンピュータシステム。
JP2003379250A 2002-11-12 2003-11-10 メモリバンクへのアドレスのマッピングをするメモリコントローラ Expired - Lifetime JP4771654B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/292,144 2002-11-12
US10/292,144 US6912616B2 (en) 2002-11-12 2002-11-12 Mapping addresses to memory banks based on at least one mathematical relationship

Publications (3)

Publication Number Publication Date
JP2004164641A JP2004164641A (ja) 2004-06-10
JP2004164641A5 true JP2004164641A5 (ja) 2006-11-24
JP4771654B2 JP4771654B2 (ja) 2011-09-14

Family

ID=32229382

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003379250A Expired - Lifetime JP4771654B2 (ja) 2002-11-12 2003-11-10 メモリバンクへのアドレスのマッピングをするメモリコントローラ

Country Status (2)

Country Link
US (1) US6912616B2 (ja)
JP (1) JP4771654B2 (ja)

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US20100262751A1 (en) * 2009-04-09 2010-10-14 Sun Microsystems, Inc. Memory Control Unit Mapping Physical Address to DRAM Address for a Non-Power-of-Two Number of Memory Ranks Using Lower Order Physical Address Bits
JP5365336B2 (ja) * 2009-05-01 2013-12-11 ソニー株式会社 メモリ制御装置およびメモリ制御方法
US9348751B2 (en) * 2009-09-25 2016-05-24 Nvidia Corporation System and methods for distributing a power-of-two virtual memory page across a non-power-of two number of DRAM partitions
JP2011175450A (ja) * 2010-02-24 2011-09-08 Renesas Electronics Corp メモリアクセスシステムおよびメモリアクセス制御方法
US8799553B2 (en) 2010-04-13 2014-08-05 Apple Inc. Memory controller mapping on-the-fly
US9477597B2 (en) * 2011-03-25 2016-10-25 Nvidia Corporation Techniques for different memory depths on different partitions
US8701057B2 (en) 2011-04-11 2014-04-15 Nvidia Corporation Design, layout, and manufacturing techniques for multivariant integrated circuits
US9529712B2 (en) 2011-07-26 2016-12-27 Nvidia Corporation Techniques for balancing accesses to memory having different memory types
US9405681B2 (en) 2011-12-28 2016-08-02 Intel Corporation Workload adaptive address mapping
US9009570B2 (en) * 2012-06-07 2015-04-14 Micron Technology, Inc. Integrity of an address bus
US9323608B2 (en) 2012-06-07 2016-04-26 Micron Technology, Inc. Integrity of a data bus
US9268691B2 (en) * 2012-06-11 2016-02-23 Intel Corporation Fast mechanism for accessing 2n±1 interleaved memory system
US20140122807A1 (en) * 2012-10-31 2014-05-01 Hewlett-Packard Development Company, Lp. Memory address translations
KR102202575B1 (ko) 2013-12-31 2021-01-13 삼성전자주식회사 메모리 관리 방법 및 장치
US9424181B2 (en) 2014-06-16 2016-08-23 Empire Technology Development Llc Address mapping for solid state devices
JP2016218721A (ja) 2015-05-20 2016-12-22 ソニー株式会社 メモリ制御回路およびメモリ制御方法
CN106356088A (zh) * 2015-07-15 2017-01-25 深圳市中兴微电子技术有限公司 一种数据处理方法及其装置
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