JP2004164185A - Computer device comprising volatile system memory and nonvolatile semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a computer device, which is shock-proof and enables a system program and/or various programs to get the system up and down at high speed when power is shutdown, the system runs, the operation stops, the power is recovered or the operation is restarted. <P>SOLUTION: The system stores at least a segment of memory contents memorized in a volatile memory 2 based on an action by a CPU 1 when the power for the CPU 1, the volatile memory 2, and a computer device with a nonvolatile semiconductor memory 7 is shutdown. The system, then, rewrites the segment of memory contents stored in the nonvolatile semiconductor memory 7 into the volatile system memory 2 when the power is recovered. <P>COPYRIGHT: (C)2004,JPO

Description

【０１５２】
あるいは又、Ｂｉ_２ＳｒＴａ_２Ｏ_９から成る強誘電体薄膜をパルスレーザアブレーション法、ゾル−ゲル法、あるいはＲＦスパッタ法にて全面に形成することもできる。これらの場合の形成条件を、以下の表３、表４、表５に例示する。尚、ゾル−ゲル法によって厚い強誘電体薄膜を形成する場合、所望の回数、スピンコート及び乾燥、あるいはスピンコート及び焼成（又は、アニール処理）を繰り返せばよい。
【０１５３】
［表３］
［パルスレーザアブレーション法による形成］
ターゲット：Ｂｉ_２ＳｒＴａ_２Ｏ_９
使用レーザ：ＫｒＦエキシマレーザ（波長２４８ｎｍ、パルス幅２５ｎ秒、５Ｈｚ）
形成温度 ：４００〜８００゜Ｃ
酸素濃度 ：３Ｐａ
【０１５４】

【０１５５】
［表５］
［ＲＦスパッタ法による形成］
ターゲット：Ｂｉ_２ＳｒＴａ_２Ｏ_９セラミックターゲット
ＲＦパワー：１．２Ｗ〜２．０Ｗ／ターゲット１ｃｍ^２
雰囲気圧力：０．２〜１．３Ｐａ
形成温度 ：室温〜６００゜Ｃ
プロセスガス：Ａｒ／Ｏ_２の流量比＝２／１〜９／１
【０１５６】
強誘電体層を、ＰＺＴあるいはＰＬＺＴから構成するときの、マグネトロンスパッタ法によるＰＺＴあるいはＰＬＺＴの形成条件を以下の表６に例示する。あるいは又、ＰＺＴやＰＬＺＴを、反応性スパッタ法、電子ビーム蒸着法、ゾル−ゲル法（表７の条件を参照）、ＭＯＣＶＤ法（表８の条件を参照）、パルスレーザアブレーション法（表９の条件を参照）にて形成することもできる。
【０１５７】
［表６］
［マグネトロンスパッタ法］
ターゲット ：ＰＺＴあるいはＰＬＺＴ
プロセスガス：Ａｒ／Ｏ_２＝９０体積％／１０体積％
圧力 ：４Ｐａ
パワー ：５０Ｗ
形成温度 ：５００゜Ｃ
【０１５８】

【０１５９】

【０１６０】
［表９］
［パルスレーザアブレーション法］
ターゲット：ＰＺＴ又はＰＬＺＴ
使用レーザ：ＫｒＦエキシマレーザ（波長２４８ｎｍ、パルス幅２５ｎ秒、３Ｈｚ）
出力エネルギー：４００ｍＪ（１．１Ｊ／ｃｍ^２）
形成温度 ：５５０〜６００゜Ｃ
酸素濃度 ：４０〜１２０Ｐａ
【０１６１】
［クロスポイント型不揮発性メモリユニット−変形例４］
ビット線の延びる方向と平行な仮想垂直面で不揮発性メモリユニットを切断したときの模式的な一部断面図を図１６に示す。更には、この不揮発性半導体メモリにおける不揮発性メモリユニットの概念的な等価回路図を図１７の（Ａ）及び（Ｂ）に示し、図１７の（Ａ）の概念的な等価回路図のより具体的な等価回路図を図１８に示し、図１７の（Ｂ）の概念的な等価回路図のより具体的な等価回路図を図１９に示す。尚、図１８及び図１９には、２つの不揮発性メモリユニットＭＵ_１，ＭＵ_２を図示するが、これらの不揮発性メモリユニットＭＵ_１，ＭＵ_２の構造は同一であり、以下においては、不揮発性メモリユニットＭＵ_１に関しての説明を行う。
【０１６２】
この不揮発性メモリユニットＭＵ_１は、
（Ａ）ビット線ＢＬ_１と、
（Ｂ）Ｎ個（但し、Ｎ≧２であり、図示した例ではＮ＝２）の選択用トランジスタＴＲ_１Ｎと、
（Ｃ）それぞれがＭ個（但し、Ｍ≧２であり、図示した例ではＭ＝４）のメモリセルＭＣ_１ＮＭから構成された、Ｎ個のサブメモリユニットＳＭＵ_１Ｎと、
（Ｄ）Ｍ本のプレート線ＰＬ_Ｍ、
から成る。
【０１６３】
そして、Ｎ個のサブメモリユニットＳＭＵ_１Ｎは、層間絶縁層２６を介して積層されている。各メモリセルは、第１の電極と強誘電体層と第２の電極とから成る。具体的には、第１層目のサブメモリユニットＳＭＵ_１１を構成する各メモリセルＭＣ_１１Ｍは、第１の電極２１と強誘電体層２２と第２の電極２３とから成り、第２層目のサブメモリユニットＳＭＵ_１２を構成する各メモリセルＭＣ_１２Ｍは、第１の電極３１と強誘電体層３２と第２の電極３３とから成る。更には、各サブメモリユニットＳＭＵ_１ｎにおいて、メモリセルＭＣ_１ｎｍの第１の電極２１，３１は共通である。具体的には、第１層目のサブメモリユニットＳＭＵ_１１において、メモリセルＭＣ_１１Ｍの第１の電極２１は共通である。この共通の第１の電極２１を第１の共通ノードＣＮ_１１と呼ぶ場合がある。また、第２層目のサブメモリユニットＳＭＵ_１２において、メモリセルＭＣ_１２Ｍの第１の電極３１は共通である。この共通の第１の電極３１を第２の共通ノードＣＮ_１２と呼ぶ場合がある。一般には、第ｎ層目（但し、ｎ＝１，２・・・，Ｎ）のサブメモリユニットＳＭＵ_１ｎにおいて、第ｍ番目（但し、ｍ＝１，２・・・，Ｍ）のメモリセルの第２の電極２３，３３は、サブメモリユニットＳＭＵ_１ｎ間で共通とされた第ｍ番目のプレート線ＰＬ_ｍに接続されている。より具体的には、各プレート線は、第２の電極２３，３３から延在しており、これらのプレート線は図示しない領域において接続されている。
【０１６４】
第ｎ層目（但し、ｎ＝１，２・・・，Ｎ）のサブメモリユニットＳＭＵ_１ｎにおける共通の第１の電極は、第ｎ番目の選択用トランジスタＴＲ_１ｎを介してビット線ＢＬ_１に接続されている。具体的には、各選択用トランジスタＴＲ_１１，ＴＲ_１２の一方のソース／ドレイン領域１４Ａはビット線ＢＬ_１に接続され、第１番目の選択用トランジスタＴＲ_１１の他方のソース／ドレイン領域１４Ｂは、絶縁層１６に設けられた第１層目の接続孔１７を介して、第１層目のサブメモリユニットＳＭＵ_１１における共通の第１の電極２１（第１の共通ノードＣＮ_１１）に接続されている。また、第２番目の選択用トランジスタＴＲ_１２の他方のソース／ドレイン領域１４Ｂは、絶縁層１６に設けられた第１層目の接続孔１７、パッド部２５、及び、層間絶縁層２６に設けられた第２層目の接続孔２７を介して、第２層目のサブメモリユニットＳＭＵ_１２における共通の第１の電極３１（第２の共通ノードＣＮ_１２）に接続されている。
【０１６５】
ビット線ＢＬ_１は、センスアンプＳＡに接続されている。また、プレート線ＰＬ_Ｍはプレート線デコーダ／ドライバＰＤに接続されている。更には、ワード線ＷＬ_１，ＷＬ_２（あるいはワード線ＷＬ_１１，ＷＬ_１２，ＷＬ_２１，ＷＬ_２２）は、ワード線デコーダ／ドライバＷＤに接続されている。ワード線ＷＬ_１，ＷＬ_２は、図１６の紙面垂直方向に延びている。また、不揮発性メモリユニットＭＵ_１を構成するメモリセルＭＣ_１１ｍの第２の電極２３は、図１６の紙面垂直方向に隣接する不揮発性メモリユニットＭＵ_２を構成するメモリセルＭＣ_２１ｍの第２の電極と共通であり、プレート線ＰＬ_ｍを兼ねている。更には、不揮発性メモリユニットＭＵ_１を構成するメモリセルＭＣ_１２ｍの第２の電極３３は、図１６の紙面垂直方向に隣接する不揮発性メモリユニットＭＵ_２を構成するメモリセルＭＣ_２２ｍの第２の電極と共通であり、プレート線ＰＬ_ｍを兼ねている。これらのプレート線ＰＬ_ｍは、図示しない領域において接続されている。また、ワード線ＷＬ_１は、不揮発性メモリユニットＭＵ_１を構成する選択用トランジスタＴＲ_１１と、図１６の紙面垂直方向に隣接する不揮発性メモリユニットＭＵ_２を構成する選択用トランジスタＴＲ_２１とで共通である。更には、ワード線ＷＬ_２は、不揮発性メモリユニットＭＵ_１を構成する選択用トランジスタＴＲ_１２と、図１６の紙面垂直方向に隣接する不揮発性メモリユニットＭＵ_２を構成する選択用トランジスタＴＲ_２２とで共通である。
【０１６６】
図１７の（Ａ）及び図１８に等価回路図を示す不揮発性メモリユニットＭＵ_１，ＭＵ_２において、不揮発性メモリユニットＭＵ_１，ＭＵ_２を構成する選択用トランジスタＴＲ_１ｎ，ＴＲ_２ｎは同じワード線ＷＬ_ｎに接続されている。そして、対となったメモリセルＭＣ_１ｎｍ，ＭＣ_２ｎｍ（ｎ＝１，２、及び、ｍ＝１，２・・・，Ｍ）に相補的なデータが記憶される。例えば、メモリセルＭＣ_１１ｍ，ＭＣ_２１ｍ（ここで、ｍは１，２，３，４のいずれか）に記憶されたデータを読み出す場合、ワード線ＷＬ_１を選択し、プレート線ＰＬ_ｊ（ｍ≠ｊ）には、例えば（１／２）Ｖ_ｃｃの電圧を印加した状態で、プレート線ＰＬ_ｍを駆動する。これによって、相補的なデータが、対となったメモリセルＭＣ_１１ｍ，ＭＣ_２１ｍから選択用トランジスタＴＲ_１１，ＴＲ_２１を介して対となったビット線ＢＬ_１，ＢＬ_２に電圧（ビット線電位）として現れる。そして、かかる対となったビット線ＢＬ_１，ＢＬ_２の電圧（ビット線電位）を、センスアンプＳＡで検出する。尚、不揮発性メモリユニットＭＵ_１，ＭＵ_２を構成する選択用トランジスタＴＲ_１１，ＴＲ_１２，ＴＲ_２１，ＴＲ_２２を、それぞれ、異なるワード線ＷＬ_１１，ＷＬ_１２，ＷＬ_２１，ＷＬ_２２に接続し、メモリセルＭＣ_１ｎｍ，ＭＣ_２ｎｍを独立して制御し、対となったビット線ＢＬ_１，ＢＬ_２の一方に参照電位を印加することによって、メモリセルＭＣ_１ｎｍ，ＭＣ_２ｎｍのそれぞれからデータを読み出すこともできる。このような構成を採用する場合の等価回路図は、図１７の（Ｂ）及び図１９を参照のこと。尚、選択用トランジスタＴＲ_１１，ＴＲ_２１を同時に駆動し、選択用トランジスタＴＲ_１２，ＴＲ_２２を同時に駆動すれば、図１７の（Ａ）及び図１８に示した回路と等価となる。このように、各メモリセルＭＣ_１ｎｍ，ＭＣ_２ｎｍ（ｎ＝１，２であり、ｍ＝１，２，３，４）のそれぞれに１ビットがデータとして記憶され（図１７の（Ｂ）及び図１９参照）、あるいは又、対となったメモリセルＭＣ_１ｎｍ，ＭＣ_２ｎｍに相補的なデータが１ビットとして記憶される（図１７の（Ａ）及び図１８参照）。実際の不揮発性半導体メモリにおいては、この１６ビットあるいは８ビットを記憶する不揮発性メモリユニットの集合がアクセス単位ユニットとしてアレイ状に配設されている。尚、Ｍの値は４に限定されない。Ｍの値は、Ｍ≧２を満足すればよく、実際的なＭの値として、例えば、２のべき数（２，４，８，１６・・・）を挙げることができる。また、Ｎの値は、Ｎ≧２を満足すればよく、実際的なＮの値として、例えば、２のべき数（２，４，８・・・）を挙げることができる。
【０１６７】
［クロスポイント型不揮発性メモリユニット−変形例５］
ビット線の延びる方向と平行な仮想垂直面で不揮発性メモリユニットを切断したときの模式的な一部断面図を図２０に示す。更には、不揮発性メモリユニットの概念的な等価回路図を図２１の（Ａ）及び（Ｂ）に示し、具体的な等価回路図を図２２に示す。尚、図２１の（Ａ）及び（Ｂ）には、２つの不揮発性メモリユニットＭＵ_１，ＭＵ_２を図示するが、これらの不揮発性メモリユニットＭＵ_１，ＭＵ_２の構造は同一であり、以下においては、不揮発性メモリユニットＭＵ_１に関しての説明を行う。
【０１６８】
この不揮発性メモリユニットＭＵ_１は、
（Ａ）Ｎ本（但し、Ｎ≧２であり、図示した例ではＮ＝２）のビット線ＢＬ_１Ｎと、
（Ｂ）Ｎ個の選択用トランジスタＴＲ_１Ｎと、
（Ｃ）それぞれがＭ個（但し、Ｍ≧２であり、図示した例ではＭ＝４）のメモリセルＭＣ_１ＮＭから構成された、Ｎ個のサブメモリユニットＳＭＵ_１Ｎと、
（Ｄ）Ｍ本のプレート線ＰＬ_Ｍ、
から成る。
【０１６９】
そして、Ｎ個のサブメモリユニットＳＭＵ_１Ｎは、層間絶縁層２６を介して積層されている。各メモリセルは、第１の電極と強誘電体層と第２の電極とから成る。具体的には、第１層目のサブメモリユニットＳＭＵ_１１を構成する各メモリセルＭＣ_１１Ｍは、第１の電極２１と強誘電体層２２と第２の電極２３とから成り、第２層目のサブメモリユニットＳＭＵ_１２を構成する各メモリセルＭＣ_１２Ｍは、第１の電極３１と強誘電体層３２と第２の電極３３とから成る。更には、各サブメモリユニットＳＭＵ_１ｎにおいて、メモリセルＭＣ_１ｎｍの第１の電極２１，３１は共通である。具体的には、第１層目のサブメモリユニットＳＭＵ_１１において、メモリセルＭＣ_１１Ｍの第１の電極２１は共通である。この共通の第１の電極２１を第１の共通ノードＣＮ_１１と呼ぶ場合がある。また、第２層目のサブメモリユニットＳＭＵ_１２において、メモリセルＭＣ_１２Ｍの第１の電極３１は共通である。この共通の第１の電極３１を第２の共通ノードＣＮ_１２と呼ぶ場合がある。一般には、第ｎ層目（但し、ｎ＝１，２・・・，Ｎ）のサブメモリユニットＳＭＵ_１ｎにおいて、第ｍ番目（但し、ｍ＝１，２・・・，Ｍ）のメモリセルの第２の電極２３，３３は、サブメモリユニットＳＭＵ_１ｎ間で共通とされた第ｍ番目のプレート線ＰＬ_ｍに接続されている。より具体的には、各プレート線は、第２の電極２３，３３から延在しており、これらのプレート線は図示しない領域において接続されている。
【０１７０】
第ｎ層目（但し、ｎ＝１，２・・・，Ｎ）のサブメモリユニットＳＭＵ_１ｎにおける共通の第１の電極は、第１番目の選択用トランジスタＴＲ_１１を介して第１番目のビット線ＢＬ_１１に接続されている。具体的には、第ｎ番目の選択用トランジスタＴＲ_１ｎの一方のソース／ドレイン領域１４Ａは第ｎ番目のビット線ＢＬ_１ｎに接続され、第１番目の選択用トランジスタＴＲ_１１の他方のソース／ドレイン領域１４Ｂは、絶縁層１６に設けられた第１層目の接続孔１７を介して、第１層目のサブメモリユニットＳＭＵ_１１における共通の第１の電極２１（第１の共通ノードＣＮ_１１）に接続されている。また、第２番目の選択用トランジスタＴＲ_１２の他方のソース／ドレイン領域１４Ｂは、絶縁層１６に設けられた第１層目の接続孔１７、パッド部２５、及び、層間絶縁層２６に設けられた第２層目の接続孔２７を介して、第２層目のサブメモリユニットＳＭＵ_１２における共通の第１の電極３１（第２の共通ノードＣＮ_１２）に接続されている。
【０１７１】
ビット線ＢＬ_１ｎは、センスアンプＳＡに接続されている。また、プレート線ＰＬ_Ｍはプレート線デコーダ／ドライバＰＤに接続されている。更には、ワード線ＷＬ_１，ＷＬ_２（あるいはワード線ＷＬ_１１，ＷＬ_１２，ＷＬ_２１，ＷＬ_２２）は、ワード線デコーダ／ドライバＷＤに接続されている。ワード線ＷＬ_１，ＷＬ_２は、図２０の紙面垂直方向に延びている。また、不揮発性メモリユニットＭＵ_１を構成するメモリセルＭＣ_１１ｍの第２の電極２３は、図２０の紙面垂直方向に隣接する不揮発性メモリユニットＭＵ_２を構成するメモリセルＭＣ_２１ｍの第２の電極と共通であり、プレート線ＰＬ_ｍを兼ねている。更には、不揮発性メモリユニットＭＵ_１を構成するメモリセルＭＣ_１２ｍの第２の電極３３は、図２０の紙面垂直方向に隣接する不揮発性メモリユニットＭＵ_２を構成するメモリセルＭＣ_２２ｍの第２の電極と共通であり、プレート線ＰＬ_ｍを兼ねている。これらのプレート線ＰＬ_ｍは、図示しない領域において接続されている。また、ワード線ＷＬ_１は、不揮発性メモリユニットＭＵ_１を構成する選択用トランジスタＴＲ_１１と、図２０の紙面垂直方向に隣接する不揮発性メモリユニットＭＵ_２を構成する選択用トランジスタＴＲ_２１とで共通である。更には、ワード線ＷＬ_２は、不揮発性メモリユニットＭＵ_１を構成する選択用トランジスタＴＲ_１２と、図２０の紙面垂直方向に隣接する不揮発性メモリユニットＭＵ_２を構成する選択用トランジスタＴＲ_２２とで共通である。
【０１７２】
図２１の（Ａ）及び図２２に等価回路図を示す不揮発性メモリユニットＭＵ_１，ＭＵ_２においては、不揮発性メモリユニットＭＵ_１，ＭＵ_２を構成する選択用トランジスタＴＲ_１１，ＴＲ_２１は同じワード線ＷＬ_１に接続され、選択用トランジスタＴＲ_１２，ＴＲ_２２は同じワード線ＷＬ_２に接続されている。そして、対となったメモリセルＭＣ_１ｎｍ，ＭＣ_２ｎｍ（ｎ＝１，２、及び、ｍ＝１，２・・・，Ｍ）に相補的なデータが記憶される。例えば、メモリセルＭＣ_１１ｍ，ＭＣ_２１ｍ（ここで、ｍは１，２，３，４のいずれか）に記憶されたデータを読み出す場合、ワード線ＷＬ_１を選択し、プレート線ＰＬ_ｊ（ｍ≠ｊ）には、例えば（１／２）Ｖ_ｃｃの電圧を印加した状態で、プレート線ＰＬ_ｍを駆動する。これによって、相補的なデータが、対となったメモリセルＭＣ_１１ｍ，ＭＣ_２１ｍから選択用トランジスタＴＲ_１１，ＴＲ_２１を介して対となったビット線ＢＬ_１１，ＢＬ_２１に電圧（ビット線電位）として現れる。そして、かかる対となったビット線ＢＬ_１１，ＢＬ_２１の電圧（ビット線電位）を、センスアンプＳＡで検出する。尚、不揮発性メモリユニットＭＵ_１，ＭＵ_２を構成する選択用トランジスタＴＲ_１１，ＴＲ_１２，ＴＲ_２１，ＴＲ_２２を、それぞれ、異なるワード線ＷＬ_１１，ＷＬ_１２，ＷＬ_２１，ＷＬ_２２に接続し、メモリセルＭＣ_１ｎｍ，ＭＣ_２ｎｍを独立して制御し、対となったビット線ＢＬ_１１，ＢＬ_２１、あるいは、対となったビット線ＢＬ_１２，ＢＬ_２２の一方に参照電位を印加することによって、メモリセルＭＣ_１ｎｍ，ＭＣ_２ｎｍのそれぞれからデータを読み出すこともできる。このような構成を採用する場合の等価回路図は、図２１の（Ｂ）及び図２２を参照のこと。尚、選択用トランジスタＴＲ_１１，ＴＲ_２１を同時に駆動し、選択用トランジスタＴＲ_１２，ＴＲ_２２を同時に駆動すれば、図２１の（Ａ）に示した回路と等価となる。このように、各メモリセルＭＣ_１ｎｍ，ＭＣ_２ｎｍ（ｎ＝１，２であり、ｍ＝１，２，３，４）のそれぞれに１ビットがデータとして記憶され（図２１の（Ｂ）参照）、あるいは又、対となったメモリセルＭＣ_１ｎｍ，ＭＣ_２ｎｍに相補的なデータが１ビットとして記憶される（図２１の（Ａ）参照）。実際の不揮発性半導体メモリにおいては、この１６ビットあるいは８ビットを記憶する不揮発性メモリユニットの集合がアクセス単位ユニットとしてアレイ状に配設されている。尚、Ｍの値は４に限定されない。Ｍの値は、Ｍ≧２を満足すればよく、実際的なＭの値として、例えば、２のべき数（２，４，８，１６・・・）を挙げることができる。また、Ｎの値は、Ｎ≧２を満足すればよく、実際的なＮの値として、例えば、２のべき数（２，４，８・・・）を挙げることができる。
【０１７３】
あるいは又、図２１の（Ａ）及び図２２に等価回路図を示す不揮発性メモリユニットＭＵ_１において、例えば、対となったメモリセルＭＣ_１１ｍ，ＭＣ_１２ｍ（ｍ＝１，２・・・，Ｍ）に相補的なデータを記憶してもよい。例えば、メモリセルＭＣ_１１ｍ，ＭＣ_１２ｍ（ここで、ｍは１，２，３，４のいずれか）に記憶されたデータを読み出す場合、ワード線ＷＬ_１，ＷＬ_２を選択し、プレート線ＰＬ_ｊ（ｍ≠ｊ）には、例えば（１／２）Ｖ_ｃｃの電圧を印加した状態で、プレート線ＰＬ_ｍを駆動する。これによって、相補的なデータが、対となったメモリセルＭＣ_１１ｍ，ＭＣ_１２ｍから選択用トランジスタＴＲ_１１，ＴＲ_１２を介して対となったビット線ＢＬ_１１，ＢＬ_１２に電圧（ビット線電位）として現れる。そして、かかる対となったビット線ＢＬ_１１，ＢＬ_１２の電圧（ビット線電位）を、センスアンプＳＡで検出する。尚、メモリセルＭＣ_１１ｍ，ＭＣ_１２ｍを独立して制御し、対となったビット線ＢＬ_１１，ＢＬ_１２の一方に参照電位を印加することによって、メモリセルＭＣ_１１ｍ，ＭＣ_１２ｍのそれぞれからデータを読み出すこともできる。このような構成を採用する場合の等価回路図は、図２１の（Ｂ）及び図２２を参照のこと。
【０１７４】
［クロスポイント型不揮発性メモリユニット−変形例６］
［クロスポイント型不揮発性メモリユニット−変形例４］において説明した不揮発性メモリユニットを、図２３に示す構造のように変形することもできる。尚、等価回路図を図２４に示す。
【０１７５】
この不揮発性メモリユニットは、センスアンプＳＡに接続されているビット線ＢＬ_１と、ＭＯＳ型ＦＥＴから構成されたＮ個（但し、Ｎ≧２であり、この例においてはＮ＝４）の選択用トランジスタＴＲ_１１，ＴＲ_１２，ＴＲ_１３，ＴＲ_１４と、Ｎ個のサブメモリユニットＳＭＵ_１１，ＳＭＵ_１２，ＳＭＵ_１３，ＳＭＵ_１４と、プレート線から構成されている。第１層目のサブメモリユニットＳＭＵ_１１は、Ｍ個（但し、Ｍ≧２であり、この例においてはＭ＝８）のメモリセルＭＣ_１１ｍ（ｍ＝１，２，・・・，８）から構成されている。また、第２層目のサブメモリユニットＳＭＵ_１２も、Ｍ個（Ｍ＝８）のメモリセルＭＣ_１２ｍ（ｍ＝１，２・・・，８）から構成されている。更には、第３層目のサブメモリユニットＳＭＵ_１３も、Ｍ個（Ｍ＝８）のメモリセルＭＣ_１３ｍ（ｍ＝１，２・・・，８）から構成され、第４層目のサブメモリユニットＳＭＵ_１４も、Ｍ個（Ｍ＝８）のメモリセルＭＣ_１４ｍ（ｍ＝１，２・・・，８）から構成されている。プレート線の数は、Ｍ本（この例においては８本）であり、ＰＬ_ｍ（ｍ＝１，２・・・，８）で表している。選択用トランジスタＴＲ_１ｎのゲート電極に接続されたワード線ＷＬ_１ｎは、ワード線デコーダ／ドライバＷＤに接続されている。一方、各プレート線ＰＬ_ｍは、プレート線デコーダ／ドライバＰＤに接続されている。
【０１７６】
また、第１層目のサブメモリユニットＳＭＵ_１１を構成する各メモリセルＭＣ_１１ｍは、第１の電極２１Ａと強誘電体層２２Ａと第２の電極２３とから成り、第２層目のサブメモリユニットＳＭＵ_１２を構成する各メモリセルＭＣ_１２ｍは、第１の電極２１Ｂと強誘電体層２２Ｂと第２の電極２３とから成り、第３層目のサブメモリユニットＳＭＵ_１３を構成する各メモリセルＭＣ_１３ｍは、第１の電極３１Ａと強誘電体層３２Ａと第２の電極３３とから成り、第４層目のサブメモリユニットＳＭＵ_１４を構成する各メモリセルＭＣ_１４ｍは、第１の電極３１Ｂと強誘電体層３２Ｂと第２の電極３３とから成る。そして、各サブメモリユニットＳＭＵ_１１，ＳＭＵ_１２，ＳＭＵ_１３，ＳＭＵ_１４において、メモリセルの第１の電極２１Ａ，２１Ｂ，３１Ａ，３１Ｂは共通である。この共通の第１の電極２１Ａ，２１Ｂ，３１Ａ，３１Ｂを、便宜上、共通ノードＣＮ_１１，ＣＮ_１２，ＣＮ_１３，ＣＮ_１４と呼ぶ。
【０１７７】
ここで、第１層目のサブメモリユニットＳＭＵ_１１における共通の第１の電極２１Ａ（第１の共通ノードＣＮ_１１）は、第１番目の選択用トランジスタＴＲ_１１を介してビット線ＢＬ_１に接続されている。また、第２層目のサブメモリユニットＳＭＵ_１２における共通の第１の電極２１Ｂ（第２の共通ノードＣＮ_１２）は、第２番目の選択用トランジスタＴＲ_１２を介してビット線ＢＬ_１に接続されている。更には、第３層目のサブメモリユニットＳＭＵ_１３における共通の第１の電極３１Ａ（第３の共通ノードＣＮ_１３）は、第３番目の選択用トランジスタＴＲ_１３を介してビット線ＢＬ_１に接続されている。また、第４層目のサブメモリユニットＳＭＵ_１４における共通の第１の電極３１Ｂ（第４の共通ノードＣＮ_１４）は、第４番目の選択用トランジスタＴＲ_１４を介してビット線ＢＬ_１に接続されている。
【０１７８】
また、第１層目のサブメモリユニットＳＭＵ_１１を構成するメモリセルＭＣ_１１ｍと、第２層目のサブメモリユニットＳＭＵ_１２を構成するメモリセルＭＣ_１２ｍは、第２の電極２３を共有しており、この共有された第ｍ番目の第２の電極２３はプレート線ＰＬ_ｍに接続されている。更には、第３層目のサブメモリユニットＳＭＵ_１３を構成するメモリセルＭＣ_１３ｍと、第４層目のサブメモリユニットＳＭＵ_１４を構成するメモリセルＭＣ_１４ｍは、第２の電極３３を共有しており、この共有された第ｍ番目の第２の電極３３はプレート線ＰＬ_ｍに接続されている。具体的には、この共有された第ｍ番目の第２の電極２３の延在部からプレート線ＰＬ_ｍが構成され、この共有された第ｍ番目の第２の電極３３の延在部からプレート線ＰＬ_ｍが構成されており、各プレート線ＰＬ_ｍは図示しない領域で接続されている。
【０１７９】
この不揮発性メモリユニットにおいては、サブメモリユニットＳＭＵ_１１，ＳＭＵ_１２とサブメモリユニットＳＭＵ_１３，ＳＭＵ_１４は、層間絶縁層２６を介して積層されている。サブメモリユニットＳＭＵ_１４は絶縁膜３６Ａで被覆されている。また、サブメモリユニットＳＭＵ_１１は、半導体基板１０の上方に絶縁層１６を介して形成されている。半導体基板１０には素子分離領域１１が形成されている。また、選択用トランジスタＴＲ_１１，ＴＲ_１２，ＴＲ_１３，ＴＲ_１４は、ゲート絶縁膜１２、ゲート電極１３、ソース／ドレイン領域１４Ａ，１４Ｂから構成されている。そして、第１の選択用トランジスタＴＲ_１１、第２の選択用トランジスタＴＲ_１２、第３の選択用トランジスタＴＲ_１３、第４の選択用トランジスタＴＲ_１４の一方のソース／ドレイン領域１４Ａはコンタクトホール１５を介してビット線ＢＬ_１に接続されている。また、第１の選択用トランジスタＴＲ_１１の他方のソース／ドレイン領域１４Ｂは、絶縁層１６に形成された開口部中に設けられた接続孔１７を介して第１の共通ノードＣＮ_１１に接続されている。更には、第２の選択用トランジスタＴＲ_１２の他方のソース／ドレイン領域１４Ｂは、接続孔１７を介して第２の共通ノードＣＮ_１２に接続されている。また、第３の選択用トランジスタＴＲ_１３の他方のソース／ドレイン領域１４Ｂは、接続孔１７、パッド部２５、層間絶縁層２６に形成された開口部中に設けられた接続孔２７を介して第３の共通ノードＣＮ_１３に接続されている。更には、第４の選択用トランジスタＴＲ_１４の他方のソース／ドレイン領域１４Ｂは、接続孔１７、パッド部２５、接続孔２７を介して第４の共通ノードＣＮ_１４に接続されている。
【０１８０】
［クロスポイント型不揮発性メモリユニット−変形例７］
例えば、図２５に示すように、［クロスポイント型不揮発性メモリユニット−変形例４］の不揮発性メモリユニットの変形例として、第１の電極２１’，３１’を上部電極とし、第２の電極２３’，３３’を下部電極とすることもできる。このような構造は、他のクロスポイント型不揮発性メモリユニットにも適用することができる。
【０１８１】
［クロスポイント型不揮発性メモリユニット−変形例８］
以上に説明した各種のクロスポイント型不揮発性メモリユニットを、特開２００２−１９７８５７に開示された所謂ゲインセル型とすることもできる。このような不揮発性メモリユニットの等価回路図を図２６に示し、不揮発性メモリユニットを構成する各種のトランジスタの模式的なレイアウトを図２７に示し、不揮発性メモリユニットの模式的な一部断面図を図２８及び図２９に示す。尚、図２７において、各種のトランジスタの領域を点線で囲み、活性領域及び配線を実線で示し、ゲート電極あるいはワード線を一点鎖線で示した。また、図２８に示す不揮発性メモリユニットの模式的な一部断面図は、図２７の線Ａ−Ａに沿った模式的な一部断面図であり、図２９に示す不揮発性メモリユニットの模式的な一部断面図は、図２７の線Ｂ−Ｂに沿った模式的な一部断面図である。
【０１８２】
図６に示したクロスポイント型不揮発性メモリユニットから構成された不揮発性メモリユニットにゲインセル型を適用した例を、以下に説明する。この不揮発性メモリユニットは、例えば、ビット線ＢＬと、書込用トランジスタ示した（図６に不揮発性メモリユニットにおける選択用トランジスタである）ＴＲ_Ｗと、Ｍ個（但し、Ｍ≧２であり、例えば、Ｍ＝８）のメモリセルＭＣ_Ｍから構成され、例えば層間絶縁層を介して積層されたＮ個のサブメモリユニットＳＭＵと、Ｍ本のプレート線ＰＬ_Ｍから成る不揮発性メモリユニットＭＵから構成されている。そして、各メモリセルＭＣ_Ｍは、第１の電極２１と強誘電体層２２と第２の電極２３とから成り、サブメモリユニットＳＭＵを構成するメモリセルＭＣ_Ｍの第１の電極２１は、サブメモリユニットＳＭＵにおいて共通であり、この共通の第１の電極（共通ノードＣＮ）は、書込用トランジスタＴＲ_Ｗを介してビット線ＢＬに接続され、各メモリセルＭＣ_ｍを構成する第２の電極２３はプレート線ＰＬ_ｍに接続されている。メモリセルＭＣ_Ｍは層間絶縁層２６によって被覆されている。尚、不揮発性メモリユニットのサブメモリユニットＳＭＵを構成するメモリセルの数（Ｍ）は８個に限定されず、一般には、Ｍ≧２を満足すればよく、２のべき数（Ｍ＝２，４，８，１６・・・）とすることが好ましい。
【０１８３】
更には、共通の第１の電極の電位変化を検出し、該検出結果をビット線に電流又は電圧として伝達する信号検出回路を備えている。言い換えれば、検出用トランジスタＴＲ_Ｓ、及び、読出用トランジスタＴＲ_Ｒを備えている。信号検出回路は、検出用トランジスタＴＲ_Ｓ及び読出用トランジスタＴＲ_Ｒから構成されている。そして、検出用トランジスタＴＲ_Ｓの一端は所定の電位Ｖ_ｃｃを有する配線（例えば、不純物層から構成された電源線）に接続され、他端は読出用トランジスタＴＲ_Ｒを介してビット線ＢＬに接続され、各メモリセルＭＣ_ｍに記憶されたデータの読出し時、読出用トランジスタＴＲ_Ｒが導通状態とされ、各メモリセルＭＣ_ｍに記憶されたデータに基づき共通の第１の電極（共通ノードＣＮ）に生じた電位により、検出用トランジスタＴＲ_Ｓの動作が制御される。
【０１８４】
具体的には、各種のトランジスタはＭＯＳ型ＦＥＴから構成されており、書込用トランジスタ（選択用トランジスタ）ＴＲ_Ｗの一方のソース／ドレイン領域は絶縁層１６に形成されたコンタクトホール１５を介してビット線ＢＬに接続され、他方のソース／ドレイン領域は、絶縁層１６に形成された開口部中に設けられた接続孔１７を介して共通の第１の電極（共通ノードＣＮ）に接続されている。また、検出用トランジスタＴＲ_Ｓの一方のソース／ドレイン領域は、所定の電位Ｖ_ｃｃを有する配線に接続され、他方のソース／ドレイン領域は、読出用トランジスタＴＲ_Ｒの一方のソース／ドレイン領域に接続されている。より具体的には、検出用トランジスタＴＲ_Ｓの他方のソース／ドレイン領域と読出用トランジスタＴＲ_Ｒの一方のソース／ドレイン領域とは、１つのソース／ドレイン領域を占めている。更には、読出用トランジスタＴＲ_Ｒの他方のソース／ドレイン領域はコンタクトホール１５を介してビット線ＢＬに接続され、更に、共通の第１の電極（共通ノードＣＮ、あるいは、書込用トランジスタＴＲ_Ｗの他方のソース／ドレイン領域）は、開口部中に設けられた接続孔１７Ａ、ワード線ＷＬ_Ｓを介して検出用トランジスタＴＲ_Ｓのゲート電極に接続されている。また、書込用トランジスタＴＲ_Ｗのゲート電極に接続されたワード線ＷＬ_Ｗ及び読出用トランジスタＴＲ_Ｒのゲート電極に接続されたワード線ＷＬ_Ｒは、ワード線デコーダ／ドライバＷＤに接続されている。一方、各プレート線ＰＬ_ｍは、プレート線デコーダ／ドライバＰＤに接続されている。更には、ビット線ＢＬはセンスアンプＳＡに接続されている。
【０１８５】
この不揮発性メモリユニットのメモリセルＭＣ_１からデータを読み出す場合、選択プレート線ＰＬ_１にＶ_ｃｃを印加する。このとき、選択メモリセルＭＣ_１にデータ「１」が記憶されていれば、強誘電体層に分極反転が生じ、蓄積電荷量が増加し、共通ノードＣＮの電位が上昇する。一方、選択メモリセルＭＣ_１にデータ「０」が記憶されていれば、強誘電体層に分極反転が生ぜず、共通ノードＣＮの電位は殆ど上昇しない。即ち、共通ノードＣＮは、非選択メモリセルの強誘電体層を介して複数の非選択プレート線ＰＬ_ｊにカップリングされているので、共通ノードＣＮの電位は０ボルトに比較的近いレベルに保たれる。このようにして、選択メモリセルＭＣ_１に記憶されたデータに依存して共通ノードＣＮの電位に変化が生じる。従って、選択メモリセルの強誘電体層には、分極反転に十分な電界を与えることができる。そして、ビット線ＢＬを浮遊状態とし、読出用トランジスタＴＲ_Ｒをオン状態とする。一方、選択メモリセルＭＣ_１に記憶されたデータに基づき共通の第１の電極（共通ノードＣＮ）に生じた電位により、検出用トランジスタＴＲ_Ｓの動作が制御される。具体的には、選択メモリセルＭＣ_１に記憶されたデータに基づき共通の第１の電極（共通ノードＣＮ）に高い電位が生じれば、検出用トランジスタＴＲ_Ｓは導通状態となり、検出用トランジスタＴＲ_Ｓの一方のソース／ドレイン領域は所定の電位Ｖ_ｃｃを有する配線に接続されているので、かかる配線から、検出用トランジスタＴＲ_Ｓ及び読出用トランジスタＴＲ_Ｒを介してビット線ＢＬに電流が流れ、ビット線ＢＬの電位が上昇する。即ち、信号検出回路によって共通の第１の電極（共通ノードＣＮ）の電位変化が検出され、この検出結果がビット線ＢＬに電圧（電位）として伝達される。ここで、検出用トランジスタＴＲ_Ｓの閾値をＶ_ｔｈ、検出用トランジスタＴＲ_Ｓのゲート電極の電位（即ち、共通ノードＣＮの電位）をＶ_ｇとすれば、ビット線ＢＬの電位は概ね（Ｖ_ｇ−Ｖ_ｔｈ）となる。尚、検出用トランジスタＴＲ_Ｓをディプレッション型のＮＭＯＳＦＥＴとすれば、閾値Ｖ_ｔｈは負の値をとる。これにより、ビット線ＢＬの負荷の大小に拘わらず、安定したセンス信号量を確保できる。尚、検出用トランジスタＴＲ_ＳをＰＭＯＳＦＥＴから構成することもできる。
【０１８６】
尚、検出用トランジスタの一端が接続された配線の所定の電位はＶ_ｃｃに限定されず、例えば、接地されていてもよい。即ち、検出用トランジスタの一端が接続された配線の所定の電位を０ボルトとしてもよい。但し、この場合には、選択メモリセルにおけるデータの読出し時に電位（Ｖ_ｃｃ）がビット線に現れた場合、再書込み時には、ビット線の電位を０ボルトとし、選択メモリセルにおけるデータの読出し時に０ボルトがビット線に現れた場合、再書込み時には、ビット線の電位をＶ_ｃｃとする必要がある。そのためには、図３０に例示するような、トランジスタＴＲ_ＩＶ−１，ＴＲ_ＩＶ−２，ＴＲ_ＩＶ−３，ＴＲ_ＩＶ−４から構成された一種のスイッチ回路（反転回路）をビット線間に配設し、データの読出し時には、トランジスタＴＲ_ＩＶ−２，ＴＲ_ＩＶ−４をオン状態とし，データの再書込み時には、トランジスタＴＲ_ＩＶ−１，ＴＲ_ＩＶ−３をオン状態とすればよい。
【０１８７】
以上、各種のクロスポイント型不揮発性メモリユニットを説明したが、［クロスポイント型不揮発性メモリユニット−変形例３］〜［クロスポイント型不揮発性メモリユニット−変形例８］において、複数のメモリセルに１つの選択用トランジスタを共有させ、しかも、サブメモリユニットを三次元積層構造とすることにより、半導体基板表面を占有するトランジスタの数に制約されることが無くなり、従来の強誘電体型不揮発性半導体メモリに比べて飛躍的に記憶容量を増大させることができ、ビット記憶単位の実効占有面積を大幅に縮小することが可能となる。
【０１８８】
また、［クロスポイント型不揮発性メモリユニット−変形例３］〜［クロスポイント型不揮発性メモリユニット−変形例８］にあっては、Ｎ≧２を満足すればよく、実際的なＮの値として、例えば、２のべき数（２，４，８・・・）を挙げることができる。
【０１８９】
上方に位置するサブメモリユニットのメモリセルを構成する強誘電体層の結晶化温度が、下方に位置するサブメモリユニットのメモリセルを構成する強誘電体層の結晶化温度よりも低いことが好ましい。ここで、メモリセルを構成する強誘電体層の結晶化温度は、例えば、Ｘ線回折装置や表面走査型電子顕微鏡を用いて調べることができる。具体的には、例えば、強誘電体材料層を形成した後、強誘電体材料層の結晶化を行うための熱処理温度を種々変えて結晶化促進のための熱処理を行い、熱処理後の強誘電体材料層のＸ線回折分析を行い、強誘電体材料に特有の回折パターン強度（回折ピークの高さ）を評価することによって、強誘電体層の結晶化温度を求めることができる。
【０１９０】
ところで、サブメモリユニットが積層された構成を有する不揮発性半導体メモリを製造する場合、強誘電体層、あるいは、強誘電体層を構成する強誘電体薄膜の結晶化のために、熱処理（結晶化熱処理と呼ぶ）を積層されたサブメモリユニットの段数だけ行わなければならない。従って、下段に位置するサブメモリユニットほど長時間の結晶化熱処理を受け、上段に位置するほどサブメモリユニットは短時間の結晶化熱処理を受けることになる。それ故、上段に位置するサブメモリユニットに対して最適な結晶化熱処理を施すと、下段に位置するサブメモリユニットは過度の熱負荷を受ける虞があり、下段に位置するサブメモリユニットの特性劣化が生じる虞がある。尚、多段のサブメモリユニットを作製した後、一度で結晶化熱処理を行う方法も考えられるが、結晶化の際に強誘電体層に大きな体積変化が生じたり、各強誘電体層から脱ガスが生じる可能性が高く、強誘電体層にクラックや剥がれが生じるといった問題が発生し易い。上方に位置するサブメモリユニットを構成する強誘電体層の結晶化温度を、下方に位置するサブメモリユニットを構成する強誘電体層の結晶化温度よりも低くすれば、積層されたサブメモリユニットの段数だけ結晶化熱処理を行っても、下方に位置するサブメモリユニットを構成するメモリセルの特性劣化といった問題は生じない。また、各段におけるサブメモリユニットを構成するメモリセルに対して、最適な条件での結晶化熱処理を行うことができ、特性の優れた不揮発性半導体メモリを得ることができる。以下の表１０に、強誘電体層を構成する代表的な材料の結晶化温度を示すが、強誘電体層を構成する材料をかかる材料に限定するものではない。
【０１９１】
［表１０］
材料名 結晶化温度
Ｂｉ_２ＳｒＴａ_２Ｏ_９ ７００〜８００゜Ｃ
Ｂｉ_２Ｓｒ（Ｔａ_１．５，Ｎｂ_０．５）Ｏ_９ ６５０〜７５０゜Ｃ
Ｂｉ_４Ｔｉ_３Ｏ_１２ ６００〜７００゜Ｃ
Ｐｂ（Ｚｒ_０．４８，Ｔｉ_０．５２）Ｏ_３ ５５０〜６５０゜Ｃ
ＰｂＴｉＯ_３ ５００〜６００゜Ｃ
【０１９２】
強誘電体層を構成する材料として、ビスマス層状化合物、より具体的には、Ｂｉ系層状構造ペロブスカイト型の強誘電体材料を挙げることができる。Ｂｉ系層状構造ペロブスカイト型の強誘電体材料は、所謂不定比化合物に属し、金属元素、アニオン（Ｏ等）元素の両サイトにおける組成ずれに対する寛容性がある。また、化学量論的組成からやや外れたところで最適な電気的特性を示すことも珍しくない。Ｂｉ系層状構造ペロブスカイト型の強誘電体材料は、例えば、一般式（Ｂｉ_２Ｏ_２）^２＋（Ａ_ｍ−１Ｂ_ｍＯ_３ｍ＋１）^２−で表すことができる。ここで、「Ａ」は、Ｂｉ、Ｐｂ、Ｂａ、Ｓｒ、Ｃａ、Ｎａ、Ｋ、Ｃｄ等の金属から構成された群から選択された１種類の金属を表し、「Ｂ」は、Ｔｉ、Ｎｂ、Ｔａ、Ｗ、Ｍｏ、Ｆｅ、Ｃｏ、Ｃｒから成る群から選択された１種類、若しくは複数種の任意の比率による組み合わせを表す。また、ｍは１以上の整数である。
【０１９３】
あるいは又、強誘電体層を構成する材料は、
（Ｂｉ_Ｘ，Ｓｒ_１−Ｘ）_２（Ｓｒ_Ｙ，Ｂｉ_１−Ｙ）（Ｔａ_Ｚ，Ｎｂ_１−Ｚ）_２Ｏ_ｄ 式（１）
（但し、０．９≦Ｘ≦１．０、０．７≦Ｙ≦１．０、０≦Ｚ≦１．０、８．７≦ｄ≦９．３）で表される結晶相を主たる結晶相として含んでいることが好ましい。あるいは又、強誘電体層を構成する材料は、
Ｂｉ_ＸＳｒ_ＹＴａ_２Ｏ_ｄ 式（２）
（但し、Ｘ＋Ｙ＝３、０．７≦Ｙ≦１．３、８．７≦ｄ≦９．３）で表される結晶相を主たる結晶相として含んでいることが好ましい。これらの場合、式（１）若しくは式（２）で表される結晶相を主たる結晶相として８５％以上含んでいることが一層好ましい。尚、式（１）中、（Ｂｉ_Ｘ，Ｓｒ_１−Ｘ）の意味は、結晶構造における本来Ｂｉが占めるサイトをＳｒが占め、このときのＢｉとＳｒの割合がＸ：（１−Ｘ）であることを意味する。また、（Ｓｒ_Ｙ，Ｂｉ_１−Ｙ）の意味は、結晶構造における本来Ｓｒが占めるサイトをＢｉが占め、このときのＳｒとＢｉの割合がＹ：（１−Ｙ）であることを意味する。式（１）若しくは式（２）で表される結晶相を主たる結晶相として含む強誘電体層を構成する材料には、Ｂｉの酸化物、ＴａやＮｂの酸化物、Ｂｉ、ＴａやＮｂの複合酸化物が若干含まれている場合もあり得る。
【０１９４】
あるいは又、強誘電体層を構成する材料は、
Ｂｉ_Ｘ（Ｓｒ，Ｃａ，Ｂａ）_Ｙ（Ｔａ_Ｚ，Ｎｂ_１−Ｚ）_２Ｏ_ｄ 式（３）
（但し、１．７≦Ｘ≦２．５、０．６≦Ｙ≦１．２、０≦Ｚ≦１．０、８．０≦ｄ≦１０．０）で表される結晶相を含んでいてもよい。尚、「（Ｓｒ，Ｃａ，Ｂａ）」は、Ｓｒ、Ｃａ及びＢａから構成された群から選択された１種類の元素を意味する。これらの各式で表される強誘電体層を構成する材料の組成を化学量論的組成で表せば、例えば、例えば、Ｂｉ_２ＳｒＴａ_２Ｏ_９（タンタル酸ストロンチウムビスマス）、Ｂｉ_２ＳｒＮｂ_２Ｏ_９（ニオブ酸ストロンチウムビスマス）、Ｂｉ_２ＢａＴａ_２Ｏ_９（タンタル酸バリウムビスマス）、Ｂｉ_２ＢａＮｂ_２Ｏ_９（ニオブ酸バリウムビスマス）、Ｂｉ_２Ｓｒ（Ｔａ，Ｎｂ）_２Ｏ_９（ニオブ酸タンタル酸ストロンチウムビスマス）等を挙げることができる。あるいは又、強誘電体材料として、Ｂｉ_４ＳｒＴｉ_４Ｏ_１５（チタン酸ストロンチウムビスマス）、Ｂｉ_３ＴｉＮｂＯ_９（ニオブ酸ビスマスチタン）、Ｂｉ_３ＴｉＴａＯ_９（タンタル酸ビスマスチタン）、Ｂｉ_４Ｔｉ_３Ｏ_１２（チタン酸ビスマス）、（Ｂｉ，Ｌａ）_４Ｔｉ_３Ｏ_１２（チタン酸ランタンビスマス）、Ｂｉ_２ＰｂＴａ_２Ｏ_９（タンタル酸ビスマス鉛）等を例示することができるが、これらの場合においても、各金属元素の比率は、結晶構造が変化しない程度に変化させ得る。即ち、金属元素及び酸素元素の両サイトにおける組成ずれがあってもよい。
【０１９５】
あるいは又、強誘電体材料として、ＰｂＴｉＯ_３（チタン酸鉛）、ＢａＴｉＯ_３（チタン酸バリウム）、ＬｉＮｂＯ_３（ニオブ酸リチウム）、ＬｉＴａＯ_３（タンタル酸リチウム）、ＹＭｎＯ_３（マンガン酸イットリウム）、ペロブスカイト型構造を有するＰｂＺｒＯ_３とＰｂＴｉＯ_３の固溶体であるチタン酸ジルコン酸鉛［ＰＺＴ，Ｐｂ（Ｚｒ_１−ｙ，Ｔｉ_ｙ）Ｏ_３（但し、０＜ｙ＜１）］、ＰＺＴにＬａを添加した金属酸化物であるＰＬＺＴ［（Ｐｂ，Ｌａ）（Ｚｒ，Ｔｉ）Ｏ_３（チタン酸ジルコン酸ランタン鉛）］、あるいはＰＺＴにＮｂを添加した金属酸化物であるＰＮＺＴ、ＰＺＴにストロンチウム（Ｓｒ）を添加した金属酸化物であるＰＳＺＴ［（Ｐｂ，Ｓｒ）（Ｚｒ_Ｘ，Ｔｉ_Ｙ）Ｏ_３］、これらの混合物を挙げることができる。
【０１９６】
以上に説明した強誘電体層を構成する材料において、これらの組成を化学量論的組成から外すことによって、結晶化温度を変化させることが可能である。
【０１９７】
強誘電体層を得るためには、強誘電体薄膜を形成した後の工程において、強誘電体薄膜をパターニングすればよい。場合によっては、強誘電体薄膜のパターニングは不要である。強誘電体薄膜の形成は、例えば、ＭＯＣＶＤ法；ビスマス−酸素結合を有するビスマス有機金属化合物（ビスマスアルコキシド化合物）を原料としたＭＯＤ（Ｍｅｔａｌ Ｏｒｇａｎｉｃ Ｄｅｃｏｍｐｏｓｉｔｉｏｎ）法；ＬＳＭＣＤ（Ｌｉｑｕｉｄ Ｓｏｕｒｃｅ Ｍｉｓｔ Ｃｈｅｍｉｃａｌ Ｄｅｐｏｓｉｔｉｏｎ）法；パルスレーザアブレーション法；マグネトロンスパッタリング法や反応性スパッタリング法といったスパッタリング法；電子ビーム蒸着法；スプレー塗布法、スピンコート法といった溶液化学法（ゾル−ゲル法）といった強誘電体薄膜を構成する材料に適した方法にて適宜行うことができる。また、強誘電体薄膜のパターニングは、例えば異方性イオンエッチング（ＲＩＥ）法にて行うことができる。
【０１９８】
先に説明したとおり、強誘電体層の下に第１の電極を形成し、強誘電体層の上に第２の電極を形成する構成（即ち、第１の電極は下部電極に相当し、第２の電極は上部電極に相当する）とすることもできるし、強誘電体層の上に第１の電極を形成し、強誘電体層の下に第２の電極を形成する構成（即ち、第１の電極は上部電極に相当し、第２の電極は下部電極に相当する）とすることもできる。プレート線は、第２の電極から延在している構成とすることが、配線構造の簡素化といった観点から好ましい。第１の電極が共通である構造として、具体的には、ストライプ状の第１の電極を形成し、かかるストライプ状の第１の電極の全面を覆うように強誘電体層を形成する構成を挙げることができる。尚、このような構造においては、第１の電極と強誘電体層と第２の電極の重複領域がメモリセルに相当する。第１の電極が共通である構造として、その他、第１の電極の所定の領域に、それぞれの強誘電体層が形成され、強誘電体層上に第２の電極が形成された構造、あるいは又、配線の所定の表面領域に、それぞれの第１の電極が形成され、かかるそれぞれの第１の電極上に強誘電体層が形成され、強誘電体層上に第２の電極が形成された構造を挙げることができるが、これらの構成に限定するものではない。
【０１９９】
第１の電極が共通である構造として、具体的には、ストライプ状の第１の電極を形成し、かかるストライプ状の第１の電極の全面を覆うように強誘電体層を形成する構成を挙げることができる。尚、このような構造においては、第１の電極と強誘電体層と第２の電極の重複領域がメモリセルに相当する。第１の電極が共通である構造として、その他、第１の電極の所定の領域に、それぞれの強誘電体層が形成され、強誘電体層上に第２の電極が形成された構造、あるいは又、配線層の所定の表面領域に、それぞれの第１の電極が形成され、かかるそれぞれの第１の電極上に強誘電体層が形成され、強誘電体層上に第２の電極が形成された構造を挙げることができるが、これらの構成に限定するものではない。
【０２００】
第１の電極及び第２の電極は、白金族から選択された少なくとも１種類の金属、あるいは、その酸化物から構成され、あるいは又、ルテニウム（Ｒｕ）、ロジウム（Ｒｈ）、パラジウム（Ｐｄ）、オスミウム（Ｏｓ）、イリジウム（Ｉｒ）、白金（Ｐｔ）及びレニウム（Ｒｅ）から成る群から選択された少なくとも１種類の金属、あるいは、その酸化物から構成されていることが望ましく、具体的には、例えば、Ｉｒ、ＩｒＯ_２−Ｘ、ＩｒＯ_２−Ｘ／Ｉｒ、Ｉｒ／ＩｒＯ_２−Ｘ、ＳｒＩｒＯ_３、Ｒｕ、ＲｕＯ_２−Ｘ、ＳｒＲｕＯ_３、Ｐｔ、Ｐｔ／ＩｒＯ_２−Ｘ、Ｐｔ／ＲｕＯ_２−Ｘ、Ｐｄ、Ｐｔ／Ｔｉの積層構造、Ｐｔ／Ｔａの積層構造、Ｐｔ／Ｔｉ／Ｔａの積層構造を例示することができ、あるいは又、Ｌａ_０．５Ｓｒ_０．５ＣｏＯ_３（ＬＳＣＯ）、Ｐｔ／ＬＳＣＯの積層構造、ＹＢａ_２Ｃｕ_３Ｏ_７を挙げることができる。ここで、Ｘの値は、０≦Ｘ＜２である。ｕ尚、積層構造においては、「／」の後ろに記載された材料が強誘電体層と接する。第１の電極と第２の電極は、同じ材料から構成されていてもよいし、同種の材料から構成されていてもよいし、異種の材料から構成されていてもよい。第１の電極あるいは第２の電極を形成するためには、第１の電極材料層あるいは第２の電極材料層を形成した後の工程において、第１の電極材料層あるいは第２の電極材料層をパターニングすればよい。第１の電極材料層あるいは第２の電極材料層の形成は、例えばスパッタ法、反応性スパッタ法、電子ビーム蒸着法、ＭＯＣＶＤ法、あるいはパルスレーザアブレーション法といった第１の電極材料層や第２の電極材料層を構成する材料に適宜適した方法にて行うことができる。また、第１の電極材料層や第２の電極材料層のパターニングは、例えばイオンミーリング法やＲＩＥ法にて行うことができる。
【０２０１】
強誘電体層の下に第１の電極を形成し、強誘電体層の上に第２の電極を形成する構成の場合、メモリセルを構成する第１の電極は、所謂ダマシン構造を有しており、強誘電体層の上に第１の電極を形成し、強誘電体層の下に第２の電極を形成する構成の場合、メモリセルを構成する第２の電極は、所謂ダマシン構造を有していることが、強誘電体層を平坦な下地上に形成することができるといった観点から好ましい。
【０２０２】
層間絶縁層を構成する材料として、酸化シリコン（ＳｉＯ_２）、窒化シリコン（ＳｉＮ）、ＳｉＯＮ、ＳＯＧ、ＮＳＧ、ＢＰＳＧ、ＰＳＧ、ＢＳＧあるいはＬＴＯを例示することができる。
【０２０３】
メモリセルの下方の半導体基板に絶縁層を介して形成された選択用トランジスタ（スイッチング用トランジスタ）や各種のトランジスタは、例えば、周知のＭＩＳ型ＦＥＴやＭＯＳ型ＦＥＴから構成することができる。ビット線を構成する材料として、不純物がドーピングされたポリシリコンや高融点金属材料を挙げることができる。共通の第１の電極と選択用トランジスタとの電気的な接続は、共通の第１の電極と選択用トランジスタとの間に形成された絶縁層に設けられた接続孔（コンタクトホール）を介して、あるいは又、かかる絶縁層に設けられた接続孔（コンタクトホール）及び絶縁層上に形成された配線層を介して行うことができる。尚、絶縁層を構成する材料として、酸化シリコン（ＳｉＯ_２）、窒化シリコン（ＳｉＮ）、ＳｉＯＮ、ＳＯＧ、ＮＳＧ、ＢＰＳＧ、ＰＳＧ、ＢＳＧあるいはＬＴＯを例示することができる。また、メモリセルを、例えば酸化アルミニウム（Ａｌ_２Ｏ_３）等から成る水素ガス不透過層で被覆してもよい。
【０２０４】
以上、本発明を、発明の実施の形態に基づき説明したが、本発明はこれらに限定されるものではない。発明の実施の形態にて説明したコンピュータ機器の構造や構成、不揮発性半導体メモリの構造、使用した材料、各種の形成条件、回路構成、駆動方法等は例示であり、適宜変更することができる。
【０２０５】
【発明の効果】
本発明の第１の態様、第２の態様あるいは第３の態様に係るコンピュータ機器においては、不揮発性半導体メモリを備えることによって、ハイバーネーション機能あるいはメモリスワップ機能が高速化され、コンピュータ機器の使い勝手が大幅に向上する。即ち、従来のシステムを大きく変更することなく、あたかも揮発性メインメモリが不揮発性であるが如くに高速にシステムを立ち上げ、立ち下げすることができる。更には、揮発性メインメモリの容量が増加したが如く、高速にメモリ領域をスワップすることができ、コンピュータ機器の使用の利便性を大幅に向上させることができる。
【０２０６】
尚、フラッシュメモリ等の不揮発性半導体メモリにあっては書込みにハードディスク記憶装置以上の長時間を要するものもあるが、不揮発性半導体メモリは衝撃性に強いため、ハイバーネーション機能の実行において電源切断時に書込み終了を待つ必要がなく、コンピュータ機器を速やかに移動させることができる。従って、読出し時間さえハードディスク記憶装置よりも高速であれば、コンピュータ機器の使用者にとっての利便性は向上する。
【０２０７】
また、本発明の第１の態様、第２の態様あるいは第３の態様に係るコンピュータ機器において、不揮発性半導体メモリをコンピュータ機器に内蔵するのではなく、外部のＩＣカード内に設置し、可搬性のある記憶メディアとして利用すれば、不揮発性半導体メモリを有効利用できる。即ち、コンピュータ機器の使用者は、システムの全体コストを増大させることなく、即ち、コンピュータ機器本体に余分な投資をすることなく、高速なハイバーネーション機能やメモリスワップ機能による利便性を享受することができる。更には、ハイバーネーション機能を外部ＩＣカードを用いて行えば、同一種類又は規格を統一したコンピュータ機器間であれば、作業状態を移植することも可能である。
【０２０８】
本発明の第４の態様に係るコンピュータ機器にあっては、コンピュータ機器の使用停止中（不使用中）、例えばＤＲＡＭから成る揮発性メインメモリの待機電流をゼロ、若しくは、最小限に留め、バッテリーの寿命を大幅に向上させることができる。更には、使用停止中（不使用中）、生成データを自動的に不揮発性半導体メモリにコピーするため、不使用の間にバッテリーが切れても生成データが失われることがなく、煩雑なバックアップ作業を必要としない。
【０２０９】
更には、本発明において、クロスポイント型不揮発性メモリユニットを不揮発性半導体メモリとして使用すれば、頻繁な書き換えに対する信頼性が保証されると共に、揮発性の半導体メモリに記憶された記憶内容の格納、退避、コピー、並びに、記憶内容の復帰を非常に高速に行うことができ、利便性は更に向上する。更には、このような構成にすれば、揮発性メインメモリをキャッシュメモリの如くに使用し、クロスポイント型不揮発性メモリユニットを恰もメインメモリの如くに使用することができる。
【図面の簡単な説明】
【図１】図１の（Ａ）及び（Ｂ）は、それぞれ、発明の実施の形態１及び発明の実施の形態２のコンピュータ機器の概念図である。
【図２】図２の（Ａ）及び（Ｂ）は、それぞれ、発明の実施の形態３及び発明の実施の形態４のコンピュータ機器の概念図である。
【図３】図３は、発明の実施の形態６のコンピュータ機器の概念図である。
【図４】図４は、クロスポイント型不揮発性メモリユニットを構成する強誘電体型不揮発性半導体メモリ群の等価回路図の一例を示す図である。
【図５】図５は、１つの強誘電体型不揮発性半導体メモリユニットの等価回路図の一例を示す図である。
【図６】図６は、ビット線に延びる方向に沿った強誘電体型不揮発性半導体メモリユニットの模式的な一部断面図である。
【図７】図７の（Ａ）及び（Ｂ）は、それぞれ、強誘電体型不揮発性半導体メモリユニットを構成するメモリセルへの書込み動作、及び、読出し／再書込み動作を説明するための動作波形を示す図である。
【図８】図８は、［クロスポイント型不揮発性メモリユニット−変形例１］における強誘電体型不揮発性半導体メモリ群の等価回路図である。
【図９】図９は、［クロスポイント型不揮発性メモリユニット−変形例１］における２つの強誘電体型不揮発性半導体メモリユニットの等価回路図である。
【図１０】図１０は、［クロスポイント型不揮発性メモリユニット−変形例２］における強誘電体型不揮発性半導体メモリ群の等価回路図である。
【図１１】図１１は、［クロスポイント型不揮発性メモリユニット−変形例２］における２つの強誘電体型不揮発性半導体メモリユニットの等価回路図である。
【図１２】図１２は、［クロスポイント型不揮発性メモリユニット−変形例３］における強誘電体型不揮発性半導体メモリユニットを切断したときの模式的な一部断面図である。
【図１３】図１３の（Ａ）及び（Ｂ）は、それぞれ、［クロスポイント型不揮発性メモリユニット−変形例３］における２つの強誘電体型不揮発性半導体メモリユニットの等価回路図である。
【図１４】図１４は、図１３の（Ａ）に示す概念的な等価回路図のより具体的な等価回路図である。
【図１５】図１５は、図１３の（Ｂ）に示す概念的な等価回路図のより具体的な等価回路図である。
【図１６】図１６は、［クロスポイント型不揮発性メモリユニット−変形例４］における強誘電体型不揮発性半導体メモリユニットを切断したときの模式的な一部断面図である。
【図１７】図１７の（Ａ）及び（Ｂ）は、それぞれ、［クロスポイント型不揮発性メモリユニット−変形例４］における２つの強誘電体型不揮発性半導体メモリユニットの等価回路図である。
【図１８】図１８は、図１７の（Ａ）に示す概念的な等価回路図のより具体的な等価回路図である。
【図１９】図１９は、図１７の（Ｂ）に示す概念的な等価回路図のより具体的な等価回路図である。
【図２０】図２０は、［クロスポイント型不揮発性メモリユニット−変形例５］における強誘電体型不揮発性半導体メモリユニットを切断したときの模式的な一部断面図である。
【図２１】図２１の（Ａ）及び（Ｂ）は、それぞれ、［クロスポイント型不揮発性メモリユニット−変形例５］における２つの強誘電体型不揮発性半導体メモリユニットの等価回路図である。
【図２２】図２２は、図２１の（Ａ）及び（Ｂ）に示す概念的な等価回路図のより具体的な等価回路図である。
【図２３】図２３は、［クロスポイント型不揮発性メモリユニット−変形例６］における強誘電体型不揮発性半導体メモリユニットを切断したときの模式的な一部断面図である。
【図２４】図２４は、図２３に示す［クロスポイント型不揮発性メモリユニット−変形例６］における１つの強誘電体型不揮発性半導体メモリユニットの等価回路図である。
【図２５】図２５は、［クロスポイント型不揮発性メモリユニット−変形例７］における強誘電体型不揮発性半導体メモリユニットを切断したときの模式的な一部断面図である。
【図２６】図２６は、［クロスポイント型不揮発性メモリユニット−変形例８］における強誘電体型不揮発性半導体メモリユニットの等価回路図である。
【図２７】図２７は、図２６に示した［クロスポイント型不揮発性メモリユニット−変形例８］における強誘電体型不揮発性半導体メモリユニットのレイアウト図である。
【図２８】図２８は、図２６に示した強誘電体型不揮発性半導体メモリユニットの模式的な一部断面図である。
【図２９】図２９は、図２６に示した強誘電体型不揮発性半導体メモリユニットの、図２８とは異なる断面で見たときの模式的な一部断面図である。
【図３０】図３０は、検出用トランジスタの一端が接続された配線の所定の電位を０ボルトとした場合の、ビット線間に配設された一種のスイッチ回路を示す等価回路図である。
【図３１】強誘電体のＰ−Ｅ（Ｖ）ヒステリシスループ図である。
【図３２】図３２の（Ａ）及び（Ｂ）は、それぞれ、従来のコンピュータの概念図、及び、従来のモバイル型コンピュータ等のシステム構成例の概念図である。
【符号の説明】
１，１０１・・・ＣＰＵ、２，１０２・・・揮発性システムメモリ、３・・・レジスタ群、４，４Ａ，４Ｂ，１０４，１０４Ａ，１０４Ｂ・・・揮発性メインメモリ、５・・・ＶＲＡＭ、６・・・ハードディスク記憶装置、７，１０７・・・不揮発性半導体メモリ、８・・・ＩＣカード、１０・・・シリコン半導体基板、１１・・・素子分離領域、１２・・・ゲート絶縁膜、１３・・・ゲート電極、１４Ａ，１４Ｂ・・・ソース／ドレイン領域、１５・・・コンタクトホール、１６・・・絶縁層、１７，２７・・・接続孔、２１，２１Ａ，２１Ｂ，２１’，３１，３１Ａ，３１Ｂ，３１’・・・第１の電極、２２，２２Ａ，２２Ｂ，３２，３２Ａ，３２Ｂ・・・強誘電体層、２３，２３’，３３，３３’・・・第２の電極、２５・・・パッド部、２６・・・層間絶縁層、３６Ａ・・・絶縁膜、ＴＲ・・・選択用トランジスタ、ＴＲ_Ｗ・・・書込用トランジスタ、ＴＲ_Ｒ・・・読出用トランジスタ、ＴＲ_Ｓ・・・検出用トランジスタ、ＷＬ・・・ワード線、ＢＬ・・・ビット線、ＰＬ・・・プレート線、ＷＤ・・・ワード線デコーダ／ドライバ、ＳＡ・・・センスアンプ、ＰＤ・・・プレート線デコーダ／ドライバ、ＣＮ・・・共通ノード[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a computer device including a volatile system memory and a nonvolatile semiconductor memory.
[0002]
[Prior art]
At present, various types of computers utilize storage and saving of a storage area of a volatile system memory using a hard disk storage device (HDD). Examples of the application include a hibernation (hibernation) function and a memory swap function. Can be mentioned.
[0003]
The hibernation function in the computer whose conceptual diagram is shown in FIG. 32A is a volatile main memory 204 composed of a DRAM, various registers 203 in a CPU 201, a VRAM 205, and the like (these are collectively referred to as a volatile system memory). 202) is stored in the hard disk storage device 206 based on the operation of the CPU 201 when the power is turned off. When the power is turned on again (when the power is restored), the contents stored in the hard disk storage device 206 are written back from the hard disk storage device 206 to the volatile system memory 202 based on the operation of the CPU 201.
[0004]
With such a hibernation function, information of the computer immediately before the power is turned off can be stored without consuming the standby power of the computer. In addition, when the power is turned on again (when the power is restored), initialization of various drivers and the like is not required, and simple data transfer is mainly performed. Therefore, the system can be started up faster than starting from the beginning. This hibernation function is becoming indispensable for notebook personal computers and the like that require battery backup.
[0005]
When the memory area requested by the system exceeds the capacity of the volatile main memory, the memory swap function saves part of the storage contents stored in the volatile main memory to the hard disk storage device, This function releases some memory areas. The stored contents saved in the hard disk storage device are written back to the volatile main memory as needed. This allows the computer to continue operating even when the system requests a memory area that exceeds the capacity of the mounted volatile main memory.
[0006]
In recent years, so-called mobile computers, mobile phones, and PDAs having a CPU and a volatile system memory have attracted attention. In addition, a mobile computer, a mobile phone, and a PDA may be collectively referred to as a mobile computer or the like hereinafter.
[0007]
A conceptual diagram of a system configuration example of a mobile computer or the like is shown in FIG. The volatile main memory 304 is composed of a volatile semiconductor memory such as a DRAM or an SRAM, and is connected to the CPU 301 in a known configuration. In addition, a nonvolatile semiconductor memory 307 including a flash memory is provided as a secondary storage unit.
[0008]
The operation system (OS) and various programs are usually stored (saved) in the nonvolatile semiconductor memory 307, and are downloaded from the nonvolatile semiconductor memory 307 to the volatile main memory 304 and initialized when the system is first started. Is done. Then, various programs are executed by the CPU 301. Data generated during execution of various programs in the CPU 301 is stored in an area secured in the volatile main memory 304.
[0009]
Conventionally, an inexpensive flash memory has been used as the nonvolatile semiconductor memory 307. However, the flash memory has limitations on the access unit and access speed at the time of writing and reading. Therefore, in the prior art, the volatile main memory 304 composed of DRAM or SRAM is used as a work area, and the nonvolatile semiconductor memory 307 is used for storing (storing) the operation system and various programs and for backing up user data and generated data. Roles are assigned by using.
[0010]
Usually, in such a mobile computer or the like, after the system is first started, the contents stored in the volatile main memory 304 are stored in the volatile main memory 304 even during power-off (standby). Saved as is. This is because the system does not need to be initialized when the power is turned on again, and the system is quickly started. It is also for maintaining the environment and various data just before the power is turned off (just before the standby state). In this case, the operation system, various programs, and various data downloaded from the nonvolatile semiconductor memory 307 to the volatile main memory 304 are stored in the volatile main memory 304 without being discarded. to continue. Therefore, the volatile main memory 304 needs to be energized at all times, and in particular, a DRAM performs a timely refresh operation to retain the stored contents.
[0011]
[Patent Document 1] JP-A-9-116107
[Patent Document 2] JP-A-2000-349248
[Patent Document 3] JP-A-2002-197857
[0012]
[Problems to be solved by the invention]
In the hibernation function and the memory swap function, since the access speed to the hard disk storage device 206 is much slower than that of the volatile system memory 202, the following problems occur.
[0013]
That is, in the hibernation function, when the power is turned off, the contents stored in the volatile system memory 202 are written to the hard disk storage device 206 that is vulnerable to impact, so that the computer cannot be freely moved for a while. Further, when the power is turned on again, the time until the stored contents are written back from the hard disk storage device 206 to the volatile system memory 202, that is, the power-on startup time is longer than when the operation system is started from the reset state. Is fast, but still requires several seconds to several tens of seconds, which is inconvenient.
[0014]
Further, in the memory swap function, as soon as the evacuation to the hard disk storage device 206 is started, the system performance is limited by the access speed to the hard disk storage device 206, and the processing performance is greatly reduced.
[0015]
As described above, the mobile computer or the like keeps storing various programs and various data in the volatile main memory 304 even when the power is turned off. However, for that purpose, it is necessary to always keep the volatile main memory 304 energized. Therefore, power consumption occurs even in an unused state (during standby). Accordingly, the following problem occurs.
[0016]
The first problem is that if a battery-backed mobile computer or the like is left unused for a long period of time, the battery runs out unknowingly and the contents stored in the volatile main memory 304 are lost. It is in. Therefore, the user must frequently back up the necessary storage contents of the volatile main memory 304 to the nonvolatile semiconductor memory 307. However, such an operation is a very complicated operation. Such a problem is not necessarily limited to the case where the volatile main memory 304 is constituted by a DRAM, but also occurs when the volatile main memory 304 is constituted by an SRAM which consumes less power during standby. That is, as long as the main memory 304 is volatile, it is necessary to energize it to retain the stored contents, and the above problem cannot be avoided.
[0017]
The second problem is an increase in power consumption. Generally, a mobile computer or the like has a longer non-use time. Therefore, the effect of power consumption during non-use on total power consumption is significant. This becomes remarkable especially when the volatile main memory 304 is configured by a DRAM. That is, in the DRAM, it is necessary to perform a refresh operation as needed in order to keep the stored contents. Since this refresh operation requires the same power consumption as that at the time of access, the total power consumption is very large.
[0018]
Therefore, an object of the present invention is to have resistance to an impact, and to shut down a system and / or various programs at the time of power-off, operation, stop of use, power-on or restart of use, It is an object of the present invention to provide a computer device capable of performing startup and the like at a high speed and minimizing power consumption during use suspension (standby).
[0019]
[Means for Solving the Problems]
A computer device according to a first aspect of the present invention for achieving the above object is at least a computer device including a CPU, a volatile system memory, and a nonvolatile semiconductor memory,
When the power is turned off, at least a part of the storage contents of the volatile system memory is stored in the nonvolatile semiconductor memory based on the operation of the CPU. When the power is turned on again, the data stored in the nonvolatile semiconductor memory is stored based on the operation of the CPU. The storage contents are written back to the volatile system memory.
[0020]
A computer device according to a second aspect of the present invention for achieving the above object is a computer device including at least a CPU, a volatile system memory, and a nonvolatile semiconductor memory,
At the time of operation, based on the operation of the CPU, a part of the storage contents of the volatile system memory is evacuated to the non-volatile semiconductor memory to release the area of the volatile system memory, and then the non-volatile semiconductor memory is operated based on the operation of the CPU. And writing the stored contents back to the volatile system memory.
[0021]
A computer device according to a third aspect of the present invention for achieving the above object is at least a computer device including a CPU, a volatile system memory, and a nonvolatile semiconductor memory,
At the time of operation, based on the operation of the CPU, a part of the storage contents of the volatile system memory is evacuated to the non-volatile semiconductor memory to release the area of the volatile system memory, and then the non-volatile semiconductor memory is operated based on the operation of the CPU. Write the stored contents back to the volatile system memory,
When the power is turned off, at least a part of the storage contents of the volatile system memory is stored in the nonvolatile semiconductor memory based on the operation of the CPU. When the power is turned on again, the data stored in the nonvolatile semiconductor memory is stored based on the operation of the CPU. The storage contents are written back to the volatile system memory.
[0022]
In the computer device according to the second or third aspect of the present invention, during operation, a part of the storage content of the volatile system memory is saved in the nonvolatile semiconductor memory based on the operation of the CPU. The save operation is performed when a memory area is requested from the volatile system memory and there is no free memory area in the volatile system memory. In addition, the storage contents saved in the nonvolatile semiconductor memory are written back to the volatile system memory based on the operation of the CPU. However, this write-back operation requires access to the storage contents saved in the nonvolatile semiconductor memory. Will be executed if
[0023]
A computer device according to a fourth aspect of the present invention for achieving the above object is a computer device including at least a CPU, a volatile system memory, and a nonvolatile semiconductor memory,
When the use is stopped, at least a part of the storage contents of the volatile system memory is copied to the nonvolatile semiconductor memory based on the operation of the CPU. When the use is resumed, the storage copied to the nonvolatile semiconductor memory is performed based on the operation of the CPU. The contents are written back to the volatile system memory.
[0024]
In the computer device according to the fourth aspect of the present invention, “when the use of the computer device is stopped” means, for example, when the power of the computer device is turned off, or when the user performs any operation on the computer device for a certain period of time. "When resuming use" means, for example, when the power of the computer device is turned on again, or when the user performs some operation on the computer device after stopping use. Means
[0025]
In the computer device according to the fourth aspect of the present invention, the volatile system memory comprises a DRAM, and at the time of use suspension, after copying at least a part of the storage contents of the volatile system memory to the nonvolatile semiconductor memory, From the viewpoint of further reducing the power consumption of the computer device, it is preferable to stop the refresh operation in the portion of the volatile system memory that has stored the memory content copied to the nonvolatile semiconductor memory. Note that such a configuration is referred to as a computer device according to the fourth embodiment of the present invention for convenience.
[0026]
A so-called desktop personal computer may be used as the computer device according to the first embodiment to the fourth embodiment or the fourth embodiment 4A (hereinafter, these may be collectively referred to as the computer device of the present invention). A notebook personal computer, a mobile personal computer, a PDA (personal digital assist), a mobile phone, and a game machine can be given. The volatile system memory in the computer device according to the first to fourth aspects of the present invention includes a volatile main memory including a DRAM and an SRAM, various registers in a CPU, a VRAM, and the like.
[0027]
In general, the configuration of the volatile main memory has various variations, such as providing a cache memory between the DRAM and the CPU, and allocating the function of the VRAM to a part of the volatile main memory. The volatile system memory in the device also includes these configurations. In addition, the storage contents of the volatile main memory can be easily reconstructed by calculation or the like, or can be discarded by writing back to the original volatile main memory such as a cache memory. There may be a possible part, a part that does not need to be saved or cannot be saved, and a part that does not need to be copied or cannot be copied. In such a case, in the computer device of the present invention, it is not always necessary to store, save, and copy the storage contents of the entire volatile system memory, and the storage, save, and copy may be the main parts.
[0028]
In the computer device of the present invention, the nonvolatile semiconductor memory may be installed inside the computer device or may be installed in a removable IC card. That is, it may have a structure in which a nonvolatile semiconductor memory is embedded in a plastic card. When the non-volatile semiconductor memory is installed in a removable IC card, the CPU and the volatile system memory are arranged in the computer device main body. The connection of the IC card to the main body of the computer device may employ a known method. As described above, if the nonvolatile semiconductor memory is installed in the removable IC card, the nonvolatile semiconductor memory can be effectively used. That is, the user of the computer device can enjoy, for example, a high-speed hibernation function and a memory swap function without any extra investment, and work between computer devices of the same type or standardized. The transplantation of the state can be easily performed. The specification of the IC card is not limited to the PCMCIA standard card, but may be any specification IC card.
[0029]
When the nonvolatile semiconductor memory is installed in a removable IC card, in the computer device according to the first aspect of the present invention, at least a part of the storage content of the volatile system memory is stored in the nonvolatile semiconductor memory. It is preferable that the nonvolatile semiconductor memory be configured to simultaneously store identification information for alternatively identifying a computer device. In the computer device according to the second aspect of the present invention, when a part of the storage content of the volatile system memory is saved in the nonvolatile semiconductor memory, the computer device is selected as the nonvolatile semiconductor memory. It is preferable that the identification information for identification is simultaneously stored. Further, in the computer device according to the third aspect of the present invention, when a part of the storage content of the volatile system memory is saved in the nonvolatile semiconductor memory, the computer device is selected as the nonvolatile semiconductor memory. It is preferable that identification information to be uniquely identified is simultaneously stored, and / or when at least a part of the storage content of the volatile system memory is stored in the nonvolatile semiconductor memory, It is preferable that identification information for alternatively identifying a computer device is stored at the same time. Further, in the computer device according to the fourth aspect or the fourth aspect of the present invention, when copying at least a part of the storage content of the volatile system memory to the nonvolatile semiconductor memory, the nonvolatile semiconductor memory includes It is preferable that identification information for alternatively identifying a computer device is stored at the same time.
[0030]
It is preferable that the identification information is also stored in a nonvolatile semiconductor memory separately built in the computer device. With such a configuration, when the IC card once removed from the computer device is attached to another computer device different from the computer device, the identification information becomes inconsistent, for example, a warning can be issued, and Misuse of the device can be prevented. The identification information may be any information, for example, a date and time when a bit string generated by a random number and the storage contents (at least a part) of the volatile system memory are stored, saved, and copied in the nonvolatile semiconductor memory. be able to.
[0031]
When storing, saving, and copying (at least a part of) the contents of the volatile system memory in the nonvolatile semiconductor memory, a file name is defined, stored, saved, and copied in the nonvolatile semiconductor memory. For example, it is preferable that the same file name as the file name stored, saved, or copied in the nonvolatile semiconductor memory is stored in the nonvolatile semiconductor memory separately incorporated in the nonvolatile semiconductor memory. This makes it easy to search the nonvolatile semiconductor memory for a file storing the stored content when the stored content saved, saved, or copied in the nonvolatile semiconductor memory is written back to the volatile system memory, and the file collation can be performed. You can do it too.
[0032]
In the computer device of the present invention including the above-described various embodiments, the nonvolatile semiconductor memory includes a flash memory or an MRAM (magnetic memory), one memory cell, and a selection transistor (switching transistor). A ferroelectric nonvolatile semiconductor memory, which can be composed of a ferroelectric nonvolatile semiconductor memory composed of a pair of memory cells and a pair of selection transistors, can be constituted by a ferroelectric nonvolatile semiconductor memory unit described below. (For convenience, referred to as a cross-point nonvolatile memory unit).
[0033]
That is, the nonvolatile semiconductor memory includes a group of ferroelectric nonvolatile semiconductor memories in which K cross-point nonvolatile memory units are aggregated,
Each cross-point nonvolatile memory unit is
(A) a bit line;
(B) a selection transistor;
(C) a sub-memory unit composed of M (where M ≧ 2) memory cells;
(D) M plate lines,
Consisting of
The sub memory unit is formed above the semiconductor substrate via an insulating layer,
Each memory cell includes a first electrode, a ferroelectric layer, and a second electrode,
In the sub memory unit, the first electrode of the memory cell is common, and the common first electrode is connected to the bit line via the selection transistor, and the m-th (where m = 1, 2) , M) are connected to the m-th plate line,
In the group of ferroelectric nonvolatile semiconductor memories, it is preferable that the m-th plate line is common.
[0034]
Note that it suffices to satisfy M ≧ 2, and examples of practical values of M include a power of 2 (2, 4, 8, 16,...).
[0035]
The cross-point nonvolatile memory unit can achieve high integration and can be manufactured at low cost because the selection transistor is shared by a plurality of memory cells. Further, instantaneous writing to an arbitrary sector and instantaneous reading from an arbitrary sector are possible without requiring an erasing operation, and a data transfer speed (data writing speed, reading speed) comparable to that of a DRAM can be obtained.
[0036]
In this case, it is preferable that the M × K memory cells constituting the ferroelectric nonvolatile semiconductor memory group be accessed collectively. That is, it is preferable to execute collective access in sector units in the computer device file system. Specifically, in the computer device according to the first aspect of the present invention, when storing at least a part of the storage content of the volatile system memory in the nonvolatile semiconductor memory, When writing back the stored contents to the volatile system memory, it is preferable that M × K memory cells constituting the group of ferroelectric nonvolatile semiconductor memories are collectively accessed. Further, in the computer device according to the second aspect of the present invention, when a part of the storage contents of the volatile system memory is saved in the nonvolatile semiconductor memory, and when the storage contents saved in the nonvolatile semiconductor memory are saved. Is written back to the volatile system memory, it is preferable that M × K memory cells constituting the ferroelectric nonvolatile semiconductor memory group be accessed collectively. Furthermore, in the computer device according to the third aspect of the present invention, when a part of the storage content of the volatile system memory is saved to the nonvolatile semiconductor memory, and when the saved content is saved to the nonvolatile semiconductor memory. When writing the contents back into the volatile system memory, when storing at least a part of the storage contents of the volatile system memory in the nonvolatile semiconductor memory, and when storing the storage contents stored in the nonvolatile semiconductor memory in the volatile system memory. When writing back to the memory, it is preferable that batch access is made to M × K memory cells constituting the ferroelectric nonvolatile semiconductor memory group. Also, in the computer device according to the fourth aspect or the fourth aspect of the present invention, when copying at least a part of the storage content of the volatile system memory to the nonvolatile semiconductor memory, When writing back the stored contents to the volatile system memory, it is preferable that batch access is made to the M × K memory cells constituting the ferroelectric nonvolatile semiconductor memory group. Furthermore, the value of M × K is 2⁹(512) bytes, 2¹⁰(1024) bytes, 2¹¹(2048) bytes, 2¹²(4096) bytes or 2^ThirteenIt is preferably a value corresponding to (8192) bytes. If necessary, a cross-point nonvolatile memory unit for error detection or error correction may be added to the ferroelectric nonvolatile semiconductor memory group.
[0037]
Alternatively, in this case, it is preferable that the group of ferroelectric nonvolatile semiconductor memories include at least two K-bit registers. Providing at least two K-bit registers in this manner makes it possible to execute data transfer to memory cells in parallel, and to speed up data transfer to memory cells. Data transfer from cells can be executed in parallel, and data transfer from memory cells can be speeded up.
[0038]
In the computer device according to the first to third aspects of the present invention, the provision of the nonvolatile semiconductor memory speeds up the hibernation function or the memory swap function, thereby greatly improving the usability of the computer device. Also, in the computer device according to the fourth aspect of the present invention, by providing the nonvolatile semiconductor memory, the standby current of the volatile main memory when the use of the computer device is stopped (when not in use) is reduced to zero, or In addition, the life of the battery can be greatly improved, and even if the battery runs out while the computer device is not used, no data or the like is lost, and a complicated backup operation is not required.
[0039]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be described based on embodiments of the present invention (hereinafter, abbreviated as embodiments) with reference to the drawings.
[0040]
(Embodiment 1)
The first embodiment relates to a computer device according to the first embodiment of the present invention, specifically, a notebook personal computer. FIG. 1A is a conceptual diagram of the computer device according to the first embodiment.
[0041]
The computer device according to the first embodiment includes at least a CPU 1, a volatile system memory 2, and a nonvolatile semiconductor memory 7. The volatile system memory 2 includes a group of various registers 3 in the CPU 1, a volatile main memory 4 including a DRAM, a VRAM 5, and the like. The CPU 1, the volatile main memory 4, the VRAM 5, and the nonvolatile semiconductor memory 7 are connected by a known bus line (not shown). In the first embodiment, the nonvolatile semiconductor memory 7 is built in a computer device. The state of the system is stored (saved) in the volatile system memory 2 when the computer device operates.
[0042]
When the power is turned off, at least a part of the storage contents of the volatile system memory 2 is stored in the nonvolatile semiconductor memory 7 based on the operation of the CPU 1, and when the power is turned on again, the nonvolatile semiconductor memory 7 is stored based on the operation of the CPU 1. Is written back to the volatile system memory 2. That is, the non-volatile semiconductor memory 7 realizes a hibernation (hibernation) function.
[0043]
When the operation system and / or various programs are started, the operation of the CPU 1 secures an independent memory area in the volatile system memory 2 for each of the operation system and various programs, and the hard disk storage device 6 or the nonvolatile semiconductor memory 7 The operating system and / or various programs are read from the CPU, and the operation system and / or various programs and work data are stored in a memory area secured in the volatile system memory 2.
[0044]
When the power is turned off, the storage program stored in the hard disk storage device 6 or the nonvolatile semiconductor memory 7 is started, transferred to the volatile main memory 4, and executed in response to the user's operation of turning off the power. The storage program is stored in a non-volatile semiconductor memory (not shown) separately built in the computer device, and the CPU 1 accesses the non-volatile semiconductor memory to execute the storage program. Good.
[0045]
In executing the storage program, specifically, the CPU 1 that has received the power-off command in response to the power-off operation first operates the volatile system memory that stores the storage contents to be stored in the nonvolatile semiconductor memory 7. It is confirmed whether or not the total capacity of No. 2 is a capacity that can be secured on the nonvolatile semiconductor memory 7. If it cannot be secured, the user is notified, and in some cases, the storage contents of the volatile system memory 2 to be stored in the nonvolatile semiconductor memory 7 are stored in the hard disk storage device 6. If it can be secured, at least a part of the storage contents of the volatile system memory 2 (may be all except the storage program) is stored (transferred) to the nonvolatile semiconductor memory 7. At this time, in order to save the capacity required for storage in the nonvolatile semiconductor memory 7, the code area of the operation system or the program may be excluded from the storage target. In this case, for example, the initial call source (the hard disk) It is desirable to store these operation systems and program file paths or file start addresses in the nonvolatile semiconductor memory 7 instead of the storage device 6 and the nonvolatile semiconductor memory 7. Here, the above-mentioned stored contents are stored (saved) in the nonvolatile semiconductor memory 7 under a predetermined file name, for example, as one or a plurality of “storage files”. The file name may be stored in a non-volatile semiconductor memory (not shown) separately built in the computer device. Thereafter, the power is turned off based on the operation of the CPU 1.
[0046]
Conventionally, such data storage has been performed in the hard disk storage device 6. However, since the data transfer speed is insufficient, it takes a considerable time before the power is actually turned off. Furthermore, since the hard disk storage device 6 is vulnerable to impact, there is a problem that the computer equipment cannot be moved during that time. In the first embodiment, by using the non-volatile semiconductor memory 7 that is strong against impact, the computer device can be moved immediately at least after the execution of the power-off command is started, and the usability of the computer device is improved.
[0047]
Further, in the hard disk storage device 6, when writing is distributed to discontinuous sectors as in a normal access, the seek time causes a significant decrease in access speed. Therefore, means for securing a storage area in a highly continuous block is often employed in advance. However, when such a means is employed, not only does the capacity of the hard disk storage device be squeezed, but also if the volatile main memory 4 is added to the computer device, it will not operate properly. On the other hand, some of the nonvolatile semiconductor memories 7 can quickly access discontinuous sectors. In this case, a storage area is reserved in the nonvolatile semiconductor memory 7 in advance. No need. Therefore, even if the configuration of the volatile main memory 4 in the computer device changes, it can be flexibly handled.
[0048]
On the other hand, when the power is turned on again, first, the recovery program stored in the hard disk storage device 6 or the nonvolatile semiconductor memory 7 is started, transferred to the volatile main memory 4 and executed based on the operation of the CPU 1. The return program is stored in a non-volatile semiconductor memory (not shown) separately built in the computer device, and the CPU 1 accesses the non-volatile semiconductor memory to execute the return program. Good.
[0049]
Specifically, in executing the return program, first, the CPU 1 accesses the nonvolatile semiconductor memory 7 and checks whether or not the “storage file” exists. If the “storage file” exists, various data stored in the “storage file” is written back to the volatile system memory 2. If the file name of the “storage file” is stored in the nonvolatile semiconductor memory separately built in the computer device, the storage contents stored in the “storage file” are stored in the volatile system memory 2. Before rewriting the file, the file name of the “storage file” in the nonvolatile semiconductor memory 7 is compared with the file name of the “storage file” stored in the nonvolatile semiconductor memory separately built in the computer device. May be. If the collation results do not match, it may be determined that the “storage file” does not exist. When the code area of the operating system or the program is excluded from the storage target at the time of storage, the hard disk storage device 6 or the nonvolatile semiconductor memory 7 reads the operating system from the hard disk storage device 6 or the non-volatile semiconductor memory 7 based on the file path or address stored instead of the code. And the code of the activated program is transferred to the volatile system memory 2 again. After that, the “storage file” stored in the nonvolatile semiconductor memory 7 may be deleted or may be left as it is. In the latter case, a new “storage file” is used when the storage program is executed. File may overwrite the old "storage file". If the “storage file” does not exist, the CPU 1 issues a warning to the user, and reboots the system from the initial state, for example.
[0050]
The read operation of most nonvolatile semiconductor memories such as a flash memory, a ferroelectric nonvolatile semiconductor memory (FeRAM), and an MRAM is performed purely by electrical connection of a logic circuit. Therefore, the operation (return operation) when the power of the system is turned on again when the nonvolatile semiconductor memory 7 is used is generally easier to operate at a higher speed than when the hard disk storage device 6 is used. Therefore, the computer device can be started up at a high speed.
[0051]
(Embodiment 2)
The second embodiment is a modification of the first embodiment. As shown in the conceptual diagram of FIG. 1B, a CPU 1 and a volatile system memory 2 are arranged in a computer device main body, and a non-volatile semiconductor The memory 7 is installed in a removable IC card 8. When storing at least a part of the storage content of the volatile system memory 2 in the nonvolatile semiconductor memory 7, the nonvolatile semiconductor memory 7 includes identification information (for example, a random number generated by a random number) for identifying a computer device. The bit string and the date and time when at least a part of the storage contents of the volatile system memory are stored in the nonvolatile semiconductor memory 7 are simultaneously stored in the “identification file” in the nonvolatile semiconductor memory 7.
[0052]
The storage in the “identification file” is performed by executing the storage program described in the first embodiment, specifically, the CPU 1 that receives the power-off command in response to the power-off operation, It is checked whether or not the total capacity of the volatile system memory 2 storing the storage contents to be stored in the nonvolatile semiconductor memory 7 is a capacity that can be secured on the nonvolatile semiconductor memory 7. Is stored in the “identification file” in the nonvolatile semiconductor memory 7, and at least a part of the storage contents of the volatile system memory 2 (or all except the storage program) may be stored in the nonvolatile semiconductor memory 7. It may be stored (transferred). At the same time, the identification information is stored as an “identification file” in a non-volatile semiconductor memory (not shown) separately provided in the computer device.
[0053]
On the other hand, as in Embodiment 1, when the power is turned on again, the return program is executed based on the operation of the CPU 1. Specifically, the CPU 1 first accesses the nonvolatile semiconductor memory 7 and Check if the "identification file" exists. If the "identification file" exists, the CPU 1 reads out the content and compares it with the identification information in the "identification file" stored in the non-volatile semiconductor memory separately provided in the computer device. If the collation results match, check for the existence of a “storage file”. If the “storage file” exists, various data stored in the “storage file” is written back to the volatile system memory 2. After that, the “storage file” stored in the nonvolatile semiconductor memory 7 may be deleted or may be left as it is. In the latter case, a new “storage file” is used when the storage program is executed. File may overwrite the old "storage file". If the “identification file” does not exist, or if the identification information does not match, the CPU 1 issues a warning to the user. If the “storage file” does not exist, for example, the system is rebooted from the initial state.
[0054]
In the second embodiment, an ordinary portable semiconductor storage medium can be used as the nonvolatile semiconductor memory. In recent years, such a portable semiconductor storage medium has been actively used as a mobile medium in place of a digital still camera file storage and a flexible disk. There is no burden and no increase in computer equipment costs.
[0055]
Further, by storing (transferring) the contents of the volatile system memory 2 in the IC card 8 as described above, it is possible to instantaneously transfer a work environment between a plurality of computer devices having the same specifications. For example, the work environment can be smoothly unified between the home and the office, such that one work can be continued without carrying the computer equipment.
[0056]
Further, an IC card storing the storage contents of a certain computer device may be connected to a computer device having different specifications. In such a case, it is expected that confusion will occur in the startup of the computer device. However, since the identification information of the storage source computer device is simultaneously stored in the IC card, it is possible to reliably prevent such confusion.
[0057]
(Embodiment 3)
Embodiment 3 relates to a computer device according to the second embodiment of the present invention, specifically, a notebook personal computer. FIG. 2A is a conceptual diagram of a computer device according to the third embodiment.
[0058]
The computer device according to the third embodiment includes at least a CPU 1, a volatile system memory 2, and a nonvolatile semiconductor memory 7 as in the first embodiment. As in the first embodiment, the volatile system memory 2 includes various register groups 3 in the CPU 1, a volatile main memory 4 including a DRAM, a VRAM 5, and the like. The CPU 1, the volatile main memory 4, the VRAM 5, and the nonvolatile semiconductor memory 7 are connected by a known bus line (not shown). In the third embodiment, the nonvolatile semiconductor memory 7 is built in a computer device. The state of the system is stored (saved) in the volatile system memory 2 when the computer device operates.
[0059]
At the time of operation, based on the operation of the CPU 1, a part of the storage contents of the volatile system memory 2 (more specifically, the storage contents of a partial area 4 </ b> B of the volatile main memory 4) is stored in the nonvolatile semiconductor memory 7. To save the area of the volatile system memory 2 (more specifically, a part of the area 4B of the volatile main memory 4), and then save the area to the nonvolatile semiconductor memory 7 based on the operation of the CPU 1. The stored contents are written back to the volatile system memory (more specifically, a part of the volatile main memory 4). That is, the nonvolatile semiconductor memory 7 realizes a memory swap function.
[0060]
When the operation system and / or various programs are started, the operation of the CPU 1 secures an independent memory area in the volatile system memory 2 for each of the operation system and various programs, and the hard disk storage device 6 or the nonvolatile semiconductor memory 7 The operating system and / or various programs are read from the CPU, and the operation system and / or various programs and work data are stored in a memory area secured in the volatile system memory 2.
[0061]
During operation, when the system requests a memory area from the volatile main memory 4 and there is no free memory area in the volatile main memory 4, the data is stored in the hard disk storage device 6 or the nonvolatile semiconductor memory 7. The evacuation program is started, transferred to the volatile main memory 4, and executed. The evacuation program is stored in a non-volatile semiconductor memory (not shown) separately built in the computer device, and the CPU 1 accesses the non-volatile semiconductor memory to execute the evacuation program. Good.
[0062]
In the following description, the contents of the running program and the like are stored in the area 4A of the volatile main memory 4, and the programs and the like to be saved are stored in the remaining area 4B of the volatile main memory 4. It is assumed that
[0063]
In executing the evacuation program, specifically, the CPU 1 firstly stores the volatile system memory 2 (more specifically, the volatile main memory 4) storing the storage contents to be saved in the nonvolatile semiconductor memory 7. It is confirmed whether or not the total capacity of the area 4B) is a capacity that can be secured on the nonvolatile semiconductor memory 7. If it cannot be secured, the user is notified, and in some cases, the storage contents of the volatile main memory 4 to be saved to the nonvolatile semiconductor memory 7 are saved to the hard disk storage device 6. If it can be secured, for example, the contents of the running program and the like are left in the area 4A of the volatile main memory 4, and the contents of other programs and the like stored in the area 4B of the volatile main memory 4 are stored. The data is saved (transferred) to the nonvolatile semiconductor memory 7. At this time, in order to save the capacity required for saving (transferring) to the nonvolatile semiconductor memory 7, the code part of the operation system or the program in the area 4B of the volatile main memory 4 is excluded from the saving (transferring) target. In this case, for example, instead of the initial call source (on the hard disk storage device 6 or the nonvolatile semiconductor memory 7), the operating system or the file path of the program or the head address of the file is replaced with the nonvolatile semiconductor memory. 7 is desirably stored. Here, the above-mentioned stored contents are saved (saved) in the nonvolatile semiconductor memory 7 under a predetermined file name, for example, as one or a plurality of “save files”. The file name may be stored in a non-volatile semiconductor memory (not shown) separately built in the computer device.
[0064]
After the evacuation is completed, the area of the volatile system memory 2 (more specifically, the area 4B of the volatile main memory 4) is released. For example, a memory area requested by the system is allocated to the area 4B of the volatile main memory 4 by the operation of the CPU 1, and a new program or the like is stored, for example.
[0065]
On the other hand, when the system requests access to the stored contents saved in the nonvolatile semiconductor memory 7, first, the recovery program stored in the hard disk storage device 6 or the nonvolatile semiconductor memory 7 is started based on the operation of the CPU 1. Then, it is transferred to the volatile main memory 4 and executed. The return program is stored in a non-volatile semiconductor memory (not shown) separately built in the computer device, and the CPU 1 accesses the non-volatile semiconductor memory to execute the return program. Good. Then, the restoration program is executed based on the operation of the CPU 1. Specifically, first, the non-volatile semiconductor memory 7 is accessed to check whether or not the “save file” exists. If the “save file” exists, the storage contents saved in the “save file” are written back to the volatile system memory 2. When the operation system or the code area of the program is excluded from the storage target at the time of evacuation, the operation system is read from the hard disk storage device 6 or the nonvolatile semiconductor memory 7 on the basis of the file path or address stored instead of the code. And the code of the activated program is transferred to the volatile system memory 2 again. At this time, if there is not enough free space in the volatile main memory 4, processing such as saving the contents stored in another memory area of the volatile main memory 4 not to be accessed to the nonvolatile semiconductor memory 7 is performed. . Thereafter, the “save file” stored in the nonvolatile semiconductor memory 7 may be deleted or may be left as it is. In the latter case, a new “save file” is executed when the save program is executed. File overwrites the old "save file". If the "evacuation file" does not exist, the CPU 1 issues a warning to the user and, for example, reboots the system from the initial state. If the file name of the “evacuation file” is stored in the non-volatile semiconductor memory separately built in the computer device, the storage contents stored in the “evacuation file” are stored in the volatile system memory 2. Before writing back to the computer, the file name of the “save file” in the nonvolatile semiconductor memory 7 is compared with the file name of the “save file” stored in the nonvolatile semiconductor memory separately built in the computer device. May be. If the collation results do not match, it may be determined that the “evacuation file” does not exist.
[0066]
As described above, the memory swap function is performed not on the basis of the hard disk storage device 6 but on the basis of the nonvolatile semiconductor memory 7, so that there is no time lag due to the seek to the hard disk storage device 6 and the save area is secured at high speed. , Necessary storage contents can be saved. Further, the nonvolatile semiconductor memory 7 can be read out faster than the hard disk storage device 6.
[0067]
(Embodiment 4)
The fourth embodiment is a modification of the third embodiment. As shown in a conceptual diagram of FIG. 2B, a CPU 1 and a volatile system memory 2 are arranged in a computer device main body, and a non-volatile semiconductor The memory 7 is installed in a removable IC card 8. Then, a part of the storage contents of the volatile system memory 2 (more specifically, the volatile main memory 4) (more specifically, the storage contents stored in a partial area 4B of the volatile main memory 4) ) Is saved in the nonvolatile semiconductor memory 7, the nonvolatile semiconductor memory 7 includes identification information (for example, a bit string generated by a random number or at least a storage content of the volatile system memory) for selectively identifying the computer device. The date and time when a part of the data is saved in the nonvolatile semiconductor memory 7) is simultaneously stored in the “identification file” in the nonvolatile semiconductor memory 7.
[0068]
Such storage in the “identification file” is performed by executing the save program described in the third embodiment. Specifically, the CPU 1 first stores the storage contents to be saved in the nonvolatile semiconductor memory 7. It is confirmed whether the total capacity of the volatile system memory 2 (more specifically, the area 4B of the volatile main memory 4) is a capacity that can be secured on the nonvolatile semiconductor memory 7, and if it can be secured. After storing the identification information in the “identification file” in the nonvolatile semiconductor memory 7, a part of the storage contents of the volatile system memory 2 may be saved (transferred) to the nonvolatile semiconductor memory 7. At the same time, the identification information is stored as a “save file” in a non-volatile semiconductor memory (not shown) separately provided in the computer device.
[0069]
On the other hand, as in the third embodiment, when the system requests access to the storage contents saved in the nonvolatile semiconductor memory 7, the return program is executed based on the operation of the CPU 1. Specifically, First, the CPU 1 accesses the nonvolatile semiconductor memory 7 and checks whether or not the “identification file” exists. When the “identification file” exists, the CPU 1 reads the content and compares it with the identification information in the “evacuation file” stored in the nonvolatile semiconductor memory separately provided in the computer device. If the collation results match, check whether there is a "save file". If the “save file” exists, the storage contents saved in the “save file” are written back to the volatile system memory 2. Thereafter, the “save file” stored in the nonvolatile semiconductor memory 7 may be deleted or may be left as it is. In the latter case, a new “save file” is executed when the save program is executed. File overwrites the old "save file". When there is no “evacuation file” or when the identification information does not match, the CPU 1 issues a warning to the user.
[0070]
An IC card in which the storage content of a certain computer device has been saved may be connected to a computer device having a different specification. In such a case, it is expected that the operation of the computer device will be confused. However, since the identification information of the storage source computer device is simultaneously stored in the IC card, it is possible to reliably prevent such confusion.
[0071]
In the fourth embodiment, a normal portable semiconductor storage medium can be used as the nonvolatile semiconductor memory as in the second embodiment.
[0072]
(Embodiment 5)
Embodiment 5 relates to a computer device according to the third aspect of the present invention, specifically, a notebook personal computer. The conceptual diagram of the computer device according to the fifth embodiment is the same as the conceptual diagram shown in FIG. 2A or FIG. 2B. The computer device of the fifth embodiment is a combination of the computer device of the first embodiment and the computer device of the third embodiment, or a combination of the computer device of the second embodiment and the computer device of the fourth embodiment. Alternatively, it is a combination of the computer device of the first embodiment and the computer device of the fourth embodiment, or a combination of the computer device of the second embodiment and the computer device of the third embodiment.
[0073]
That is, the computer device according to the fifth embodiment includes at least a CPU 1, a group of registers 3 in the CPU 1, a volatile main memory 4 including a DRAM, a volatile system memory 2 including a VRAM 5, and the like, and a nonvolatile semiconductor memory. 7 is provided. In the fifth embodiment, similarly to the first and third embodiments, the nonvolatile semiconductor memory 7 may be built in a computer device, or may be the same as in the second and fourth embodiments. Alternatively, the nonvolatile semiconductor memory 7 may be installed in a removable IC card 8.
[0074]
Then, during operation, based on the operation of the CPU 1, a part of the storage content of the volatile system memory 2 is evacuated to the non-volatile semiconductor memory 7 to open the area of the volatile system memory 2, and thereafter, based on the operation of the CPU 1. Then, the storage contents saved in the nonvolatile semiconductor memory 7 are written back to the volatile system memory 2. Note that this operation can be the same as the operation of the computer device described in the third embodiment or the fourth embodiment, and a detailed description thereof will be omitted.
[0075]
When the power is turned off, at least a part of the storage contents of the volatile system memory 2 is stored in the nonvolatile semiconductor memory 7 based on the operation of the CPU 1, and when the power is turned on again, the nonvolatile semiconductor memory 7 is stored based on the operation of the CPU 1. Is written back to the volatile system memory 2. Note that this operation can be the same as the operation of the computer device described in the first embodiment or the second embodiment, and a detailed description thereof will be omitted.
[0076]
(Embodiment 6)
Embodiment 6 relates to the computer apparatus according to the fourth aspect of the present invention, more specifically, the computer apparatus according to the fourth aspect of the present invention, specifically, to a mobile phone. FIG. 3 shows a conceptual diagram of a computer device according to the sixth embodiment.
[0077]
The computer device according to the sixth embodiment includes at least a CPU 101, a volatile system memory 102, and a nonvolatile semiconductor memory 107. More specifically, the volatile system memory 102 includes a volatile main memory 104 composed of, for example, a synchronous DRAM. The CPU 101, the volatile main memory 104, and the nonvolatile semiconductor memory 107 are connected by a known bus line (not shown). In the sixth embodiment, the nonvolatile semiconductor memory 107 is incorporated in a computer device, and the operation system and various programs are stored in the nonvolatile semiconductor memory 107 in advance. The state of the system is stored (saved) in the volatile system memory 102 when the computer device operates. In the volatile main memory 104, the refresh area of the volatile main memory 104 composed of the synchronous DRAM can be limited to the remaining area 104A other than the partial area 104B of the volatile main memory 104 by an external command. Functions are provided.
[0078]
At the time of suspension of use, based on the operation of the CPU 101, at least a part of the storage contents of the volatile system memory 102 (in the sixth embodiment, more specifically, stored in the area 104B of the volatile main memory 104). Is copied to the nonvolatile semiconductor memory 107, and when the use is resumed, based on the operation of the CPU 101, the stored content copied to the nonvolatile semiconductor memory 107 is stored in the volatile system memory 102 (in the sixth embodiment). More specifically, write back to the area 104B) of the volatile main memory 104.
[0079]
When the operation system and various programs are started, the operation of the CPU 1 secures an independent memory area in the volatile system memory 102 for each operation system and various programs. Is read out, and the operation system, various programs, and work data are stored in the memory area secured in the volatile system memory 102. More specifically, the operation system and various programs required even during the suspension of use are stored in the area 104A of the volatile main memory 104, and the remaining area 104B of the volatile main memory 104 is Unnecessary programs and data are stored therein. Specifically, as a program required even during the suspension of use, for example, a program that is started intermittently at the time of standby in a mobile phone can be cited.
[0080]
When the use of the computer device is stopped, specifically, when the power of the mobile phone is turned off, for example, the contents stored in the area 104B of the volatile main memory 104 are automatically stored in the nonvolatile memory based on the operation of the CPU 101. The data is copied to a free area of the semiconductor memory 107. Thereafter, the refresh operation in the area 104B of the volatile main memory 104 is stopped, and the contents stored in the area 104B of the volatile main memory 104 are discarded. In the area 104A of the volatile main memory 104, the refresh operation is continued even while the use is stopped.
[0081]
Since the current consumption required for the refresh operation is proportional to the size of the memory area to be refreshed, the current consumption can be significantly reduced as compared with the conventional computer equipment.
[0082]
At the time of resuming use, specifically, when the power of the mobile phone is turned on, for example, based on the operation of the CPU 101, the stored contents copied automatically to a predetermined area of the nonvolatile semiconductor memory 107 this time are The data is written back to the area 104B of the volatile main memory 104 and restored. Thus, the user of the computer device (specifically, the mobile phone) can acquire the same operation environment as before the power was turned off.
[0083]
In the sixth embodiment, even if the battery runs out during use stop (during use), the data is usually stored in the non-volatile semiconductor memory 107. It is possible to take out without. Therefore, there is no need to frequently back up data. If there is no program that needs to be operated during the suspension of use (during non-use), the contents stored in all areas of the volatile main memory 104 are copied to the nonvolatile semiconductor memory 107, and the volatile main memory 104 composed of DRAM is used. The refresh operation of the memory 104 may be completely stopped. Furthermore, in this case, the power supply itself to the volatile main memory 104 may be stopped.
[0084]
Such an effect of reducing power consumption is effective for all types of computer equipment, but is particularly effective for battery-backup type portable computer equipment. Further, even in the case of using an SRAM as the volatile main memory 104 in a battery backup type computer device, it is effective in improving the safety. That is, in a battery-backup type computer device, there is always a danger that the battery will run out during use stop (during non-use), so the security of the data is low as long as the main memory is volatile. If the data in the volatile main memory 104 is automatically copied (transferred and saved) to the nonvolatile semiconductor memory 107 while the use is stopped (not used), it is possible to reliably prevent the data from being lost due to the battery exhaustion. Can be.
[0085]
[Cross-point nonvolatile memory unit]
In the computer device of the present invention described in the first to sixth embodiments, a flash memory or MRAM, one memory cell and a selection transistor (switching transistor) are used as the nonvolatile semiconductor memories 7 and 107. And a ferroelectric non-volatile semiconductor memory composed of a pair of memory cells and a pair of selection transistors can be used, but a cross-point type non-volatile semiconductor memory described below can be used. It is preferable to employ a nonvolatile memory unit (hereinafter simply referred to as a nonvolatile memory unit).
[0086]
This non-volatile memory unit is inexpensive to manufacture and does not require an erasing operation, and can write to any sector instantaneously. In addition, instantaneous writing to an arbitrary sector and instantaneous reading from an arbitrary sector are possible. Since both reading and writing can obtain a transfer speed comparable to that of a DRAM, the system performance hardly deteriorates. Furthermore, since the selection transistor is shared by a plurality of sub-memory units, high integration can be achieved.
[0087]
FIG. 4 shows an example of an equivalent circuit diagram in the case where the nonvolatile semiconductor memory is constituted by a ferroelectric nonvolatile semiconductor memory group (hereinafter, referred to as a nonvolatile semiconductor memory group) in which K nonvolatile memory units are aggregated. And one nonvolatile memory unit MU_kFIG. 5 shows an example of an equivalent circuit diagram of FIG. FIG. 6 is a schematic partial cross-sectional view of the nonvolatile memory unit along the direction extending to the bit lines. This nonvolatile semiconductor memory has K (for example, K = 256) nonvolatile memory units MU._KConsists of a group of nonvolatile semiconductor memories.
[0088]
The structure of such a nonvolatile memory unit is disclosed in, for example, JP-A-9-116107 and JP-A-2000-349248.
[0089]
Then, each nonvolatile memory unit MU_k(Where k = 1, 2,..., K)
(A) Bit line BL_kWhen,
(B) Selection transistor TR_kWhen,
(C) M (where M ≧ 2) memory cells MC_kmMemory unit SMU composed of_kWhen,
(D) M plate lines PL_M,
Consists of
[0090]
Sub memory unit SMU_kIs formed above the semiconductor substrate 10 via an insulating layer 16.
[0091]
Then, each memory cell MC_km(M = 1, 2,..., M, M = 16 in the illustrated example) is formed by the first electrode (lower electrode) 21, the ferroelectric layer 22, and the second electrode (upper electrode) 23. Become. Also, the sub memory unit SMU_kMemory cell MC constituting_kmOf the sub-memory unit SMU_kAnd the common first electrode 21 (common node CN_k) May be referred to as the selection transistor TR._kThrough the bit line BL_kIt is connected to the. Specifically, the selection transistor TR_kOne of the source / drain regions 14A is connected to the bit line BL via a contact hole 15 provided in the insulating layer 16._kAnd the selection transistor TR_kThe other source / drain region 14B is connected to the sub memory unit SMU via a connection hole 17 provided in an opening provided in the insulating layer 16._kOf the common first electrode 21 (common node CN_k)It is connected to the. Also, the sub memory unit SMU_kMemory cell MC constituting_kmOf the second electrode 23 is a plate line PL_mIt is connected to the. Further, in the nonvolatile semiconductor memory group, the m-th plate line PL_kAre common. In FIG. 6, the selection transistor TR_kAnd memory cell MC_kmAnd the bit line BL_kSelect transistor TR 'adjacent in the direction in which_kAnd the memory cell MC '_kmAre also illustrated.
[0092]
Memory cell MC_kmPlate line PL at_mAre connected to a plate line decoder / driver PD. Further, the selection transistor TR_kAre connected to a word line WL, and the word line WL is connected to a word line decoder / driver WD. Also, the bit line BL_kIs the sense amplifier SA_kIt is connected to the. Sense amplifier SA_kIs composed of, for example, a latch circuit.
[0093]
This memory cell is a high-speed rewritable non-volatile memory that uses a high-speed polarization inversion of a ferroelectric thin film and its residual polarization to detect a change in the amount of charge stored in a ferroelectric layer. Writing and reading of data in this memory cell are performed by applying a ferroelectric PE (V) hysteresis loop shown in FIG. That is, when the external electric field is removed after the external electric field is applied to the ferroelectric layer, the ferroelectric layer exhibits remanent polarization. The remanent polarization of the ferroelectric layer becomes + P when an external electric field in the positive direction is applied._r, When an external electric field in the negative direction is applied, -P_rBecomes Here, the remanent polarization is + P_r(See “D” in FIG. 31) is “0” and the remanent polarization is −P_r(See “A” in FIG. 31) is “1”.
[0094]
To determine the state of “1” or “0”, for example, an external positive electric field is applied to the ferroelectric layer. As a result, the polarization of the ferroelectric layer is in the state of “C” in FIG. At this time, if the data is “0”, the polarization state of the ferroelectric layer changes from “D” to “C”. On the other hand, if the data is “1”, the polarization state of the ferroelectric layer changes from “A” to “C” via “B”. When the data is "0", no polarization inversion of the ferroelectric layer occurs. On the other hand, when the data is “1”, polarization inversion occurs in the ferroelectric layer. As a result, a difference occurs in the amount of charge stored in the memory cell. By turning on the selection transistor of the selected memory cell, this accumulated charge is detected as a signal current. If the external electric field is set to 0 after reading the data, the polarization state of the ferroelectric layer becomes the state of "D" in FIG. 31 regardless of whether the data is "0" or "1". That is, at the time of reading, data "1" is temporarily destroyed. Therefore, when the data is “1”, an external electric field in the negative direction is applied to change the state to “A” along the paths “D” and “E”, and the data “1” is written again.
[0095]
The nonvolatile semiconductor memory group includes a two-stage K-bit register (256-bit register) RS₁, RS₂Is provided. Each sense amplifier SA_kIs the second-stage K-bit register RS₂Is connected to the second-stage K-bit register RS by a 32-bit bus line.₂Is the first-stage K-bit register RS₁And the first-stage K-bit register RS₁Are connected to an I / O circuit (not shown). The I / O circuit has, for example, an 8-bit configuration.
[0096]
In writing data to a memory cell, the first-stage K-bit register RS₁After sending 256 bits of data in 32 cycles to the first stage, the first-stage K-bit register RS₁In the second-stage K-bit register RS₂Transfer to
[0097]
First-stage K-bit register RS from I / O circuit₁The following operation is performed while new 256-bit data is sent in 32 cycles during the period. That is, the second-stage K-bit register RS₂1 bit data from each sense amplifier SA_kIs forwarded to Transfer of a total of 256 bits of data is completed in eight cycles. In the remaining cycle (32-8 = 24 cycles), the memory cell MC_k1Write data in batches.
[0098]
By repeating such an operation 16 times, the memory cell MC_k1, MC_k2, MC_k3...., MC_{k, M-1}, MC_{k, M}Writing of data to is completed. In this manner, M × K (= 16 × 256 = 4096) memory cells constituting the nonvolatile semiconductor memory group are collectively accessed. It should be noted that the value of M × K is a value corresponding to batch access in sector units in the file system.⁹(512) A value corresponding to a byte.
[0099]
Hereinafter, a method of writing data to each memory cell will be described. Incidentally, as an example, the memory cell MC_kmIt is assumed that data is written to FIG. 7A shows an operation waveform. In FIG. 7A, the numbers in parentheses correspond to the numbers of the steps described below.
[0100]
(1) In the standby state, word lines, all plate lines, bit lines BL_kIs 0 volt. Also, the sense amplifier SA_kContains the data to be written (high potential V_ccAlternatively, it is assumed that low potential = 0 volt) is held. Where V_ccIs the power supply voltage.
[0101]
(2) At the start of data writing, bit line BL_kIs the sense amplifier SA_kConnect to. Memory cell MC_kmBit line BL depending on the data to be written to_kIs V_ccOr it becomes 0 volt.
[0102]
(3) Next, by setting the word line WL to high level, the selection transistor TR_kIs turned on. In addition, select plate line PL_mHigh potential V_ccIs applied to the unselected plate line PL_j(J ≠ m) has an intermediate potential V_PL[= (1/2) V_cc] Is applied. Thereby, the bit line BL_kIs low potential (0 volt), memory cell MC_km, The selection plate line PL_mIs high potential V_ccAnd data "0" is written. On the other hand, the bit line BL_kIs high potential V_cc, The memory cell MC_kmNo data is written to.
[0103]
(4) Then, select plate line PL_mAt a low potential (0 volt). Thereby, the bit line BL_kIs low potential (0 volt), memory cell MC_kmDoes not change the data. On the other hand, the bit line BL_kIs high potential V_cc, The memory cell MC_kmIs written with data "1".
[0104]
(5) When the data reading is completed, the word line WL is set to the low level to set the selection transistor TR._kIs turned off, the bit line BL_kTo 0 volts, and the unselected plate line PL_jTo 0 volts.
[0105]
In reading data from a memory cell, each memory cell MC_k1Data read from the memory at once. Then, each sense amplifier SA_k1-bit data is stored in the second-stage K-bit register RS₂Is forwarded to Transfer of a total of 256 bits of data is completed in eight cycles.
[0106]
During the above cycle, the first-stage K-bit register RS₁The 256-bit data is sent to the I / O circuit in 32 cycles from.
[0107]
Then, collectively, the second-stage K-bit register RS₂Are stored in the first-stage K-bit register RS₁Transfer to
[0108]
By repeating such an operation 16 times, the memory cell MC_k1, MC_k2, MC_k3...., MC_{k, M-1}, MC_{k, M}Is completed. In this manner, M × K (= 16 × 256 = 4096) memory cells constituting the nonvolatile semiconductor memory group are collectively accessed.
[0109]
Next, an example of a method of reading data from each memory cell and rewriting data in each memory cell will be described below. Incidentally, as an example, the memory cell MC_kmIt is assumed that data is read from. FIG. 7B shows an operation waveform. In FIG. 7B, the numbers in parentheses correspond to the numbers of the steps described below.
[0110]
(11) In the standby state, all bit lines, all word lines, and all plate lines are grounded. Then, a ground line (not shown) and a bit line BL_kElectrical connection with the bit line BL_kTo a floating state.
[0111]
(12) At the start of data reading, the word line WL is set to the high level, thereby selecting the transistor for selection TR._kIs turned on. In addition, select plate line PL_mHigh potential V_ccIs applied. In addition, unselected plate lines PL_jTo a floating state. Thereby, the memory cell MC_kmDepends on the stored data of the bit line BL._k, A high potential or a low potential appears. Next, the sense amplifier SA_kTo activate the bit line BL_kIs read as data.
[0112]
(13) After that, by setting the word line WL to low level, the selection transistor TR_kIs turned off. In addition, select plate line PL_mTo 0 volts. At the same time, the bit line BL_kIs the sense amplifier SA_kTo charge and discharge the bit line BL_kV depends on the data_ccAlternatively, 0 volt is applied.
[0113]
(14) After that, by executing the above (3) to (5), the memory cell MC_kmIs written again.
[0114]
As described above, the provision of the two-stage K-bit register makes it possible to take in data from the outside and write data to the memory cell, or read data from the memory cell and send data to the outside in parallel. And run it.
[0115]
Further, by adopting the method of reading and rewriting data from the memory cells described above, that is, by matching the array block (nonvolatile semiconductor memory group) of the nonvolatile memory unit with the file sector serving as an access unit, The upper limit of disturbance can be specified without being aware from the outside, and data destruction can be prevented. Note that this method can be applied not only to the operation of the computer device described in the first to sixth embodiments, but also to data writing to memory cells in a nonvolatile semiconductor memory group forming a general file storage. Alternatively, the present invention can be applied to reading and rewriting from a memory cell. Here, disturb refers to a phenomenon in which an electric field is applied to a ferroelectric layer of a non-selected memory cell in a direction in which polarization is inverted, that is, in a direction in which stored data is deteriorated or destroyed. .
[0116]
Further, in the above description, the nonvolatile semiconductor memory group is configured by 16 × 256 = 4096 memory cells, but the I / O circuit may be configured to have a 9-bit (8 + 1) configuration, for example. Here, the added one bit is used for error detection or error correction. In such a case, K = 9 × 32 = 288. Also, the K-bit register RS₁, RS₂Use a 288-bit register.
[0117]
Further, the nonvolatile semiconductor memory may be configured from a plurality of nonvolatile semiconductor memory groups, and plate lines of the same address (plate lines having the same value of m) may be simultaneously operated in the plurality of nonvolatile semiconductor memory groups. For example, in the above-described example, two nonvolatile semiconductor memory groups may be simultaneously driven with K = 128.
[0118]
Hereinafter, various modifications of the nonvolatile memory unit will be described.
[0119]
[Cross-point nonvolatile memory unit-Modification 1]
FIG. 8 shows an equivalent circuit diagram of a nonvolatile semiconductor memory group, and FIG. 9 shows an equivalent circuit diagram of two nonvolatile memory units. Two nonvolatile memory units are paired and connected to one sense amplifier. It can be configured. Then, complementary 1-bit data is stored in a pair of memory cells having a common plate line. In FIG. 9, only k = 1 and k are shown.
[0120]
Hereinafter, a data write operation in such a configuration will be described. Incidentally, as an example, the paired memory cells MC₁₁, MC₂₁Data to the memory cell MC.₁₁Data "1" to the memory cell MC.₂₁Data "0" is written in
[0121]
(21) In the standby state, the word lines and all plate lines are at 0 volt. Also, the bit line BL₁, BL₂Is equalized to 0 volts. Note that the sense amplifier SA₁Holds data to be written.
[0122]
(22) At the start of data writing, bit line BL₁To V_ccAnd the bit line BL₂0 volts.
(23) Next, by setting the word line WL to a high level, the selection transistor TR₁, TR₂Is turned on. In addition, select plate line PL₁High potential V_ccIs applied to the unselected plate line PL_j(J ≠ 1) has an intermediate potential V_PL[= (1/2) V_cc] Is applied. Thereby, the memory cell MC₂₁, The selection plate line PL₁Is high potential V_ccAnd the bit line BL₂Is 0 volt, data "0" is written.
(24) Then, select plate line PL₁To 0 volts. Thereby, the memory cell MC₁₁, The selection plate line PL₁Is 0 volt and the bit line BL₁Is V_ccTherefore, data "1" is written.
(25) When ending the data writing, the word line WL is set to the low level, and the selection transistor TR is set.₁, TR₂Is turned off, the bit line BL₁To 0 volts, and the unselected plate line PL_jTo 0 volts.
[0123]
Next, an example of a method for reading data from a memory cell and rewriting data will be described below. Incidentally, as an example, the paired memory cells MC₁₁, MC₂₁From the memory cell MC₁₁Has data "1" in memory cell MC.₂₁Is assumed to store data "0".
[0124]
(31) In the standby state, all bit lines, all word lines, and all plate lines are grounded. Then, a ground line (not shown) and a bit line BL₁, BL₂Electrical connection with the bit line BL₁, BL₂To a floating state.
[0125]
(32) At the start of data reading, the word line WL is set to the high level, thereby selecting the transistor for selection TR.₁, TR₂Is turned on. In addition, select plate line PL₁High potential V_ccIs applied. In addition, unselected plate lines PL_jTo a floating state. Thus, memory cell MC storing data "1"₁₁Releases an inverted charge from the bit line BL₁, BL₂, A potential difference occurs. Next, the sense amplifier SA₁To activate the bit line BL₁, BL₂Is read as data.
[0126]
(33) After that, by setting the word line WL to low level, the selection transistor TR₁, TR₂Is turned off. In addition, select plate line PL₁To 0 volts. At the same time, the bit line BL₁, BL₂With the sense amplifier SA₁To charge and discharge the bit line BL₁Has V_ccAnd the bit line BL₂Is applied with 0 volt.
[0127]
(34) Thereafter, by performing the step (23) described above, the memory cell MC₂₁Is written with data "0" again.
[0128]
(35) Next, by executing the above-described step (24), that is, by selecting the selected plate line PL₁To 0 volts, the memory cell MC₁₁Is rewritten with data "1".
[0129]
(36) When ending the data writing, the bit line BL₁, BL₂To 0 volts, and the unselected plate line PL_jTo 0 volts.
[0130]
[Cross-point nonvolatile memory unit-Modification 2]
FIG. 10 shows an equivalent circuit diagram of the nonvolatile semiconductor memory group (however, illustration of the plate line decoder / driver PD and word line decoder / driver WD is omitted). FIG. 11 shows an equivalent circuit diagram of two nonvolatile memory units. As shown, two non-volatile memory units are paired and connected to one sense amplifier, and two selection transistors constituting the paired non-volatile memory units are connected to different word lines and independently controlled. It can also be configured to be. Then, 1-bit data is stored in each of a pair of memory cells sharing a plate line. In FIG. 11, k = 1 and 2 are shown.
[0131]
The data write operation and the read / rewrite operation in such a configuration are performed except that the two select transistors constituting the paired nonvolatile memory units are independently controlled (that is, the write operation is not performed). Cycle and read / rewrite cycle are doubled), and can be substantially the same as the above (1) to (5) and (11) to (14). Omitted. In (12), at the start of data reading, for example, the word line WL₁Is set to a high level, the selection transistor TR₁Is turned on, and the word line WL₂Is set to the low level, the selection transistor TR₂Is turned off, and the bit line BL₂To the bit line BL by applying a reference potential (between a potential appearing on the bit line based on data "1" and a potential appearing on the bit line based on data "0") to the bit line BL.₁Can be read out more reliably.
[0132]
[Cross-point nonvolatile memory unit-Modification 3]
FIG. 12 is a schematic partial cross-sectional view when the nonvolatile memory unit is cut along a virtual vertical plane parallel to the direction in which the bit lines extend. Further, conceptual equivalent circuit diagrams of a pair (two) of non-volatile memory units are shown in FIGS. 13A and 13B, and more specific examples of the conceptual equivalent circuit diagram of FIG. FIG. 14 shows a typical equivalent circuit diagram, and FIG. 15 shows a more specific equivalent circuit diagram of the conceptual equivalent circuit diagram of FIG. 14 and 15 show two nonvolatile memory units MU.₁, MU₂(K = 1, 2), these nonvolatile memory units MU₁, MU₂Are the same, and hereinafter, the nonvolatile memory unit MU₁Will be described. 13 (A) and (B), FIGS. 17 (A) and (B), and FIGS. 21 (A) and (B), plate lines, plate line decoders / drivers, and word line decoders / drivers. Illustration of the driver and the sense amplifier is omitted.
[0133]
This nonvolatile memory unit MU₁Is
(A) Bit line BL₁When,
(B) Selection transistor TR₁When,
(C) Each of M memory cells MC (where M ≧ 2, M = 4 in the illustrated example)_1NM(Where N ≧ 2 and N = 2 in the example shown) composed of N sub memory units SMU_1NWhen,
(D) M × N plate wires,
Consists of
[0134]
Then, the N sub memory units SMU_1NAre stacked with an interlayer insulating layer 26 interposed therebetween. Each memory cell includes first electrodes 21 and 31, ferroelectric layers 22 and 32, and second electrodes 23 and 33. SMU_1NAt the memory cell MC_1NMAre common, and the common first electrode is connected to the selection transistor TR.₁Through the bit line BL₁It is connected to the. Specifically, the sub memory unit SMU₁₁At the memory cell MC_11MAre common to each other (the common first electrode is connected to a first common node CN).₁₁), A common first electrode 21 (first common node CN)₁₁) Is the selection transistor TR₁Through the bit line BL₁It is connected to the. Also, the sub memory unit SMU₁₂At the memory cell MC_12MAre common (the common first electrode is connected to a second common node CN).₁₂), Common first electrode 31 (second common node CN)₁₂) Is the selection transistor TR₁Through the bit line BL₁It is connected to the. Generally, the sub memory unit SMU of the n-th layer (where n = 1, 2,..., N)_1n, The m-th (where m = 1, 2,..., M) memory cell MC_{1 nm}Are connected to the [(n-1) M + m] -th plate line PL_{(N-1) M + m}It is connected to the. In addition, this plate line PL_{(N-1) M + m}Is a nonvolatile memory unit MU₂Are also connected to the second electrodes 23 and 33 of each memory cell. More specifically, each plate line extends from the second electrode 23, 33, and these plate lines are connected in a region (not shown).
[0135]
Selection transistor TR₁One source / drain region 14A is connected to the bit line BL.₁And the selection transistor TR₁The other source / drain region 14B is connected to the first-layer sub-memory unit SMU through the first-layer connection hole 17 provided in the insulating layer 16.₁₁In the first common electrode 21 (first common node CN₁₁)It is connected to the. Further, the selection transistor TR₁The other source / drain region 14 </ b> B is formed via a first-layer connection hole 17 provided in the insulating layer 16 and a second-layer connection hole 27 provided in the interlayer insulating layer 26. The sub memory unit SMU of the layer₁₂Of the common first electrode 31 (the second common node CN₁₂)It is connected to the. In FIG. 12, reference numeral 36A denotes an insulating film.
[0136]
Bit line BL₁Are connected to the sense amplifier SA. The plate line PL_{(N-1) M + m}Are connected to a plate line decoder / driver PD. Further, the word line WL (or the word line WL₁, WL₂) Is connected to the word line decoder / driver WD. The word line WL extends in the direction perpendicular to the plane of FIG. In addition, the nonvolatile memory unit MU₁Memory cell MC constituting_11mOf the nonvolatile memory unit MU adjacent in the direction perpendicular to the paper surface of FIG.₂Memory cell MC constituting_21mAnd the plate line PL_{(N-1) M + m}Also serves as. Further, the nonvolatile memory unit MU₁Memory cell MC constituting_12mOf the nonvolatile memory unit MU adjacent in the direction perpendicular to the paper surface of FIG.₂Memory cell MC constituting_22mAnd the plate line PL_{(N-1) M + m}Also serves as. The word line WL is connected to the non-volatile memory unit MU.₁Selection transistor TR that constitutes₁And the nonvolatile memory units MU adjacent to each other in the direction perpendicular to the paper surface of FIG.₂Selection transistor TR that constitutes₂And is common to
[0137]
Nonvolatile memory unit MU whose equivalent circuit diagrams are shown in FIGS.₁, MU₂, The nonvolatile memory unit MU₁, MU₂Selection transistor TR that constitutes₁, TR₂Are connected to the same word line WL. Then, the paired memory cells MC_{1 nm}, MC_{2 nm}(N = 1, 2,..., N, and m = 1, 2,..., M) store complementary data. For example, the memory cell MC_{1 nm}, MC_{2 nm}(Where m is one of 1, 2, 3, and 4), the word line WL is selected and the plate line PL is read._j(M ≠ j) is, for example, (１ ／) V_ccWith the voltage applied to the plate line PL_{(N-1) M + m}Drive. Where V_ccIs, for example, a power supply voltage. As a result, the complementary data is transferred to the paired memory cells MC._{1 nm}, MC_{2 nm}To select transistor TR₁, TR₂Bit line BL paired through₁, BL₂Appear as a voltage (bit line potential). Then, the paired bit lines BL₁, BL₂(Bit line potential) is detected by the sense amplifier SA. The nonvolatile memory unit MU₁, MU₂Selection transistor TR that constitutes₁, TR₂To different word lines WL₁, WL₂To the memory cell MC_{1 nm}, MC_{2 nm}Are independently controlled to form a pair of bit lines BL₁, BL₂Of the memory cell MC by applying a reference potential to one of_{1 nm}, MC_{2 nm}Data can be read from each of them. See FIG. 13B and FIG. 15 for an equivalent circuit diagram in the case of employing such a configuration. The selection transistor TR₁, TR₂, Are equivalent to the circuits shown in FIG. 13A and FIG. Thus, each memory cell MC_{1 nm}, MC_{2 nm}(N = 1, 2, and m = 1, 2, 3, 4), one bit is stored as data (see FIG. 13B and FIG. 15), or a pair of memories. Cell MC_{1 nm}, MC_{2 nm}Is stored as one bit (see FIG. 13A and FIG. 14). In an actual nonvolatile semiconductor memory, a set of nonvolatile memory units for storing 16 bits or 8 bits is arranged in an array as an access unit. Note that the value of M is not limited to 4. The value of M only needs to satisfy M ≧ 2, and a practical value of M can be, for example, a power of 2 (2, 4, 8, 16,...). The value of N only needs to satisfy N ≧ 2, and a practical value of N may be, for example, a power of 2 (2, 4, 8,...).
[0138]
Hereinafter, an outline of a method for manufacturing the nonvolatile semiconductor memory will be described. Note that other non-volatile semiconductor memories can be manufactured in substantially the same steps.
[0139]
[Step-100]
First, a MOS transistor functioning as a transistor constituting a selection transistor in a nonvolatile memory unit is formed on a semiconductor substrate 10. For that purpose, for example, the element isolation region 11 having a LOCOS structure is formed based on a known method. Note that the element isolation region may have a trench structure or a combination of a LOCOS structure and a trench structure. After that, the surface of the semiconductor substrate 10 is oxidized by, for example, a pyrogenic method to form the gate insulating film 12. Next, after a polysilicon layer doped with impurities is formed on the entire surface by a CVD method, the polysilicon layer is patterned to form a gate electrode 13. This gate electrode 13 also serves as a word line. Incidentally, instead of forming the gate electrode 13 from the polysilicon layer, the gate electrode 13 may be formed from polycide or metal silicide. Next, ions are implanted into the semiconductor substrate 10 to form an LDD structure. Thereafter, the entire surface is formed by SiO₂After forming the layer, the SiO₂A gate sidewall (not shown) is formed on the side surface of the gate electrode 13 by etching back the layer. Next, after ion implantation is performed on the semiconductor substrate 10, the source / drain regions 14A and 14B are formed by performing activation annealing treatment of the ion-implanted impurities.
[0140]
[Step-110]
Then, SiO₂Is formed by CVD, and an opening is formed by RIE in the lower insulating layer above one of the source / drain regions 14A. Then, a polysilicon layer doped with impurities is formed on the lower insulating layer including the inside of the opening by a CVD method. Thus, a contact hole 15 is formed. Next, by patterning the polysilicon layer on the lower insulating layer, the bit line BL₁To form Thereafter, an upper insulating layer made of BPSG is formed on the entire surface by a CVD method. After the formation of the upper insulating layer made of BPSG, it is preferable to reflow the upper insulating layer in a nitrogen gas atmosphere, for example, at 900 ° C. for 20 minutes. Further, if necessary, it is desirable to planarize the upper insulating layer by chemically and mechanically polishing the top surface of the upper insulating layer by, for example, a chemical mechanical polishing method (CMP method). Note that the lower insulating layer and the upper insulating layer are collectively referred to as an insulating layer 16.
[0141]
[Step-120]
Next, after an opening is formed in the insulating layer 16 above the other source / drain region 14B by RIE, the inside of the opening is filled with impurity-doped polysilicon, and a contact hole (contact hole) 17 is formed. Finalize. Bit line BL₁Extends over the lower insulating layer in the left-right direction of the drawing so as not to contact the connection hole 17.
[0142]
The connection hole 17 is formed in an opening formed in the insulating layer 16 by, for example, tungsten, Ti, Pt, Pd, Cu, TiW, TiNW, or WSi.₂, MoSi₂It can also be formed by embedding a metal wiring material made of a metal having a high melting point or a metal silicide. It is preferable that the top surface of the connection hole 17 exists on substantially the same plane as the surface of the insulating layer 16. Table 1 shows the conditions for filling the opening with tungsten and forming the connection hole 17. It is preferable that a Ti layer and a TiN layer are sequentially formed on the insulating layer 16 including the inside of the opening by, for example, magnetron sputtering before filling the opening with tungsten. Here, the reason for forming the Ti layer and the TiN layer is to obtain an ohmic low contact resistance, to prevent the semiconductor substrate 10 from being damaged by the blanket tungsten CVD method, and to improve the adhesion of tungsten.
[0143]
[Table 1]
[Sputtering conditions for Ti layer (thickness: 20 nm)]
Process gas: Ar = 35 sccm
Pressure: 0.52Pa
RF power: 2kW
Substrate heating: None
[Sputtering conditions for TiN layer (thickness: 100 nm)]
Process gas: N₂/ Ar = 100 / 35sccm
Pressure: 1.0Pa
RF power: 6kW
Substrate heating: None
[Tungsten CVD forming conditions]
Gas used: WF₆/ H₂/ Ar = 40/400 / 2250sccm
Pressure: 10.7kPa
Forming temperature: 450 ° C
[Etching conditions for tungsten layer, TiN layer and Ti layer]
First stage etching: Tungsten layer etching
Gas used: SF₆/ Ar / He = 110: 90: 5 sccm
Pressure: 46Pa
RF power: 275W
Second stage etching: TiN layer / Ti layer etching
Gas used: Ar / Cl₂= 75 / 5sccm
Pressure: 6.5 Pa
RF power: 250W
[0144]
[Step-130]
Next, it is desirable to form an adhesion layer (not shown) made of titanium nitride (TiN) on the insulating layer 16. Then, a first conductive material layer constituting a first electrode (lower electrode) 21 made of Ir is formed on the adhesion layer by, for example, a sputtering method, and the first conductive material layer and the adhesion layer are formed by photolithography. By patterning based on the dry etching technique, the stripe-shaped first electrode 21 can be obtained. After that, the entire surface is made of SiO₂Film or SiO₂/ TiO₂A film (not shown) is formed, and the film is planarized by the CMP method, so that a state (a so-called damascene structure) in which the space between the first electrodes 21 is buried with the film can be obtained. In the CMP method, a slurry containing alumina may be used as an abrasive.
[0145]
Note that, for example, a SiN film is formed on the insulating layer 16, and then the SiN film in a portion where the first electrode is to be formed is selectively removed. The first electrode having a so-called damascene structure can also be formed by forming one conductive material layer and then removing the first conductive material layer and the adhesion layer on the SiN film by the CMP method.
[0146]
[Step-140]
After that, a ferroelectric thin film is formed on the entire surface, and then, if necessary, the ferroelectric thin film is patterned to form a ferroelectric layer 22.
[0147]
[Step-150]
Next, after an Ir layer is formed on the entire surface by a sputtering method, the Ir layer is patterned based on a photolithography technique and a dry etching technique to form a second electrode 23 on the ferroelectric layer 22. A plate line PL extending from the second electrode 23 is formed. When the ferroelectric layer 22 is damaged by the etching, the damage recovery annealing may be performed at a temperature required for the damage recovery.
[0148]
[Step-160]
afterwards,
-Formation and planarization of interlayer insulating layer 26
.Formation of opening and formation of connection hole 27
-For example, formation of the first electrode 31 having a damascene structure
.Formation of ferroelectric layer 32
.Formation of the second electrode 33
-Formation of insulating film 36A
Are sequentially performed.
[0149]
Note that each of the second electrodes 23 and 33 does not have to double as a plate line. In this case, for example, after an upper insulating layer is formed on the insulating layer 16 and the ferroelectric layer 22, a plate line is formed on the upper insulating layer. May be connected by a connection hole (via hole) provided in the upper insulating layer.
[0150]
For example, Bi₂SrTa₂O₉Table 2 below shows the conditions for forming the ferroelectric thin film composed of: In Table 2, "thd" is an abbreviation for tetramethylheptanedionate. Further, the source materials shown in Table 2 are dissolved in a solvent containing tetrahydrofuran (THF) as a main component.
[0151]

[0152]
Alternatively, Bi₂SrTa₂O₉Can be formed on the entire surface by a pulsed laser ablation method, a sol-gel method, or an RF sputtering method. The forming conditions in these cases are illustrated in Tables 3, 4, and 5 below. When a thick ferroelectric thin film is formed by the sol-gel method, spin coating and drying, or spin coating and firing (or annealing) may be repeated a desired number of times.
[0153]
[Table 3]
[Formation by pulsed laser ablation method]
Target: Bi₂SrTa₂O₉
Laser used: KrF excimer laser (wavelength 248 nm, pulse width 25 ns, 5 Hz)
Forming temperature: 400-800 ° C
Oxygen concentration: 3Pa
[0154]

[0155]
[Table 5]
[Formation by RF sputtering method]
Target: Bi₂SrTa₂O₉Ceramic target
RF power: 1.2 W to 2.0 W / target 1 cm²
Atmospheric pressure: 0.2 to 1.3 Pa
Forming temperature: room temperature to 600 ° C
Process gas: Ar / O₂Flow ratio = 2/1 to 9/1
[0156]
Table 6 shows the conditions for forming PZT or PLZT by magnetron sputtering when the ferroelectric layer is made of PZT or PLZT. Alternatively, PZT or PLZT is prepared by reactive sputtering, electron beam evaporation, sol-gel method (see the conditions in Table 7), MOCVD method (see the conditions in Table 8), pulse laser ablation method (see Table 9). (See conditions).
[0157]
[Table 6]
[Magnetron sputtering method]
Target: PZT or PLZT
Process gas: Ar / O₂= 90% by volume / 10% by volume
Pressure: 4Pa
Power: 50W
Forming temperature: 500 ° C
[0158]

[0159]

[0160]
[Table 9]
[Pulse laser ablation method]
Target: PZT or PLZT
Laser used: KrF excimer laser (wavelength 248 nm, pulse width 25 ns, 3 Hz)
Output energy: 400 mJ (1.1 J / cm²)
Forming temperature: 550-600 ° C
Oxygen concentration: 40 to 120 Pa
[0161]
[Cross-point nonvolatile memory unit-Modification 4]
FIG. 16 is a schematic partial cross-sectional view when the nonvolatile memory unit is cut along a virtual vertical plane parallel to the direction in which the bit lines extend. Further, conceptual equivalent circuit diagrams of the nonvolatile memory unit in this nonvolatile semiconductor memory are shown in FIGS. 17A and 17B, and more specific examples of the conceptual equivalent circuit diagram of FIG. FIG. 18 shows a typical equivalent circuit diagram, and FIG. 19 shows a more specific equivalent circuit diagram of the conceptual equivalent circuit diagram of FIG. 18 and 19 show two nonvolatile memory units MU.₁, MU₂Are shown, these non-volatile memory units MU₁, MU₂Are the same, and hereinafter, the nonvolatile memory unit MU₁Will be described.
[0162]
This nonvolatile memory unit MU₁Is
(A) Bit line BL₁When,
(B) N (where N ≧ 2, where N = 2 in the illustrated example) selection transistors TR_1NWhen,
(C) Each of M memory cells MC (where M ≧ 2, M = 4 in the illustrated example)_1NM, And N sub memory units SMU_1NWhen,
(D) M plate lines PL_M,
Consists of
[0163]
Then, the N sub memory units SMU_1NAre stacked with an interlayer insulating layer 26 interposed therebetween. Each memory cell includes a first electrode, a ferroelectric layer, and a second electrode. Specifically, the sub memory unit SMU of the first layer₁₁Each memory cell MC constituting_11MIs composed of a first electrode 21, a ferroelectric layer 22, and a second electrode 23, and is a sub-memory unit SMU of the second layer.₁₂Each memory cell MC constituting_12MIs composed of a first electrode 31, a ferroelectric layer 32, and a second electrode 33. Further, each sub memory unit SMU_1nAt the memory cell MC_{1 nm}The first electrodes 21 and 31 are common. Specifically, the sub memory unit SMU of the first layer₁₁At the memory cell MC_11MThe first electrode 21 is common. This common first electrode 21 is connected to a first common node CN.₁₁It may be called. Also, the sub-memory unit SMU of the second layer₁₂At the memory cell MC_12MThe first electrode 31 is common. This common first electrode 31 is connected to a second common node CN.₁₂It may be called. Generally, the sub memory unit SMU of the n-th layer (where n = 1, 2,..., N)_1n, The second electrodes 23 and 33 of the m-th (where m = 1, 2,..., M) memory cell are connected to the sub-memory unit SMU._1nThe m-th plate line PL shared between_mIt is connected to the. More specifically, each plate line extends from the second electrode 23, 33, and these plate lines are connected in a region (not shown).
[0164]
Sub memory unit SMU of the n-th layer (where n = 1, 2,..., N)_1nAre common to the n-th selection transistor TR_1nThrough the bit line BL₁It is connected to the. Specifically, each selection transistor TR₁₁, TR₁₂One source / drain region 14A is connected to the bit line BL.₁And the first selection transistor TR₁₁The other source / drain region 14B is connected to the first-layer sub-memory unit SMU through the first-layer connection hole 17 provided in the insulating layer 16.₁₁In the first common electrode 21 (first common node CN₁₁)It is connected to the. Also, the second selection transistor TR₁₂The other source / drain region 14B is connected via a first layer connection hole 17 provided in the insulating layer 16, a pad portion 25, and a second layer connection hole 27 provided in the interlayer insulating layer 26. The sub-memory unit SMU of the second layer₁₂Of the common first electrode 31 (the second common node CN₁₂)It is connected to the.
[0165]
Bit line BL₁Are connected to the sense amplifier SA. The plate line PL_MAre connected to a plate line decoder / driver PD. Further, the word line WL₁, WL₂(Or the word line WL₁₁, WL₁₂, WL₂₁, WL₂₂) Is connected to the word line decoder / driver WD. Word line WL₁, WL₂Extend in the direction perpendicular to the plane of the paper of FIG. In addition, the nonvolatile memory unit MU₁Memory cell MC constituting_11mOf the non-volatile memory unit MU adjacent in the direction perpendicular to the paper surface of FIG.₂Memory cell MC constituting_21mAnd the plate line PL_mAlso serves as. Further, the nonvolatile memory unit MU₁Memory cell MC constituting_12mOf the non-volatile memory unit MU adjacent in the direction perpendicular to the paper surface of FIG.₂Memory cell MC constituting_22mAnd the plate line PL_mAlso serves as. These plate lines PL_mAre connected in a region not shown. Also, the word line WL₁Is a nonvolatile memory unit MU₁Selection transistor TR that constitutes₁₁And the non-volatile memory units MU adjacent to each other in the vertical direction of FIG.₂Selection transistor TR that constitutes₂₁And is common to Further, the word line WL₂Is a nonvolatile memory unit MU₁Selection transistor TR that constitutes₁₂And the non-volatile memory units MU adjacent to each other in the vertical direction of FIG.₂Selection transistor TR that constitutes₂₂And is common to
[0166]
Nonvolatile memory unit MU whose equivalent circuit diagram is shown in FIGS.₁, MU₂, The nonvolatile memory unit MU₁, MU₂Selection transistor TR that constitutes_1n, TR_2nAre the same word line WL_nIt is connected to the. Then, the paired memory cells MC_{1 nm}, MC_{2 nm}(N = 1, 2, and m = 1, 2,..., M) store complementary data. For example, the memory cell MC_11m, MC_21m(Where m is one of 1, 2, 3, and 4), the word line WL₁Select the plate line PL_j(M ≠ j) is, for example, (１ ／) V_ccWith the voltage applied to the plate line PL_mDrive. As a result, the complementary data is transferred to the paired memory cells MC._11m, MC_21mTo select transistor TR₁₁, TR₂₁Bit line BL paired through₁, BL₂Appear as a voltage (bit line potential). Then, the paired bit lines BL₁, BL₂(Bit line potential) is detected by the sense amplifier SA. The nonvolatile memory unit MU₁, MU₂Selection transistor TR that constitutes₁₁, TR₁₂, TR₂₁, TR₂₂To different word lines WL₁₁, WL₁₂, WL₂₁, WL₂₂To the memory cell MC_{1 nm}, MC_{2 nm}Are independently controlled to form a pair of bit lines BL₁, BL₂Of the memory cell MC by applying a reference potential to one of_{1 nm}, MC_{2 nm}Data can be read from each of them. See FIG. 17B and FIG. 19 for an equivalent circuit diagram in the case of employing such a configuration. The selection transistor TR₁₁, TR₂₁At the same time, and the selection transistor TR₁₂, TR₂₂Are simultaneously driven, the circuit becomes equivalent to the circuits shown in FIGS. Thus, each memory cell MC_{1 nm}, MC_{2 nm}(N = 1, 2, and m = 1, 2, 3, 4), one bit is stored as data (see FIG. 17B and FIG. 19), or a pair of memories. Cell MC_{1 nm}, MC_{2 nm}Is stored as one bit (see FIG. 17A and FIG. 18). In an actual nonvolatile semiconductor memory, a set of nonvolatile memory units for storing 16 bits or 8 bits is arranged in an array as an access unit. Note that the value of M is not limited to 4. The value of M only needs to satisfy M ≧ 2, and a practical value of M can be, for example, a power of 2 (2, 4, 8, 16,...). The value of N only needs to satisfy N ≧ 2, and a practical value of N may be, for example, a power of 2 (2, 4, 8,...).
[0167]
[Cross-point nonvolatile memory unit-Modification 5]
FIG. 20 is a schematic partial cross-sectional view when the nonvolatile memory unit is cut along a virtual vertical plane parallel to the direction in which the bit lines extend. Further, conceptual equivalent circuit diagrams of the nonvolatile memory unit are shown in FIGS. 21A and 21B, and a specific equivalent circuit diagram is shown in FIG. 21A and 21B show two nonvolatile memory units MU.₁, MU₂Are shown, these non-volatile memory units MU₁, MU₂Are the same, and hereinafter, the nonvolatile memory unit MU₁Will be described.
[0168]
This nonvolatile memory unit MU₁Is
(A) N (where N ≧ 2, N = 2 in the illustrated example) bit lines BL_1NWhen,
(B) N selection transistors TR_1NWhen,
(C) Each of M memory cells MC (where M ≧ 2, M = 4 in the illustrated example)_1NM, And N sub memory units SMU_1NWhen,
(D) M plate lines PL_M,
Consists of
[0169]
Then, the N sub memory units SMU_1NAre stacked with an interlayer insulating layer 26 interposed therebetween. Each memory cell includes a first electrode, a ferroelectric layer, and a second electrode. Specifically, the sub memory unit SMU of the first layer₁₁Each memory cell MC constituting_11MIs composed of a first electrode 21, a ferroelectric layer 22, and a second electrode 23, and is a sub-memory unit SMU of the second layer.₁₂Each memory cell MC constituting_12MIs composed of a first electrode 31, a ferroelectric layer 32, and a second electrode 33. Further, each sub memory unit SMU_1nAt the memory cell MC_{1 nm}The first electrodes 21 and 31 are common. Specifically, the sub memory unit SMU of the first layer₁₁At the memory cell MC_11MThe first electrode 21 is common. This common first electrode 21 is connected to a first common node CN.₁₁It may be called. Also, the sub-memory unit SMU of the second layer₁₂At the memory cell MC_12MThe first electrode 31 is common. This common first electrode 31 is connected to a second common node CN.₁₂It may be called. Generally, the sub memory unit SMU of the n-th layer (where n = 1, 2,..., N)_1n, The second electrodes 23 and 33 of the m-th (where m = 1, 2,..., M) memory cell are connected to the sub-memory unit SMU._1nThe m-th plate line PL shared between_mIt is connected to the. More specifically, each plate line extends from the second electrode 23, 33, and these plate lines are connected in a region (not shown).
[0170]
Sub memory unit SMU of the n-th layer (where n = 1, 2,..., N)_1nAre common first electrodes in the first selection transistor TR.₁₁Via the first bit line BL₁₁It is connected to the. Specifically, the n-th selection transistor TR_1nOne source / drain region 14A is connected to the n-th bit line BL._1nAnd the first selection transistor TR₁₁The other source / drain region 14B is connected to the first-layer sub-memory unit SMU through the first-layer connection hole 17 provided in the insulating layer 16.₁₁In the first common electrode 21 (first common node CN₁₁)It is connected to the. Also, the second selection transistor TR₁₂The other source / drain region 14B is connected via a first layer connection hole 17 provided in the insulating layer 16, a pad portion 25, and a second layer connection hole 27 provided in the interlayer insulating layer 26. The sub-memory unit SMU of the second layer₁₂Of the common first electrode 31 (the second common node CN₁₂)It is connected to the.
[0171]
Bit line BL_1nAre connected to the sense amplifier SA. The plate line PL_MAre connected to a plate line decoder / driver PD. Further, the word line WL₁, WL₂(Or the word line WL₁₁, WL₁₂, WL₂₁, WL₂₂) Is connected to the word line decoder / driver WD. Word line WL₁, WL₂Extend in the direction perpendicular to the plane of the paper of FIG. In addition, the nonvolatile memory unit MU₁Memory cell MC constituting_11mOf the nonvolatile memory unit MU adjacent in the direction perpendicular to the paper surface of FIG.₂Memory cell MC constituting_21mAnd the plate line PL_mAlso serves as. Further, the nonvolatile memory unit MU₁Memory cell MC constituting_12mOf the non-volatile memory unit MU adjacent in the direction perpendicular to the paper surface of FIG.₂Memory cell MC constituting_22mAnd the plate line PL_mAlso serves as. These plate lines PL_mAre connected in a region not shown. Also, the word line WL₁Is a nonvolatile memory unit MU₁Selection transistor TR that constitutes₁₁And the non-volatile memory units MU adjacent to each other in the vertical direction of FIG.₂Selection transistor TR that constitutes₂₁And is common to Further, the word line WL₂Is a nonvolatile memory unit MU₁Selection transistor TR that constitutes₁₂And the non-volatile memory units MU adjacent to each other in the vertical direction of FIG.₂Selection transistor TR that constitutes₂₂And is common to
[0172]
Nonvolatile memory unit MU whose equivalent circuit diagram is shown in FIGS.₁, MU₂, The nonvolatile memory unit MU₁, MU₂Selection transistor TR that constitutes₁₁, TR₂₁Are the same word line WL₁And the selection transistor TR₁₂, TR₂₂Are the same word line WL₂It is connected to the. Then, the paired memory cells MC_{1 nm}, MC_{2 nm}(N = 1, 2, and m = 1, 2,..., M) store complementary data. For example, the memory cell MC_11m, MC_21m(Where m is one of 1, 2, 3, and 4), the word line WL₁Select the plate line PL_j(M ≠ j) is, for example, (１ ／) V_ccWith the voltage applied to the plate line PL_mDrive. As a result, the complementary data is transferred to the paired memory cells MC._11m, MC_21mTo select transistor TR₁₁, TR₂₁Bit line BL paired through₁₁, BL₂₁Appear as a voltage (bit line potential). Then, the paired bit lines BL₁₁, BL₂₁(Bit line potential) is detected by the sense amplifier SA. The nonvolatile memory unit MU₁, MU₂Selection transistor TR that constitutes₁₁, TR₁₂, TR₂₁, TR₂₂To different word lines WL₁₁, WL₁₂, WL₂₁, WL₂₂To the memory cell MC_{1 nm}, MC_{2 nm}Are independently controlled to form a pair of bit lines BL₁₁, BL₂₁Or the paired bit lines BL₁₂, BL₂₂Of the memory cell MC by applying a reference potential to one of_{1 nm}, MC_{2 nm}Data can be read from each of them. See FIG. 21B and FIG. 22 for an equivalent circuit diagram in the case of employing such a configuration. The selection transistor TR₁₁, TR₂₁At the same time, and the selection transistor TR₁₂, TR₂₂Are simultaneously driven, the circuit becomes equivalent to the circuit shown in FIG. Thus, each memory cell MC_{1 nm}, MC_{2 nm}(N = 1, 2, and m = 1, 2, 3, 4), one bit is stored as data (see FIG. 21B), or alternatively, a pair of memory cells MC_{1 nm}, MC_{2 nm}Is stored as one bit (see FIG. 21A). In an actual nonvolatile semiconductor memory, a set of nonvolatile memory units for storing 16 bits or 8 bits is arranged in an array as an access unit. Note that the value of M is not limited to 4. The value of M only needs to satisfy M ≧ 2, and a practical value of M can be, for example, a power of 2 (2, 4, 8, 16,...). The value of N only needs to satisfy N ≧ 2, and a practical value of N may be, for example, a power of 2 (2, 4, 8,...).
[0173]
Alternatively, the nonvolatile memory unit MU whose equivalent circuit diagram is shown in FIGS.₁In, for example, the paired memory cells MC_11m, MC_12m(M = 1, 2,..., M) may store complementary data. For example, the memory cell MC_11m, MC_12m(Where m is one of 1, 2, 3, and 4), the word line WL₁, WL₂Select the plate line PL_j(M ≠ j) is, for example, (１ ／) V_ccWith the voltage applied to the plate line PL_mDrive. As a result, the complementary data is transferred to the paired memory cells MC._11m, MC_12mTo select transistor TR₁₁, TR₁₂Bit line BL paired through₁₁, BL₁₂Appear as a voltage (bit line potential). Then, the paired bit lines BL₁₁, BL₁₂(Bit line potential) is detected by the sense amplifier SA. The memory cell MC_11m, MC_12mAre independently controlled to form a pair of bit lines BL₁₁, BL₁₂Of the memory cell MC by applying a reference potential to one of_11m, MC_12mData can be read from each of them. See FIG. 21B and FIG. 22 for an equivalent circuit diagram in the case of employing such a configuration.
[0174]
[Cross-point nonvolatile memory unit-Modification 6]
The nonvolatile memory unit described in [Cross-point nonvolatile memory unit-Modification 4] may be modified as shown in FIG. FIG. 24 shows an equivalent circuit diagram.
[0175]
This nonvolatile memory unit includes a bit line BL connected to a sense amplifier SA.₁And N (where N ≧ 2, N = 4 in this example) selection transistors TR composed of MOS FETs₁₁, TR₁₂, TR_Thirteen, TR₁₄And N sub-memory units SMU₁₁, SMU₁₂, SMU_Thirteen, SMU₁₄And a plate line. First layer sub memory unit SMU₁₁Is M (where M ≧ 2, M = 8 in this example) memory cells MC_11m(M = 1, 2,..., 8). Also, the sub-memory unit SMU of the second layer₁₂Also have M (M = 8) memory cells MC_12m(M = 1, 2,..., 8). Further, the third layer sub memory unit SMU_ThirteenAlso have M (M = 8) memory cells MC_13m(M = 1, 2,..., 8), and the fourth layer sub memory unit SMU₁₄Also have M (M = 8) memory cells MC_14m(M = 1, 2,..., 8). The number of plate lines is M (eight in this example) and PL_m(M = 1, 2,..., 8). Selection transistor TR_1nWord line WL connected to the gate electrode of_1nAre connected to a word line decoder / driver WD. On the other hand, each plate line PL_mAre connected to a plate line decoder / driver PD.
[0176]
Also, the first-layer sub memory unit SMU₁₁Each memory cell MC constituting_11mIs composed of a first electrode 21A, a ferroelectric layer 22A and a second electrode 23, and the sub memory unit SMU of the second layer₁₂Each memory cell MC constituting_12mIs composed of a first electrode 21B, a ferroelectric layer 22B and a second electrode 23, and a third-layer sub memory unit SMU._ThirteenEach memory cell MC constituting_13mIs composed of a first electrode 31A, a ferroelectric layer 32A and a second electrode 33, and the fourth sub memory unit SMU₁₄Each memory cell MC constituting_14mIs composed of a first electrode 31B, a ferroelectric layer 32B, and a second electrode 33. Then, each sub memory unit SMU₁₁, SMU₁₂, SMU_Thirteen, SMU₁₄, The first electrodes 21A, 21B, 31A, 31B of the memory cell are common. The common first electrodes 21A, 21B, 31A, 31B are connected to a common node CN for convenience.₁₁, CN₁₂, CN_Thirteen, CN₁₄Call.
[0177]
Here, the first layer sub memory unit SMU₁₁Of the first common electrode 21A (first common node CN₁₁) Is the first selection transistor TR₁₁Through the bit line BL₁It is connected to the. Also, the sub-memory unit SMU of the second layer₁₂Of the first common electrode 21B (the second common node CN₁₂) Is the second selection transistor TR₁₂Through the bit line BL₁It is connected to the. Further, the third layer sub memory unit SMU_ThirteenIn the first common electrode 31A (third common node CN_Thirteen) Is the third selection transistor TR_ThirteenThrough the bit line BL₁It is connected to the. In addition, the sub memory unit SMU of the fourth layer₁₄Of the common first electrode 31B (fourth common node CN₁₄) Is the fourth selection transistor TR₁₄Through the bit line BL₁It is connected to the.
[0178]
Also, the first-layer sub memory unit SMU₁₁Memory cell MC constituting_11mAnd the second layer sub memory unit SMU₁₂Memory cell MC constituting_12mShare the second electrode 23, and the shared m-th second electrode 23 is connected to the plate line PL._mIt is connected to the. Further, the third layer sub memory unit SMU_ThirteenMemory cell MC constituting_13mAnd the sub-memory unit SMU in the fourth layer₁₄Memory cell MC constituting_14mShare the second electrode 33, and the shared m-th second electrode 33 is connected to the plate line PL._mIt is connected to the. Specifically, from the shared extension of the m-th second electrode 23, the plate line PL_mIs formed, and a plate line PL is extended from the shared extension of the m-th second electrode 33._mAnd each plate line PL_mAre connected in a region not shown.
[0179]
In this nonvolatile memory unit, a sub memory unit SMU₁₁, SMU₁₂And sub memory unit SMU_Thirteen, SMU₁₄Are stacked with an interlayer insulating layer 26 interposed therebetween. Sub memory unit SMU₁₄Is covered with an insulating film 36A. Also, the sub memory unit SMU₁₁Is formed above the semiconductor substrate 10 via an insulating layer 16. An element isolation region 11 is formed in a semiconductor substrate 10. Also, the selection transistor TR₁₁, TR₁₂, TR_Thirteen, TR₁₄Comprises a gate insulating film 12, a gate electrode 13, and source / drain regions 14A and 14B. Then, the first selection transistor TR₁₁, The second selection transistor TR₁₂, The third selection transistor TR_Thirteen, The fourth selection transistor TR₁₄One of the source / drain regions 14A is connected via a contact hole 15 to a bit line BL.₁It is connected to the. Further, the first selection transistor TR₁₁The other source / drain region 14B is connected to a first common node CN via a connection hole 17 provided in an opening formed in the insulating layer 16.₁₁It is connected to the. Further, the second selection transistor TR₁₂Is connected to the second common node CN via the connection hole 17.₁₂It is connected to the. Further, the third selection transistor TR_ThirteenThe other source / drain region 14B is connected to a third common node CN via a connection hole 17, a pad portion 25, and a connection hole 27 provided in an opening formed in the interlayer insulating layer 26._ThirteenIt is connected to the. Further, the fourth selection transistor TR₁₄The other source / drain region 14B is connected to a fourth common node CN₁₄It is connected to the.
[0180]
[Cross-point nonvolatile memory unit-Modification 7]
For example, as shown in FIG. 25, as a modification of the nonvolatile memory unit of [Cross-point nonvolatile memory unit-Modification 4], the first electrodes 21 'and 31' are used as upper electrodes and the second electrodes are used as second electrodes. 23 'and 33' can be used as lower electrodes. Such a structure can be applied to other cross-point nonvolatile memory units.
[0181]
[Cross-point nonvolatile memory unit-Modification 8]
The various cross-point nonvolatile memory units described above may be of a so-called gain cell type disclosed in JP-A-2002-197857. FIG. 26 shows an equivalent circuit diagram of such a nonvolatile memory unit, FIG. 27 shows a schematic layout of various transistors included in the nonvolatile memory unit, and a schematic partial cross-sectional view of the nonvolatile memory unit. Are shown in FIGS. 28 and 29. In FIG. 27, regions of various transistors are surrounded by dotted lines, active regions and wirings are indicated by solid lines, and gate electrodes or word lines are indicated by dashed lines. The schematic partial cross-sectional view of the nonvolatile memory unit illustrated in FIG. 28 is a schematic partial cross-sectional view taken along line AA in FIG. 27, and is a schematic view of the nonvolatile memory unit illustrated in FIG. The typical partial cross-sectional view is a schematic partial cross-sectional view along the line BB in FIG.
[0182]
An example in which the gain cell type is applied to a non-volatile memory unit including the cross-point type non-volatile memory unit shown in FIG. 6 will be described below. This non-volatile memory unit includes, for example, a bit line BL and a transistor TR (shown in FIG. 6 as a selection transistor in the non-volatile memory unit)._WAnd M memory cells MC (where M ≧ 2, for example, M = 8)_M, For example, N sub-memory units SMU stacked via an interlayer insulating layer, and M plate lines PL_MMU. Then, each memory cell MC_MConsists of a first electrode 21, a ferroelectric layer 22, and a second electrode 23, and constitutes a memory cell MC constituting a sub-memory unit SMU._MIs common in the sub memory unit SMU, and the common first electrode (common node CN) is connected to the write transistor TR._WIs connected to a bit line BL through each memory cell MC._mIs formed on the plate line PL_mIt is connected to the. Memory cell MC_MIs covered with an interlayer insulating layer 26. Note that the number (M) of memory cells constituting the sub-memory unit SMU of the nonvolatile memory unit is not limited to eight, and generally needs to satisfy M ≧ 2, and is generally a power of two (M = 2, 4, 8, 16,...).
[0183]
Further, a signal detection circuit is provided for detecting a potential change of the common first electrode and transmitting the detection result to the bit line as a current or a voltage. In other words, the detection transistor TR_SAnd the reading transistor TR_RIt has. The signal detection circuit includes a detection transistor TR_SAnd reading transistor TR_RIt is composed of Then, the detection transistor TR_SHas a predetermined potential V_cc(For example, a power supply line formed of an impurity layer), and the other end is connected to the read transistor TR._RIs connected to a bit line BL through each memory cell MC._mWhen reading the data stored in the memory cell, read transistor TR_RAre turned on, and each memory cell MC_mThe potential generated at the common first electrode (common node CN) based on the data stored in the detection transistor TR_SIs controlled.
[0184]
Specifically, the various transistors are composed of MOS FETs, and the write transistor (selection transistor) TR_WOne of the source / drain regions is connected to a bit line BL via a contact hole 15 formed in an insulating layer 16, and the other source / drain region is provided in an opening formed in the insulating layer 16. It is connected to a common first electrode (common node CN) via a connection hole 17. Also, the detection transistor TR_SOne source / drain region has a predetermined potential V_ccAnd the other source / drain region is connected to the read transistor TR_RIs connected to one of the source / drain regions. More specifically, the detection transistor TR_SSource / drain region and read transistor TR_RThe one source / drain region occupies one source / drain region. Further, the read transistor TR_RThe other source / drain region is connected to the bit line BL via a contact hole 15 and further connected to a common first electrode (common node CN or write transistor TR)._WThe other source / drain region) has a connection hole 17A provided in the opening, and a word line WL._SThrough the detection transistor TR_SConnected to the gate electrode of Also, the writing transistor TR_WWord line WL connected to the gate electrode of_WAnd reading transistor TR_RWord line WL connected to the gate electrode of_RAre connected to a word line decoder / driver WD. On the other hand, each plate line PL_mAre connected to a plate line decoder / driver PD. Further, the bit line BL is connected to the sense amplifier SA.
[0185]
The memory cell MC of this nonvolatile memory unit₁When reading data from the selected plate line PL₁To V_ccIs applied. At this time, the selected memory cell MC₁, The polarization inversion occurs in the ferroelectric layer, the amount of accumulated charge increases, and the potential of the common node CN increases. On the other hand, the selected memory cell MC₁Is stored in the ferroelectric layer, the polarization of the ferroelectric layer does not occur, and the potential of the common node CN hardly rises. That is, the common node CN is connected to the plurality of unselected plate lines PL via the ferroelectric layer of the unselected memory cells._j, The potential of the common node CN is kept at a level relatively close to 0 volt. Thus, the selected memory cell MC₁Changes in the potential of the common node CN depending on the data stored in the common node CN. Therefore, an electric field sufficient for polarization inversion can be applied to the ferroelectric layer of the selected memory cell. Then, the bit line BL is floated, and the read transistor TR_RIs turned on. On the other hand, the selected memory cell MC₁The potential generated at the common first electrode (common node CN) based on the data stored in the detection transistor TR_SIs controlled. Specifically, the selected memory cell MC₁If a high potential is generated at the common first electrode (common node CN) based on the data stored in the detection transistor TR_SBecomes conductive and the detection transistor TR_SHas a predetermined potential V_cc, The detection transistor TR_SAnd reading transistor TR_R, A current flows through the bit line BL, and the potential of the bit line BL rises. That is, the potential change of the common first electrode (common node CN) is detected by the signal detection circuit, and the detection result is transmitted to the bit line BL as a voltage (potential). Here, the detection transistor TR_SThreshold of V_th, Detection transistor TR_SOf the gate electrode (that is, the potential of the common node CN) is V_gThen, the potential of the bit line BL is substantially (V_g-V_th). The detection transistor TR_SIs a depletion type NMOSFET, the threshold V_thTakes a negative value. Thus, a stable sense signal amount can be ensured regardless of the magnitude of the load on the bit line BL. The detection transistor TR_SCan be composed of PMOSFETs.
[0186]
The predetermined potential of the wiring to which one end of the detection transistor is connected is V_ccThe present invention is not limited to this, and may be, for example, grounded. That is, the predetermined potential of the wiring to which one end of the detection transistor is connected may be set to 0 volt. However, in this case, when data is read from the selected memory cell, the potential (V_cc) Appears on the bit line, the potential of the bit line is set to 0 volt at the time of rewriting, and when 0 volt appears at the bit line at the time of reading data from the selected memory cell, the potential of the bit line is set at V at the time of rewriting._ccIt is necessary to For this purpose, a transistor TR as illustrated in FIG._IV-1, TR_IV-2, TR_IV-3, TR_IV-4Is arranged between bit lines, and a transistor TR is used for reading data._IV-2, TR_IV-4Is turned on, and when data is rewritten, the transistor TR_IV-1, TR_IV-3May be turned on.
[0187]
The various cross-point nonvolatile memory units have been described above. However, in [Cross-point nonvolatile memory unit-Modification 3] to [Cross-point nonvolatile memory unit-Modification 8], a plurality of memory cells are used. By sharing one selection transistor and making the sub memory unit have a three-dimensional stacked structure, the number of transistors occupying the surface of the semiconductor substrate is not restricted, and the conventional ferroelectric nonvolatile semiconductor memory In this case, the storage capacity can be dramatically increased, and the effective occupied area of the bit storage unit can be significantly reduced.
[0188]
Further, in [Cross-point nonvolatile memory unit-Modification 3] to [Cross-point nonvolatile memory unit-Modification 8], it suffices to satisfy N ≧ 2. For example, a power of 2 (2, 4, 8...) Can be cited.
[0189]
It is preferable that the crystallization temperature of the ferroelectric layer forming the memory cell of the upper sub memory unit is lower than the crystallization temperature of the ferroelectric layer forming the memory cell of the lower sub memory unit. . Here, the crystallization temperature of the ferroelectric layer constituting the memory cell can be checked using, for example, an X-ray diffractometer or a surface scanning electron microscope. Specifically, for example, after forming a ferroelectric material layer, a heat treatment for promoting crystallization is performed by changing the heat treatment temperature for performing crystallization of the ferroelectric material layer variously, and the ferroelectric material after the heat treatment is performed. The crystallization temperature of the ferroelectric layer can be obtained by performing X-ray diffraction analysis of the body material layer and evaluating the diffraction pattern intensity (height of the diffraction peak) peculiar to the ferroelectric material.
[0190]
By the way, when manufacturing a nonvolatile semiconductor memory having a configuration in which sub-memory units are stacked, heat treatment (crystallization) is performed to crystallize a ferroelectric layer or a ferroelectric thin film constituting a ferroelectric layer. (Referred to as heat treatment) for the number of stacked sub-memory units. Therefore, the lower sub-memory unit receives the crystallization heat treatment for a longer time, and the upper sub-memory unit receives the crystallization heat treatment for a shorter time. Therefore, when an optimal crystallization heat treatment is performed on the upper sub memory unit, the lower sub memory unit may receive an excessive heat load, and the characteristics of the lower sub memory unit may be deteriorated. May occur. Note that a method of performing crystallization heat treatment at once after fabricating a multi-stage sub-memory unit is also conceivable. However, a large volume change occurs in the ferroelectric layer during crystallization, Is likely to occur, and problems such as cracks and peeling of the ferroelectric layer are likely to occur. If the crystallization temperature of the ferroelectric layer forming the upper sub memory unit is lower than the crystallization temperature of the ferroelectric layer forming the lower sub memory unit, the stacked sub memory units Even if the crystallization heat treatment is performed for the number of stages described above, a problem such as deterioration of characteristics of memory cells constituting the sub memory unit located below does not occur. Further, crystallization heat treatment can be performed on the memory cells constituting the sub memory unit in each stage under optimal conditions, and a nonvolatile semiconductor memory with excellent characteristics can be obtained. Table 10 below shows the crystallization temperatures of typical materials constituting the ferroelectric layer, but the materials constituting the ferroelectric layer are not limited to such materials.
[0191]
[Table 10]
Material name Crystallization temperature
Bi₂SrTa₂O₉                    700-800 ° C
Bi₂Sr (Ta_1.5, Nb_0.5) O₉    650-750 ° C
Bi₄Ti₃O₁₂                      600-700 ° C
Pb (Zr_0.48, Ti_0.52) O₃        550-650 ° C
PbTiO₃                          500-600 ° C
[0192]
Examples of the material forming the ferroelectric layer include a bismuth layered compound, more specifically, a Bi-based layered structure perovskite type ferroelectric material. The Bi-based layered structure perovskite ferroelectric material belongs to a so-called non-stoichiometric compound, and has tolerance to a composition deviation at both sites of a metal element and an anion (such as O) element. Also, it is not uncommon for the composition to exhibit optimal electrical characteristics at a position slightly deviating from the stoichiometric composition. The Bi-based layered structure perovskite-type ferroelectric material has, for example, the general formula (Bi₂O₂)²⁺(A_m-1B_mO_{3m + 1})^2-Can be represented by Here, “A” represents one kind of metal selected from the group consisting of metals such as Bi, Pb, Ba, Sr, Ca, Na, K, and Cd, and “B” represents Ti, Nb , Ta, W, Mo, Fe, Co, Cr and one type selected from the group consisting of, or a combination of a plurality of types at an arbitrary ratio. M is an integer of 1 or more.
[0193]
Alternatively, the material constituting the ferroelectric layer is
(Bi_X, Sr_1-X)₂(Sr_Y, Bi_1-Y) (Ta_Z, Nb_1-Z)₂O_d  Equation (1)
(Where 0.9 ≦ X ≦ 1.0, 0.7 ≦ Y ≦ 1.0, 0 ≦ Z ≦ 1.0, 8.7 ≦ d ≦ 9.3) It is preferable to include it as a phase. Alternatively, the material constituting the ferroelectric layer is
Bi_XSr_YTa₂O_d  Equation (2)
(However, it is preferable that a crystal phase represented by X + Y = 3, 0.7 ≦ Y ≦ 1.3, 8.7 ≦ d ≦ 9.3) is included as a main crystal phase. In these cases, it is more preferable that the crystal phase represented by the formula (1) or (2) be contained in a proportion of 85% or more as a main crystal phase. Note that, in equation (1), (Bi_X, Sr_1-XThe meaning of () means that Sr occupies the site originally occupied by Bi in the crystal structure, and the ratio of Bi and Sr at this time is X: (1-X). Also, (Sr_Y, Bi_1-YThe meaning of ()) means that Bi occupies the site originally occupied by Sr in the crystal structure, and the ratio of Sr to Bi at this time is Y: (1-Y). Materials constituting the ferroelectric layer containing the crystal phase represented by the formula (1) or (2) as a main crystal phase include oxides of Bi, oxides of Ta and Nb, and oxides of Bi, Ta and Nb. In some cases, the composite oxide may be slightly contained.
[0194]
Alternatively, the material constituting the ferroelectric layer is
Bi_X(Sr, Ca, Ba)_Y(Ta_Z, Nb_1-Z)₂O_d  Equation (3)
(However, a crystal phase represented by 1.7 ≦ X ≦ 2.5, 0.6 ≦ Y ≦ 1.2, 0 ≦ Z ≦ 1.0, 8.0 ≦ d ≦ 10.0) is included. It may be. “(Sr, Ca, Ba)” means one element selected from the group consisting of Sr, Ca, and Ba. If the composition of the material constituting the ferroelectric layer represented by each of these formulas is represented by a stoichiometric composition, for example, for example, Bi₂SrTa₂O₉(Strontium bismuth tantalate), Bi₂SrNb₂O₉(Strontium bismuth niobate), Bi₂BaTa₂O₉(Barium bismuth tantalate), Bi₂BaNb₂O₉(Barium bismuth niobate), Bi₂Sr (Ta, Nb)₂O₉(Strontium bismuth tantalate niobate) and the like. Alternatively, as a ferroelectric material, Bi₄SrTi₄O_Fifteen(Strontium bismuth titanate), Bi₃TiNbO₉(Bismuth titanium niobate), Bi₃TiTaO₉(Bismuth titanium tantalate), Bi₄Ti₃O₁₂(Bismuth titanate), (Bi, La)₄Ti₃O₁₂(Lanthanum bismuth titanate), Bi₂PbTa₂O₉(Bismuth lead tantalate) can be exemplified. In these cases, the ratio of each metal element can be changed to such an extent that the crystal structure does not change. That is, there may be a composition deviation at both sites of the metal element and the oxygen element.
[0195]
Alternatively, as a ferroelectric material, PbTiO₃(Lead titanate), BaTiO₃(Barium titanate), LiNbO₃(Lithium niobate), LiTaO₃(Lithium tantalate), YMnO₃(Yttrium manganate), PbZrO having a perovskite structure₃And PbTiO₃Lead zirconate titanate [PZT, Pb (Zr_1-y, Ti_y) O₃(Where 0 <y <1)], PLZT [(Pb, La) (Zr, Ti) O, which is a metal oxide obtained by adding La to PZT.₃(Lanthanum lead zirconate titanate)], or PNZT, a metal oxide obtained by adding Nb to PZT, and PSZT [(Pb, Sr) (Zr), a metal oxide obtained by adding strontium (Sr) to PZT._X, Ti_Y) O₃And mixtures thereof.
[0196]
In the materials constituting the ferroelectric layer described above, the crystallization temperature can be changed by excluding these compositions from the stoichiometric composition.
[0197]
In order to obtain a ferroelectric layer, the ferroelectric thin film may be patterned in a step after the formation of the ferroelectric thin film. In some cases, patterning of the ferroelectric thin film is unnecessary. The ferroelectric thin film is formed by, for example, MOCVD; Metal Organic Decomposition (MOD) using a bismuth organometallic compound having a bismuth-oxygen bond (bismuth alkoxide compound); LSMCD (Liquid Source Mist Chemical Deposition); Pulse laser ablation method; sputtering method such as magnetron sputtering method or reactive sputtering method; electron beam evaporation method; suitable for materials constituting ferroelectric thin film such as solution chemistry method (sol-gel method) such as spray coating method and spin coating method It can be performed appropriately by the method described above. The patterning of the ferroelectric thin film can be performed by, for example, an anisotropic ion etching (RIE) method.
[0198]
As described above, the first electrode is formed below the ferroelectric layer, and the second electrode is formed above the ferroelectric layer (that is, the first electrode corresponds to the lower electrode, The second electrode may correspond to the upper electrode, or a configuration in which the first electrode is formed on the ferroelectric layer and the second electrode is formed below the ferroelectric layer (that is, the second electrode is equivalent to the upper electrode). , The first electrode corresponds to the upper electrode, and the second electrode corresponds to the lower electrode). It is preferable that the plate line extend from the second electrode from the viewpoint of simplifying the wiring structure. As a structure in which the first electrode is common, specifically, a structure in which a stripe-shaped first electrode is formed and a ferroelectric layer is formed so as to cover the entire surface of the stripe-shaped first electrode. Can be mentioned. In such a structure, the overlapping region of the first electrode, the ferroelectric layer, and the second electrode corresponds to a memory cell. As a structure in which the first electrode is common, a structure in which a ferroelectric layer is formed in a predetermined region of the first electrode, and a second electrode is formed on the ferroelectric layer, or A first electrode is formed on a predetermined surface area of the wiring, a ferroelectric layer is formed on each of the first electrodes, and a second electrode is formed on the ferroelectric layer. However, the present invention is not limited to these configurations.
[0199]
As a structure in which the first electrode is common, specifically, a structure in which a stripe-shaped first electrode is formed and a ferroelectric layer is formed so as to cover the entire surface of the stripe-shaped first electrode. Can be mentioned. In such a structure, the overlapping region of the first electrode, the ferroelectric layer, and the second electrode corresponds to a memory cell. As a structure in which the first electrode is common, a structure in which a ferroelectric layer is formed in a predetermined region of the first electrode, and a second electrode is formed on the ferroelectric layer, or A first electrode is formed in a predetermined surface area of the wiring layer, a ferroelectric layer is formed on each of the first electrodes, and a second electrode is formed on the ferroelectric layer. However, the present invention is not limited to these configurations.
[0200]
The first electrode and the second electrode are made of at least one kind of metal selected from the platinum group or an oxide thereof, or alternatively, ruthenium (Ru), rhodium (Rh), palladium (Pd), It is desirable to be made of at least one kind of metal selected from the group consisting of osmium (Os), iridium (Ir), platinum (Pt) and rhenium (Re), or an oxide thereof. , For example, Ir, IrO_2-X, IrO_2-X/ Ir, Ir / IrO_2-X, SrIrO₃, Ru, RuO_2-X, SrRuO₃, Pt, Pt / IrO_2-X, Pt / RuO_2-X, Pd, a laminated structure of Pt / Ti, a laminated structure of Pt / Ta, a laminated structure of Pt / Ti / Ta, or La._0.5Sr_0.5CoO₃(LSCO), Pt / LSCO laminated structure, YBa₂Cu₃O₇Can be mentioned. Here, the value of X is 0 ≦ X <2. In the laminated structure, the material described after "/" is in contact with the ferroelectric layer. The first electrode and the second electrode may be made of the same material, may be made of the same material, or may be made of different materials. In order to form the first electrode or the second electrode, in the step after forming the first electrode material layer or the second electrode material layer, the first electrode material layer or the second electrode material layer is formed. May be patterned. The first electrode material layer or the second electrode material layer is formed by, for example, a first electrode material layer such as a sputtering method, a reactive sputtering method, an electron beam evaporation method, a MOCVD method, or a pulse laser ablation method. It can be carried out by a method suitable for the material constituting the electrode material layer. The patterning of the first electrode material layer and the second electrode material layer can be performed by, for example, an ion milling method or an RIE method.
[0201]
In the case where the first electrode is formed below the ferroelectric layer and the second electrode is formed above the ferroelectric layer, the first electrode forming the memory cell has a so-called damascene structure. In the case where the first electrode is formed on the ferroelectric layer and the second electrode is formed below the ferroelectric layer, the second electrode forming the memory cell has a so-called damascene structure. Is preferable from the viewpoint that the ferroelectric layer can be formed on a flat base.
[0202]
Silicon oxide (SiO 2) is used as a material for forming the interlayer insulating layer.₂), Silicon nitride (SiN), SiON, SOG, NSG, BPSG, PSG, BSG or LTO.
[0203]
The selection transistor (switching transistor) and various transistors formed on the semiconductor substrate below the memory cell with an insulating layer interposed therebetween can be composed of, for example, a well-known MIS type FET or MOS type FET. Examples of a material forming the bit line include polysilicon doped with impurities and a high melting point metal material. Electrical connection between the common first electrode and the selection transistor is established via a connection hole (contact hole) provided in an insulating layer formed between the common first electrode and the selection transistor. Alternatively, it can be performed through a connection hole (contact hole) provided in the insulating layer and a wiring layer formed on the insulating layer. Note that silicon oxide (SiO 2) was used as a material for forming the insulating layer.₂), Silicon nitride (SiN), SiON, SOG, NSG, BPSG, PSG, BSG or LTO. Further, the memory cell is made of, for example, aluminum oxide (Al₂O₃) And the like.
[0204]
As described above, the present invention has been described based on the embodiments of the present invention, but the present invention is not limited to these. The structure and configuration of the computer device, the structure of the nonvolatile semiconductor memory, the materials used, various forming conditions, the circuit configuration, the driving method, and the like described in the embodiments of the invention are examples, and can be changed as appropriate.
[0205]
【The invention's effect】
In the computer device according to the first, second, or third aspect of the present invention, by providing the nonvolatile semiconductor memory, the hibernation function or the memory swap function is speeded up, and the usability of the computer device is improved. Significantly improved. That is, the system can be started up and shut down at a high speed as if the volatile main memory is non-volatile, without largely changing the conventional system. Furthermore, as with the increase in the capacity of the volatile main memory, the memory area can be swapped at a high speed, and the usability of the computer device can be greatly improved.
[0206]
Some nonvolatile semiconductor memories, such as flash memories, require a longer time to write than hard disk storage devices.However, since nonvolatile semiconductor memories are more resistant to shocks, when the power is turned off during execution of the hibernation function, There is no need to wait for the end of writing, and the computer device can be moved quickly. Therefore, if the reading time is even faster than the hard disk storage device, the convenience for the user of the computer device is improved.
[0207]
In the computer device according to the first, second, or third aspect of the present invention, the non-volatile semiconductor memory is not installed in the computer device, but is installed in an external IC card to be portable. If it is used as a storage medium having a memory, the nonvolatile semiconductor memory can be used effectively. That is, the user of the computer device can enjoy the convenience of the high-speed hibernation function and the memory swap function without increasing the overall cost of the system, that is, without making an extra investment in the computer device itself. it can. Furthermore, if the hibernation function is performed by using an external IC card, the work state can be transplanted between computer devices of the same type or standardized.
[0208]
In a computer device according to a fourth aspect of the present invention, the standby current of a volatile main memory such as a DRAM is reduced to zero or to a minimum while the computer device is not used (during use). Life can be greatly improved. Furthermore, since the generated data is automatically copied to the non-volatile semiconductor memory when the use is stopped (not in use), the generated data is not lost even if the battery runs out during the non-use, and a complicated backup operation is performed. Do not need.
[0209]
Furthermore, in the present invention, if a cross-point type nonvolatile memory unit is used as a nonvolatile semiconductor memory, reliability against frequent rewriting is guaranteed, and storage of stored contents stored in a volatile semiconductor memory can be performed. Saving, copying, and restoring the stored contents can be performed very quickly, and the convenience is further improved. Further, with such a configuration, the volatile main memory can be used like a cache memory, and the cross-point nonvolatile memory unit can be used like a main memory.
[Brief description of the drawings]
FIGS. 1A and 1B are conceptual diagrams of computer devices according to a first embodiment of the present invention and a second embodiment of the present invention, respectively.
FIGS. 2A and 2B are conceptual diagrams of computer devices according to a third embodiment and a fourth embodiment of the present invention, respectively.
FIG. 3 is a conceptual diagram of a computer device according to a sixth embodiment of the present invention.
FIG. 4 is a diagram showing an example of an equivalent circuit diagram of a group of ferroelectric nonvolatile semiconductor memories constituting a cross-point nonvolatile memory unit;
FIG. 5 is a diagram showing an example of an equivalent circuit diagram of one ferroelectric nonvolatile semiconductor memory unit;
FIG. 6 is a schematic partial cross-sectional view of a ferroelectric nonvolatile semiconductor memory unit along a direction extending to a bit line.
FIGS. 7A and 7B are operation waveforms for explaining a write operation and a read / rewrite operation for a memory cell constituting a ferroelectric nonvolatile semiconductor memory unit, respectively; FIG.
FIG. 8 is an equivalent circuit diagram of a ferroelectric nonvolatile semiconductor memory group in [Cross-point nonvolatile memory unit—Modification 1].
FIG. 9 is an equivalent circuit diagram of two ferroelectric nonvolatile semiconductor memory units in [Cross-point nonvolatile memory unit-Modification 1].
FIG. 10 is an equivalent circuit diagram of a ferroelectric nonvolatile semiconductor memory group in [Cross-point nonvolatile memory unit—Modification 2].
FIG. 11 is an equivalent circuit diagram of two ferroelectric nonvolatile semiconductor memory units in [Cross-point nonvolatile memory unit—Modification 2].
FIG. 12 is a schematic partial cross-sectional view when a ferroelectric nonvolatile semiconductor memory unit in [Cross-point nonvolatile memory unit—Modification 3] is cut off.
FIGS. 13A and 13B are equivalent circuit diagrams of two ferroelectric nonvolatile semiconductor memory units in [Cross-point nonvolatile memory unit—Modification 3], respectively.
FIG. 14 is a more specific equivalent circuit diagram of the conceptual equivalent circuit diagram shown in FIG.
FIG. 15 is a more specific equivalent circuit diagram of the conceptual equivalent circuit diagram shown in FIG.
FIG. 16 is a schematic partial cross-sectional view when a ferroelectric nonvolatile semiconductor memory unit in [Cross-point nonvolatile memory unit—Modification 4] is cut off.
FIGS. 17A and 17B are equivalent circuit diagrams of two ferroelectric nonvolatile semiconductor memory units in [Cross-point nonvolatile memory unit—Modification 4], respectively.
FIG. 18 is a more specific equivalent circuit diagram of the conceptual equivalent circuit diagram shown in FIG.
FIG. 19 is a more specific equivalent circuit diagram of the conceptual equivalent circuit diagram shown in FIG. 17 (B).
FIG. 20 is a schematic partial cross-sectional view when a ferroelectric nonvolatile semiconductor memory unit in [Cross-point nonvolatile memory unit—Modification 5] is cut off.
FIGS. 21A and 21B are equivalent circuit diagrams of two ferroelectric nonvolatile semiconductor memory units in [Cross-point nonvolatile memory unit-Modification 5], respectively.
FIG. 22 is a more specific equivalent circuit diagram of the conceptual equivalent circuit diagram shown in FIGS. 21 (A) and 21 (B).
FIG. 23 is a schematic partial cross-sectional view when a ferroelectric nonvolatile semiconductor memory unit in [Cross-point nonvolatile memory unit-Modification 6] is cut off.
FIG. 24 is an equivalent circuit diagram of one ferroelectric nonvolatile semiconductor memory unit in [Cross-point nonvolatile memory unit-Modification 6] shown in FIG. 23;
FIG. 25 is a schematic partial cross-sectional view when the ferroelectric nonvolatile semiconductor memory unit in [Cross-point nonvolatile memory unit—Modification 7] is cut off.
FIG. 26 is an equivalent circuit diagram of a ferroelectric nonvolatile semiconductor memory unit in [Cross-point nonvolatile memory unit-Modification 8].
FIG. 27 is a layout diagram of a ferroelectric nonvolatile semiconductor memory unit in [Cross-point nonvolatile memory unit-Modification 8] shown in FIG. 26;
FIG. 28 is a schematic partial cross-sectional view of the ferroelectric nonvolatile semiconductor memory unit shown in FIG. 26;
FIG. 29 is a schematic partial cross-sectional view of the ferroelectric nonvolatile semiconductor memory unit shown in FIG. 26 when viewed from a cross section different from that of FIG. 28;
FIG. 30 is an equivalent circuit diagram showing a type of switch circuit provided between bit lines when a predetermined potential of a wiring to which one end of a detection transistor is connected is set to 0 volt;
FIG. 31 is a PE (V) hysteresis loop diagram of a ferroelectric substance.
32A and 32B are a conceptual diagram of a conventional computer and a conceptual diagram of a system configuration example of a conventional mobile computer or the like, respectively.
[Explanation of symbols]
1, 101 CPU, 2, 102 volatile system memory, 3 register group, 4, 4A, 4B, 104, 104A, 104B volatile main memory, 5 VRAM 6, hard disk storage device, 7, 107 nonvolatile semiconductor memory, 8 IC card, 10 silicon semiconductor substrate, 11 element isolation region, 12 gate insulating film , 13 gate electrode, 14A, 14B source / drain region, 15 contact hole, 16 insulating layer, 17, 27 connection hole, 21, 21A, 21B, 21 ' , 31, 31A, 31B, 31 '... first electrode, 22, 22A, 22B, 32, 32A, 32B ... ferroelectric layer, 23, 23', 33, 33 '... second Electrode, 25 ... pad , 26 ... interlayer dielectric layer, 36A ... insulating film, TR ... selection transistor, TR_W... Transistor for writing, TR_R... Transistor for reading, TR_S... Detection transistor, WL ... word line, BL ... bit line, PL ... plate line, WD ... word line decoder / driver, SA ... sense amplifier, PD ... plate Line decoder / driver, CN ... common node

Claims (28)

At least a CPU, a volatile system memory, and a computer device including a nonvolatile semiconductor memory,
When the power is turned off, at least a part of the storage contents of the volatile system memory is stored in the nonvolatile semiconductor memory based on the operation of the CPU. A computer device for writing stored contents back to a volatile system memory. The computer device according to claim 1, wherein the non-volatile semiconductor memory is installed in a removable IC card. When storing at least a part of the storage contents of the volatile system memory in the nonvolatile semiconductor memory, identification information for selectively identifying a computer device is simultaneously stored in the nonvolatile semiconductor memory. The computer device according to claim 2. The nonvolatile semiconductor memory includes a ferroelectric nonvolatile semiconductor memory group in which K ferroelectric nonvolatile semiconductor memory units are aggregated,
Each ferroelectric nonvolatile semiconductor memory unit
(A) a bit line;
(B) a selection transistor;
(C) a sub-memory unit composed of M (where M ≧ 2) memory cells;
(D) M plate lines,
Consisting of
The sub memory unit is formed above the semiconductor substrate via an insulating layer,
Each memory cell includes a first electrode, a ferroelectric layer, and a second electrode,
In the sub memory unit, the first electrode of the memory cell is common, and the common first electrode is connected to the bit line via the selection transistor, and the m-th (where m = 1, 2) , M) are connected to the m-th plate line,
4. The computer device according to claim 1, wherein the m-th plate line is common in the group of ferroelectric nonvolatile semiconductor memories. 5. The computer device according to claim 4, wherein batch access is made to M × K memory cells constituting the ferroelectric nonvolatile semiconductor memory group. The value of M × K is ^{2 9 bytes, 2 10 bytes, 2 11 bytes, 2 12} bytes, or ^{2 13} computing device according to claim 5, characterized in that a value corresponding to the byte. 5. The computer device according to claim 4, wherein the group of ferroelectric nonvolatile semiconductor memories includes at least two K-bit registers. At least a CPU, a volatile system memory, and a computer device including a nonvolatile semiconductor memory,
At the time of operation, based on the operation of the CPU, a part of the storage contents of the volatile system memory is evacuated to the non-volatile semiconductor memory to release the area of the volatile system memory, and then the non-volatile semiconductor memory is operated based on the operation of the CPU. A computer device for writing back the stored contents saved in a volatile system memory. The computer device according to claim 8, wherein the nonvolatile semiconductor memory is installed in a removable IC card. When a part of the storage content of the volatile system memory is saved in the nonvolatile semiconductor memory, identification information for selectively identifying a computer device is simultaneously stored in the nonvolatile semiconductor memory. Item 9. Computer equipment according to item 8. The nonvolatile semiconductor memory includes a ferroelectric nonvolatile semiconductor memory group in which K ferroelectric nonvolatile semiconductor memory units are aggregated,
Each ferroelectric nonvolatile semiconductor memory unit
(A) a bit line;
(B) a selection transistor;
(C) a sub-memory unit composed of M (where M ≧ 2) memory cells;
(D) M plate lines,
Consisting of
The sub memory unit is formed above the semiconductor substrate via an insulating layer,
Each memory cell includes a first electrode, a ferroelectric layer, and a second electrode,
In the sub memory unit, the first electrode of the memory cell is common, and the common first electrode is connected to the bit line via the selection transistor, and the m-th (where m = 1, 2) , M) are connected to the m-th plate line,
11. The computer device according to claim 8, wherein the m-th plate line is common in the group of ferroelectric nonvolatile semiconductor memories. 12. The computer device according to claim 11, wherein M × K memory cells constituting the ferroelectric nonvolatile semiconductor memory group are accessed collectively. The value of M × K is ^{2 9 bytes, 2 10 bytes, 2 11 bytes, 2 12} bytes, or ^{2 13} computing device according to claim 12, characterized in that a value corresponding to a byte. 12. The computer device according to claim 11, wherein the ferroelectric nonvolatile semiconductor memory group includes at least two K-bit registers. At least a CPU, a volatile system memory, and a computer device including a nonvolatile semiconductor memory,
At the time of operation, based on the operation of the CPU, a part of the storage contents of the volatile system memory is evacuated to the non-volatile semiconductor memory to release the area of the volatile system memory, and then the non-volatile semiconductor memory is operated based on the operation of the CPU. Write the stored contents back to the volatile system memory,
When the power is turned off, at least a part of the storage contents of the volatile system memory is stored in the nonvolatile semiconductor memory based on the operation of the CPU. A computer device for writing stored contents back to a volatile system memory. The computer device according to claim 15, wherein the nonvolatile semiconductor memory is installed in a removable IC card. When a part of the storage content of the volatile system memory is saved in the nonvolatile semiconductor memory, identification information for selectively identifying a computer device is simultaneously stored in the nonvolatile semiconductor memory. Item 17. Computer equipment according to Item 16. When storing at least a part of the storage contents of the volatile system memory in the nonvolatile semiconductor memory, identification information for selectively identifying a computer device is simultaneously stored in the nonvolatile semiconductor memory. The computer device according to claim 16. The nonvolatile semiconductor memory includes a ferroelectric nonvolatile semiconductor memory group in which K ferroelectric nonvolatile semiconductor memory units are aggregated,
Each ferroelectric nonvolatile semiconductor memory unit
(A) a bit line;
(B) a selection transistor;
(C) a sub-memory unit composed of M (where M ≧ 2) memory cells;
(D) M plate lines,
Consisting of
The sub memory unit is formed above the semiconductor substrate via an insulating layer,
Each memory cell includes a first electrode, a ferroelectric layer, and a second electrode,
In the sub memory unit, the first electrode of the memory cell is common, and the common first electrode is connected to the bit line via the selection transistor, and the m-th (where m = 1, 2) , M) are connected to the m-th plate line,
19. The computer device according to claim 15, wherein the m-th plate line is common in the group of ferroelectric nonvolatile semiconductor memories. 20. The computer device according to claim 19, wherein M × K memory cells constituting the ferroelectric nonvolatile semiconductor memory group are accessed collectively. The value of M × K is ^{2 9 bytes, 2 10 bytes, 2 11 bytes, 2 12} bytes, or ^{2 13} computing device according to claim 20, characterized in that a value corresponding to a byte. 20. The computer device according to claim 19, wherein the ferroelectric nonvolatile semiconductor memory group includes at least two K-bit registers. At least a CPU, a volatile system memory, and a computer device including a nonvolatile semiconductor memory,
At the time of suspension of use, at least a part of the storage contents of the volatile system memory is copied to the non-volatile semiconductor memory based on the operation of the CPU. A computer device characterized by writing contents back to volatile system memory. Volatile system memory consists of DRAM,
At the time of suspension of use, after at least a part of the storage content of the volatile system memory is copied to the nonvolatile semiconductor memory, the refresh operation in the portion of the volatile system memory that has stored the storage content copied to the nonvolatile semiconductor memory is performed. The computer device according to claim 23, wherein the computer device stops. The nonvolatile semiconductor memory includes a ferroelectric nonvolatile semiconductor memory group in which K ferroelectric nonvolatile semiconductor memory units are aggregated,
Each ferroelectric nonvolatile semiconductor memory unit
(A) a bit line;
(B) a selection transistor;
(C) a sub-memory unit composed of M (where M ≧ 2) memory cells;
(D) M plate lines,
Consisting of
The sub memory unit is formed above the semiconductor substrate via an insulating layer,
Each memory cell includes a first electrode, a ferroelectric layer, and a second electrode,
In the sub memory unit, the first electrode of the memory cell is common, and the common first electrode is connected to the bit line via the selection transistor, and the m-th (where m = 1, 2) , M) are connected to the m-th plate line,
25. The computer device according to claim 23, wherein the m-th plate line is common in the group of ferroelectric nonvolatile semiconductor memories. 26. The computer device according to claim 25, wherein batch access is made to M × K memory cells constituting the ferroelectric nonvolatile semiconductor memory group. The value of M × K is ^{2 9 bytes, 2 10 bytes, 2 11 bytes, 2 12} bytes, or ^{2 13} computing device according to claim 26, characterized in that a value corresponding to a byte. 26. The computer device according to claim 25, wherein the group of ferroelectric nonvolatile semiconductor memories includes at least two stages of K-bit registers.

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