JP4069607B2 - Ferroelectric nonvolatile semiconductor memory - Google Patents

Description

【０１１４】
あるいは又、Ｂｉ₂ＳｒＴａ₂Ｏ₉から成る強誘電体薄膜をパルスレーザアブレーション法、ゾル−ゲル法、あるいはＲＦスパッタ法にて全面に形成することもできる。これらの場合の形成条件を、以下の表４、表５、表６に例示する。尚、ゾル−ゲル法によって厚い強誘電体薄膜を形成する場合、所望の回数、スピンコート及び乾燥、あるいはスピンコート及び焼成（又は、アニール処理）を繰り返せばよい。
【０１１５】
［表４］
パルスレーザアブレーション法による形成
ターゲット：Ｂｉ₂ＳｒＴａ₂Ｏ₉
使用レーザ：ＫｒＦエキシマレーザ（波長２４８ｎｍ、パルス幅２５ｎ秒、５Ｈｚ）
形成温度 ：４００〜８００゜Ｃ
酸素濃度 ：３Ｐａ
【０１１６】

【０１１７】
［表６］
ＲＦスパッタ法による形成
ターゲット：Ｂｉ₂ＳｒＴａ₂Ｏ₉セラミックターゲット
ＲＦパワー：１．２Ｗ〜２．０Ｗ／ターゲット１ｃｍ²
雰囲気圧力：０．２〜１．３Ｐａ
形成温度 ：室温〜６００゜Ｃ
プロセスガス：Ａｒ／Ｏ₂の流量比＝２／１〜９／１
【０１１８】
強誘電体層を、ＰＺＴあるいはＰＬＺＴから構成するときの、マグネトロンスパッタ法によるＰＺＴあるいはＰＬＺＴの形成条件を以下の表７に例示する。あるいは又、ＰＺＴやＰＬＺＴを、反応性スパッタ法、電子ビーム蒸着法、ゾル−ゲル法、又はＭＯＣＶＤ法にて形成することもできる。
【０１１９】
［表７］
ターゲット ：ＰＺＴあるいはＰＬＺＴ
プロセスガス：Ａｒ／Ｏ₂＝９０体積％／１０体積％
圧力 ：４Ｐａ
パワー ：５０Ｗ
形成温度 ：５００゜Ｃ
【０１２０】
更には、ＰＺＴやＰＬＺＴをパルスレーザアブレーション法にて形成することもできる。この場合の形成条件を以下の表８に例示する。
【０１２１】
［表８］
ターゲット：ＰＺＴ又はＰＬＺＴ
使用レーザ：ＫｒＦエキシマレーザ（波長２４８ｎｍ、パルス幅２５ｎ秒、３Ｈｚ）
出力エネルギー：４００ｍＪ（１．１Ｊ／ｃｍ²）
形成温度 ：５５０〜６００゜Ｃ
酸素濃度 ：４０〜１２０Ｐａ
【０１２２】
プレート線の延びる方向に隣接した実施の形態１の２つの不揮発性メモリのそれぞれを構成するメモリセル（これらのメモリセルは同じプレート線を共通している）を、同時に動作させることによって、２つのメモリセルに相補的に１ビットを記憶させることもできるし、独立して動作させることによって、２つのメモリセルのＰそれぞれに１ビットを記憶させることもできる。これらの動作のより詳細は、実施の形態２において説明する。
【０１２３】
（実施の形態２）
実施の形態２は、本発明の第３の態様及び第４の態様に係るゲインセルタイプの不揮発性メモリに関する。実施の形態２の不揮発性メモリの回路図を図９に示し、図９におけるメモリユニットのより具体的な回路図を図１０に示す。また、不揮発性メモリを切断したときのビット線の延びる方向と平行における実施の形態２の不揮発性メモリの模式的な一部断面図を図１１に示す。図においては、ビット線方向に隣接する２つのメモリユニットブロック（１つの不揮発性メモリを構成する）を図示するが、メモリユニットブロックの一方の構成要素の参照番号には「’」を付した。尚、２つのメモリユニットブロックは同一の構成であるが故に、以下、一方のメモリユニットブロックについて説明を行う。ここで、図１０には、プレート線の延びる方向に隣接する別の不揮発性メモリＭ_Bにおける１つのメモリユニットブロックＭＢ_Bを示すが、このメモリユニットブロックＭＢ_BはメモリユニットブロックＭＢ_Aと同じ構成を有する。
【０１２４】
実施の形態２の不揮発性メモリＭ_Aは、
（Ａ）信号検出回路と、
（Ｂ）複数のメモリユニットブロックＭＢ_A，ＭＢ_A’、
から成り、
例えば、メモリユニットブロックＭＢ_Aは、
（Ｂ−１）選択用トランジスタＴＲ_SAと、
（Ｂ−２）それぞれがＭ個（但し、Ｍ≧２であり、実施の形態２においては、Ｍ＝８）のメモリセルＭＣ_ANMから構成された、Ｎ個（但し、Ｎ≧２であり、実施の形態２においては、Ｎ＝２）のメモリユニットＭＵ_ANと、
（Ｂ−３）Ｍ×Ｎ本のプレート線、
から成る。
【０１２５】
そして、メモリユニットブロックＭＢ_AのＮ個のメモリユニットＭＵ_ANは、絶縁層２６（以下、便宜上、層間絶縁層２６と呼ぶ）を介して積層されており、各メモリセルＭＣ_ANMは、第１の電極２１，３１と強誘電体層２２，３２と第２の電極２３，３３とから成る。そして、メモリユニットブロックＭＢ_Aの各メモリユニットＭＵ_Anにおいて、メモリセルＭＣ_Anmの第１の電極は共通であり、これらの共通の第１の電極は、メモリユニットブロックＭＢ_Aの選択用トランジスタＴＲ_SAを介して、信号検出回路に接続されている。更には、メモリユニットブロックＭＢ_Aの第ｎ層目（但し、ｎ＝１，２・・・，Ｎ）のメモリユニットＭＵ_Anにおいて、第ｍ番目（但し、ｍ＝１，２・・・，Ｍ）のメモリセルＭＣ_Anmの第２の電極は、メモリユニットブロックＭＢ_Aの第［（ｎ−１）Ｍ＋ｍ］番目のプレート線ＰＬ_(n-1)M+mに接続されている。そして、信号検出回路は、メモリユニットブロックＭＢ_AのメモリユニットＭＵ_Anにおける共通の第１の電極の電位変化（メモリセルＭＣ_Anmに記憶されたデータに基づく）を検出し、この検出結果をビット線ＢＬ_Aに電流又は電圧として伝達する。この信号検出回路は、具体的には、次に説明する書込用トランジスタＴＲ_Wと、読出用トランジスタＴＲ_Rと、検出用トランジスタＴＲ_Dから構成されている。
【０１２６】
あるいは又、実施の形態２の不揮発性メモリＭ_Aは、
（Ａ）ビット線ＢＬ_Aと、
（Ｂ）書込用トランジスタＴＲ_Wと、
（Ｃ）読出用トランジスタＴＲ_Rと、
（Ｄ）検出用トランジスタＴＲ_Dと、
（Ｅ）複数のメモリユニットブロックＭＢ_A，ＭＢ_A’、
から成り、
例えば、メモリユニットブロックＭＢ_Aは、
（Ｅ−１）選択用トランジスタＴＲ_SAと、
（Ｅ−２）それぞれがＭ個（但し、Ｍ≧２であり、実施の形態２においては、Ｍ＝８）のメモリセルＭＣ_ANMから構成された、Ｎ個（但し、Ｎ≧２であり、実施の形態２においては、Ｎ＝２）のメモリユニットＭＵ_ANと、
（Ｅ−３）Ｍ×Ｎ本のプレート線、
から成る。
【０１２７】
そして、メモリユニットブロックＭＢ_AのＮ個のメモリユニットＭＵ_ANは、層間絶縁層２６を介して積層されており、各メモリセルＭＣ_ANMは、第１の電極２１，３１と強誘電体層２２，３２と第２の電極２３，３３とから成る。メモリユニットブロックＭＢ_Aの各メモリユニットＭＵ_Anにおいて、メモリセルＭＣ_Anmの第１の電極は共通であり、これらの共通の第１の電極は、メモリユニットブロックＭＢ_Aの選択用トランジスタＴＲ_SA、及び、書込用トランジスタＴＲ_Wを介してビット線ＢＬ_Aに接続されている。具体的には、メモリユニットＭＵ_A1において、メモリセルＭＣ_A1Mの第１の電極２１は共通であり（この共通の第１の電極を第１の共通ノードＣＮ_A1と呼ぶ）、共通の第１の電極２１（第１の共通ノードＣＮ_A1）は、選択用トランジスタＴＲ_SA、及び、書込用トランジスタＴＲ_Wを介してビット線ＢＬ_Aに接続されている。また、メモリユニットＭＵ_A2において、メモリセルＭＣ_A2Mの第１の電極３１は共通であり（この共通の第１の電極を第２の共通ノードＣＮ_A2と呼ぶ）、共通の第１の電極３１（第２の共通ノードＣＮ_A2）は、選択用トランジスタＴＲ_SA、及び、書込用トランジスタＴＲ_Wを介してビット線ＢＬ_Aに接続されている。更には、第ｎ層目（但し、ｎ＝１，２・・・，Ｎ）のメモリユニットＭＵ_Anにおいて、第ｍ番目（但し、ｍ＝１，２・・・，Ｍ）のメモリセルＭＣ_Anmの第２の電極２３，３３は、第［（ｎ−１）Ｍ＋ｍ］番目のプレート線ＰＬ_(n-1)M+mに接続されている。尚、このプレート線ＰＬ_(n-1)M+mは、プレート線の延びる方向に隣接する不揮発性メモリＭ_BのメモリユニットブロックＭＢ_Bを構成する各メモリセルＭＣ_BNMの第２の電極２３，３３にも接続されている。実施の形態２においては、より具体的には、各プレート線は、第２の電極２３，３３から延在している。
【０１２８】
選択用トランジスタＴＲ_SAの一方のソース／ドレイン領域１４は、接続孔１８Ｃ、サブビット線１９、接続孔１８Ｂ、書込用トランジスタＴＲ_Wを介してビット線ＢＬ_Aに接続されている。一方、選択用トランジスタＴＲ_SAの他方のソース／ドレイン領域１４は、絶縁層１６に設けられた接続孔１７を介して、第１層目のメモリユニットＭＵ_A1における共通の第１の電極２１（第１の共通ノードＣＮ_A1）に接続されている。更には、選択用トランジスタＴＲ_SAの他方のソース／ドレイン領域１４は、絶縁層１６に設けられた接続孔１７、及び、層間絶縁層２６に設けられた接続孔２７を介して、第２層目のメモリユニットＭＵ_A2における共通の第１の電極３１（第２の共通ノードＣＮ_A2）に接続されている。尚、図中、参照番号３６Ａは絶縁膜である。
【０１２９】
ビット線ＢＬ_Aは、センスアンプＳＡに接続されている。また、プレート線ＰＬ_(n-1)M+mはプレート線デコーダ／ドライバＰＤに接続されている。更には、ワード線ＷＬ_Sは、ワード線デコーダ／ドライバＷＤに接続されている。ワード線ＷＬは、図１１の紙面垂直方向に延びている。また、不揮発性メモリＭ_AのメモリユニットブロックＭＢ_Aを構成するメモリセルＭＣ_A1mの第２の電極２３は、図１１の紙面垂直方向に隣接する別の不揮発性メモリＭ_BのメモリユニットブロックＭＢ_Bを構成するメモリセルＭＣ_B1mの第２の電極と共通であり、プレート線ＰＬ_(n-1)M+mを兼ねている。更には、不揮発性メモリＭ_AのメモリユニットブロックＭＢ_Aを構成するメモリセルＭＣ_A2mの第２の電極３３は、図１１の紙面垂直方向に隣接する別の不揮発性メモリＭ_BのメモリユニットブロックＭＢ_Bを構成するメモリセルＭＣ_B2mの第２の電極と共通であり、プレート線ＰＬ_(n-1)M+mを兼ねている。また、ワード線ＷＬ_Sは、不揮発性メモリＭ_Aを構成する選択用トランジスタＴＲ_SAと、図１１の紙面垂直方向に隣接する別の不揮発性メモリＭ_Bを構成する選択用トランジスタＴＲ_SBとで共通である。
【０１３０】
検出用トランジスタＴＲ_Dの一端は所定の電位（例えば、電源Ｖ_cc）を有する配線に接続され、他端は読出用トランジスタＴＲ_Rを介してビット線ＢＬ_Aに接続されている。書込用トランジスタＴＲ_W、読出用トランジスタＴＲ_R、及び、検出用トランジスタＴＲ_Dの構成、これらの動作、これらとメモリユニットブロックとの関係は、実質的に実施の形態１と同様とすることができるので、詳細な説明は省略する。
【０１３１】
そして、メモリユニットブロックＭＢ_Aの例えばメモリセルＭＣ_Anmへのデータの書き込み時、
▲１▼ 書込用トランジスタＴＲ_W、及び、
▲２▼ メモリユニットブロックＭＢ_Aの選択用トランジスタＴＲ_SA、
が導通状態とされ、
▲３▼ 読出用トランジスタＴＲ_R、及び、
▲４▼ メモリユニットブロックＭＢ_A以外のメモリユニットブロックＭＢ_A’の選択用トランジスタＴＲ_SA’、
が非導通状態とされ、
メモリユニットブロックＭＢ_Aの例えばメモリセルＭＣ_Anmに記憶されたデータの読み出し時、
▲１▼ 書込用トランジスタＴＲ_W、及び、
▲２▼ メモリユニットブロックＭＢ_A以外のメモリユニットブロックＭＢ_A’の選択用トランジスタＴＲ_SA’、
が非導通状態とされ、
▲３▼ 読出用トランジスタＴＲ_R、及び、
▲４▼ メモリユニットブロックＭＢ_Aの選択用トランジスタＴＲ_SA、
が導通状態とされ、メモリユニットブロックＭＢ_Aの例えばメモリセルＭＣ_Anmに記憶されたデータに基づき共通の第１の電極（ＣＮ_An）に生じた電位により、検出用トランジスタＴＲ_Dの動作が制御される。
【０１３２】
図１０に回路図を示す不揮発性メモリＭ_A，Ｍ_Bにおいて、不揮発性メモリＭ_A，Ｍ_Bを構成する選択用トランジスタＴＲ_SA，ＴＲ_SBは同じワード線ＷＬ_Sに接続されている。そして、対となったメモリセルＭＣ_Anm，ＭＣ_Bnm（ｎ＝１，２・・・，Ｎ、及び、ｍ＝１，２・・・，Ｍ）に相補的なデータが記憶される。例えば、メモリセルＭＣ_Anm，ＭＣ_Bnm（ここで、ｍは１，２・・・，８のいずれか）に記憶されたデータを読み出す場合、ワード線ＷＬ_Sを選択し、プレート線ＰＬ_j（ｍ≠ｊ）には、例えば（１／２）Ｖ_ccの電圧を印加した状態で、プレート線ＰＬ_(n-1)M+mを駆動する。ここで、Ｖ_ccは、例えば、電源電圧である。これによって、相補的なデータに相当する電位が、対となったメモリセルＭＣ_Anm，ＭＣ_Bnmから共通ノードＣＮ_An，ＣＮ_Bnに出現し、その結果、検出用トランジスタＴＲ_D，検出用トランジスタＴＲ_BD（この検出用トランジスタＴＲ_BDは、不揮発性メモリＭ_Bを構成する検出用トランジスタである）の動作が制御され、相補的なデータに相当する電位が、検出用トランジスタＴＲ_D、読出用トランジスタＴＲ_R、及び、検出用トランジスタＴＲ_BD、読出用トランジスタＴＲ_BR（この読出用トランジスタＴＲ_BRは、不揮発性メモリＭ_Bを構成する読出用トランジスタである）を介して対となったビット線ＢＬ_A，ＢＬ_Bに電圧（ビット線電位）として現れる。そして、かかる対となったビット線ＢＬ_A，ＢＬ_Bの電圧（ビット線電位）を、センスアンプＳＡで検出する。
【０１３３】
以下、実施の形態２の不揮発性メモリからデータを読み出し、再書き込みする方法について説明する。尚、一例として、対となった不揮発性メモリＭ_A，Ｍ_Bにおける対となった（即ち、プレート線が共通である）メモリセルＭＣ_A11，ＭＣ_B11からデータを読み出すものとし、メモリセルＭＣ_A11にはデータ「１」が、メモリセルＭＣ_B11にはデータ「０」が記憶されているとする。図１２に動作波形を示す。尚、図１２中、括弧内の数字は、以下に説明する工程の番号と対応している。
【０１３４】
（１Ｃ）待機状態では、ビット線、ワード線、全プレート線が０ボルトとなっている。更には、共通ノードＣＮ_A1，ＣＮ_A2，ＣＮ_B1，ＣＮ_B2も０ボルトで浮遊状態となっている。データの読出し時、及び、再書込み時、メモリユニットブロックＭＢ_A，ＭＢ_B以外のメモリユニットブロックＭＢ_A’，ＭＢ_Bの選択用トランジスタは、常にオフ状態にある。
【０１３５】
（２Ｃ）データ読み出し時、選択プレート線ＰＬ₁にＶ_ccを印加する。このとき、選択メモリセルＭＣ_A11にはデータ「１」が記憶されているので、強誘電体層に分極反転が生じ、蓄積電荷量が増加し、共通ノードＣＮ_A1，ＣＮ_A2の電位が上昇する。一方、選択メモリセルＭＣ_B11にはデータ「０」が記憶されているので、強誘電体層に分極反転が生ぜず、共通ノードＣＮ_B1，ＣＮ_B2の電位は殆ど上昇しない。即ち、共通ノードＣＮ_B1，ＣＮ_B2は、非選択メモリセルの強誘電体層を介して複数の非選択プレート線ＰＬ_jにカップリングされているので、共通ノードＣＮ_B1，ＣＮ_B2の電位は０ボルトに比較的近いレベルに保たれる。このようにして、選択メモリセルＭＣ_A11，ＭＣ_B11に記憶されたデータに依存して共通ノードＣＮ_A1，ＣＮ_A2，ＣＮ_B1，ＣＮ_B2の電位に変化が生じる。従って、選択メモリセルの強誘電体層には、分極反転に十分な電界を与えることができる。
【０１３６】
（３Ｃ）次に、ビット線ＢＬ_A，ＢＬ_Bを浮遊状態とし、選択用トランジスタＴＲ_SA，ＴＲ_SB及び読出用トランジスタＴＲ_R，ＴＲ_BR（この読出用トランジスタＴＲ_BRは、不揮発性メモリＭ_Bを構成する読出用トランジスタである）をオン状態とする。これによって、選択メモリセルＭＣ_A11に記憶されたデータに基づき共通の第１の電極（共通ノードＣＮ_A1，ＣＮ_A2）に生じた電位により、検出用トランジスタＴＲ_Dの動作が制御され、選択メモリセルＭＣ_B11に記憶されたデータに基づき共通の第１の電極（共通ノードＣＮ_B1，ＣＮ_B2）に生じた電位により、検出用トランジスタＴＲ_BD（この検出用トランジスタＴＲ_BDは、不揮発性メモリＭ_Bを構成する検出用トランジスタである）の動作が制御される。具体的には、検出用トランジスタＴＲ_Dの一方のソース／ドレイン領域１４は所定の電位Ｖ_ccを有する配線（電位：Ｖ_cc）に接続されており、選択メモリセルＭＣ_A11にデータ「１」が記憶されているので、検出用トランジスタＴＲ_Dがオン状態となり、かかる配線から検出用トランジスタＴＲ_D及び読出用トランジスタＴＲ_Rを介してビット線ＢＬ_Aに電流が流れ、ビット線ＢＬ_Aの電位が上昇する。一方、選択メモリセルＭＣ_B11にはデータ「０」が記憶されているので、検出用トランジスタＴＲ_BDはオフ状態となり、ビット線ＢＬ_Bの電位は上昇しない。
【０１３７】
（４Ｃ）次いで、選択用トランジスタＴＲ_SA，ＴＲ_SB及び読出用トランジスタＴＲ_R，ＴＲ_BRをオフ状態とする。
【０１３８】
（５Ｃ）その後、ビット線ＢＬに接続されたセンスアンプＳＡを活性化してデータを増幅し、データの読み出し動作を完了する。
【０１３９】
以上の動作によって、選択メモリセルＭＣ_A11，ＭＣ_B11に記憶されていたデータが一旦破壊されてしまうので、データの再書き込み動作を行う。
【０１４０】
（６Ｃ）そのために、先ず、非選択プレート線ＰＬ_j（ｊ≠１）の電位を（１／２）Ｖ_ccとする。
【０１４１】
（７Ｃ）その後、選択用トランジスタＴＲ_SA，ＴＲ_SB、及び、書込用トランジスタＴＲ_W，ＴＲ_BW（この書込用トランジスタＴＲ_BWは、不揮発性メモリＭ_Bを構成する書込用トランジスタである）をオン状態とする。これによって、共通ノードＣＮ_A1，ＣＮ_A2，ＣＮ_B1，ＣＮ_B2の電位はビット線ＢＬ_A，ＢＬ_Bの電位と等しくなる。即ち、選択メモリセルＭＣ_A11に記憶されていたデータが「１」の場合には、共通ノードＣＮ_A1，ＣＮ_A2の電位はＶ_ccとなり、選択メモリセルＭＣ_B11に記憶されていたデータが「０」の場合には、共通ノードＣＮ_B1，ＣＮ_B2の電位は０ボルトとなる。選択プレート線ＰＬ₁の電位はＶ_ccのままであるが故に、共通ノードＣＮ_B1，ＣＮ_B2の電位が０ボルトの場合、選択メモリセルＭＣ_B11にはデータ「０」が再書き込みされる。
【０１４２】
（８Ｃ）次に、選択プレート線ＰＬ₁の電位を０ボルトとする。これによって、選択メモリセルＭＣ_A11に記憶されていたデータが「１」の場合には、共通ノードＣＮ_A1，ＣＮ_A2の電位がＶ_ccであるが故に、データ「１」が再書き込みされる。選択メモリセルＭＣ_B11にデータ「０」が既に再書き込みされていた場合には、選択メモリセルに変化は生じない。
【０１４３】
（９Ｃ）その後、ビット線ＢＬを０ボルトとする。
【０１４４】
（１０Ｃ）最後に、非選択プレート線ＰＬ_jを０ボルトとし、選択用トランジスタＴＲ_SA，ＴＲ_SB、及び、書込用トランジスタＴＲ_W，ＴＲ_BWをオフ状態とする。
【０１４５】
他のメモリセル（ＭＣ_Anm，ＭＣ_Bnm）からデータを読み出し、データを再書き込みする場合には、同様の操作を繰り返す。
【０１４６】
不揮発性メモリＭ_A，Ｍ_Bを構成する選択用トランジスタＴＲ_SA，ＴＲ_SBを、それぞれ、異なるワード線ＷＬ_SA，ＷＬ_SBに接続し、メモリセルＭＣ_Anm，ＭＣ_Bnmを独立して制御し、例えばダミーセル等を用いて、対となったビット線ＢＬ_A，ＢＬ_Bの一方に参照電圧（データ「１」の読み出し電位と、データ「０」の読み出し電位の中間の参照電位）を印加することによって、メモリセルＭＣ_Anm，ＭＣ_Bnmのそれぞれからデータを読み出すこともできる。このような構成を採用する場合の回路図は、図１３を参照のこと。尚、選択用トランジスタＴＲ_SA，ＴＲ_SBを同時に駆動すれば、図１０に示した回路と等価となる。
【０１４７】
このように、各メモリセルＭＣ_Anm，ＭＣ_Bnm（ｎ＝１，２であり、ｍ＝１，２・・・，８）のそれぞれに１ビットがデータとして記憶され（図１３の参照）、あるいは又、対となったメモリセルＭＣ_Anm，ＭＣ_Bnmに相補的なデータが１ビットとして記憶される（図１０参照）。実際の不揮発性メモリにおいては、この１６ビットあるいは８ビットを記憶するメモリユニットの集合がアクセス単位ユニットとしてアレイ状に配設されている。そして、選択用トランジスタのワード線ＷＬ_S（ＷＬ_SA，ＷＬ_SB）、プレート線ＰＬ_(n-1)M+mが共有された複数のアクセス単位ユニットに対して、一括して、データの書き込み、あるいは、データの読み出し及び再書き込みを行う。即ち、メモリアレイにおいては、全ての不揮発性メモリが一括して、順次、作動状態となり、あるいは又、一括して不作動（待機）状態となる。
【０１４８】
対となった不揮発性メモリにおける一対の選択用トランジスタＴＲ_SA及びＴＲ_SBは、ワード線ＷＬ_S、及び、対となったビット線ＢＬ_A，ＢＬ_Bによって囲まれた領域を占めている。従って、仮に、ワード線及びビット線が最短ピッチで配置されるとすると、対となった不揮発性メモリにおける一対の選択用トランジスタＴＲ_SA及びＴＲ_SBの最小面積は、８Ｆ²である。しかしながら、トランジスタＴＲ_SA，ＴＲ_SB，ＴＲ_W，ＴＲ_R，ＴＲ_Dを、Ｍ組の対となったメモリセルＭＣ_A1m，ＭＣ_A2m，ＭＣ_B1m，ＭＣ_B2m（ｍ＝１，２・・・，Ｍ）で共有するが故に、１ビット当たりの選択用トランジスタＴＲ_SA，ＴＲ_SBの数が少なくて済み、また、ワード線ＷＬ_Sの配置も緩やかなので、不揮発性メモリの縮小化を図り易い。しかも、周辺回路についても、１本のワード線デコーダ／ドライバＷＤとＭ本のプレート線デコーダ／ドライバＰＤでＭビットを選択することができる。従って、このような構成を採用することで、セル面積が８Ｆ²に近いレイアウトを実現可能であり、ＤＲＡＭ並のチップサイズを実現することができる。
【０１４９】
（実施の形態３）
実施の形態３は、本発明の第５の態様及び第６の態様に係るゲインセルタイプの不揮発性メモリに関する。実施の形態３の不揮発性メモリの回路図を図１４に示し、図１４におけるメモリユニットのより具体的な回路図を図１５に示す。また、不揮発性メモリを切断したときのビット線の延びる方向と平行における実施の形態３の不揮発性メモリの模式的な一部断面図を図１６に示す。図においては、ビット線方向に隣接する２つのメモリユニットブロック（１つの不揮発性メモリを構成する）を図示するが、メモリユニットブロックの一方の構成要素の参照番号には「’」を付した。尚、２つのメモリユニットブロックは同一の構成であるが故に、以下、一方のメモリユニットブロックについて説明を行う。ここで、図１５には、プレート線の延びる方向に隣接する別の不揮発性メモリＭ_Bにおける１つのメモリユニットブロックＭＢ_Bを示すが、このメモリユニットブロックＭＢ_BはメモリユニットブロックＭＢ_Aと同じ構成を有する。
【０１５０】
実施の形態３の不揮発性メモリＭ_Aは、
（Ａ）信号検出回路と、
（Ｂ）複数のメモリユニットブロックＭＢ_A，ＭＢ_A’、
から成り、
例えば、メモリユニットブロックＭＢ_Aは、
（Ｂ−１）Ｎ個（但し、Ｎ≧２であり、実施の形態３においては、Ｎ＝２）の選択用トランジスタＴＲ_SANと、
（Ｂ−２）それぞれがＭ個（但し、Ｍ≧２であり、実施の形態３においては、Ｍ＝８）のメモリセルＭＣ_ANMから構成された、Ｎ個のメモリユニットＭＵ_ANと、
（Ｂ−３）Ｍ本のプレート線ＰＬ_M、
から成る。
【０１５１】
そして、メモリユニットブロックＭＢ_AにおけるＮ個のメモリユニットＭＵ_ANは、絶縁層（層間絶縁層２６）を介して積層されている。各メモリセルＭＣ_Anmは、第１の電極２１，３１と強誘電体層２２，３２と第２の電極２３，３３とから成り、メモリユニットブロックＭＢ_Aの各メモリユニットＭＵ_Anにおいて、メモリセルＭＣ_Anmの第１の電極２１，３１は共通であり、メモリユニットブロックＭＢ_Aの第ｎ番目（但し、ｎ＝１，２・・・，Ｎ）のメモリユニットＭＵ_Anにおける共通の第１の電極は、メモリユニットブロックＭＢ_Aの第ｎ番目の選択用トランジスタＴＲ_SAnを介して、信号検出回路に接続されている。更には、メモリユニットブロックＭＢ_Aの第ｎ番目のメモリユニットＭＵ_Anにおいて、第ｍ番目（但し、ｍ＝１，２・・・，Ｍ）のメモリセルＭＣ_Anmの第２の電極は、メモリユニットブロックＭＢ_AのメモリユニットＭＵ_An間で共通とされた第ｍ番目のプレート線ＰＬ_mに接続されている。そして、信号検出回路は、メモリユニットブロックＭＢ_AのメモリユニットＭＵ_Anにおける共通の第１の電極の電位変化（メモリセルＭＣ_Anmに記憶されたデータに基づく）を検出し、この検出結果をビット線ＢＬ_Aに電流又は電圧として伝達する。この信号検出回路は、具体的には、次に説明する書込用トランジスタＴＲ_Wと、読出用トランジスタＴＲ_Rと、検出用トランジスタＴＲ_Dから構成されている。
【０１５２】
あるいは又、実施の形態３の不揮発性メモリＭ_Aは、
（Ａ）ビット線ＢＬ_Aと、
（Ｂ）書込用トランジスタＴＲ_Wと、
（Ｃ）読出用トランジスタＴＲ_Rと、
（Ｄ）検出用トランジスタＴＲ_Dと、
（Ｅ）複数のメモリユニットブロックＭＢ_A，ＭＢ_A’、
から成り、
例えば、メモリユニットブロックＭＢ_Aは、
（Ｅ−１）Ｎ個（但し、Ｎ≧２であり、実施の形態３においては、Ｍ＝２）の選択用トランジスタＴＲ_SANと、
（Ｅ−２）それぞれがＭ個（但し、Ｍ≧２であり、実施の形態３においては、Ｍ＝８）のメモリセルＭＣ_ANMから構成された、Ｎ個のメモリユニットＭＵ_ANと、
（Ｅ−３）Ｍ本のプレート線ＰＬ_M、
から成る。
【０１５３】
そして、メモリユニットブロックＭＢ_AにおけるＮ個のメモリユニットＭＵ_ANは、絶縁層（層間絶縁層２６）を介して積層されている。各メモリセルは、第１の電極と強誘電体層と第２の電極とから成る。具体的には、第１番目（以下、第１層目と呼ぶ）のメモリユニットＭＵ_A1を構成する各メモリセルＭＣ_A1Mは、第１の電極２１と強誘電体層２２と第２の電極２３とから成り、第２番目（以下、第２層目と呼ぶ）のメモリユニットＭＵ_A2を構成する各メモリセルＭＣ_A2Mは、第１の電極３１と強誘電体層３２と第２の電極３３とから成る。更には、各メモリユニットＭＵ_Anにおいて、メモリセルＭＣ_Anmの第１の電極２１，３１は共通である。具体的には、第１層目のメモリユニットＭＵ_A1において、メモリセルＭＣ_A1Mの第１の電極２１は共通である。この共通の第１の電極２１を第１の共通ノードＣＮ_A1と呼ぶ場合がある。また、第２層目のメモリユニットＭＵ_A2において、メモリセルＭＣ_A2Mの第１の電極３１は共通である。この共通の第１の電極３１を第２の共通ノードＣＮ_A2と呼ぶ場合がある。更には、第ｎ番目（但し、ｎ＝１，２・・・，Ｎであり、第ｎ層目と呼ぶ）のメモリユニットＭＵ_Anにおいて、第ｍ番目（但し、ｍ＝１，２・・・，Ｍ）のメモリセルの第２の電極２３，３３は、メモリユニットＭＵ_An間で共通とされた第ｍ番目のプレート線ＰＬ_mに接続されている。実施の形態３においては、より具体的には、各プレート線は、第２の電極２３，３３から延在している。
【０１５４】
第ｎ層目（但し、ｎ＝１，２・・・，Ｎ）のメモリユニットＭＵ_Anにおける共通の第１の電極は、第ｎ番目の選択用トランジスタＴＲ_SAn、及び、書込用トランジスタＴＲ_Wを介してビット線ＢＬ_Aに接続されている。具体的には、各選択用トランジスタＴＲ_SA1，ＴＲ_SA2の一方のソース／ドレイン領域１４は、接続孔１８Ｃ、サブビット線１９、接続孔１８Ｂ、書込用トランジスタＴＲ_Wを介してビット線ＢＬ_Aに接続されている。一方、第１番目の選択用トランジスタＴＲ_SA1の他方のソース／ドレイン領域１４は、絶縁層１６に設けられた接続孔１７を介して、第１層目のメモリユニットＭＵ_A1における共通の第１の電極２１（第１の共通ノードＣＮ_A1）に接続されている。また、第２番目の選択用トランジスタＴＲ_SA2の他方のソース／ドレイン領域１４は、絶縁層１６に設けられた接続孔１７、パッド部２５、及び、層間絶縁層２６に設けられた接続孔２７を介して、第２層目のメモリユニットＭＵ_A2における共通の第１の電極３１（第２の共通ノードＣＮ_A2）に接続されている。
【０１５５】
ビット線ＢＬ_Aは、センスアンプＳＡに接続されている。また、プレート線ＰＬ_Mはプレート線デコーダ／ドライバＰＤに接続されている。更には、ワード線ＷＬ_S1，ＷＬ_S2は、ワード線デコーダ／ドライバＷＤに接続されている。ワード線ＷＬ_S1，ＷＬ_S2は、図１６の紙面垂直方向に延びている。また、不揮発性メモリＭ_Aを構成するメモリセルＭＣ_A1mの第２の電極２３は、図１６の紙面垂直方向に隣接する不揮発性メモリＭ_Bを構成するメモリセルＭＣ_B1mの第２の電極２３と共通であり、プレート線ＰＬ_mを兼ねている。更には、不揮発性メモリＭ_Aを構成するメモリセルＭＣ_A2Mの第２の電極３３は、図１６の紙面垂直方向に隣接する不揮発性メモリＭ_Bを構成するメモリセルＭＣ_B2mの第２の電極３３と共通であり、プレート線ＰＬ_mを兼ねている。これらのプレート線ＰＬ_mは、図示しない領域において接続されている。また、ワード線ＷＬ_S1は、不揮発性メモリＭ_Aを構成する選択用トランジスタＴＲ_SA1と、図１６の紙面垂直方向に隣接する不揮発性メモリＭ_Bを構成する選択用トランジスタＴＲ_SB1とで共通である。更には、ワード線ＷＬ_S2は、不揮発性メモリＭ_Aを構成する選択用トランジスタＴＲ_SA2と、図１６の紙面垂直方向に隣接する不揮発性メモリＭ_Bを構成する選択用トランジスタＴＲ_SB2とで共通である。
【０１５６】
検出用トランジスタＴＲ_Dの一端は所定の電位（例えば、電源Ｖ_cc）を有する配線に接続され、他端は読出用トランジスタＴＲ_Rを介してビット線ＢＬ_Aに接続されている。書込用トランジスタＴＲ_W、読出用トランジスタＴＲ_R、及び、検出用トランジスタＴＲ_Dの構成、これらの動作、これらとメモリユニットブロックとの関係は、実質的に実施の形態１と同様とすることができるので、詳細な説明は省略する。
【０１５７】
そして、例えば、メモリユニットブロックＭＢ_Aの第ｎ番目のメモリユニットＭＵ_AnのメモリセルＭＣ_Anmへのデータの書き込み時、
▲１▼ 書込用トランジスタＴＲ_W、及び、
▲２▼ メモリユニットブロックＭＢ_Aの第ｎ番目の選択用トランジスタＴＲ_SAn、が導通状態とされ、
▲３▼ 読出用トランジスタＴＲ_R、
▲４▼ メモリユニットブロックＭＢ_Aの第ｎ番目の選択用トランジスタＴＲ_SAn以外の選択用トランジスタ、及び、
▲５▼ メモリユニットブロックＭＢ_A以外のメモリユニットブロックＭＢ_A’の選択用トランジスタＴＲ_SAN’、
が非導通状態とされ、
メモリユニットブロックＭＢ_Aの第ｎ番目のメモリユニットＭＵ_AnのメモリセルＭＣ_Anmに記憶されたデータの読み出し時、
▲１▼ 書込用トランジスタＴＲ_W、
▲２▼ メモリユニットブロックＭＢ_Aの第ｎ番目の選択用トランジスタＴＲ_SAn以外の選択用トランジスタ、及び、
▲３▼ メモリユニットブロックＭＢ_A以外のメモリユニットブロックＭＢ_A’の選択用トランジスタＴＲ_SAN’、
が非導通状態とされ、
▲４▼ 読出用トランジスタＴＲ_R、及び、
▲５▼ メモリユニットブロックＭＢ_Aの第ｎ番目の選択用トランジスタＴＲ_SAn、が導通状態とされ、メモリユニットブロックＭＢ_Aの第ｎ番目のメモリユニットＭＵ_AnのメモリセルＭＣ_Anmに記憶されたデータに基づき共通の第１の電極（共通ノードＣＮ_An）に生じた電位により、検出用トランジスタＴＲ_Dの動作が制御される。
【０１５８】
図１５に回路図を示す不揮発性メモリＭ_A，Ｍ_Bにおいて、選択用トランジスタＴＲ_SAn，ＴＲ_SBnは同じワード線ＷＬ_Snに接続されている。そして、対となったメモリセルＭＣ_Anm，ＭＣ_Bnm（ｎ＝１，２・・・，Ｎ、及び、ｍ＝１，２・・・，Ｍ）に相補的なデータが記憶される。例えば、メモリセルＭＣ_Anm，ＭＣ_Bnm（ここで、ｍは１，２・・・，８のいずれか）に記憶されたデータを読み出す場合、ワード線ＷＬ_Snを選択し、プレート線ＰＬ_j（ｍ≠ｊ）には、例えば（１／２）Ｖ_ccの電圧を印加した状態で、プレート線ＰＬ_mを駆動する。ここで、Ｖ_ccは、例えば、電源電圧である。これによって、相補的なデータに相当する電位が、対となったメモリセルＭＣ_Anm，ＭＣ_Bnmから共通ノードＣＮ_An，ＣＮ_Bnに出現し、その結果、検出用トランジスタＴＲ_D，検出用トランジスタＴＲ_BD（この検出用トランジスタＴＲ_BDは、不揮発性メモリＭ_Bを構成する検出用トランジスタである）の動作が制御され、相補的なデータに相当する電位が、検出用トランジスタＴＲ_D、読出用トランジスタＴＲ_R、及び、検出用トランジスタＴＲ_BD、読出用トランジスタＴＲ_BR（この読出用トランジスタＴＲ_BRは、不揮発性メモリＭ_Bを構成する読出用トランジスタである）を介して対となったビット線ＢＬ_A，ＢＬ_Bに電圧（ビット線電位）として現れる。そして、かかる対となったビット線ＢＬ_A，ＢＬ_Bの電圧（ビット線電位）を、センスアンプＳＡで検出する。
【０１５９】
以下、実施の形態３の不揮発性メモリからデータを読み出し、再書き込みする方法について説明する。尚、一例として、対となった不揮発性メモリＭ_A，Ｍ_Bにおける対となった（即ち、プレート線が共通である）メモリセルＭＣ_A11，ＭＣ_{B 11}からデータを読み出すものとし、メモリセルＭＣ_A11にはデータ「１」が、メモリセルＭＣ_B11にはデータ「０」が記憶されているとする。図１７に動作波形を示す。尚、図１７中、括弧内の数字は、以下に説明する工程の番号と対応している。
【０１６０】
（１Ｄ）待機状態では、ビット線、ワード線、全プレート線が０ボルトとなっている。更には、共通ノードＣＮも０ボルトで浮遊状態となっている。データの読出し時、及び、再書込み時、メモリユニットブロックＭＢ_A，ＭＢ_B以外のメモリユニットブロックＭＢ_A’，ＭＢ_B’の選択用トランジスタは、常にオフ状態にある。
【０１６１】
（２Ｄ）データ読み出しが開始されると、先ず、選択されたメモリユニット（アクセス単位ユニット）における全プレート線ＰＬ_m（ｍ＝１，２，・・・，８）を（１／２）Ｖ_cc（但し、Ｖ_ccは電源電圧）にプレチャージし、更に、ビット線ＢＬ_A，ＢＬ_Bを（１／２）Ｖ_ccにプレチャージする。その後、ワード線ＷＬ_W、ワード線ＷＬ_S1，ＷＬ_S2をハイレベルとすることによって、書込用トランジスタＴＲ_W，ＴＲ_BW（この書込用トランジスタＴＲ_BWは、不揮発性メモリＭ_Bを構成する書込用トランジスタである）、選択用トランジスタＴＲ_SA1，ＴＲ_SA2，ＴＲ_SB1，ＴＲ_SB2をオン状態とする。これによって、共通の第１の電極２１（共通ノードＣＮ_A1，ＣＮ_A2、ＣＮ_B1，ＣＮ_B2）がビット線ＢＬ_A，ＢＬ_Bに接続され、共通ノードＣＮ_A1，ＣＮ_A2，ＣＮ_B1，ＣＮ_B2の電位は（１／２）Ｖ_ccとなる。
【０１６２】
（３Ｄ）次いで、非選択のワード線ＷＬ_S2をロウレベルとすることによって、選択用トランジスタＴＲ_SA2，ＴＲ_SB2をオフ状態とする。これによって、非選択の共通ノードＣＮ_A2，ＣＮ_B2は、電位が（１／２）Ｖ_ccのまま、浮遊状態となる。
【０１６３】
（４Ｄ）その後、選択プレート線ＰＬ₁、及び、ビット線ＢＬ_A，ＢＬ_Bを接地線（図示せず）を介して０ボルトまで放電させる。このとき、ビット線ＢＬ_A，ＢＬ_Bに接続されている共通ノードＣＮ_A1，ＣＮ_B1も０ボルトとなる。ビット線ＢＬ_A，ＢＬ_Bの放電が完了したならば、接地線とビット線ＢＬ_A，ＢＬ_Bとの電気的な接続を解き、ビット線ＢＬ_A，ＢＬ_Bを浮遊状態とする。
【０１６４】
（５Ｄ）次に、ワード線ＷＬ_Wをロウレベルとすることによって、書込用トランジスタＴＲ_W，ＴＲ_BWをオフ状態し、次いで、ワード線ＷＬ_Rをハイレベルとすることによって、読出用トランジスタＴＲ_R，ＴＲ_BR（この読出用トランジスタＴＲ_BRは、不揮発性メモリＭ_Bを構成する読出用トランジスタである）をオン状態とする。一方、選択プレート線ＰＬ₁にＶ_ccを印加する。これによって、データ「１」を記憶していたメモリセルＭＣ_A11からは、反転電荷が放出され、その結果、検出用トランジスタＴＲ_Dがオン状態となり、配線（電位：Ｖ_cc）から検出用トランジスタＴＲ_D及び読出用トランジスタＴＲ_Rを介してビット線ＢＬ_Aに電流が流れ、ビット線ＢＬ_Aの電位が上昇する。一方、選択メモリセルＭＣ_B11にはデータ「０」が記憶されているので、検出用トランジスタＴＲ_BD（この検出用トランジスタＴＲ_BDは、不揮発性メモリＭ_Bを構成する検出用トランジスタである）はオフ状態となり、ビット線ＢＬ_Bの電位は上昇しない。このようにして、ビット線ＢＬ_A，ＢＬ_Bの間に電位差が生じる。次に、センスアンプＳＡを活性化して、かかるビット線ＢＬ_A，ＢＬ_Bの間の電位差をデータとして読み出す。
【０１６５】
（６Ｄ）次いで、読出用トランジスタＴＲ_R，ＴＲ_BRをオフ状態とする。
【０１６６】
（７Ｄ）その後、ビット線ＢＬ_A，ＢＬ_Bを、センスアンプＳＡによって充放電させ、ビット線ＢＬ_AにはＶ_ccを印加し、ビット線ＢＬ_Bには０ボルトを印加する。
【０１６７】
（８Ｄ）次いで、書込用トランジスタＴＲ_W，ＴＲ_BWをオン状態とする。その結果、メモリセルＭＣ_B11には、データ「０」が再び書き込まれる。
【０１６８】
（９Ｄ）その後、選択プレート線ＰＬ₁を０ボルトとすることによって、メモリセルＭＣ_A11には、データ「１」が再び書き込まれる。
【０１６９】
（１０Ｄ）データの読み出しを終了する場合には、次いで、ビット線ＢＬ_A，ＢＬ_Bを０ボルトまで放電する。次に、プレート線ＰＬ_m（ｍ＝１，２，・・・，８）を０ボルトまで放電した後、非選択のワード線ＷＬ_S2を再びハイレベルとし、選択用トランジスタＴＲ_SA2，ＴＲ_SB2をオン状態として、メモリユニット（アクセス単位ユニット）の全ての共通ノードＣＮ_A1，ＣＮ_A2，ＣＮ_B1，ＣＮ_B2を０ボルトとする。
【０１７０】
尚、引き続き、対となった次のメモリセルのデータを読み出す場合には、再び、全プレート線ＰＬ_m（ｍ＝１，２，・・・，８）を（１／２）Ｖ_ccにプレチャージし、上述の（２Ｄ）〜（９Ｄ）の動作を繰り返す。
【０１７１】
以上のシーケンスに従えば、非選択のメモリセルに加わるディスターブは、常に、（１／２）Ｖ_cc以下に抑えられる。
【０１７２】
尚、非選択状態であって、しかも、浮遊状態の共通ノードＣＮ_B1，ＣＮ_B2の電位は、選択プレート線ＰＬ₁と（１／２）Ｖ_ccに固定された非選択プレート線ＰＬ_j（ｊ＝２，・・・，８）とのカップリング比に従って変動するが、非選択プレート線側のカップリング容量の方が大きい。従って、共通ノードＣＮ_A2，ＣＮ_B2の電位変動は、（１／２）Ｖ_cc〜Ｖ_ccの範囲に抑えられ、メモリセルＭＣ_A2m，ＭＣ_B2m（ｍ＝１〜８）に加わるディスターブは、（１／２）Ｖ_cc以下である。
【０１７３】
また、このような回路構成においては、ディスターブ回数を有限回に制限するために、プレート線又は共通ノードを共有する全メモリセルを一括して、且つ、連続してシリアルにアクセスする仕様とすることが望ましい。即ち、ワード線ＷＬ_S1にアクセスした場合には、共通ノードＣＮ_A1，ＣＮ_B1に関連したメモリセル_A1m，ＭＣ_B1m（ｍ＝１，２，・・・，８）の全てを、順次アクセスする。続いて、ワード線ＷＬ_S2にアクセスし、共通ノードＣＮ_A2，ＣＮ_B2に関連したメモリセルＭＣ_A2m，ＭＣ_B2m（ｍ＝１，２，・・・，８）の全てを、順次アクセスする。これにより、メモリユニット（アクセス単位ユニット）内のメモリセルの全てからデータを読み出し、その後、再書き込みを行って、ディスターブによる劣化を回復させる。このようにすれば、ディスターブ回数の上限は、メモリユニット（アクセス単位ユニット）に記憶されるビット数から１を減じた回数となり、信頼性を保証することができる。以上に説明した実施の形態３におけるディスターブ回数は７回である。
【０１７４】
不揮発性メモリＭ_A，Ｍ_Bを構成する選択用トランジスタＴＲ_SAn，ＴＲ_SBnを、それぞれ、異なるワード線ＷＬ_SAn，ＷＬ_SBnに接続し、メモリセルＭＣ_Anm，ＭＣ_Bnmを独立して制御し、例えばダミーセル等を用いて、対となったビット線ＢＬ_A，ＢＬ_Bの一方に参照電圧（データ「１」の読み出し電位と、データ「０」の読み出し電位の中間の参照電位）を印加することによって、メモリセルＭＣ_Anm，ＭＣ_Bnmのそれぞれからデータを読み出すこともできる。このような構成を採用する場合の回路図は、図１８を参照のこと。尚、選択用トランジスタＴＲ_SAn，ＴＲ_SBnを同時に駆動すれば、図１５に示した回路と等価となる。
【０１７５】
このように、各メモリセルＭＣ_Anm，ＭＣ_Bnm（ｎ＝１，２であり、ｍ＝１，２・・・，８）のそれぞれに１ビットがデータとして記憶され（図１８の参照）、あるいは又、対となったメモリセルＭＣ_Anm，ＭＣ_Bnmに相補的なデータが１ビットとして記憶される（図１５参照）。実際の不揮発性メモリにおいては、この１６ビットあるいは８ビットを記憶するメモリユニットの集合がアクセス単位ユニットとしてアレイ状に配設されている。そして、選択用トランジスタのワード線ＷＬ_Sn（ＷＬ_SAn，ＷＬ_SBn）、プレート線ＰＬ_mが共有された複数のアクセス単位ユニットに対して、一括して、データの書き込み、あるいは、データの読み出し及び再書き込みを行う。即ち、メモリアレイにおいては、全ての不揮発性メモリが一括して、順次、作動状態となり、あるいは又、一括して不作動（待機）状態となる。
【０１７６】
（実施の形態４）
実施の形態４は、本発明の第７の態様及び第８の態様に係るゲインセルタイプの不揮発性メモリに関する。実施の形態４の不揮発性メモリの回路図を図１９に示す。図１９におけるメモリユニットのより具体的な回路図を図２０に示す。また、不揮発性メモリを切断したときのビット線の延びる方向と平行における実施の形態４の不揮発性メモリの模式的な一部断面図は、実質的に、図１６に示したと同様である。図１９においては、ビット線方向に隣接する２つのメモリユニットブロック（１つの不揮発性メモリを構成する）の一部分を図示するが、メモリユニットブロックの一方の構成要素の参照番号には「’」を付した。尚、２つのメモリユニットブロックは同一の構成であるが故に、以下、一方のメモリユニットブロックについて説明を行う。ここで、図２０には、プレート線の延びる方向に隣接する別の不揮発性メモリＭ_Bにおける１つのメモリユニットブロックＭＢ_Bを示すが、このメモリユニットブロックＭＢ_BはメモリユニットブロックＭＢ_Aと同じ構成を有する。
【０１７７】
また、図１９には、ビット線ＢＬ_An、書込用トランジスタＴＲ_Wn、読出用トランジスタＴＲ_Rn、検出用トランジスタＴＲ_Dn、２つの選択用トランジスタＴＲ_SAn，ＴＲ_SAn’、及び、２つのメモリユニットＭＵ_An，ＭＵ_An’を１組として図示したが、実際には、１つの不揮発性メモリには、この組がＮ組、備えられている。
【０１７８】
実施の形態４の不揮発性メモリＭ_Aは、
（Ａ）Ｎ個（但し、Ｎ≧２であり、実施の形態４においては、Ｎ＝２）の信号検出回路と、
（Ｂ）複数のメモリユニットブロックＭＢ_A，ＭＢ_A’、
から成り、
例えば、メモリユニットブロックＭＢ_Aは、
（Ｂ−１）Ｎ個の選択用トランジスタＴＲ_SANと、
（Ｂ−２）それぞれがＭ個（但し、Ｍ≧２であり、実施の形態４においては、Ｍ＝８）のメモリセルＭＣ_ANMから構成された、Ｎ個のメモリユニットＭＵ_ANと、
（Ｂ−３）Ｍ本のプレート線ＰＬ_M、
から成る。
【０１７９】
そして、メモリユニットブロックＭＢ_AのＮ個のメモリユニットＭＵ_ANは、絶縁層（層間絶縁層２６）を介して積層されている。各メモリセルＭＣ_Anmは、第１の電極２１，３１と強誘電体層２２，３２と第２の電極２３，３３とから成る。メモリユニットブロックＭＢ_Aの各メモリユニットＭＵ_Anにおいて、メモリセルＭＣ_Anmの第１の電極２１，３１は共通であり、メモリユニットブロックＭＢ_Aの第ｎ番目（第ｎ層目）（但し、ｎ＝１，２・・・，Ｎ）のメモリユニットＭＵ_Anにおける共通の第１の電極は、メモリユニットブロックＭＢ_Aの第ｎ番目の選択用トランジスタＴＲ_SAnを介して、第ｎ番目の信号検出回路に接続されている。更には、メモリユニットブロックＭＢ_Aの第ｎ番目（第ｎ層目）のメモリユニットＭＵ_Anにおいて、第ｍ番目（但し、ｍ＝１，２・・・，Ｍ）のメモリセルＭＣ_Anmの第２の電極は、メモリユニットブロックＭＢ_AのメモリユニットＭＵ_An間で共通とされた第ｍ番目のプレート線ＰＬ_mに接続されている。そして、第ｎ番目の信号検出回路は、メモリユニットブロックＭＢ_Aの第ｎ層目のメモリユニットＭＵ_Anにおける共通の第１の電極の電位変化（メモリセルＭＣ_Anmに記憶されたデータに基づく）を検出し、この検出結果を第ｎ番目のビット線ＢＬ_Anに電流又は電圧として伝達する。第ｎ番目の信号検出回路は、具体的には、次に説明する書込用トランジスタＴＲ_Wnと、読出用トランジスタＴＲ_Rnと、検出用トランジスタＴＲ_Dnから構成されている。
【０１８０】
あるいは又、実施の形態４の不揮発性メモリＭ_Aは、
（Ａ）Ｎ本（但し、Ｎ≧２であり、実施の形態４においては、Ｎ＝２）のビット線ＢＬ_ANと、
（Ｂ）Ｎ個の書込用トランジスタＴＲ_WNと、
（Ｃ）Ｎ個の読出用トランジスタＴＲ_RNと、
（Ｄ）Ｎ個の検出用トランジスタＴＲ_DNと、
（Ｅ）複数のメモリユニットブロックＭＢ_A，ＭＢ_A’、
から成り、
例えば、メモリユニットブロックＭＢ_Aは、
（Ｅ−１）Ｎ個の選択用トランジスタＴＲ_SANと、
（Ｅ−２）それぞれがＭ個（但し、Ｍ≧２であり、実施の形態４においては、Ｍ＝８）のメモリセルＭＣ_ANMから構成された、Ｎ個のメモリユニットＭＵ_ANと、
（Ｅ−３）Ｍ本のプレート線ＰＬ_M、
から成る。
【０１８１】
そして、メモリユニットブロックＭＢ_AのＮ個のメモリユニットは、絶縁層（層間絶縁層２６）を介して積層されている。各メモリセルは、第１の電極と強誘電体層と第２の電極とから成る。具体的には、第１番目（第１層目）のメモリユニットＭＵ_A1を構成する各メモリセルＭＣ_A1Mは、第１の電極２１と強誘電体層２２と第２の電極２３とから成り、第２番目（第２層目）のメモリユニットＭＵ_A2を構成する各メモリセルＭＣ_A2Mは、第１の電極３１と強誘電体層３２と第２の電極３３とから成る。メモリユニットブロックＭＢ_Aの各メモリユニットＭＵ_Anにおいて、メモリセルＭＣ_Anmの第１の電極は共通である。具体的には、第１層目のメモリユニットＭＵ_A1において、メモリセルＭＣ_A1Mの第１の電極２１は共通である。この共通の第１の電極２１を第１の共通ノードＣＮ_A1と呼ぶ場合がある。また、第２層目のメモリユニットＭＵ_A2において、メモリセルＭＣ_A2Mの第１の電極３１は共通である。この共通の第１の電極３１を第２の共通ノードＣＮ_A2と呼ぶ場合がある。更には、メモリユニットブロックＭＢ_Aの第ｎ番目（第ｎ層目）（但し、ｎ＝１，２・・・，Ｎ）のメモリユニットＭＵ_Anにおいて、第ｍ番目（但し、ｍ＝１，２・・・，Ｍ）のメモリセルの第２の電極２３，３３は、メモリユニットＭＵ_An間で共通とされた第ｍ番目のプレート線ＰＬ_mに接続されている。実施の形態４においては、より具体的には、各プレート線は、第２の電極２３，３３から延在している。これらのプレート線ＰＬ_mは、図示しない領域において接続されている。
【０１８２】
メモリユニットブロックＭＢ_Aの第ｎ層目（但し、ｎ＝１，２・・・，Ｎ）のメモリユニットＭＵ_Anにおける共通の第１の電極は、第ｎ番目の選択用トランジスタＴＲ_SAn、及び、第ｎ番目の書込用トランジスタＴＲ_Wnを介して、第ｎ番目のビット線ＢＬ_Anに接続されている。具体的には、第ｎ番目の選択用トランジスタＴＲ_SAnの一方のソース／ドレイン領域１４は接続孔１８Ｃ、サブビット線１９、接続孔１８Ｂ、第ｎ番目の書込用トランジスタＴＲ_Wnを介して第ｎ番目のビット線ＢＬ_Anに接続されている。一方、第１番目の選択用トランジスタＴＲ_SA1の他方のソース／ドレイン領域１４は、絶縁層１６に設けられた接続孔１７を介して、第１層目のメモリユニットＭＵ_A1における共通の第１の電極２１（第１の共通ノードＣＮ_A1）に接続されている。また、第２番目の選択用トランジスタＴＲ_SA2の他方のソース／ドレイン領域１４は、絶縁層１６に設けられた接続孔１７、パッド部２５、及び、層間絶縁層２６に設けられた接続孔２７を介して、第２層目のメモリユニットＭＵ_A2における共通の第１の電極３１（第２の共通ノードＣＮ_A2）に接続されている。
【０１８３】
ビット線ＢＬ_A1はセンスアンプＳＡ₁に接続され、ビット線ＢＬ_A2はセンスアンプＳＡ₂に接続されている。また、プレート線ＰＬ_Mはプレート線デコーダ／ドライバＰＤに接続されている。更には、ワード線ＷＬ_Snは、ワード線デコーダ／ドライバＷＤに接続されている。また、不揮発性メモリＭ_Aを構成するメモリセルＭＣ_A1mの第２の電極２３は、プレート線の延びる方向に隣接する別の不揮発性メモリＭ_Bを構成するメモリセルＭＣ_B1mの第２の電極２３と共通であり、プレート線ＰＬ_mを兼ねている。更には、不揮発性メモリＭ_Aを構成するメモリセルＭＣ_A2Mの第２の電極３３は、プレート線の延びる方向に隣接する別の不揮発性メモリＭ_Bを構成するメモリセルＭＣ_B2mの第２の電極３３と共通であり、プレート線ＰＬ_mを兼ねている。これらのプレート線ＰＬ_mは、図示しない領域において接続されている。また、ワード線ＷＬ_Snは、不揮発性メモリＭ_Aを構成する選択用トランジスタＴＲ_SAnと、ワード線の延びる方向に隣接する別の不揮発性メモリＭ_Bを構成する選択用トランジスタＴＲ_SBnとで共通である。
【０１８４】
第ｎ番目の検出用トランジスタＴＲ_Dnの一端は所定の電位（例えば、電源Ｖ_cc）を有する配線に接続され、他端は第ｎ番目の読出用トランジスタＴＲ_Rnを介して第ｎ番目のビット線ＢＬ_Anに接続されている。書込用トランジスタＴＲ_Wn、読出用トランジスタＴＲ_Rn、及び、検出用トランジスタＴＲ_Dnの構成、これらの動作、これらとメモリユニットブロックとの関係は、実質的に実施の形態１と同様とすることができるので、詳細な説明は省略する。
【０１８５】
そして、例えば、メモリユニットブロックＭＢ_Aの第ｎ番目（第ｎ層目）のメモリユニットＭＵ_AnのメモリセルＭＣ_Anmへのデータの書き込み時、
▲１▼ 第ｎ番目の書込用トランジスタＴＲ_Wn、及び、
▲２▼ メモリユニットブロックＭＢ_Aの第ｎ番目の選択用トランジスタＴＲ_SAn、が導通状態とされ、
▲３▼ 第ｎ番目の書込用トランジスタＴＲ_Wn以外の書込用トランジスタ、
▲４▼ 読出用トランジスタＴＲ_RN、
▲５▼ メモリユニットブロックＭＢ_Aの第ｎ番目の選択用トランジスタＴＲ_SAn以外の選択用トランジスタ、及び、
▲６▼ メモリユニットブロックＭＢ_A以外のメモリユニットブロックＭＢ_A’の選択用トランジスタＴＲ_SAN’、
が非導通状態とされ、
例えば、メモリユニットブロックＭＢ_Aの第ｎ番目（第ｎ層目）のメモリユニットＭＵ_AnのメモリセルＭＣ_Anmに記憶されたデータの読み出し時、
▲１▼ 書込用トランジスタＴＲ_WN、
▲２▼ メモリユニットブロックＭＢ_Aの第ｎ番目の読出用トランジスタＴＲ_Rn以外の読出用トランジスタ、及び、
▲３▼ メモリユニットブロックＭＢ_Aの第ｎ番目の選択用トランジスタＴＲ_SAn以外の選択用トランジスタ、
▲４▼ メモリユニットブロックＭＢ_A以外のメモリユニットブロックＭＢ_A’の選択用トランジスタＴＲ_SAn’、
が非導通状態とされ、
▲５▼ 第ｎ番目の読出用トランジスタＴＲ_Rn、及び、
▲６▼ メモリユニットブロックＭＢ_Aの第ｎ番目の選択用トランジスタＴＲ_SAn、が導通状態とされ、メモリユニットブロックＭＢ_Aの第ｎ層目のメモリユニットＭＵ_AnのメモリセルＭＣ_Anmに記憶されたデータに基づき共通の第１の電極（共通ノードＣＮ_An）に生じた電位により、第ｎ番目の検出用トランジスタＴＲ_Dnの動作が制御される。
【０１８６】
実施の形態４における不揮発性メモリにおけるデータの書込み動作、並びに、データの読出し及び再書込み動作は、実質的に実施の形態２にて説明した動作と同様とすることができるので、詳細な説明は省略する。
【０１８７】
図２０に回路図を示す不揮発性メモリＭ_A，Ｍ_Bにおいては、選択用トランジスタＴＲ_SA1，ＴＲ_SB1は同じワード線ＷＬ_S1に接続され、選択用トランジスタＴＲ_SA2，ＴＲ_SB2は同じワード線ＷＬ_S2に接続されている。そして、対となったメモリセルＭＣ_Anm，ＭＣ_Bnm（ｎ＝１，２、及び、ｍ＝１，２・・・，Ｍ）に相補的なデータが記憶される。例えば、メモリセルＭＣ_A1m，ＭＣ_B1m（ここで、ｍは１，２・・・，８のいずれか）に記憶されたデータを読み出す場合、ワード線ＷＬ_S1を選択し、プレート線ＰＬ_j（ｍ≠ｊ）には、例えば（１／２）Ｖ_ccの電圧を印加した状態で、プレート線ＰＬ_mを駆動する。これによって、相補的なデータに相当する電位が、対となったメモリセルＭＣ_Anm，ＭＣ_Bnmから共通ノードＣＮ_An，ＣＮ_Bnに出現し、その結果、検出用トランジスタＴＲ_Dn，検出用トランジスタＴＲ_BDn（この検出用トランジスタＴＲ_BDnは、不揮発性メモリＭ_Bを構成する検出用トランジスタである）の動作が制御され、相補的なデータに相当する電位が、検出用トランジスタＴＲ_Dn、読出用トランジスタＴＲ_Rn、及び、検出用トランジスタＴＲ_BDn、読出用トランジスタＴＲ_BRn（この読出用トランジスタＴＲ_BRnは、不揮発性メモリＭ_Bを構成する読出用トランジスタである）を介して対となったビット線ＢＬ_An，ＢＬ_Bnに電圧（ビット線電位）として現れる。そして、かかる対となったビット線ＢＬ_An，ＢＬ_Bnの電圧（ビット線電位）を、センスアンプＳＡ_nで検出する。
【０１８８】
不揮発性メモリＭ_A，Ｍ_Bを構成する選択用トランジスタＴＲ_SAn，ＴＲ_SBnを、それぞれ、異なるワード線ＷＬ_SAn，ＷＬ_SBnに接続し、メモリセルＭＣ_Anm，ＭＣ_Bnmを独立して制御し、例えばダミーセル等を用いて、対となったビット線ＢＬ_An，ＢＬ_Bnの一方に参照電圧（データ「１」の読み出し電位と、データ「０」の読み出し電位の中間の参照電位）を印加することによって、メモリセルＭＣ_Anm，ＭＣ_Bnmのそれぞれからデータを読み出すこともできる。このような構成を採用する場合の回路図は、図２１を参照のこと。尚、選択用トランジスタＴＲ_SAn，ＴＲ_SBnを同時に駆動すれば、図２０に示した回路と等価となる。
【０１８９】
このように、各メモリセルＭＣ_Anm，ＭＣ_Bnm（ｎ＝１，２であり、ｍ＝１，２・・・，８）のそれぞれに１ビットがデータとして記憶され（図２１の参照）、あるいは又、対となったメモリセルＭＣ_Anm，ＭＣ_Bnmに相補的なデータが１ビットとして記憶される（図２０参照）。実際の不揮発性メモリにおいては、この１６ビットあるいは８ビットを記憶するメモリユニットの集合がアクセス単位ユニットとしてアレイ状に配設されている。そして、選択用トランジスタのワード線ＷＬ_Sn（ＷＬ_SAn，ＷＬ_SBn）、プレート線ＰＬ_mが共有された複数のアクセス単位ユニットに対して、一括して、データの書き込み、あるいは、データの読み出し及び再書き込みを行う。即ち、メモリアレイにおいては、全ての不揮発性メモリが一括して、順次、作動状態となり、あるいは又、一括して不作動（待機）状態となる。
【０１９０】
（実施の形態５）
実施の形態５は、本発明の第９の態様及び第１０の態様に係るゲインセルタイプの不揮発性メモリに関する。実施の形態５の不揮発性メモリの回路図を図２２に示し、図２２におけるメモリユニットのより具体的な回路図を図２３に示す。また、不揮発性メモリを切断したときのビット線の延びる方向と平行における実施の形態５の不揮発性メモリの模式的な一部断面図は、実質的に、図１６に示したと同様である。図２２においては、ビット線方向に隣接する２つのメモリユニットブロック（１つの不揮発性メモリを構成する）を図示するが、メモリユニットブロックの一方の構成要素の参照番号には「’」を付した。尚、２つのメモリユニットブロックは同一の構成であるが故に、以下、一方のメモリユニットブロックについて説明を行う。ここで、図２３には、プレート線の延びる方向に隣接する別の不揮発性メモリＭ_Bにおける１つのメモリユニットブロックＭＢ_Bを示すが、このメモリユニットブロックＭＢ_BはメモリユニットブロックＭＢと同じ構成を有する。
【０１９１】
また、図２２には、ビット線ＢＬ_An、書込用トランジスタＴＲ_Wn、読出用トランジスタＴＲ_Rn、検出用トランジスタＴＲ_Dn、２つの選択用トランジスタＴＲ_SAn，ＴＲ_SAn’、及び、２つのメモリユニットＭＵ_An，ＭＵ_An’を１組として図示したが、実際には、１つの不揮発性メモリには、この組がＮ組、備えられている。
【０１９２】
実施の形態５の不揮発性メモリＭは、
（Ａ）２Ｎ個（但し、Ｎ≧１であり、実施の形態５においては、Ｎ＝１）の信号検出回路と、
（Ｂ）複数のメモリユニットブロックＭＢ，ＭＢ’、
から成り、
例えば、メモリユニットブロックＭＢは、
（Ｂ−１）２Ｎ個の選択用トランジスタＴＲ_Sと、
（Ｂ−２）それぞれがＭ個（但し、Ｍ≧２）のメモリセルＭＣ_NMから構成された、２Ｎ個のメモリユニットＭＵ_Nと、
（Ｂ−３）Ｍ本のプレート線ＰＬ_M、
から成る。
【０１９３】
そして、メモリユニットブロックＭＢの２Ｎ個のメモリユニットＭＵ_nは、絶縁層（層間絶縁層２６）を介して積層されている。各メモリセルＭＣ_nmは、第１の電極２１，３１と強誘電体層２２，３２と第２の電極２３，３３とから成る。そして、メモリユニットブロックＭＢの各メモリユニットＭＵ_nにおいて、メモリセルＭＣ_nmの第１の電極２１，３１は共通であり、メモリユニットブロックＭＢの第ｎ層目（但し、ｎ＝１，２・・・，２Ｎ）のメモリユニットＭＵ_nにおける共通の第１の電極２１，３１は、このメモリユニットブロックＭＢの第ｎ番目の選択用トランジスタＴＲ_Snを介して、第ｎ番目のビット線ＢＬ_nに接続されている。更には、メモリユニットブロックＭＢの第ｎ層目のメモリユニットＭＵ_nにおいて、第ｍ番目（但し、ｍ＝１，２・・・，Ｍ）のメモリセルＭＣ_nmの第２の電極２３，３３は、このメモリユニットブロックＭＢのメモリユニットＭＵ_n間で共通とされた第ｍ番目のプレート線ＰＬ_mに接続されている。そして、メモリユニットブロックＭＢの第（２ｎ’−１）層目及び第２ｎ’層目（但し、ｎ’＝１，２・・・，Ｎ）のメモリユニットＭＵ_(2n'-1)，ＭＵ_2n'におけるプレート線が共通とされた２つのメモリセルＭＣ_(2n'-1),m，ＭＣ_2n',mへのデータの書き込み、及び、データの読み出しが行われる。そして、第（２ｎ’−１）番目及び第２ｎ’番目の信号検出回路は、メモリユニットブロックＭＢの第（２ｎ’−１）層目及び第２ｎ’層目のメモリユニットＭＵ_(2n'-1)，ＭＵ_2n'における共通の第１の電極の電位変化（メモリセルＭＣ_(2n'-1),m，ＭＣ_2n',mに記憶されたデータに基づく）を検出し、これらの検出結果を第（２ｎ’−１）番目及び第２ｎ’番目のビット線ＢＬ_(2n'-1)，ＢＬ_2n'に電流又は電圧として伝達する。各信号検出回路は、具体的には、次に説明する書込用トランジスタＴＲ_Wnと、読出用トランジスタＴＲ_Rnと、検出用トランジスタＴＲ_Dnから構成されている。
【０１９４】
あるいは又、実施の形態５の不揮発性メモリＭは、
（Ａ）２Ｎ本（但し、Ｎ≧１であり、実施の形態５においては、Ｎ＝１）のビット線ＢＬ_Nと、
（Ｂ）２Ｎ個の書込用トランジスタＴＲ_WNと、
（Ｃ）２Ｎ個の読出用トランジスタＴＲ_RNと、
（Ｄ）２Ｎ個の検出用トランジスタＴＲ_DNと、
（Ｅ）複数のメモリユニットブロックＭＢ，ＭＢ’、
から成り、
例えば、メモリユニットブロックＭＢは、
（Ｅ−１）２Ｎ個の選択用トランジスタＴＲ_SNと、
（Ｅ−２）それぞれがＭ個（但し、Ｍ≧２であり、実施の形態５においては、Ｍ＝８）のメモリセルＭＣ_NMから構成された、２Ｎ個のメモリユニットＭＵ_Nと、
（Ｅ−３）Ｍ本のプレート線ＰＬ_M、
から成る。
【０１９５】
そして、メモリユニットブロックＭＢのＮ個のメモリユニットは、絶縁層（層間絶縁層２６）を介して積層されている。各メモリセルは、第１の電極と強誘電体層と第２の電極とから成る。具体的には、第１層目のメモリユニットＭＵ₁を構成する各メモリセルＭＣ_1Mは、第１の電極２１と強誘電体層２２と第２の電極２３とから成り、第２層目のメモリユニットＭＵ₂を構成する各メモリセルＭＣ_2Mは、第１の電極３１と強誘電体層３２と第２の電極３３とから成る。メモリユニットブロックＭＢの各メモリユニットＭＵ_nにおいて、メモリセルＭＣ_nmの第１の電極は共通である。具体的には、第１層目のメモリユニットＭＵ₁において、メモリセルＭＣ_1Mの第１の電極２１は共通である。この共通の第１の電極２１を第１の共通ノードＣＮ₁と呼ぶ場合がある。また、第２層目のメモリユニットＭＵ₂において、メモリセルＭＣ_2Mの第１の電極３１は共通である。この共通の第１の電極３１を第２の共通ノードＣＮ₂と呼ぶ場合がある。更には、メモリユニットブロックＭＢの第ｎ層目（但し、ｎ＝１，２・・・，Ｎ）のメモリユニットＭＵ_nにおいて、第ｍ番目（但し、ｍ＝１，２・・・，Ｍ）のメモリセルの第２の電極２３，３３は、メモリユニットＭＵ_n間で共通とされた第ｍ番目のプレート線ＰＬ_mに接続されている。実施の形態５においては、より具体的には、各プレート線は、第２の電極２３，３３から延在している。これらのプレート線ＰＬ_mは、図示しない領域において接続されている。
【０１９６】
メモリユニットブロックＭＢの第ｎ層目（但し、ｎ＝１，２・・・，Ｎ）のメモリユニットＭＵ_nにおける共通の第１の電極は、第ｎ番目の選択用トランジスタＴＲ_Sn、及び、第ｎ番目の書込用トランジスタＴＲ_Wnを介して、第ｎ番目のビット線ＢＬ_nに接続されている。具体的には、第ｎ番目の選択用トランジスタＴＲ_Snの一方のソース／ドレイン領域１４は接続孔１８Ｃ、サブビット線１９、接続孔１８Ｂ、第ｎ番目の書込用トランジスタＴＲ_Wnを介して第ｎ番目のビット線ＢＬ_nに接続されている。一方、第１番目の選択用トランジスタＴＲ_S1の他方のソース／ドレイン領域１４は、絶縁層１６に設けられた接続孔１７を介して、第１層目のメモリユニットＭＵ₁における共通の第１の電極２１（第１の共通ノードＣＮ₁）に接続されている。また、第２番目の選択用トランジスタＴＲ_S2の他方のソース／ドレイン領域１４は、絶縁層１６に設けられた接続孔１７、パッド部２５、及び、層間絶縁層２６に設けられた接続孔２７を介して、第２層目のメモリユニットＭＵ₂における共通の第１の電極３１（第２の共通ノードＣＮ₂）に接続されている。
【０１９７】
ビット線ＢＬ₁，ＢＬ₂はセンスアンプＳＡ₁に接続されている。また、プレート線ＰＬ_Mはプレート線デコーダ／ドライバＰＤに接続されている。更には、ワード線ＷＬ_Snは、ワード線デコーダ／ドライバＷＤに接続されている。また、不揮発性メモリＭを構成するメモリセルＭＣ_1mの第２の電極２３は、プレート線の延びる方向に隣接する別の不揮発性メモリＭ_Bを構成するメモリセルＭＣ_B1mの第２の電極２３と共通であり、プレート線ＰＬ_mを兼ねている。更には、不揮発性メモリＭを構成するメモリセルＭＣ_2Mの第２の電極３３は、プレート線の延びる方向に隣接する別の不揮発性メモリＭ_Bを構成するメモリセルＭＣ_B2mの第２の電極３３と共通であり、プレート線ＰＬ_mを兼ねている。これらのプレート線ＰＬ_mは、図示しない領域において接続されている。また、ワード線ＷＬ_Snは、不揮発性メモリＭを構成する選択用トランジスタＴＲ_Snと、ワード線の延びる方向に隣接する別の不揮発性メモリＭ_Bを構成する選択用トランジスタＴＲ_SBnとで共通である。
【０１９８】
第ｎ番目の検出用トランジスタＴＲ_Dnの一端は所定の電位（例えば、電源Ｖ_cc）を有する配線に接続され、他端は第ｎ番目の読出用トランジスタＴＲ_Rnを介して第ｎ番目のビット線ＢＬ_nに接続されている。書込用トランジスタＴＲ_Wn、読出用トランジスタＴＲ_Rn、及び、検出用トランジスタＴＲ_Dnの構成、これらの動作、これらとメモリユニットブロックとの関係は、実質的に実施の形態１と同様とすることができるので、詳細な説明は省略する。
【０１９９】
そして、メモリユニットブロックＭＢの第（２ｎ’−１）層目及び第２ｎ’層目（但し、ｎ’＝１，２・・・，Ｎ）の例えばメモリユニットＭＵ_(2n'-1)，ＭＵ_2n'におけるプレート線ＰＬ_Mが共通とされた２つのメモリセルＭＣ_(2n'-1),m，ＭＣ_2n',mへのデータの書き込み時、
▲１▼ 第（２ｎ’−１）番目及び第２ｎ’番目の書込用トランジスタＴＲ_W,(2n'-1)、ＴＲ_W,2n'、及び、
▲２▼ メモリユニットブロックＭＢの第（２ｎ’−１）番目及び第２ｎ’番目の選択用トランジスタＴＲ_S,(2n'-1)、ＴＲ_S,2n'、
が導通状態とされ、
▲３▼ 第（２ｎ’−１）番目及び第２ｎ’番目の書込用トランジスタＴＲ_W,(2n'-1)、ＴＲ_W,2n'以外の書込用トランジスタ、
▲４▼ 読出用トランジスタＴＲ_Rn、
▲５▼ メモリユニットブロックＭＢの第（２ｎ’−１）番目及び第２ｎ’番目の選択用トランジスタＴＲ_S,(2n'-1)、ＴＲ_S,2n'以外の選択用トランジスタ、及び、
▲６▼ メモリユニットブロックＭＢ以外のメモリユニットブロックＭＢ’の選択用トランジスタＴＲ_SN’、
が非導通状態とされ、
メモリユニットブロックＭＢの第（２ｎ’−１）層目及び第２ｎ’層目のメモリユニットＭＵ_(2n'-1)，ＭＵ_2n'におけるプレート線ＰＬ_mが共通とされた２つのメモリセルＭＣ_(2n'-1),m，ＭＣ_2n',mに記憶されたデータの読み出し時、
▲１▼ 書込用トランジスタＴＲ_WN、
▲２▼ メモリユニットブロックＭＢの第（２ｎ’−１）番目及び第２ｎ’番目の読出用トランジスタＴＲ_R,(2n'-1)、ＴＲ_R,2n'以外の読出用トランジスタ、
▲３▼ メモリユニットブロックＭＢの第（２ｎ’−１）番目及び第２ｎ’番目の選択用トランジスタＴＲ_S,(2n'-1)、ＴＲ_S,2n'以外の選択用トランジスタ、及び、
▲４▼ メモリユニットブロックＭＢ以外のメモリユニットブロックＭＢ’の選択用トランジスタＴＲ_SN’、
が非導通状態とされ、
▲５▼ 第（２ｎ’−１）番目及び第２ｎ’番目の読出用トランジスタＴＲ_R,(2n'-1)、ＴＲ_R,2n'、及び、
▲６▼ メモリユニットブロックＭＢの第（２ｎ’−１）番目及び第２ｎ’番目の選択用トランジスタＴＲ_S,(2n'-1)、ＴＲ_S,2n'、
が導通状態とされ、メモリユニットブロックＭＢの第（２ｎ’−１）層目及び第２ｎ’層目のメモリユニットＭＵ_(2n'-1)，ＭＵ_2n'におけるプレート線ＰＬ_mが共通とされた２つのメモリセルＭＣ_(2n'-1),m，ＭＣ_2n',mに記憶されたデータに基づき共通の第１の電極（共通ノードＣＮ_(2n'-1)，ＣＮ_2n'）のそれぞれに生じた電位により、第（２ｎ’−１）番目及び第２ｎ’番目の検出用トランジスタＴＲ_D,(2n'-1)、ＴＲ_D,2n'の動作が制御される。
【０２００】
実施の形態５における不揮発性メモリＭにおけるデータの書込み動作、並びに、データの読出し及び再書込み動作は、実質的に実施の形態２にて説明した動作と同様とすることができるので、詳細な説明は省略する。
【０２０１】
図２３に回路図を示す不揮発性メモリＭにおいては、不揮発性メモリＭを構成する選択用トランジスタＴＲ_S1，ＴＲ_S1は異なるワード線ＷＬ_S1，ＷＬ_S2に接続されている。そして、対となったメモリセルＭＣ_1m，ＭＣ_2mに相補的なデータが記憶される。例えば、メモリセルＭＣ_1m，ＭＣ_2m（ここで、ｍは１，２・・・，８のいずれか）に記憶されたデータを読み出す場合、ワード線ＷＬ_S1及びワード線ＷＬ_S2を選択し、プレート線ＰＬ_j（ｍ≠ｊ）には、例えば（１／２）Ｖ_ccの電圧を印加した状態で、プレート線ＰＬ_mを駆動する。これによって、相補的なデータに相当する電位が、対となったメモリセルＭＣ_1m，ＭＣ_2mから共通ノードＣＮ₁，ＣＮ₂に出現し、その結果、検出用トランジスタＴＲ_D1，検出用トランジスタＴＲ_D2の動作が制御され、相補的なデータに相当する電位が、検出用トランジスタＴＲ_D1、読出用トランジスタＴＲ_R1、及び、検出用トランジスタＴＲ_D2、読出用トランジスタＴＲ_R2を介して対となったビット線ＢＬ₁，ＢＬ₂に電圧（ビット線電位）として現れる。そして、かかる対となったビット線ＢＬ₁，ＢＬ₂の電圧（ビット線電位）を、センスアンプＳＡ₁で検出する。
【０２０２】
このように、対となったメモリセルＭＣ_(2n'-1),m，ＭＣ_2n',mに相補的なデータが１ビットとして記憶される。実際の不揮発性メモリにおいては、この８ビットを記憶するメモリユニットの集合がアクセス単位ユニットとしてアレイ状に配設されている。そして、選択用トランジスタのワード線ＷＬ_S1，ＷＬ_S2、プレート線ＰＬ_mが共有された複数のアクセス単位ユニットに対して、一括して、データの書き込み、あるいは、データの読み出し及び再書き込みを行う。即ち、メモリアレイにおいては、全ての不揮発性メモリが一括して、順次、作動状態となり、あるいは又、一括して不作動（待機）状態となる。
【０２０３】
メモリセルＭＣ_1m，ＭＣ_2mを独立して制御し、対となったビット線ＢＬ₁，ＢＬ₂の一方に参照電圧を印加することによって、メモリセルＭＣ_1m，ＭＣ_2mのそれぞれからデータを読み出すこともできる。このような構成は、実質的に、実施の形態４にて説明した不揮発性メモリの動作と同じとなる。
【０２０４】
以上、本発明を、発明の実施の形態に基づき説明したが、本発明はこれらに限定されるものではない。発明の実施の形態にて説明した不揮発性メモリの構造、使用した材料、各種の形成条件、回路構成、駆動方法等は例示であり、適宜変更することができる。
【０２０５】
検出用トランジスタの一端が接続された配線の所定の電位はＶ_ccに限定されず、例えば、接地されていてもよい。即ち、検出用トランジスタの一端が接続された配線の所定の電位を０ボルトとしてもよい。但し、この場合には、選択メモリセルにおけるデータの読み出し時に電位（Ｖ_cc）がビット線に現れた場合、再書き込み時には、ビット線の電位を０ボルトとし、選択メモリセルにおけるデータの読み出し時に０ボルトがビット線に現れた場合、再書き込み時には、ビット線の電位をＶ_ccとする必要がある。そのためには、図２４に例示するような、トランジスタＴＲ_IV-1，ＴＲ_IV-2，ＴＲ_IV-3，ＴＲ_IV-4から構成された一種のスイッチ回路（反転回路）をビット線間に配設し、データの読み出し時には、トランジスタＴＲ_IV-2，ＴＲ_IV-4をオン状態とし，データの再書き込み時には、トランジスタＴＲ_IV-1，ＴＲ_IV-3をオン状態とすればよい。
【０２０６】
Ｍの値は８に限定されない。Ｍの値は、Ｍ≧２を満足すればよく、実際的なＭの値として、例えば、２のべき数（２，４，８，１６・・・）を挙げることができる。また、実施の形態１〜実施の形態４において、Ｎの値は、Ｎ≧２を満足すればよく、実際的なＮの値として、例えば、２のべき数（２，４，８・・・）を挙げることができる。更には、実施の形態５において、Ｎの値は、Ｎ≧１を満足すればよく、実際的なＮの値として、例えば、１あるいは２のべき数（２，４，８・・・）を挙げることができる。メモリユニットブロックの数も２つに限定されない。
【０２０７】
一般に、単位ユニットの駆動用の信号線の合計本数をＡ本、その内のワード線本数をＢ本、プレート線の本数をＣ本とすると、Ａ＝Ｂ＋Ｃである。ここで、合計本数Ａを一定とした場合、単位ユニットの総アドレス数（＝Ｂ×Ｃ）が最大となるには、Ｂ＝Ｃを満足すればよい。従って、最も効率良く周辺回路を配置するためには、単位ユニットにおけるワード線本数Ｂとプレート線の本数Ｃとを等しくすればよい。また、ロー・アドレスのアクセス単位ユニットにおけるワード線本数は、例えば、メモリセルの積層段数（Ｎ）に一致し、プレート線本数はメモリユニットを構成するメモリセルの数（Ｍ）に一致するが、これらのワード線本数、プレート線本数が多いほど、実質的な不揮発性メモリの集積度は向上する。そして、ワード線本数とプレート線本数の積がアクセス可能なアドレス回数である。ここで、一括して、且つ、連続したアクセスを前提とすると、その積から「１」を減じた値がディスターブ回数である。従って、ワード線本数とプレート線本数の積の値は、メモリセルのディスターブ耐性、プロセス要因等から決定される。ここで、ディスターブとは、非選択のメモリセルを構成する強誘電体層に対して、分極が反転する方向に、即ち、保存されていたデータが劣化若しくは破壊される方向に、電界が加わる現象を指す。
【０２０８】
実施の形態３にて説明した不揮発性メモリを、図２５に示す構造のように変形することもできる。尚、回路図を図２６に示す。尚、図２５、図２６においては、書込用トランジスタ、読出用トランジスタ、検出用トランジスタの図示を省略した。
【０２０９】
この不揮発性メモリは、センスアンプＳＡに接続されているビット線ＢＬ_Aと、ＭＯＳ型ＦＥＴから構成されたＮ個（但し、Ｎ≧２であり、この例においてはＮ＝４）の選択用トランジスタＴＲ_S1，ＴＲ_S2，ＴＲ_S3，ＴＲ_S4と、Ｎ個のメモリユニットＭＵ_A1，ＭＵ_A2，ＭＵ_A3，ＭＵ_A4と、プレート線から構成されている。第１層目のメモリユニットＭＵ_A1は、Ｍ個（但し、Ｍ≧２であり、この例においてはＭ＝８）のメモリセルＭＣ_A1m（ｍ＝１，２，・・・，８）から構成されている。また、第２層目のメモリユニットＭＵ_A2も、Ｍ個（Ｍ＝８）のメモリセルＭＣ_A2m（ｍ＝１，２・・・，８）から構成されている。更には、第３層目のメモリユニットＭＵ_A3も、Ｍ個（Ｍ＝８）のメモリセルＭＣ_A3m（ｍ＝１，２・・・，８）から構成され、第４層目のメモリユニットＭＵ_A4も、Ｍ個（Ｍ＝８）のメモリセルＭＣ_A4m（ｍ＝１，２・・・，８）から構成されている。プレート線の数は、Ｍ本（この例においては８本）であり、ＰＬ_m（ｍ＝１，２・・・，８）で表している。選択用トランジスタＴＲ_Snのゲート電極に接続されたワード線ＷＬ_Snは、ワード線デコーダ／ドライバＷＤに接続されている。一方、各プレート線ＰＬ_mは、プレート線デコーダ／ドライバＰＤに接続されている。
【０２１０】
また、第１層目のメモリユニットＭＵ_A1を構成する各メモリセルＭＣ_A1mは、第１の電極２１Ａと強誘電体層２２Ａと第２の電極２３とから成り、第２層目のメモリユニットＭＵ_A2を構成する各メモリセルＭＣ_A2mは、第１の電極２１Ｂと強誘電体層２２Ｂと第２の電極２３とから成り、第３層目のメモリユニットＭＵ_A3を構成する各メモリセルＭＣ_A3mは、第１の電極３１Ａと強誘電体層３２Ａと第２の電極３３とから成り、第４層目のメモリユニットＭＵ_A4を構成する各メモリセルＭＣ_A4mは、第１の電極３１Ｂと強誘電体層３２Ｂと第２の電極３３とから成る。そして、各メモリユニットＭＵ_A1，ＭＵ_A2，ＭＵ_A3，ＭＵ_A4において、メモリセルの第１の電極２１Ａ，２１Ｂ，３１Ａ，３１Ｂは共通である。この共通の第１の電極２１Ａ，２１Ｂ，３１Ａ，３１Ｂを、便宜上、共通ノードＣＮ_A1，ＣＮ_A2，ＣＮ_A3，ＣＮ_A4と呼ぶ。
【０２１１】
ここで、第１層目のメモリユニットＭＵ_A1における共通の第１の電極２１Ａ（第１の共通ノードＣＮ_A1）は、第１番目の選択用トランジスタＴＲ_S1及び例えば書込用トランジスタＴＲ_Wを介してビット線ＢＬ_Aに接続されている。また、第２層目のメモリユニットＭＵ_A2における共通の第１の電極２１Ｂ（第２の共通ノードＣＮ_A2）は、第２番目の選択用トランジスタＴＲ_S2及び例えば書込用トランジスタＴＲ_Wを介してビット線ＢＬ_Aに接続されている。更には、第３層目のメモリユニットＭＵ_A3における共通の第１の電極３１Ａ（第３の共通ノードＣＮ_A3）は、第３番目の選択用トランジスタＴＲ_S3及び例えば書込用トランジスタＴＲ_Wを介してビット線ＢＬ_Aに接続されている。また、第４層目のメモリユニットＭＵ_A4における共通の第１の電極３１Ｂ（第４の共通ノードＣＮ_A4）は、第４番目の選択用トランジスタＴＲ_S4及び例えば書込用トランジスタＴＲ_Wを介してビット線ＢＬ_Aに接続されている。
【０２１２】
また、第１層目のメモリユニットＭＵ_A1を構成するメモリセルＭＣ_A1mと、第２層目のメモリユニットＭＵ_A2を構成するメモリセルＭＣ_A2mは、第２の電極２３を共有しており、この共有された第ｍ番目の第２の電極２３はプレート線ＰＬ_mに接続されている。更には、第３層目のメモリユニットＭＵ_A3を構成するメモリセルＭＣ_A3mと、第４層目のメモリユニットＭＵ_A4を構成するメモリセルＭＣ_A4mは、第２の電極３３を共有しており、この共有された第ｍ番目の第２の電極３３はプレート線ＰＬ_mに接続されている。具体的には、この共有された第ｍ番目の第２の電極２３の延在部からプレート線ＰＬ_mが構成され、この共有された第ｍ番目の第２の電極３３の延在部からプレート線ＰＬ_mが構成されており、各プレート線ＰＬ_mは図示しない領域で接続されている。
【０２１３】
この不揮発性メモリにおいては、メモリユニットＭＵ_A1，ＭＵ_A2とメモリユニットＭＵ_A3，ＭＵ_A4は、絶縁層（層間絶縁層２６）を介して積層されている。メモリユニットＭＵ_A4は絶縁膜３６Ａで被覆されている。また、メモリユニットＭＵ_A1は、半導体基板１０の上方に絶縁層１６を介して形成されている。半導体基板１０には素子分離領域１１が形成されている。また、選択用トランジスタＴＲ_S1，ＴＲ_S2，ＴＲ_S3，ＴＲ_S4は、ゲート絶縁膜１２、ゲート電極１３、ソース／ドレイン領域１４から構成されている。そして、第１の選択用トランジスタＴＲ_S1、第２の選択用トランジスタＴＲ_S2、第３の選択用トランジスタＴＲ_S3、第４の選択用トランジスタＴＲ_S4の一方のソース／ドレイン領域１４は接続孔、サブビット線、例えば書込用トランジスタＴＲ_Wnを介してビット線ＢＬ_Aに接続されている。また、第１の選択用トランジスタＴＲ_S1の他方のソース／ドレイン領域１４は、絶縁層１６に形成された開口部中に設けられた接続孔１７を介して第１の共通ノードＣＮ_A1に接続されている。更には、第２の選択用トランジスタＴＲ_S2の他方のソース／ドレイン領域１４は、接続孔１７を介して第２の共通ノードＣＮ_A2に接続されている。また、第３の選択用トランジスタＴＲ_S3の他方のソース／ドレイン領域１４は、接続孔１７、パッド部２５、層間絶縁層２６に形成された開口部中に設けられた接続孔２７を介して第３の共通ノードＣＮ_A3に接続されている。更には、第４の選択用トランジスタＴＲ_S4の他方のソース／ドレイン領域１４は、接続孔１７、パッド部２５、接続孔２７を介して第４の共通ノードＣＮ_A4に接続されている。
【０２１４】
以上に説明した不揮発性メモリの構造は、他の発明の実施の形態における不揮発性メモリにも適宜適用することができる。
【０２１５】
また、例えば、図２７に示すように、実施の形態３の不揮発性メモリの変形例として、第１の電極２１’，３１’を上部電極とし、第２の電極２３’，３３’を下部電極とすることもできる。このような構造は、他の発明の実施の形態における不揮発性メモリにも適宜適用することができる。尚、図２７には、書込用トランジスタ、読出用トランジスタ、検出用トランジスタの図示を省略した。
【０２１６】
【発明の効果】
本発明の強誘電体型不揮発性半導体メモリにおいては、複数のメモリセルが設けられているが故に、１ビット当たりのセル面積の減少を図ることができるし、更には、複数のメモリユニットブロックを備えているが故に、一層、１ビット当たりのセル面積の減少を図ることができる。しかも、第１の電極は、メモリユニットを構成する複数のメモリセルの第１の電極が共通であるが故に、第１の電極に一種の追加の負荷容量が付加された状態にあり、データの読み出し時、プレート線に電圧を印加した際、浮遊状態にある第１の電極の電位上昇を抑制することができ、第１の電極と第２の電極との間に十分な電位差を生じさせることができるので、強誘電体層に分極反転を確実に発生させることが可能となる。また、書込用トランジスタや、読出用トランジスタ、検出用トランジスタを設けるが、これらのトランジスタの面積的なオーバーヘッドは極く僅かである。しかも、スケーリングが向上し、メモリセルが縮小化されても、ほぼ同等のセンス信号量を確保することができる。
【図面の簡単な説明】
【図１】発明の実施の形態１の強誘電体型不揮発性半導体メモリの回路図である。
【図２】発明の実施の形態１の強誘電体型不揮発性半導体メモリにおけるメモリユニットの部分のより具体的な回路図である。
【図３】発明の実施の形態１の強誘電体型不揮発性半導体メモリを構成する各種のトランジスタの模式的なレイアウトを示す図である。
【図４】発明の実施の形態１の強誘電体型不揮発性半導体メモリを、図３の矢印Ａ−Ａに沿って切断したときのビット線の延びる方向と平行における模式的な一部断面図である。
【図５】発明の実施の形態１の強誘電体型不揮発性半導体メモリを、図３の矢印Ｂ−Ｂに沿って切断したときのビット線の延びる方向と平行における模式的な一部断面図である。
【図６】発明の実施の形態１の強誘電体型不揮発性半導体メモリのデータ書き込み動作における動作波形を示す図である。
【図７】発明の実施の形態１の強誘電体型不揮発性半導体メモリのデータ読み出し及び再書き込み動作における動作波形を示す図である。
【図８】発明の実施の形態１において、メモリユニットを構成するメモリセルの個数（Ｍ）の値と信号電位との関係をシミュレーションした結果を示すグラフである。
【図９】発明の実施の形態２の強誘電体型不揮発性半導体メモリの回路図である。
【図１０】発明の実施の形態２の強誘電体型不揮発性半導体メモリにおけるメモリユニットの部分のより具体的な回路図である。
【図１１】発明の実施の形態２の強誘電体型不揮発性半導体メモリのビット線の延びる方向と平行における模式的な一部断面図である。
【図１２】発明の実施の形態２の強誘電体型不揮発性半導体メモリのデータ読み出し及び再書き込み動作における動作波形を示す図である。
【図１３】発明の実施の形態２の強誘電体型不揮発性半導体メモリの変形例におけるメモリユニットの部分のより具体的な回路図である。
【図１４】発明の実施の形態３の強誘電体型不揮発性半導体メモリの回路図である。
【図１５】発明の実施の形態３の強誘電体型不揮発性半導体メモリにおけるメモリユニットの部分のより具体的な回路図である。
【図１６】発明の実施の形態３の強誘電体型不揮発性半導体メモリのビット線の延びる方向と平行における模式的な一部断面図である。
【図１７】発明の実施の形態３の強誘電体型不揮発性半導体メモリのデータ読み出し及び再書き込み動作における動作波形を示す図である。
【図１８】発明の実施の形態３の強誘電体型不揮発性半導体メモリの変形例におけるメモリユニットの部分のより具体的な回路図である。
【図１９】発明の実施の形態４の強誘電体型不揮発性半導体メモリの回路図である。
【図２０】発明の実施の形態４の強誘電体型不揮発性半導体メモリにおけるメモリユニットの部分のより具体的な回路図である。
【図２１】発明の実施の形態４の強誘電体型不揮発性半導体メモリの変形例におけるメモリユニットの部分のより具体的な回路図である。
【図２２】発明の実施の形態５の強誘電体型不揮発性半導体メモリの回路図である。
【図２３】発明の実施の形態５の強誘電体型不揮発性半導体メモリにおけるメモリユニットの部分のより具体的な回路図である。
【図２４】検出用トランジスタの一端が接続された配線の所定の電位を０ボルトとした場合の、ビット線間に配設された一種のスイッチ回路を示す回路図である。
【図２５】発明の実施の形態３にて説明した強誘電体型不揮発性半導体メモリの変形例を示す模式的な一部断面図である。
【図２６】図２５に示す強誘電体型不揮発性半導体メモリの回路図である。
【図２７】発明の実施の形態３の強誘電体型不揮発性半導体メモリの別の変形例の模式的な一部断面図である。
【図２８】強誘電体のＰ−Ｅヒステリシスループ図である。
【図２９】米国特許第４８７３６６４号に開示された強誘電体型不揮発性半導体メモリの回路図である。
【図３０】特開平９−１２１０３２号公報に開示された強誘電体型不揮発性半導体メモリの回路図である。
【図３１】ＤＲＡＭにおけるゲインセルの等価回路図、及び、従来の米国特許第４８７３６６４号に開示された不揮発性メモリにこのゲインセルを適用した場合の等価回路図である。
【符号の説明】
１０・・・シリコン半導体基板、１１・・・素子分離領域、１２・・・ゲート絶縁膜、１３・・・ゲート電極、１４・・・ソース／ドレイン領域、１５，１７，１８Ａ，１８Ｂ，１８Ｃ，２７・・・接続孔（コンタクトホール）、１６・・・絶縁層、２１，２１Ａ，２１Ｂ，２１’，３１，３１Ａ，３１Ｂ，３１’・・・第１の電極、２２，２２Ａ，２２Ｂ，３２，３２Ａ，３２Ｂ・・・強誘電体層、２３，２３’，３３，３３’・・・第２の電極、２５・・・パッド部、２６・・・絶縁層（層間絶縁層）、２６Ａ，３６Ａ・・・絶縁膜、Ｍ・・・強誘電体型不揮発性半導体メモリ、ＭＢ・・・メモリユニットブロック、ＭＣ・・・メモリセル、ＴＲ_S・・・選択用トランジスタ、ＴＲ_W・・・書込用トランジスタ、ＴＲ_R・・・読出用トランジスタ、ＴＲ_D・・・検出用トランジスタ、ＷＬ・・・ワード線、ＢＬ・・・ビット線、ＰＬ・・・プレート線、ＷＤ・・・ワード線デコーダ／ドライバ、ＳＡ・・・センスアンプ、ＰＤ・・・プレート線デコーダ／ドライバ、ＣＮ・・・共通ノード[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a so-called gain cell type ferroelectric nonvolatile semiconductor memory.
[0002]
[Prior art]
In recent years, research on large-capacity ferroelectric nonvolatile semiconductor memories has been actively conducted. A ferroelectric type nonvolatile semiconductor memory (hereinafter sometimes abbreviated as “nonvolatile memory”) is capable of high-speed access, is nonvolatile, is small in size and has low power consumption, and is also susceptible to impact. For example, various electronic devices having file storage and resume functions, such as portable computers, mobile phones, game machines as main storage devices, or recording media for recording audio and video Use is expected.
[0003]
This non-volatile memory uses a high-speed polarization inversion of the ferroelectric thin film and its remanent polarization, and is capable of high-speed rewriting of a method of detecting a change in the accumulated charge amount of the ferroelectric layer in the memory cell (capacitor portion). The nonvolatile memory is basically composed of a memory cell (capacitor portion) and a selection transistor (switching transistor). The memory cell includes, for example, a lower electrode, an upper electrode, and a ferroelectric layer sandwiched between these electrodes. Data is written into and read from the nonvolatile memory by applying a ferroelectric PE hysteresis loop shown in FIG. That is, when an external electric field is applied to the ferroelectric layer and then the external electric field is removed, the ferroelectric layer exhibits spontaneous polarization. The residual polarization of the ferroelectric layer is + P when an external electric field in the positive direction is applied._rWhen an external electric field in the negative direction is applied, -P_rIt becomes. Here, the remanent polarization is + P_rIn the case of the state (see “D” in FIG. 28), the residual polarization is −P._rIn this state (see “A” in FIG. 28), “1” is set.
[0004]
In order to determine the state of “1” or “0”, for example, an external electric field in the positive direction is applied to the ferroelectric layer. As a result, the polarization of the ferroelectric layer becomes the state “C” in FIG. At this time, if the data is “0”, the polarization state of the ferroelectric layer changes from “D” to “C”. On the other hand, if the data is “1”, the polarization state of the ferroelectric layer changes from “A” to “C” via “B”. When the data is “0”, the polarization inversion of the ferroelectric layer does not occur. On the other hand, when the data is “1”, polarization inversion occurs in the ferroelectric layer. As a result, a difference occurs in the amount of charge stored in the memory cells. By turning on the selection transistor of the selected nonvolatile memory, this accumulated charge is detected as a signal current. When the external electric field is set to 0 after the data is read, the polarization state of the ferroelectric layer becomes the state “D” in FIG. 28 regardless of whether the data is “0” or “1”. That is, at the time of reading, the data “1” is once destroyed. Therefore, when the data is “1”, an external electric field in the negative direction is applied to make the state “A” along the paths “D” and “E”, and the data “1” is written again.
[0005]
The structure and operation of nonvolatile memories which are currently mainstream are disclosed in US Pat. Shefiled et al. This non-volatile memory is composed of two non-volatile memory cells as shown in the circuit diagram of FIG. In FIG. 29, one nonvolatile memory is surrounded by a dotted line. Each nonvolatile memory cell includes, for example, a selection transistor TR₁₁, TR₁₂, Memory cell MC₁₁, MC₁₂It is composed of
[0006]
Note that a 2-digit number, for example, the subscript “11” is originally a subscript to be displayed as the subscript “1, 1”, but is displayed with a 2-digit subscript for simplification of display. The same applies to the 3-digit subscript. The subscript “M” is used, for example, when collectively displaying a plurality of memory cells or plate lines, and the subscript “m” is used, for example, when displaying a plurality of memory cells or plate lines individually. The subscript “N” is used, for example, when the selection transistors and memory units are displayed collectively, and the subscript “n” is used, for example, when the selection transistors and memory units are individually displayed.
[0007]
Then, 1 bit is stored by writing complementary data in each nonvolatile memory cell. In FIG. 29, symbol “WL” indicates a word line, symbol “BL” indicates a bit line, and symbol “PL” indicates a plate line. Focusing on one nonvolatile memory, the word line WL₁Are connected to a word line decoder / driver WD. In addition, the bit line BL₁, BL₂Are connected to the sense amplifier SA. Furthermore, plate line PL₁Are connected to a plate line decoder / driver PD.
[0008]
When reading stored data in a nonvolatile memory having such a structure, the word line WL₁And, further, plate line PL₁, The complementary data is stored in a pair of memory cells MC.₁₁, MC₁₂To transistor for selection TR₁₁, TR₁₂Bit line BL paired via₁, BL₂Appears as a voltage (bit line potential). The paired bit lines BL₁, BL₂Is detected by the sense amplifier SA.
[0009]
One nonvolatile memory is a word line WL₁And paired bit lines BL₁, BL₂Occupies the area surrounded by. Therefore, if the word lines and the bit lines are arranged at the shortest pitch, the minimum area of one nonvolatile memory is 8F when the minimum processing dimension is F.²It is. Therefore, the minimum area of the nonvolatile memory having such a structure is 8F.²It is.
[0010]
In order to increase the capacity of the nonvolatile memory having such a structure, the realization of the nonvolatile memory depends only on the miniaturization of the processing dimensions. In addition, two selection transistors and two memory cells are required to form one nonvolatile memory. Furthermore, it is necessary to arrange plate lines at the same pitch as the word lines. Therefore, it is almost impossible to arrange the nonvolatile memories at the minimum pitch, and in reality, the area occupied by one nonvolatile memory is 8F.²Will increase significantly.
[0011]
Moreover, it is necessary to dispose the word line decoder / driver WD and the plate line decoder / driver PD at the same pitch as that of the nonvolatile memory. In other words, two decoders / drivers are required to select one row address. Therefore, the layout of the peripheral circuit becomes difficult, and the area occupied by the peripheral circuit becomes large.
[0012]
One means for reducing the area of the nonvolatile memory is known from Japanese Patent Laid-Open No. 9-121022. As shown in an equivalent circuit in FIG. 30, the nonvolatile memory disclosed in this patent publication includes a memory cell MC._1M(For example, M = 4) and these memory cells MC_1MTransistor TR having one end connected in parallel₁And a plurality of such memory cells MC_1MMemory cells MC paired with_2MAnd these memory cells MC_2MTransistor TR having one end connected in parallel₂It is composed of Selection transistor TR₁, TR₂The other end of each bit line BL₁, BL₂It is connected to the. Paired bit lines BL₁, BL₂Are connected to the sense amplifier SA. In addition, the memory cell MC_1m, MC_2mThe other end of (m = 1, 2,... M) is the plate line PL_mIs connected to the plate line PL_mAre connected to a plate line decoder / driver PD. Furthermore, the word line WL is connected to a word line decoder / driver WD.
[0013]
The paired memory cells MC_1m, MC_2mComplementary data is stored in (m = 1, 2,... M). For example, the memory cell MC_1m, MC_2mWhen data stored in (where m is any one of 1, 2, 3 and 4) is read, the word line WL is selected and the plate line PL_j(J ≠ m) has (1/2) V_ccWith the voltage of_mDrive. Where V_ccIs, for example, a power supply voltage. As a result, the complementary data is converted into a pair of memory cells MC._1m, MC_2mTo transistor for selection TR₁, TR₂Bit line BL paired via₁, BL₂Appears as a voltage (bit line potential). The paired bit lines BL₁, BL₂Is detected by the sense amplifier SA.
[0014]
A pair of selection transistors TR in a paired nonvolatile memory₁And TR₂Are the word line WL and the paired bit line BL.₁, BL₂Occupies the area surrounded by. Accordingly, if the word lines and the bit lines are arranged at the shortest pitch, a pair of selection transistors TR in the paired nonvolatile memory is assumed.₁And TR₂The minimum area is 8F²It is. However, a pair of selection transistors TR₁, TR₂M pairs of memory cells MC_1m, MC_2m(M = 1, 2,... M), so that the selection transistor TR per bit is shared.₁, TR₂Since the number of memory cells is small and the arrangement of the word lines WL is gradual, it is easy to reduce the size of the nonvolatile memory. In addition, for the peripheral circuit, M bits can be selected by one word line decoder / driver WD and M plate line decoder / driver PD. Therefore, by adopting such a configuration, the cell area is 8F.²A layout close to that of a DRAM can be realized, and a chip size comparable to that of a DRAM can be realized.
[0015]
[Problems to be solved by the invention]
By the way, when the miniaturization of the nonvolatile memory having these structures is advanced, the area of the memory cell has to be reduced. In addition, since data is stored based on polarization in the ferroelectric layer, the accumulated charge amount in the ferroelectric layer does not increase even if the thickness of the ferroelectric layer is reduced like the insulating film in DRAM. The amount of stored charge decreases in proportion to the area of the memory cell.
[0016]
For example, when realizing a 256 Mbit nonvolatile memory, the memory cell area is 0.1 μm.²It will be about. At this time, the accumulated charge amount is about 10 fC, and when the bit line capacitance is 200 fF, only a sense signal amount (potential appearing on the bit line during the read operation) of about 50 mV can be obtained. With such a sense signal amount, the sense margin is insufficient, and if the non-volatile memory is further miniaturized, the data stored in the non-volatile memory cannot be read.
[0017]
Plate wire PL_mDriving the bit line BL₁, BL₂When reading a signal from the non-selected memory cell MC_jBit line BL₁, BL₂Bit line BL₁, BL₂Includes an unselected memory cell MC._jIs added as a driving load. Bit line BL₁, BL₂In general, dozens of non-volatile memories are connected to each of these via a selection transistor, and their wiring capacitance and junction capacitance are considerably large load capacitances. Therefore, the capacity of a plurality of non-selected memory cells is further added to the load capacity, and driving of the nonvolatile memory becomes extremely difficult. Further, the unselected memory cell MC_jIn some cases, a voltage is applied in the direction of polarization deterioration, and in this case, the amount of polarization is reduced, which also contributes to the difficulty of driving the nonvolatile memory.
[0018]
In order to solve such a problem, the bit line BL₁, BL₂Is divided into bit lines BL₁, BL₂Reduce the number of non-volatile memories connected to the non-selected memory cells MC_jThere is no choice but to reduce the load capacity. However, such a measure increases the number of sense amplifiers. Since the sense amplifier is composed of a large number of components such as flip-flops and transistors for connection to the bus, there is a problem that the occupied area of the sense amplifier increases.
[0019]
One measure for dealing with a decrease in the amount of sense signal in a DRAM is an amplification type memory cell called a gain cell (see, for example, Japanese Patent Laid-Open Nos. 62-67861 and 1-255269). The gain cell shown in the equivalent circuit diagram of FIG._WAnd reading transistor TR_RAnd detection transistor TR_DAnd the capacitor portion C. Write transistor TR when writing data to gain cell_WIs turned on, and charges are accumulated in the capacitor portion C. When reading data from the gain cell, the reading transistor TR_RIs turned on. On the other hand, the detection transistor TR_DDepending on the data stored in the capacitor part C, it is turned on or off.
[0020]
FIG. 31B shows an equivalent circuit diagram in the case where the gain cell having such a configuration is applied to a nonvolatile memory disclosed in US Pat. No. 4,873,664. Such a gain cell type nonvolatile memory cell includes a write transistor TR._WRead transistor TR_R, Detection transistor TR_DAnd the memory cell MC. Write transistor TR_WOne source / drain region is connected to the bit line BL, and the other source / drain region is connected to the lower electrode of the memory cell MC. Detection transistor TR_DOne end of the_ccIs connected to a wiring (for example, a power supply line composed of an impurity layer), and the other end is a reading transistor TR_RTo the bit line BL. Further, the lower electrode of the memory cell MC is connected to the detection transistor TR._DConnected to the gate electrode.
[0021]
In the nonvolatile memory cell having such a configuration, when data is read, a pulse voltage is applied to the plate line PL, and the depletion type NMOSFET depends on the amount of accumulated charge caused by the presence or absence of polarization inversion in the memory cell MC. Detecting transistor TR composed of_DIs controlled. That is, after the bit line BL is equalized to 0 volts, the read transistor TR_RIs turned on, the power supply V_ccTo TR for detection TR_DAnd reading transistor TR_RCurrent flows through the bit line BL, and a potential appears on the bit line BL. The potential on the bit line BL depends on data stored in the nonvolatile memory cell. Thereby, it is possible to know whether the data stored in the memory cell MC is “1” or “0”. That is, a large bit line load can be driven based on a small accumulated charge in the memory cell MC.
[0022]
However, in the nonvolatile memory having such a configuration, three transistors are required for each nonvolatile memory cell, and the cell area per bit greatly increases, resulting in an increase in cost per bit. There is.
[0023]
Further, when data is read, when a pulse voltage is applied to the plate line PL, an upper electrode connected to the plate line PL and a detection transistor TR constituting a memory cell._DIf a sufficient potential difference does not occur with the lower electrode connected to the gate electrode, polarization inversion does not occur in the memory cell MC. However, when reading data, the detection transistor TR_DThe lower electrode connected to the gate electrode of the transistor is in a floating state, and its load capacitance is the detection transistor TR_DThere is only about the gate capacity. Therefore, when a pulse voltage is applied to the plate line PL, the coupling between the upper electrode and the lower electrode greatly increases the potential of the lower electrode, and a sufficient electric field is formed between the upper electrode and the lower electrode. Therefore, there is a problem that polarization inversion does not occur in the ferroelectric layer. Conversely, in order to suppress the potential increase of the lower electrode due to such coupling, it is necessary to add a load capacity several times that of the memory cell MC to the lower electrode. For this purpose, a capacitor is added separately. Will have to do. However, this greatly increases the cell area.
[0024]
Accordingly, an object of the present invention is to reduce the area per bit, and to read out stored data reliably, that is, to obtain a sufficient sense signal amount. It is an object of the present invention to provide a gain cell type ferroelectric nonvolatile semiconductor memory.
[0025]
[Means for Solving the Problems]
In order to achieve the above object, a gain cell type ferroelectric nonvolatile semiconductor memory according to the first aspect of the present invention comprises:
(A) a signal detection circuit;
(B) a plurality of memory unit blocks;
Consisting of
Each memory unit block
(B-1) a selection transistor;
(B-2) a memory unit composed of M (where M ≧ 2) memory cells;
(B-3) M plate wires,
Consisting of
Each memory cell includes a first electrode, a ferroelectric layer, and a second electrode,
In the memory unit of each memory unit block, the first electrode of the memory cell is common, and the common first electrode is connected to the signal detection circuit via the selection transistor of the memory unit block. ,
In the memory unit of each memory unit block, the second electrode of the mth (where m = 1, 2,..., M) memory cell is connected to the mth plate line of the memory unit block. A ferroelectric-type nonvolatile semiconductor memory,
The signal detection circuit detects a potential change of the common first electrode in the memory units of the memory unit blocks, and transmits the detection result to the bit line as a current or a voltage.
[0026]
In order to achieve the above object, a gain cell type ferroelectric nonvolatile semiconductor memory according to the second aspect of the present invention comprises:
(A) a bit line;
(B) a writing transistor;
(C) a reading transistor;
(D) a detection transistor;
(E) a plurality of memory unit blocks;
Consisting of
Each memory unit block
(E-1) a selection transistor;
(E-2) a memory unit composed of M (where M ≧ 2) memory cells;
(E-3) M plate wires,
Consisting of
Each memory cell includes a first electrode, a ferroelectric layer, and a second electrode,
In the memory unit of each memory unit block, the first electrode of the memory cell is common, and the common first electrode is a bit through the selection transistor and the writing transistor of the memory unit block. And the second electrode of the mth memory cell (where m = 1, 2,..., M) is connected to the line in the memory unit of each memory unit block. Connected to the second plate wire,
One end of the detection transistor is connected to a wiring having a predetermined potential, and the other end is connected to the bit line via the reading transistor,
When writing data to memory cells in the memory unit block,
(1) Write transistor and
(2) Transistor for selecting the memory unit block,
Is turned on,
(3) Reading transistor and
(4) Transistor for selecting a memory unit block other than the memory unit block,
Is turned off,
When reading the data stored in the memory cells of the memory unit block,
(1) Write transistor and
(2) Transistor for selecting a memory unit block other than the memory unit block,
Is turned off,
(3) Reading transistor and
(4) Transistor for selecting the memory unit block,
Is made conductive, and the operation of the detection transistor is controlled by the potential generated in the common first electrode based on the data stored in the memory cell of the memory unit block.
[0027]
In order to achieve the above object, a gain cell type ferroelectric nonvolatile semiconductor memory according to the third aspect of the present invention comprises:
(A) a signal detection circuit;
(B) a plurality of memory unit blocks;
Consisting of
Each memory unit block
(B-1) a selection transistor;
(B-2) N (where N ≧ 2) memory units each composed of M (where M ≧ 2) memory cells;
(B-3) M × N plate wires,
Consisting of
N memory units of each memory unit block are stacked via an insulating layer,
Each memory cell includes a first electrode, a ferroelectric layer, and a second electrode,
In each memory unit of each memory unit block, the first electrode of the memory cell is common, and the common first electrode is connected to the signal detection circuit via the selection transistor of the memory unit block. And
In the memory unit in the nth layer (where n = 1, 2,..., N) of each memory unit block, the mth (where m = 1, 2,..., M) memory cells The second electrode is a ferroelectric nonvolatile semiconductor memory connected to the [(n−1) M + m] th plate line of the memory unit block,
The signal detection circuit detects a potential change of the common first electrode in the memory units of the memory unit blocks, and transmits the detection result to the bit line as a current or a voltage.
[0028]
In order to achieve the above object, a gain cell type ferroelectric nonvolatile semiconductor memory according to the fourth aspect of the present invention comprises:
(A) a bit line;
(B) a writing transistor;
(C) a reading transistor;
(D) a detection transistor;
(E) a plurality of memory unit blocks;
Consisting of
Each memory unit block
(E-1) a selection transistor;
(E-2) N (where N ≧ 2) memory units each composed of M (where M ≧ 2) memory cells;
(E-3) M × N plate wires,
Consisting of
N memory units of each memory unit block are stacked via an insulating layer,
Each memory cell includes a first electrode, a ferroelectric layer, and a second electrode,
In each memory unit of each memory unit block, the first electrode of the memory cell is common, and the common first electrode is connected via the selection transistor and the write transistor of the memory unit block. Connected to the bit line,
In the memory unit in the nth layer (where n = 1, 2,..., N) of each memory unit block, the mth (where m = 1, 2,..., M) memory cells The second electrode is connected to the [(n−1) M + m] th plate line of the memory unit block,
One end of the detection transistor is connected to a wiring having a predetermined potential, and the other end is connected to the bit line via the reading transistor,
When writing data to memory cells in the memory unit block,
(1) Write transistor and
(2) Transistor for selecting the memory unit block,
Is turned on,
(3) Reading transistor and
(4) Transistor for selecting a memory unit block other than the memory unit block,
Is turned off,
When reading the data stored in the memory cells of the memory unit block,
(1) Write transistor and
(2) Transistor for selecting a memory unit block other than the memory unit block,
Is turned off,
(3) Reading transistor and
(4) Transistor for selecting the memory unit block,
Is made conductive, and the operation of the detection transistor is controlled by the potential generated in the common first electrode based on the data stored in the memory cell of the memory unit block.
[0029]
To achieve the above object, a gain cell type ferroelectric nonvolatile semiconductor memory according to a fifth aspect of the present invention comprises:
(A) a signal detection circuit;
(B) a plurality of memory unit blocks;
Consisting of
Each memory unit block
(B-1) N selection transistors (where N ≧ 2),
(B-2) N memory units each composed of M (where M ≧ 2) memory cells;
(B-3) M plate wires,
Consisting of
Each memory cell includes a first electrode, a ferroelectric layer, and a second electrode,
In each memory unit of each memory unit block, the first electrode of the memory cell is common,
The common first electrode in the nth (where n = 1, 2,..., N) memory unit of each memory unit block is connected via the nth selection transistor of the memory unit block. Connected to the signal detection circuit,
In the nth memory unit of each memory unit block, the second electrode of the mth memory cell (where m = 1, 2,..., M) is common among the memory units of the memory unit block. A ferroelectric nonvolatile semiconductor memory connected to the m-th plate line,
The signal detection circuit detects a potential change of a common first electrode in the nth memory unit of each memory unit block, and transmits the detection result as a current or a voltage to a bit line.
[0030]
To achieve the above object, a gain cell type ferroelectric nonvolatile semiconductor memory according to the sixth aspect of the present invention comprises:
(A) a bit line;
(B) a writing transistor;
(C) a reading transistor;
(D) a detection transistor;
(E) a plurality of memory unit blocks;
Consisting of
Each memory unit block
(E-1) N selection transistors (where N ≧ 2),
(E-2) N memory units each composed of M (where M ≧ 2) memory cells;
(E-3) M plate wires,
Consisting of
Each memory cell includes a first electrode, a ferroelectric layer, and a second electrode,
In each memory unit of each memory unit block, the first electrode of the memory cell is common,
The common first electrode in the nth (where n = 1, 2,..., N) memory unit of each memory unit block is the nth selection transistor in the memory unit block and the write It is connected to the bit line through the embedded transistor,
In the nth memory unit of each memory unit block, the second electrode of the mth memory cell (where m = 1, 2,..., M) is common among the memory units of the memory unit block. Connected to the m-th plate wire,
One end of the detection transistor is connected to a wiring having a predetermined potential, and the other end is connected to the bit line via the reading transistor,
When writing data to the memory cell of the nth memory unit in the memory unit block,
(1) Write transistor and
(2) nth selection transistor of the memory unit block,
Is turned on,
(3) Reading transistor,
(4) Selection transistors other than the nth selection transistor of the memory unit block, and
(5) A transistor for selecting a memory unit block other than the memory unit block,
Is turned off,
When reading the data stored in the memory cell of the nth memory unit of the memory unit block,
(1) Writing transistor,
(2) Selection transistors other than the nth selection transistor of the memory unit block, and
(3) A transistor for selecting a memory unit block other than the memory unit block,
Is turned off,
(4) Reading transistor, and
(5) nth selection transistor of the memory unit block,
Is made conductive, and the operation of the detection transistor is controlled by the potential generated at the common first electrode based on the data stored in the memory cell of the nth memory unit of the memory unit block. It is characterized by.
[0031]
To achieve the above object, a gain cell type ferroelectric nonvolatile semiconductor memory according to a seventh aspect of the present invention comprises:
(A) N (where N ≧ 2) signal detection circuits;
(B) a plurality of memory unit blocks;
Consisting of
Each memory unit block
(B-1) N selection transistors;
(B-2) N memory units each composed of M (where M ≧ 2) memory cells;
(B-3) M plate wires,
Consisting of
Each memory cell includes a first electrode, a ferroelectric layer, and a second electrode,
In each memory unit of each memory unit block, the first electrode of the memory cell is common,
The common first electrode in the nth (where n = 1, 2,..., N) memory unit of each memory unit block is connected via the nth selection transistor of the memory unit block. Connected to the nth signal detection circuit;
In the nth memory unit of each memory unit block, the second electrode of the mth memory cell (where m = 1, 2,..., M) is common among the memory units of the memory unit block. A ferroelectric nonvolatile semiconductor memory connected to the m-th plate line,
The nth signal detection circuit detects a potential change of the common first electrode in the nth memory unit of each memory unit block, and transmits the detection result to the nth bit line as a current or a voltage. It is characterized by doing.
[0032]
To achieve the above object, a gain cell type ferroelectric nonvolatile semiconductor memory according to an eighth aspect of the present invention comprises:
(A) N bit lines (where N ≧ 2),
(B) N write transistors;
(C) N read transistors;
(D) N detection transistors;
(E) a plurality of memory unit blocks;
Consisting of
Each memory unit block
(E-1) N selection transistors;
(E-2) N memory units each composed of M (where M ≧ 2) memory cells;
(E-3) M plate wires,
Consisting of
Each memory cell includes a first electrode, a ferroelectric layer, and a second electrode,
In each memory unit of each memory unit block, the first electrode of the memory cell is common,
The common first electrode in the nth (where n = 1, 2,..., N) memory unit of each memory unit block is the nth selection transistor in the memory unit block, and It is connected to the nth bit line via the nth write transistor,
In the nth memory unit of each memory unit block, the second electrode of the mth memory cell (where m = 1, 2,..., M) is common among the memory units of the memory unit block. Connected to the m-th plate wire,
One end of the nth detection transistor is connected to a wiring having a predetermined potential, and the other end is connected to the nth bit line via the nth read transistor,
When writing data to the memory cell of the nth memory unit in the memory unit block,
(1) The nth write transistor, and
(2) nth selection transistor of the memory unit block,
Is turned on,
(3) Write transistors other than the nth write transistor,
(4) Reading transistor,
(5) Selection transistors other than the nth selection transistor of the memory unit block, and
(6) A transistor for selecting a memory unit block other than the memory unit block,
Is turned off,
When reading the data stored in the memory cell of the nth memory unit of the memory unit block,
(1) Writing transistor,
(2) Readout transistors other than the nth readout transistor of the memory unit block,
(3) Selection transistors other than the nth selection transistor of the memory unit block, and
(4) Transistor for selecting a memory unit block other than the memory unit block,
Is turned off,
(5) n-th reading transistor, and
(6) nth selection transistor of the memory unit block,
Is turned on, and the operation of the nth detection transistor is performed by the potential generated at the common first electrode based on the data stored in the memory cell of the nth memory unit of the memory unit block. Is controlled.
[0033]
In order to achieve the above object, a gain cell type ferroelectric nonvolatile semiconductor memory according to a ninth aspect of the present invention comprises:
(A) 2N (where N ≧ 1) signal detection circuits;
(B) a plurality of memory unit blocks;
Consisting of
Each memory unit block
(B-1) 2N selection transistors;
(B-2) 2N memory units each composed of M (where M ≧ 2) memory cells;
(B-3) M plate wires,
Consisting of
2N memory units of each memory unit block are stacked via an insulating layer,
Each memory cell includes a first electrode, a ferroelectric layer, and a second electrode,
In each memory unit of each memory unit block, the first electrode of the memory cell is common,
A common first electrode in the memory unit of the nth layer (where n = 1, 2,..., 2N) of each memory unit block is connected to the nth selection transistor of the memory unit block. , Connected to the nth signal detection circuit, and in the nth memory unit of each memory unit block, the mth (where m = 1, 2,..., M) th memory cell. The second electrode is a ferroelectric nonvolatile semiconductor memory connected to the mth plate line common to the memory units of the memory unit block,
To two memory cells having the same plate line in the (2n′-1) th layer and the second n′th layer (where n ′ = 1, 2,..., N) of the memory unit block. Data writing and data reading are performed,
The (2n′−1) th and 2n′th signal detection circuits are connected to the first electrode common to the memory units in the (2n′-1) th layer and the second n′th layer of each memory unit block. A potential change is detected, and the detection result is transmitted as a current or a voltage to the (2n′−1) th and 2n′th bit lines.
[0034]
To achieve the above object, a gain cell type ferroelectric nonvolatile semiconductor memory according to a tenth aspect of the present invention comprises:
(A) 2N (where N ≧ 1) bit lines;
(B) 2N write transistors;
(C) 2N read transistors;
(D) 2N detection transistors;
(E) a plurality of memory unit blocks;
Consisting of
Each memory unit block
(E-1) 2N selection transistors;
(E-2) 2N memory units each consisting of M (where M ≧ 2) memory cells;
(E-3) M plate wires,
Consisting of
2N memory units of each memory unit block are stacked via an insulating layer,
Each memory cell includes a first electrode, a ferroelectric layer, and a second electrode,
In each memory unit of each memory unit block, the first electrode of the memory cell is common,
The common first electrode in the memory unit of the nth layer (where n = 1, 2,..., 2N) of each memory unit block is the nth selection transistor in the memory unit block, and Connected to the nth bit line via the nth write transistor,
In the memory unit of the nth layer of each memory unit block, the second electrode of the mth (where m = 1, 2,..., M) memory cell is connected between the memory units of the memory unit block. Connected to the mth plate line,
One end of the nth detection transistor is connected to a wiring having a predetermined potential, and the other end is connected to the nth bit line via the nth read transistor,
To two memory cells having the same plate line in the (2n′-1) th layer and the second n′th layer (where n ′ = 1, 2,..., N) of the memory unit block. When writing the data of
(1) The (2n'-1) th and 2n'th write transistors, and
(2) The (2n′-1) th and 2n′th selection transistors of the memory unit block,
Is turned on,
(3) Write transistors other than the (2n′-1) th and 2n′th write transistors,
(4) Reading transistor,
(5) Selection transistors other than the (2n′-1) th and 2n′th selection transistors of the memory unit block, and
(6) A transistor for selecting a memory unit block other than the memory unit block,
Is turned off,
When reading data stored in two memory cells having the same plate line in the memory units of the (2n′-1) th layer and the second n′th layer of the memory unit block,
(1) Writing transistor,
(2) Read transistors other than the (2n′-1) th and 2n′th read transistors of the memory unit block,
(3) Selection transistors other than the (2n′-1) th and 2n′th selection transistors of the memory unit block, and
(4) Transistor for selecting a memory unit block other than the memory unit block,
Is turned off,
(5) The (2n′-1) th and 2n′th read transistors, and
(6) The (2n'-1) th and 2n'th selection transistors of the memory unit block,
Is connected based on data stored in the two memory cells in which the plate lines in the (2n′-1) th layer and the second n′th layer memory unit of the memory unit block are made common. The operations of the (2n′−1) th and the 2n′th detection transistors are controlled by the potential generated in each of the first electrodes.
[0035]
In the ferroelectric nonvolatile semiconductor memory according to the ninth aspect or the tenth aspect of the present invention, the (2n′−1) th layer and the second n′th layer (however, Data writing to or reading from the two memory cells having the same plate line in the memory unit of n ′ = 1, 2,..., N) is performed simultaneously on the two memory cells. That is, a complementary 1 bit is stored in two memory cells in a pair. If data writing or data reading is separately performed for two memory cells, the data is substantially included in the ferroelectric nonvolatile semiconductor memory according to the seventh aspect or the eighth aspect of the present invention. The
[0036]
In the ferroelectric nonvolatile semiconductor memory according to the first, third, fifth, seventh, and ninth aspects of the present invention, the signal detection circuit has a common first electrode potential. A change is detected, but this potential change is a potential based on data stored in the selected memory cell.
[0037]
In the ferroelectric nonvolatile semiconductor memory according to the first to tenth aspects of the present invention (hereinafter, these may be collectively referred to simply as the ferroelectric nonvolatile semiconductor memory of the present invention). , M satisfies 2 ≦ M ≦ 128, preferably 4 ≦ M ≦ 32.
[0038]
In the ferroelectric nonvolatile semiconductor memory according to the third to eighth aspects of the present invention, it is sufficient that N ≧ 2 is satisfied. As a practical value of N, for example, a power of 2 (2, 4 , 8... Further, in the ferroelectric nonvolatile semiconductor memory according to the ninth aspect or the tenth aspect of the present invention, it is only necessary to satisfy N ≧ 1, and the practical value of N should be, for example, 1 or 2. Numbers (2, 4, 8...) Can be mentioned.
[0039]
In the ferroelectric type nonvolatile semiconductor memory of the present invention, the number of memory unit blocks is determined based on the capacity of the source / drain region of the selection transistor, or the wiring connecting the signal detection circuit or the write transistor and the selection transistor. It is desirable that the wiring capacity be a number that is sufficiently small with respect to the load capacity of the non-selected memory cells. More specifically, the number of memory unit blocks is preferably not more than twice the value of M. Thereby, a sufficiently large sense signal amount (bit line potential) can be obtained.
[0040]
In the ferroelectric nonvolatile semiconductor memory according to the first aspect, the third aspect, the fifth aspect, the seventh aspect, and the ninth aspect of the present invention, the selection transistor and the signal detection circuit are provided on the semiconductor substrate. The memory unit is preferably provided on an insulating layer formed on a semiconductor substrate.
[0041]
In the ferroelectric nonvolatile semiconductor memory according to the second aspect, the fourth aspect, the sixth aspect, the eighth aspect, and the tenth aspect of the present invention, for example, various transistors are formed on a silicon semiconductor substrate. From the viewpoint of reducing the cell area, it is preferable to form an insulating layer on such various transistors and form a memory cell on this insulating layer.
[0042]
As a specific configuration of the ferroelectric nonvolatile semiconductor memory according to the second aspect, the fourth aspect, the sixth aspect, the eighth aspect, and the tenth aspect of the present invention, various transistors are composed of FETs. In this case, the following configuration can be given. That is, one source / drain region of the writing transistor is connected to the bit line, and the other source / drain region is connected to one source / drain region of the selection transistor. In addition, one source / drain region of the detection transistor is connected to a wiring having a predetermined potential (for example, a power supply line or a ground line composed of an impurity layer), and the other source / drain region is a read transistor. The other source / drain region of the reading transistor is connected to the bit line. Further, the other source / drain region of the selection transistor is connected to the common first electrode. The other source / drain region of the writing transistor or one source / drain region of the selection transistor is connected to the gate electrode of the detection transistor. For example, in the configuration in which the other source / drain region of the detection transistor is connected to one source / drain region of the readout transistor, the other source / drain region of the detection transistor and one of the readout transistors are A configuration in which the source / drain region occupies one source / drain region is included.
[0043]
In the ferroelectric nonvolatile semiconductor memory according to the first and second aspects of the present invention, a plurality of memory units of the ferroelectric nonvolatile semiconductor memory may be stacked via an insulating layer. In the ferroelectric nonvolatile semiconductor memory according to the fifth to eighth aspects of the present invention, the N memory units constituting the memory unit block may be formed on the same insulating layer. Then, they may be laminated via an insulating layer.
[0044]
In the ferroelectric nonvolatile semiconductor memory according to the third aspect, the fourth aspect, the ninth aspect, and the tenth aspect of the present invention, or alternatively, according to the fifth to eighth aspects of the present invention. In the ferroelectric type nonvolatile semiconductor memory according to the preferred embodiment, the memory unit has a stacked structure, so that the number of transistors occupying the surface of the semiconductor substrate is not restricted, and the conventional ferroelectric type nonvolatile semiconductor memory As compared with the above, the storage capacity can be dramatically increased, and the effective occupation area of the bit storage unit can be greatly reduced.
[0045]
In the ferroelectric nonvolatile semiconductor memory according to the third to tenth aspects of the present invention, furthermore, the address selection in the row direction is performed by a two-dimensional matrix constituted by a selection transistor and a plate line. . For example, if a row address selection unit is formed by eight selection transistors and eight plate lines, for example, a 64-bit or 32-bit memory cell can be selected by 16 decoder / driver circuits. it can. Therefore, even if the integration degree of the ferroelectric nonvolatile semiconductor memory is equivalent to the conventional one, the storage capacity can be increased four times or twice. Further, it is possible to reduce the number of peripheral circuits and drive wirings in address selection.
[0046]
In the ferroelectric-type nonvolatile semiconductor memory according to the first to eighth aspects of the present invention, practically, the ferroelectric-type nonvolatile semiconductor memory is paired (for convenience, nonvolatile memory-A, nonvolatile memory). The bit lines constituting the pair of ferroelectric nonvolatile semiconductor memories can be connected to the same sense amplifier. In this case, the selection transistor constituting the nonvolatile memory-A and the selection transistor constituting the nonvolatile memory-B may be connected to the same word line or connected to different word lines. May be. Depending on the configuration and driving method of the nonvolatile memory-A and the nonvolatile memory-B, one bit can be stored in each memory cell constituting the nonvolatile memory-A and the nonvolatile memory-B. One of the memory cells constituting the volatile memory-A and one of the memory cells constituting the nonvolatile memory-B connected to the same plate line as the memory cell are used as a pair. Complementary data can also be stored.
[0047]
In the ferroelectric nonvolatile semiconductor memory of the present invention, data is collectively collected for a plurality of ferroelectric nonvolatile semiconductor memories (memory arrays) sharing the word lines and plate lines of the selection transistors. Or data reading and rewriting. That is, all the ferroelectric type nonvolatile semiconductor memories in the memory array are collectively turned on or sequentially turned off, or are collectively turned off (standby).
[0048]
In the ferroelectric nonvolatile semiconductor memory according to the third aspect, the fourth aspect, the ninth aspect, and the tenth aspect of the present invention, or alternatively, according to the fifth to eighth aspects of the present invention. In the ferroelectric nonvolatile semiconductor memory according to the preferred embodiment, the crystallization temperature of the ferroelectric layer constituting the memory cell of the memory unit located above is the ferroelectric constituting the memory cell of the memory unit located below. It is preferably lower than the crystallization temperature of the body layer. Here, the crystallization temperature of the ferroelectric layer constituting the memory cell can be examined using, for example, an X-ray diffractometer or a surface scanning electron microscope. Specifically, for example, after the ferroelectric material layer is formed, the heat treatment temperature for crystallization of the ferroelectric material layer is changed variously to perform the heat treatment for promoting crystallization. The crystallization temperature of the ferroelectric layer can be determined by performing X-ray diffraction analysis of the body material layer and evaluating the diffraction pattern intensity (diffraction peak height) peculiar to the ferroelectric material.
[0049]
By the way, when manufacturing a ferroelectric nonvolatile semiconductor memory having a structure in which memory units are stacked, a heat treatment (for the crystallization of the ferroelectric layer or the ferroelectric thin film constituting the ferroelectric layer) The number of stages of the stacked memory units must be performed. Therefore, the lower the memory unit, the longer the crystallization heat treatment, and the higher the memory unit, the shorter the crystallization heat treatment. Therefore, if an optimal crystallization heat treatment is applied to the memory unit located in the upper stage, the memory unit located in the lower stage may be subjected to an excessive heat load, and the characteristics of the memory unit located in the lower stage may be deteriorated. There is. Although a method of performing crystallization heat treatment once after manufacturing a multi-stage memory unit is conceivable, a large volume change occurs in the ferroelectric layer during crystallization, or degassing occurs from each ferroelectric layer. This is likely to occur, and problems such as cracking and peeling off of the ferroelectric layer are likely to occur. If the crystallization temperature of the ferroelectric layer constituting the upper memory unit is set lower than the crystallization temperature of the ferroelectric layer constituting the lower memory unit, the number of stacked memory units is the same. Even if the crystallization heat treatment is performed, there is no problem of deterioration in characteristics of the memory cells constituting the memory unit located below. In addition, the crystallization heat treatment can be performed on the memory cells constituting the memory unit in each stage under optimum conditions, and a ferroelectric nonvolatile semiconductor memory having excellent characteristics can be obtained. Table 1 below shows crystallization temperatures of typical materials constituting the ferroelectric layer, but the material constituting the ferroelectric layer is not limited to such materials.
[0050]
[Table 1]
Material name Crystallization temperature
Bi₂SrTa₂O₉                   700-800 ° C
Bi₂Sr (Ta_1.5, Nb_0.5) O₉    650-750 ° C
Bi_FourTi_ThreeO₁₂                      600-700 ° C
Pb (Zr_0.48, Ti_0.52) O_Three       550-650 ° C
PbTiO_Three                         500-600 ° C
[0051]
Examples of the material constituting the ferroelectric layer in the ferroelectric nonvolatile semiconductor memory of the present invention include a bismuth layered compound, more specifically, a Bi-based layered structure perovskite type ferroelectric material. Bi-based layered structure perovskite type ferroelectric materials belong to so-called non-stoichiometric compounds and are tolerant of compositional shifts at both sites of metal elements and anion (O, etc.) elements. It is also not uncommon for optimal electrical characteristics to be exhibited at a slight deviation from the stoichiometric composition. Bi-based layered structure perovskite type ferroelectric materials include, for example, a general formula (Bi₂O₂)²⁺(A_m-1B_mO_{3m + 1})^2-Can be expressed as Here, “A” represents one type of metal selected from the group consisting of metals such as Bi, Pb, Ba, Sr, Ca, Na, K, and Cd, and “B” represents Ti, Nb. , Ta, W, Mo, Fe, Co, Cr, and one type selected from the group consisting of a plurality of types, or a combination based on an arbitrary ratio. M is an integer of 1 or more.
[0052]
Alternatively, the material constituting the ferroelectric layer is
(Bi_X, Sr_1-X)₂(Sr_Y, Bi_1-Y) (Ta_Z, Nb_1-Z)₂O_d  Formula (1)
(However, 0.9 ≦ X ≦ 1.0, 0.7 ≦ Y ≦ 1.0, 0 ≦ Z ≦ 1.0, 8.7 ≦ d ≦ 9.3) It is preferable to include as a phase. Alternatively, the material constituting the ferroelectric layer is
Bi_XSr_YTa₂O_d  Formula (2)
However, it is preferable that a crystal phase represented by (X + Y = 3, 0.7 ≦ Y ≦ 1.3, 8.7 ≦ d ≦ 9.3) is included as a main crystal phase. In these cases, it is more preferable that 85% or more of the crystal phase represented by the formula (1) or (2) is contained as the main crystal phase. In formula (1), (Bi_X, Sr_1-X) Means that Sr occupies the site originally occupied by Bi in the crystal structure, and the ratio of Bi and Sr at this time is X: (1-X). Also, (Sr_Y, Bi_1-Y) Means that Bi occupies the site originally occupied by Sr in the crystal structure, and the ratio of Sr and Bi at this time is Y: (1-Y). The material constituting the ferroelectric layer including the crystal phase represented by the formula (1) or (2) as a main crystal phase includes Bi oxide, Ta and Nb oxide, Bi, Ta and Nb. There may be some composite oxides.
[0053]
Alternatively, the material constituting the ferroelectric layer is
Bi_X(Sr, Ca, Ba)_Y(Ta_Z, Nb_1-Z)₂O_d  Formula (3)
(However, the crystal phase represented by 1.7 ≦ X ≦ 2.5, 0.6 ≦ Y ≦ 1.2, 0 ≦ Z ≦ 1.0, 8.0 ≦ d ≦ 10.0) is included. May be. “(Sr, Ca, Ba)” means one type of element selected from the group consisting of Sr, Ca, and Ba. If the composition of the material constituting the ferroelectric layer represented by each of these formulas is represented by the stoichiometric composition, for example, Bi₂SrTa₂O₉, Bi₂SrNb₂O₉, Bi₂BaTa₂O₉, Bi₂Sr (Ta, Nb)₂O₉Etc. Alternatively, as a material constituting the ferroelectric layer, Bi_FourSrTi_FourO₁₅, Bi_ThreeTiNbO₉, Bi_ThreeTiTaO₉, Bi_FourTi_ThreeO₁₂, Bi₂PbTa₂O₉In these cases, the ratio of each metal element can be changed to such an extent that the crystal structure does not change. That is, there may be a composition shift at both sites of the metal element and the oxygen element.
[0054]
Alternatively, as a material constituting the ferroelectric layer, PbTiO_ThreePbZrO having a perovskite structure_ThreeAnd PbTiO_ThreeZirconate titanate [PZT, Pb (Zr_1-y, Ti_y) O_Three(However, 0 <y <1)], PZT compounds such as PLZT, which is a metal oxide in which La is added to PZT, or PNZT, which is a metal oxide in which Nb is added to PZT.
[0055]
In the materials constituting the ferroelectric layer described above, the crystallization temperature can be changed by removing these compositions from the stoichiometric composition.
[0056]
In order to obtain the ferroelectric layer, the ferroelectric thin film may be patterned in the process after the ferroelectric thin film is formed. In some cases, patterning of the ferroelectric thin film is not necessary. The ferroelectric thin film can be formed by a method suitable for the material constituting the ferroelectric thin film, such as MOCVD, pulse laser ablation, sputtering, or sol-gel. The patterning of the ferroelectric thin film can be performed by, for example, an anisotropic ion etching (RIE) method.
[0057]
In the ferroelectric nonvolatile semiconductor memory of the present invention, the first electrode is formed under the ferroelectric layer, and the second electrode is formed over the ferroelectric layer (that is, the first electrode). Corresponds to the lower electrode, and the second electrode corresponds to the upper electrode), the first electrode is formed on the ferroelectric layer, and the second electrode is formed below the ferroelectric layer. An electrode may be formed (that is, the first electrode corresponds to the upper electrode and the second electrode corresponds to the lower electrode). The plate line is preferably configured to extend from the second electrode from the viewpoint of simplifying the wiring structure. As a structure in which the first electrode is common, specifically, a configuration in which a stripe-shaped first electrode is formed and a ferroelectric layer is formed so as to cover the entire surface of the stripe-shaped first electrode. Can be mentioned. In such a structure, the overlapping region of the first electrode, the ferroelectric layer, and the second electrode corresponds to a memory cell. As a structure in which the first electrode is common, a structure in which each ferroelectric layer is formed in a predetermined region of the first electrode and the second electrode is formed on the ferroelectric layer, or In addition, each first electrode is formed on a predetermined surface region of the wiring layer, a ferroelectric layer is formed on each first electrode, and a second electrode is formed on the ferroelectric layer. However, the present invention is not limited to these configurations.
[0058]
Further, in the ferroelectric nonvolatile semiconductor memory according to the present invention, in the case where the first electrode is formed below the ferroelectric layer and the second electrode is formed on the ferroelectric layer, the memory cell 1 has a so-called damascene structure, and the first electrode is formed on the ferroelectric layer, and the second electrode is formed below the ferroelectric layer. The second electrode constituting the memory cell preferably has a so-called damascene structure from the viewpoint that the ferroelectric layer can be formed on a flat base.
[0059]
In the present invention, as a material constituting the first electrode or the second electrode, for example, Ir, IrO_2-X, Ir / IrO_2-X, SrIrO_Three, Ru, RuO_2-X, SrRuO_Three, Pt, Pt / IrO_2-X, Pt / RuO_2-X, Pd, Pt / Ti laminated structure, Pt / Ta laminated structure, Pt / Ti / Ta laminated structure, La_0.5Sr_0.5CoO_Three(LSCO), Pt / LSCO laminated structure, YBa₂Cu_ThreeO₇Can be mentioned. Here, the value of X is 0 ≦ X <2. In the laminated structure, the material described after “/” is in contact with the ferroelectric layer. The first electrode and the second electrode may be made of the same material, may be made of the same kind of material, or may be made of different materials. In order to form the first electrode or the second electrode, the conductive material layer is patterned in a step after forming the conductive material layer constituting the first electrode or the conductive material layer constituting the second electrode. do it. The conductive material layer can be formed by a method suitable for the material constituting the conductive material layer, such as sputtering, reactive sputtering, electron beam evaporation, MOCVD, or pulsed laser ablation. The patterning of the conductive material layer can be performed by, for example, an ion milling method or an RIE method.
[0060]
The selection transistor, the write transistor, the read transistor, and the detection transistor can be constituted by, for example, a well-known MIS type FET or MOS type FET. Examples of the material constituting the bit line and the wiring include polysilicon doped with impurities and a refractory metal material. The connection between the selection transistor and the common first electrode, the connection between the selection transistor and the bit line, etc. may be made through a connection hole. It can be obtained by embedding silicon.
[0061]
In the present invention, silicon oxide (SiO₂), Silicon nitride (SiN), SiON, SOG, NSG, BPSG, PSG, BSG, or LTO.
[0062]
In the ferroelectric nonvolatile semiconductor memory of the present invention, since at least 2M memory cells are provided for one write transistor, one detection transistor, and one read transistor, 1 The cell area per bit can be reduced. Furthermore, since a plurality of memory unit blocks are provided, the cell area per bit can be further reduced. In addition, a change in the potential of the common first electrode corresponding to the stored data is detected by the signal detection circuit, or is detected by the potential generated at the common first electrode based on the data stored in the memory cell. Although the operation of the transistor is controlled, since the first electrode is common to the M memory cells, a kind of additional load capacitance is added to the first electrode. As a result, when data is read, when a voltage is applied to the plate line, the potential increase of the first electrode can be suppressed, and a sufficient potential difference is generated between the first electrode and the second electrode. The polarization inversion surely occurs in the ferroelectric layer.
[0063]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described based on embodiments of the invention (hereinafter abbreviated as embodiments) with reference to the drawings.
[0064]
(Embodiment 1)
The first embodiment relates to a gain cell type ferroelectric nonvolatile semiconductor memory (hereinafter abbreviated as a nonvolatile memory) according to the first and second aspects of the present invention. A circuit diagram of the nonvolatile memory of Embodiment 1 is shown in FIG. 1, and a more specific circuit diagram of the memory unit in FIG. 1 is shown in FIG. Further, FIG. 3 shows a schematic layout of various transistors constituting the nonvolatile memory. In FIG. 3, various transistor regions are surrounded by dotted lines, active regions and wirings are indicated by solid lines, and gate electrodes or word lines are indicated by alternate long and short dash lines. FIG. 4 is a schematic partial cross-sectional view of the nonvolatile memory according to the first embodiment in parallel with the extending direction of the bit line when the nonvolatile memory is cut along the arrow AA in FIG. FIG. 5 shows a schematic partial cross-sectional view of the nonvolatile memory according to the first embodiment in a direction parallel to the extending direction of the bit line when the nonvolatile memory is cut along the arrow BB in FIG. In the figure, two memory unit blocks (which constitute one nonvolatile memory) adjacent to each other in the bit line direction are illustrated, but a reference numeral of one component of the memory unit block is denoted by “′”. Reference numerals 17, 17 'and the like in FIG. 1 correspond to the reference numbers of the connection holes and wirings in FIGS. Since the two memory unit blocks have the same configuration, one memory unit block will be described below. Further, in FIG. 1, in a memory unit in which a plate line extends in the memory unit, it means that the memory cells constituting the memory unit are controlled by the plate line. On the other hand, in the memory unit in which the plate line does not extend in the memory unit, it means that the memory cells constituting the memory unit are not controlled by the plate line.
[0065]
The nonvolatile memory in the first embodiment is
(A) a signal detection circuit;
(B) A plurality of memory unit blocks MB, MB ′,
Consisting of
For example, the memory unit block MB is
(B-1) Selection transistor TR_SWhen,
(B-2) M memory cells MC (where M ≧ 2 and M = 8 in the first embodiment)_MA memory unit MU comprising:
(B-3) M plate lines PL_M,
Consists of.
[0066]
And each memory cell MC_mIs composed of a first electrode 21, a ferroelectric layer 22, and a second electrode 23. In the memory unit MU of the memory unit block MB, the memory cell MC_mThe first electrodes 21 are common, and the common first electrode 21 (sometimes referred to as a common node CN) is a selection transistor TR of the memory unit block MB._SAnd connected to a signal detection circuit. Further, in the memory unit MU of the memory unit block MB, the mth (where m = 1, 2,..., M) memory cell MC._mThe second electrode 23 is connected to the mth plate line PL of the memory unit block MB._mIt is connected to the. The signal detection circuit then changes the potential (memory cell MC) of the common first electrode 21 (common node CN) in the memory unit MU of the memory unit block MB._mBased on the data stored in (1), and the detection result is transmitted to the bit line BL as a current or voltage. More specifically, this signal detection circuit includes a write transistor TR described below._WAnd reading transistor TR_RAnd detection transistor TR_DIt is composed of
[0067]
Alternatively, the nonvolatile memory of Embodiment 1 is
(A) a bit line BL;
(B) Write transistor TR_WWhen,
(C) Reading transistor TR_RWhen,
(D) Detection transistor TR_DWhen,
(E) a plurality of memory unit blocks MB, MB ′,
Consisting of
For example, the memory unit block MB is
(E-1) Selection transistor TR_SWhen,
(E-2) M memory cells MC (where M ≧ 2 and M = 8 in the first embodiment)_MA memory unit MU comprising:
(E-3) M plate lines PL_M,
Consists of.
[0068]
And each memory cell MC_mIs composed of a first electrode 21, a ferroelectric layer 22, and a second electrode 23. In the memory unit MU of the memory unit block MB, the memory cell MC_MThe first electrodes 21 are common, and the common first electrode 21 (common node CN) is a selection transistor TR of the memory unit block MB._SAnd the writing transistor TR_WTo the bit line BL. Furthermore, in the memory unit MU of the memory unit block MB, the mth (where m = 1, 2,..., M) memory cell MC._mThe second electrode 23 is connected to the mth plate line PL of the memory unit block MB._mIt is connected to the. Also, the detection transistor TR_DIs connected to a predetermined potential (for example, power supply V_cc), And the other end is connected to the read transistor TR._RTo the bit line BL.
[0069]
More specifically, the various transistors are composed of MOS type FETs, and the write transistor TR_WOne source / drain region 14 is connected to the bit line BL through the connection hole 15, and the other source / drain region 14 has a connection hole 18B, a wiring (may be called a sub-bit line) 19, and a connection hole 18C. Select transistor TR_SAre connected to one of the source / drain regions 14. Also, the detection transistor TR_DOne source / drain region 14 has a predetermined potential (power source V_cc), And the other source / drain region 14 is connected to the read transistor TR._RAre connected to one of the source / drain regions 14. The detection transistor TR_DSource / drain region 14 and read transistor TR_ROne source / drain region 14 occupies one source / drain region 14. Here, the fact that the source / drain region 14 of a certain transistor and the source / drain region 14 of another transistor are common means that the source / drain region 14 occupies one, or wiring Means connected. The same applies to the following description.
[0070]
Further, the reading transistor TR_RThe other source / drain region 14 is connected to the bit line BL via the connection hole 15. Read transistor TR_RSource / drain region 14 and write transistor TR_WOne source / drain region 14 occupies one source / drain region 14. The selection transistor TR_SThe other source / drain region 14 is connected to the common first electrode 21 (common node CN) via the connection hole 17. Write transistor TR_WThe other source / drain region 14 and the one source / drain region 14 of the selection transistor are connected to the detection transistor TR via the connection holes 18B and 18C, the sub bit line 19, and the connection hole 18A._DConnected to the gate electrode. Memory unit block MB_ASelection transistor TR constituting '_SThe one source / drain region 14 of 'is connected to the writing transistor TR via the connection hole 18C, the sub bit line 19, and the connection hole 18B._WIs connected to the other source / drain region 14, and the other source / drain region 14 is connected to the memory unit block MB via the connection hole 17 '._A'Is connected to a common first electrode 21 (common node) constituting'.
[0071]
For example, the memory cell MC of the memory unit block MB_mWhen writing data to
(1) Writing transistor TR_W,as well as,
(2) Transistor TR for selecting memory unit block MB_S,
Is turned on,
(3) Reading transistor TR_R,as well as,
(4) Transistor TR for selection of memory unit block MB 'other than memory unit block MB_S’,
Is turned off,
For example, the memory cell MC of the memory unit block MB_mWhen reading the data stored in
(1) Writing transistor TR_W,as well as,
(2) Transistor TR for selection of memory unit block MB 'other than memory unit block MB_S’,
Is turned off,
(3) Reading transistor TR_R,as well as,
(4) Transistor TR for selecting memory unit block MB_S,
Is rendered conductive, and the memory cell MC of the memory unit block MB_mTransistor TR for detection based on the potential generated at the common first electrode 21 (common node CN) based on the data stored in_DIs controlled.
[0072]
Write transistor TR_WRead transistor TR_R, And a selection transistor TR_S, TR_SWord line WL for controlling the operation of '_W, WL_R, WL_S, WL_S'Is connected to a word line decoder / driver WD. These word lines extend in the direction perpendicular to the plane of FIG. 4 and FIG. On the other hand, the bit line BL is connected to the sense amplifier SA. Plate wire PL_MAre connected to a plate line decoder / driver PD. Each word line WL_W, WL_R, WL_S, WL_S'Is common to another non-volatile memory adjacent in the direction perpendicular to the plane of FIG. 4 and FIG. In addition, the memory cell MC constituting the nonvolatile memory_mThe second electrode 23 is the same as the second electrode of the memory cell constituting another nonvolatile memory adjacent in the direction perpendicular to the plane of FIG. 4 and FIG._mDoubles as
[0073]
First, a data write operation to the nonvolatile memory according to the first embodiment will be described below. As an example, plate wire PL_mMemory cell MC connected to_mData shall be written to FIG. 6 shows operation waveforms. In FIG. 6 and FIG. 7 to be described later, the numbers in parentheses correspond to the numbers of the steps described below.
[0074]
(1A) In the standby state, the bit lines, all word lines, and all plate lines are at 0 volts. Furthermore, the common node CN is also floating at 0 volts. Read transistor TR during write operation_RAnd a transistor TR for selecting a memory unit block MB 'other than the memory unit block MB_S'Is always in the off state.
[0075]
(2A) At the start of data writing, the selected plate line PL_mThe potential of V_ccUnselected plate line PL_jThe potential of (j ≠ m) is set to (1/2) V_ccAnd As a result, the potential of the common node CN in the floating state becomes the plate line PL._M(1/2) V due to coupling with_ccIt rises to the vicinity. When data “1” is written to the selected memory cell, the potential of the bit line BL is set to V_ccWhen data “0” is written, the potential of the bit line BL is set to 0 volts.
[0076]
(3A) Thereafter, the writing transistor TR_WAnd selection transistor TR_SIs turned on. As a result, the potential of the common node CN becomes V V when data “1” is written in the selected memory cell._ccThus, when data “0” is written, it becomes 0 volt. Select plate line PL_mV_ccWhen the potential of the common node CN is 0 volt, the selected memory cell MC is_mData “0” is written in On the other hand, the potential of the common node CN is V_ccIn the case of the selected memory cell MC_mNo data is written to.
[0077]
(4A) Next, the selected plate line PL_mIs set to 0 volts. The potential of the common node CN is V_ccIn the case of the selected memory cell MC_mData “1” is written in Selected memory cell MC_mIf data “0” has already been written to the selected memory cell MC_mThere will be no change.
[0078]
(5A) Thereafter, the bit line BL is applied with 0 volt.
[0079]
(6A) Further, non-selected plate line PL_jIs 0 volt, and the writing transistor TR_WAnd selection transistor TR_SIs turned off.
[0080]
Other memory cells MC_mThe same operation is repeated when data is written to. In such a write operation, the non-selected memory cell MC_j(± 1/2) V_ccDisturbance occurs but V_ccBy appropriately setting the value of the unselected memory cell MC_jCan reliably prevent data destruction.
[0081]
Next, an operation of reading data from the nonvolatile memory of Embodiment 1 and rewriting the data will be described below. As an example, plate wire PL_mMemory cell MC connected to_mIt is assumed that data is read from and data is rewritten. FIG. 7 shows operation waveforms.
[0082]
(1B) In the standby state, the bit lines, word lines, and all plate lines are at 0 volts. Furthermore, the common node CN is also floating at 0 volts. A transistor TR for selecting a memory unit block MB 'other than the memory unit block MB at the time of data reading and rewriting_S'Is always in the off state.
[0083]
(2B) When reading data, select plate line PL_mV_ccApply. At this time, the selected memory cell MC_mIf data “1” is stored in the ferroelectric layer, polarization inversion occurs in the ferroelectric layer, the amount of stored charge increases, and the potential of the common node CN increases. On the other hand, the selected memory cell MC_mIf data “0” is stored in the ferroelectric layer, polarization inversion does not occur in the ferroelectric layer, and the potential of the common node CN hardly increases. That is, the common node CN is connected to a plurality of unselected plate lines PL via the ferroelectric layers of the unselected memory cells._jTherefore, the potential of the common node CN is kept at a level relatively close to 0 volts. In this way, the selected memory cell MC_mThe potential of the common node CN changes depending on the data stored in the memory. Therefore, an electric field sufficient for polarization inversion can be applied to the ferroelectric layer of the selected memory cell.
[0084]
(3B) Next, the bit line BL is brought into a floating state, and the selection transistor TR_SAnd reading transistor TR_RIs turned on. As a result, the selected memory cell MC_mTransistor TR for detection based on the potential generated at the common first electrode (common node CN) based on the data stored in_DIs controlled. Specifically, the detection transistor TR_DOne source / drain region 14 has a predetermined potential V_ccSelected memory cell MC_mIf the data “1” is stored in the detection transistor TR_DIs turned on, and the detection transistor TR_DAnd reading transistor TR_RA current flows through the bit line BL through the bit line, and the potential of the bit line BL rises. On the other hand, the selected memory cell MC_mIf data “0” is stored in the detection transistor TR_DIs turned off, and the potential of the bit line BL does not rise. Here, the detection transistor TR_DThreshold of V_th, Detection transistor TR_DThe potential of the gate electrode (that is, the potential of the common node CN) is V_gThen, the potential of the bit line BL is approximately (V_g-V_th) The detection transistor TR_DIs a depletion type NMOSFET, the threshold V_thTakes a negative value. Thereby, a stable sense signal amount can be ensured regardless of the load of the bit line BL. The detection transistor TR_DCan also be constructed from PMOSFETs. The same applies to the following embodiments.
[0085]
(4B) Next, a selection transistor TR_SAnd reading transistor TR_RIs turned off.
[0086]
(5B) Thereafter, the sense amplifier SA connected to the bit line BL is activated to amplify the data, and the data read operation is completed.
[0087]
With the above operation, the selected memory cell MC_mSince the data stored in the memory is once destroyed, the data rewrite operation is performed.
[0088]
(6B) Therefore, first, the non-selected plate line PL_jThe potential of (j ≠ m) is set to (1/2) V_ccAnd
[0089]
(7B) Thereafter, the transistor for selection TR_SAnd writing transistor TR_WIs turned on. As a result, the potential of the common node CN becomes equal to the potential of the bit line BL. That is, the selected memory cell MC_mWhen the data stored in “1” is “1”, the potential of the common node CN is V_ccThe selected memory cell MC_mWhen the data stored in is “0”, the potential of the common node CN is 0 volts. Selection plate line PL_mThe potential of V is V_ccTherefore, when the potential of the common node CN is 0 volt, the selected memory cell MC_mThe data “0” is rewritten to.
[0090]
(8B) Next, the selected plate line PL_mIs set to 0 volts. As a result, the selected memory cell MC_mWhen the data stored in is “1”, the potential of the common node CN is V_ccTherefore, the data “1” is rewritten. Selected memory cell MC_mIf data “0” has already been rewritten in the memory cell, no change occurs in the selected memory cell.
[0091]
(9B) Thereafter, the bit line BL is set to 0 volts.
[0092]
(10B) Finally, unselected plate line PL_jIs set to 0 volts, and the transistor for selection TR_SAnd writing transistor TR_WIs turned off.
[0093]
Other memory cells MC_mWhen data is read from and rewritten, the same operation is repeated.
[0094]
In the above-described step (2B), the number (M) of the memory cells constituting the memory unit MU applies a sufficiently large electric field to the ferroelectric layer of the selected memory cell, and the polarization inversion is reliably performed on the ferroelectric layer. It is necessary to make the number such that the above occurs. That is, if the value of M is too small, in the step (2B), the selected plate line PL_mV_ccWhen the voltage is applied, the potential of the first electrode in a floating state increases greatly due to the coupling between the second electrode and the first electrode, and the gap between the second electrode and the first electrode is increased. A sufficient electric field is not formed, and polarization inversion does not occur in the ferroelectric layer. On the other hand, the potential appearing on the first electrode (referred to as signal potential) is obtained by dividing the amount of accumulated charge by the load capacitance. Therefore, if the value of M is too large, the potential appearing on the first electrode becomes too low.
[0095]
FIG. 8 shows the result of simulating the relationship between the value of M and the signal potential. Here, the relationship between the number of memory cells (M) in the circuits shown in FIGS. 1 and 2 and the signal potential was obtained based on the actual measured hysteresis value of the ferroelectric layer in the memory cell. The area of the ferroelectric layer constituting each memory cell is 0.5 μm.²And load capacitance other than the memory cell of the common node CN (mainly, the detection transistor TR_D2fF, power supply voltage V_ccWas 2.5 volts.
[0096]
Selection plate line PL_mV_ccWhen data “1” is stored in the selected memory cell when an electric field is applied, an electric field is generated in the direction of inverting the polarization of the ferroelectric layer between the first electrode and the second electrode. Accordingly, the signal potential from such a selected memory cell (the potential appearing on the first electrode in the floating state, and the detection transistor TR_DPotential V applied to the gate electrode of_g) Is higher than when data “0” is stored. Then, the greater the difference between the signal potential when the data “1” is stored and the signal potential when the data “0” is stored, the higher the reliability of data reading.
[0097]
When the value of M is 1, it is equivalent to the circuit shown in FIG. 31B, and as a result of the load capacity at the common node CN being too small, the signal potential when data “1” is stored and the data “ The signal potential when “0” is stored rises to about 2.2 volts, and the selected plate line PL_mV applied to_ccThe potential difference between (= 2.5 volts) is only about 0.3 volts. Therefore, the polarization inversion of the ferroelectric layer is insufficient, and it becomes difficult to read data from the selected memory cell.
[0098]
On the other hand, when the value of M is 2 or more, the selected plate line PL is selected in the selected memory cell._mV applied to_ccThe potential difference between (= 2.5 volts) and the signal potential (indicated by “signal amount” in FIG. 8) becomes sufficiently large, and data can be reliably read from the selected memory cell. As the value of M increases, the load capacity of the common node CN increases, and when the value of M exceeds a certain level, this time, the selected plate line PL_mV applied to_ccThe value of the signal amount, which is the potential difference between the signal potential and the signal potential, starts to decrease.
[0099]
As described above, it has been found that there is an optimum value for M, and the optimum value for M is 2 ≦ M ≦ 128, preferably 4 ≦ M ≦ 32.
[0100]
Only N common nodes (two in the first embodiment) are connected to the sub-bit line 19, and the parasitic capacitance caused by the sub-bit line capacitance and the junction capacitance is very small. Therefore, the load capacity of the sub bit line 19 is defined by the number of non-selected memory cells of the selected memory unit, and a sufficiently large sense signal amount can be obtained if the number of memory cells constituting the memory unit is appropriately set. Can do. In addition, since most of the load capacity of the sub-bit line is caused by the non-selected memory cells, the load capacity is simultaneously scaled even if the non-volatile memory is miniaturized and the memory cells are reduced. Therefore, the sense signal amount hardly changes even when the memory cell is reduced.
[0101]
Hereinafter, although the manufacturing method of the non-volatile memory of Embodiment 1 is demonstrated, the non-volatile memory in other embodiment can also be manufactured by the same method.
[0102]
[Step-100]
First, various transistors TR in the nonvolatile memory_W, TR_R, TR_D, TR_SThe MOS FET functioning as is formed on the semiconductor substrate 10. Therefore, for example, the element isolation region 11 having a LOCOS structure is formed based on a known method. The element isolation region may have a trench structure, or a combination of a LOCOS structure and a trench structure. Thereafter, the surface of the semiconductor substrate 10 is oxidized by, for example, a pyrogenic method to form the gate insulating film 12. Next, after a polysilicon layer doped with impurities is formed on the entire surface by a CVD method, the polysilicon layer is patterned to form the gate electrode 13. The gate electrode 13 also serves as a word line. The gate electrode 13 can be made of polycide or metal silicide instead of the polysilicon layer. Next, ion implantation is performed on the semiconductor substrate 10 to form an LDD structure. After that, the entire surface is SiO₂After forming the layer, this SiO 2₂By etching back the layer, a gate sidewall (not shown) is formed on the side surface of the gate electrode 13. Next, after ion implantation is performed on the semiconductor substrate 10, a source / drain region 14 is formed by performing activation annealing of the implanted impurities.
[0103]
[Step-110]
Then SiO₂After forming the lower insulating layer 16A made of CVD by the CVD method, the writing transistor TR_WSource / drain region 14 and read transistor TR_RSource / drain region 14 and write transistor TR_WSource / drain region 14, and detection transistor TR_DGate electrode, selection transistor TR_SAn opening is formed in the lower insulating layer 16A above each one of the source / drain regions 14 by the RIE method. Then, a polysilicon layer doped with impurities is formed on the lower insulating layer 16A including the inside of the opening by a CVD method. Thereby, connection holes (contact holes) 15, 18A, 18B, 18C can be obtained. Next, the bit line BL and the sub bit line 19 are formed by patterning the polysilicon layer on the lower insulating layer 16A. The connection holes 18A, 18B, and 18C are electrically connected by the sub bit line 19. Thereafter, an upper insulating layer 16B made of BPSG is formed on the entire surface by a CVD method. Note that, after the formation of the upper insulating layer 16B made of BPSG, it is preferable to reflow the upper insulating layer in a nitrogen gas atmosphere, for example, at 900 ° C. for 20 minutes. Furthermore, it is desirable to planarize the upper insulating layer 16B by chemically and mechanically polishing the top surface of the upper insulating layer 16B, for example, by a chemical mechanical polishing method (CMP method) as necessary. The lower insulating layer and the upper insulating layer may be collectively referred to as an insulating layer 16 in some cases.
[0104]
[Step-120]
Next, the selection transistor TR_SAn opening is formed in the insulating layer 16 above the other source / drain region 14 by the RIE method, and then the opening is filled with polysilicon doped with impurities to complete a connection hole (contact hole) 17. . The bit line BL extends on the lower insulating layer 16A so as not to contact the connection hole 17 in the left-right direction in the drawing.
[0105]
The connection holes 15, 18 </ b> A, 18 </ b> B, 18 </ b> C, 17 are, for example, tungsten, Ti, Pt, Pd, Cu, TiW, TiNW, WSi in the opening formed in the insulating layer 16.₂, MoSi₂It can also be formed by embedding a metal wiring material composed of a refractory metal such as metal or a metal silicide. The top surface of the connection hole 17 may exist in substantially the same plane as the surface of the upper insulating layer 16B, or the top portion of the connection hole 17 may extend to the surface of the upper insulating layer 16B. The conditions for filling the openings with tungsten and forming the connection holes 17 are illustrated in Table 2 below. Note that, before the opening is filled with tungsten, it is preferable that the Ti layer and the TiN layer are sequentially formed on the insulating layer 16 including the inside of the opening by, for example, magnetron sputtering. Here, the reason for forming the Ti layer and the TiN layer is to obtain an ohmic low contact resistance, to prevent damage to the semiconductor substrate 10 in the blanket tungsten CVD method, and to improve the adhesion of tungsten.
[0106]
[Table 2]
Sputtering conditions for Ti layer (thickness: 20 nm)
Process gas: Ar = 35 sccm
Pressure: 0.52 Pa
RF power: 2kW
Substrate heating: None
Sputtering conditions for TiN layer (thickness: 100 nm)
Process gas: N₂/ Ar = 100 / 35sccm
Pressure: 1.0 Pa
RF power: 6kW
Substrate heating: None
Conditions for tungsten CVD
Gas used: WF₆/ H₂/ Ar = 40/400 / 2250sccm
Pressure: 10.7kPa
Formation temperature: 450 ° C
Etching conditions for tungsten layer, TiN layer, and Ti layer
First stage etching: Tungsten layer etching
Gas used: SF₆/ Ar / He = 110: 90: 5 sccm
Pressure: 46Pa
RF power: 275W
Second stage etching: TiN layer / Ti layer etching
Gas used: Ar / Cl₂= 75 / 5sccm
Pressure: 6.5Pa
RF power: 250W
[0107]
[Step-130]
Next, it is desirable to form an adhesion layer (not shown) made of TiN on the insulating layer 16. Then, a first electrode material layer constituting the first electrode (lower electrode) 21 made of Ir is formed on the adhesion layer by, for example, sputtering, and the first electrode material layer and the adhesion layer are formed by a photolithography technique. The first electrode 21 (common node CN) can be obtained by patterning based on the dry etching technique.
[0108]
[Step-140]
Thereafter, a Bi-based layered perovskite ferroelectric material (specifically, for example, Bi having a crystallization temperature of 750 ° C.) is formed by, for example, MOCVD.₂SrTa₂O₉Is formed over the entire surface. Then, after drying in air at 250 ° C, heat treatment was performed in an oxygen gas atmosphere at 750 ° C for 1 hour to promote crystallization, and then, if necessary, photolithography technology, dry etching The ferroelectric thin film 22 is obtained by patterning the ferroelectric thin film based on the technology.
[0109]
[Step-150]
Next, IrO_2-XAfter a layer and a Pt layer are sequentially formed on the entire surface by a sputtering method, a Pt layer, an IrO layer are formed based on a photolithography technique and a dry etching technique._2-XThe layer and the ferroelectric layer 22 are sequentially patterned to obtain the plate line PL._mThe second electrode 23 and the ferroelectric layer 22 that also serve as the above are formed. When the ferroelectric layer 22 is damaged by etching, heat treatment may be performed at a temperature required for damage recovery. Thereafter, an insulating film 26 </ b> A is formed on the insulating layer 16 and the second electrode 23.
[0110]
In the manufacture of the nonvolatile memory in Embodiments 2 to 5 described later,
-Formation and planarization of the interlayer insulating layer 26
-Formation of opening and formation of connection hole 27
First electrode 31, Bi at crystallization temperature 700 ° C₂Sr (Ta_1.5Nb_0.5) O₉Formation of the ferroelectric layer 32 and the second electrode 33
Formation of insulating film 36A
May be performed sequentially. Bi₂Sr (Ta_1.5Nb_0.5) O₉The ferroelectric layer 32 made of may be heat-treated for promoting crystallization in an oxygen gas atmosphere at 700 ° C. for 1 hour.
[0111]
Each second electrode may not serve as a plate line. In this case, after the formation of the insulating films 26A and 36A is completed, the second electrode 23 and the second electrode 33 are connected by connection holes (via holes), and the connection holes are also formed on the insulating films 26A and 36A. And a plate line connected to each other may be formed.
[0112]
For example, Bi₂SrTa₂O₉Table 3 below illustrates conditions for forming a ferroelectric thin film made of In Table 3, “thd” is an abbreviation for tetramethylheptanedionate. The source materials shown in Table 3 are dissolved in a solvent containing tetrahydrofuran (THF) as a main component.
[0113]

[0114]
Alternatively, Bi₂SrTa₂O₉It is also possible to form a ferroelectric thin film made of the above by the pulse laser ablation method, the sol-gel method, or the RF sputtering method. The formation conditions in these cases are illustrated in Table 4, Table 5, and Table 6 below. When a thick ferroelectric thin film is formed by the sol-gel method, a desired number of times of spin coating and drying, or spin coating and baking (or annealing treatment) may be repeated.
[0115]
[Table 4]
Formation by pulsed laser ablation
Target: Bi₂SrTa₂O₉
Laser used: KrF excimer laser (wavelength 248 nm, pulse width 25 ns, 5 Hz)
Formation temperature: 400-800 ° C
Oxygen concentration: 3 Pa
[0116]

[0117]
[Table 6]
Formation by RF sputtering
Target: Bi₂SrTa₂O₉Ceramic target
RF power: 1.2W-2.0W / target 1cm²
Atmospheric pressure: 0.2 to 1.3 Pa
Formation temperature: Room temperature to 600 ° C
Process gas: Ar / O₂Flow rate ratio = 2/1 to 9/1
[0118]
Table 7 below illustrates the formation conditions of PZT or PLZT by magnetron sputtering when the ferroelectric layer is made of PZT or PLZT. Alternatively, PZT or PLZT can be formed by reactive sputtering, electron beam evaporation, sol-gel, or MOCVD.
[0119]
[Table 7]
Target: PZT or PLZT
Process gas: Ar / O₂= 90% by volume / 10% by volume
Pressure: 4Pa
Power: 50W
Formation temperature: 500 ° C
[0120]
Furthermore, PZT and PLZT can be formed by a pulse laser ablation method. The formation conditions in this case are illustrated in Table 8 below.
[0121]
[Table 8]
Target: PZT or PLZT
Laser used: KrF excimer laser (wavelength 248 nm, pulse width 25 ns, 3 Hz)
Output energy: 400 mJ (1.1 J / cm²)
Formation temperature: 550-600 ° C
Oxygen concentration: 40 to 120 Pa
[0122]
By simultaneously operating the memory cells constituting each of the two nonvolatile memories of the first embodiment adjacent to each other in the direction in which the plate lines extend (these memory cells share the same plate line), One bit can be stored in a complementary manner in the memory cell, or one bit can be stored in each of the two memory cells P by operating independently. Details of these operations will be described in the second embodiment.
[0123]
(Embodiment 2)
The second embodiment relates to a gain cell type nonvolatile memory according to the third and fourth aspects of the present invention. A circuit diagram of the nonvolatile memory according to the second embodiment is shown in FIG. 9, and a more specific circuit diagram of the memory unit in FIG. 9 is shown in FIG. FIG. 11 is a schematic partial cross-sectional view of the nonvolatile memory according to the second embodiment parallel to the direction in which the bit line extends when the nonvolatile memory is cut. In the figure, two memory unit blocks (which constitute one nonvolatile memory) adjacent to each other in the bit line direction are illustrated, but a reference numeral of one component of the memory unit block is denoted by “′”. Since the two memory unit blocks have the same configuration, only one memory unit block will be described below. Here, FIG. 10 shows another nonvolatile memory M adjacent in the direction in which the plate line extends._BOne memory unit block MB in_BThis memory unit block MB_BIs memory unit block MB_AHas the same configuration.
[0124]
Nonvolatile Memory M of Embodiment 2_AIs
(A) a signal detection circuit;
(B) Multiple memory unit blocks MB_A, MB_A’,
Consisting of
For example, memory unit block MB_AIs
(B-1) Selection transistor TR_SAWhen,
(B-2) M memory cells MC each (where M ≧ 2 and M = 8 in the second embodiment)_ANMN memory units MU (where N ≧ 2, and N = 2 in the second embodiment)_ANWhen,
(B-3) M × N plate wires,
Consists of.
[0125]
And memory unit block MB_AN memory units MU_ANAre stacked via an insulating layer 26 (hereinafter referred to as an interlayer insulating layer 26 for convenience), and each memory cell MC_ANMConsists of first electrodes 21, 31, ferroelectric layers 22, 32 and second electrodes 23, 33. And memory unit block MB_AEach memory unit MU_AnMemory cell MC_AnmThe first electrodes are common, and these common first electrodes are the memory unit block MB._ASelection transistor TR_SAAnd connected to a signal detection circuit. Furthermore, the memory unit block MB_AN-th memory unit MU (where n = 1, 2,..., N)_An, The mth memory cell MC (where m = 1, 2,..., M)_AnmThe second electrode of the memory unit block MB_A[(N-1) M + m] -th plate line PL_{(n-1) M + m}It is connected to the. The signal detection circuit is connected to the memory unit block MB._AMemory unit MU_AnChange of the potential of the common first electrode in the memory cell MC_AnmBased on the data stored in the bit line BL)_AAs current or voltage. More specifically, this signal detection circuit includes a write transistor TR described below._WAnd reading transistor TR_RAnd detection transistor TR_DIt is composed of
[0126]
Alternatively, the nonvolatile memory M of the second embodiment_AIs
(A) Bit line BL_AWhen,
(B) Write transistor TR_WWhen,
(C) Reading transistor TR_RWhen,
(D) Detection transistor TR_DWhen,
(E) Multiple memory unit blocks MB_A, MB_A’,
Consisting of
For example, memory unit block MB_AIs
(E-1) Selection transistor TR_SAWhen,
(E-2) Each of M memory cells MC (where M ≧ 2 and M = 8 in the second embodiment)_ANMN memory units MU (where N ≧ 2, and N = 2 in the second embodiment)_ANWhen,
(E-3) M × N plate wires,
Consists of.
[0127]
And memory unit block MB_AN memory units MU_ANAre stacked via an interlayer insulating layer 26, and each memory cell MC_ANMConsists of first electrodes 21, 31, ferroelectric layers 22, 32 and second electrodes 23, 33. Memory unit block MB_AEach memory unit MU_AnMemory cell MC_AnmThe first electrodes are common, and these common first electrodes are the memory unit block MB._ASelection transistor TR_SAAnd the writing transistor TR_WVia the bit line BL_AIt is connected to the. Specifically, the memory unit MU_A1Memory cell MC_A1MThe first electrode 21 is common (this common first electrode is connected to the first common node CN)._A1A common first electrode 21 (first common node CN)._A1) Is a transistor for selection TR_SAAnd the writing transistor TR_WVia the bit line BL_AIt is connected to the. In addition, the memory unit MU_A2Memory cell MC_A2MThe first electrode 31 is common (this common first electrode is used as the second common node CN)._A2Common first electrode 31 (second common node CN)._A2) Is a transistor for selection TR_SAAnd the writing transistor TR_WVia the bit line BL_AIt is connected to the. Furthermore, the memory unit MU of the nth layer (where n = 1, 2,..., N)_An, The mth memory cell MC (where m = 1, 2,..., M)_AnmThe second electrodes 23 and 33 are connected to the [(n−1) M + m] -th plate line PL._{(n-1) M + m}It is connected to the. This plate line PL_{(n-1) M + m}Is a non-volatile memory M adjacent in the direction in which the plate line extends._BMemory unit block MB_BEach memory cell MC comprising_BNMThe second electrodes 23 and 33 are also connected. In the second embodiment, more specifically, each plate line extends from the second electrodes 23 and 33.
[0128]
Selection transistor TR_SAOne source / drain region 14 includes a connection hole 18C, a sub bit line 19, a connection hole 18B, and a writing transistor TR._WVia the bit line BL_AIt is connected to the. On the other hand, the selection transistor TR_SAThe other source / drain region 14 is connected to the first layer memory unit MU via a connection hole 17 provided in the insulating layer 16._A1First electrode 21 (first common node CN)_A1)It is connected to the. Furthermore, the transistor for selection TR_SAThe other source / drain region 14 is connected to the second layer memory unit MU via a connection hole 17 provided in the insulating layer 16 and a connection hole 27 provided in the interlayer insulating layer 26._A2First electrode 31 (second common node CN)_A2)It is connected to the. In the figure, reference numeral 36A is an insulating film.
[0129]
Bit line BL_AAre connected to the sense amplifier SA. Plate wire PL_{(n-1) M + m}Are connected to a plate line decoder / driver PD. Furthermore, the word line WL_SAre connected to a word line decoder / driver WD. The word line WL extends in the direction perpendicular to the paper surface of FIG. Nonvolatile memory M_AMemory unit block MB_AMemory cell MC constituting_A1mThe second electrode 23 is connected to another nonvolatile memory M adjacent in the direction perpendicular to the paper surface of FIG._BMemory unit block MB_BMemory cell MC constituting_B1mThe second electrode of the plate line PL_{(n-1) M + m}Doubles as Furthermore, the non-volatile memory M_AMemory unit block MB_AMemory cell MC constituting_A2mThe second electrode 33 is connected to another nonvolatile memory M adjacent in the direction perpendicular to the plane of FIG._BMemory unit block MB_BMemory cell MC constituting_B2mThe second electrode of the plate line PL_{(n-1) M + m}Doubles as Also, the word line WL_SIs a non-volatile memory M_ATransistor TR for configuring_SAAnd another non-volatile memory M adjacent in the direction perpendicular to the paper surface of FIG._BTransistor TR for configuring_SBAnd is common.
[0130]
Detection transistor TR_DIs connected to a predetermined potential (for example, power supply V_cc), And the other end is connected to the read transistor TR._RVia the bit line BL_AIt is connected to the. Write transistor TR_WRead transistor TR_RAnd detection transistor TR_DSince the configuration, the operation thereof, and the relationship between these and the memory unit block can be substantially the same as those in the first embodiment, detailed description thereof is omitted.
[0131]
And memory unit block MB_AFor example, memory cell MC_AnmWhen writing data to
(1) Writing transistor TR_W,as well as,
(2) Memory unit block MB_ASelection transistor TR_SA,
Is turned on,
(3) Reading transistor TR_R,as well as,
(4) Memory unit block MB_AMemory unit block MB other than_A′ Selection transistor TR_SA’,
Is turned off,
Memory unit block MB_AFor example, memory cell MC_AnmWhen reading the data stored in
(1) Writing transistor TR_W,as well as,
(2) Memory unit block MB_AMemory unit block MB other than_A′ Selection transistor TR_SA’,
Is turned off,
(3) Reading transistor TR_R,as well as,
(4) Memory unit block MB_ASelection transistor TR_SA,
Is rendered conductive and the memory unit block MB_AFor example, memory cell MC_AnmBased on the data stored in the common first electrode (CN_An), The detection transistor TR_DIs controlled.
[0132]
Non-volatile memory M whose circuit diagram is shown in FIG._A, M_BIn the non-volatile memory M_A, M_BTransistor TR for configuring_SA, TR_SBIs the same word line WL_SIt is connected to the. The paired memory cells MC_Anm, MC_BnmComplementary data is stored (n = 1, 2,..., N and m = 1, 2,..., M). For example, the memory cell MC_Anm, MC_BnmWhen reading data stored in (where m is any one of 1, 2,..., 8), the word line WL_SSelect the plate line PL_j(M ≠ j) includes, for example, (1/2) V_ccWith the voltage of_{(n-1) M + m}Drive. Where V_ccIs, for example, a power supply voltage. As a result, the potential corresponding to the complementary data becomes a pair of memory cells MC._Anm, MC_BnmTo common node CN_An, CN_BnAs a result, the detection transistor TR_D, Detection transistor TR_BD(This detection transistor TR_BDIs a non-volatile memory M_BThe potential corresponding to the complementary data is detected by the detection transistor TR._DRead transistor TR_RAnd detection transistor TR_BDRead transistor TR_BR(This reading transistor TR_BRIs a non-volatile memory M_BBit line BL paired via a read transistor constituting_A, BL_BAppears as a voltage (bit line potential). The paired bit lines BL_A, BL_BIs detected by the sense amplifier SA.
[0133]
Hereinafter, a method of reading and rewriting data from the nonvolatile memory of Embodiment 2 will be described. As an example, a pair of nonvolatile memories M_A, M_BPaired memory cells MC (ie, plate lines are common)_A11, MC_B11Data is read from the memory cell MC_A11The data “1” is stored in the memory cell MC._B11Assume that data “0” is stored in. FIG. 12 shows operation waveforms. In FIG. 12, the numbers in parentheses correspond to the numbers of the steps described below.
[0134]
(1C) In the standby state, the bit line, word line, and all plate lines are at 0 volts. Furthermore, the common node CN_A1, CN_A2, CN_B1, CN_B2Is also floating at 0 volts. When reading and rewriting data, memory unit block MB_A, MB_BMemory unit block MB other than_A', MB_BThe selection transistor is always in an off state.
[0135]
(2C) When reading data, select plate line PL₁V_ccApply. At this time, the selected memory cell MC_A11Since data “1” is stored in the ferroelectric layer, polarization inversion occurs in the ferroelectric layer, the amount of stored charge increases, and the common node CN_A1, CN_A2The potential increases. On the other hand, the selected memory cell MC_B11Since data “0” is stored in the ferroelectric layer, polarization inversion does not occur in the ferroelectric layer, and the common node CN_B1, CN_B2The potential of is hardly increased. That is, the common node CN_B1, CN_B2Through the ferroelectric layer of the non-selected memory cell, a plurality of non-selected plate lines PL_jTo the common node CN_B1, CN_B2Is maintained at a level relatively close to 0 volts. In this way, the selected memory cell MC_A11, MC_B11Depending on the data stored in the common node CN_A1, CN_A2, CN_B1, CN_B2Changes in the potential. Therefore, an electric field sufficient for polarization inversion can be applied to the ferroelectric layer of the selected memory cell.
[0136]
(3C) Next, the bit line BL_A, BL_BIs in a floating state, and the selection transistor TR_SA, TR_SBAnd reading transistor TR_R, TR_BR(This reading transistor TR_BRIs a non-volatile memory M_BIs turned on. As a result, the selected memory cell MC_A11Based on the data stored in the common first electrode (common node CN_A1, CN_A2), The detection transistor TR_DOf the selected memory cell MC_B11Based on the data stored in the common first electrode (common node CN_B1, CN_B2), The detection transistor TR_BD(This detection transistor TR_BDIs a non-volatile memory M_BThe operation of the detection transistor constituting the circuit is controlled. Specifically, the detection transistor TR_DOne source / drain region 14 has a predetermined potential V_ccWiring (potential: V_cc) And the selected memory cell MC_A11Since the data “1” is stored in the detection transistor TR_DIs turned on, and the detection transistor TR_DAnd reading transistor TR_RVia the bit line BL_ACurrent flows through the bit line BL_AThe potential increases. On the other hand, the selected memory cell MC_B11Since data “0” is stored in the detection transistor TR_BDTurns off and bit line BL_BThe potential of does not rise.
[0137]
(4C) Next, the transistor for selection TR_SA, TR_SBAnd reading transistor TR_R, TR_BRIs turned off.
[0138]
(5C) Thereafter, the sense amplifier SA connected to the bit line BL is activated to amplify the data, and the data read operation is completed.
[0139]
With the above operation, the selected memory cell MC_A11, MC_B11Since the data stored in the memory is once destroyed, the data rewrite operation is performed.
[0140]
(6C) Therefore, first, the non-selected plate line PL_jThe potential of (j ≠ 1) is set to (1/2) V_ccAnd
[0141]
(7C) Thereafter, the transistor for selection TR_SA, TR_SBAnd the writing transistor TR_W, TR_BW(This writing transistor TR_BWIs a non-volatile memory M_BIs turned on. As a result, the common node CN_A1, CN_A2, CN_B1, CN_B2Of the bit line BL_A, BL_BIs equal to the potential. That is, the selected memory cell MC_A11If the data stored in is “1”, the common node CN_A1, CN_A2The potential of V is V_ccThe selected memory cell MC_B11If the data stored in is “0”, the common node CN_B1, CN_B2The potential is 0 volts. Selection plate line PL₁The potential of V is V_ccThe common node CN_B1, CN_B2When the potential of the memory cell is 0 volts, the selected memory cell MC_B11The data “0” is rewritten to.
[0142]
(8C) Next, the selected plate line PL₁Is set to 0 volts. As a result, the selected memory cell MC_A11If the data stored in is “1”, the common node CN_A1, CN_A2Potential is V_ccTherefore, the data “1” is rewritten. Selected memory cell MC_B11If data “0” has already been rewritten in the memory cell, no change occurs in the selected memory cell.
[0143]
(9C) Thereafter, the bit line BL is set to 0 volts.
[0144]
(10C) Finally, unselected plate line PL_jIs set to 0 volts, and the transistor for selection TR_SA, TR_SBAnd the writing transistor TR_W, TR_BWIs turned off.
[0145]
Other memory cells (MC_Anm, MC_BnmThe same operation is repeated when data is read out from (1) and rewritten.
[0146]
Non-volatile memory M_A, M_BTransistor TR for configuring_SA, TR_SB, Different word lines WL_SA, WL_SBConnected to the memory cell MC_Anm, MC_BnmAre controlled independently, for example, by using a dummy cell, etc._A, BL_BA reference voltage (a reference potential intermediate between a read potential of data “1” and a read potential of data “0”) is applied to one of the memory cells MC_Anm, MC_BnmData can also be read from each of the above. Refer to FIG. 13 for a circuit diagram when such a configuration is adopted. The selection transistor TR_SA, TR_SBAre simultaneously equivalent to the circuit shown in FIG.
[0147]
Thus, each memory cell MC_Anm, MC_Bnm1 bit is stored as data in each of (n = 1, 2 and m = 1, 2,..., 8) (see FIG. 13) or a pair of memory cells MC_Anm, MC_BnmIs stored as one bit (see FIG. 10). In an actual nonvolatile memory, a set of memory units storing 16 bits or 8 bits is arranged in an array as an access unit unit. The word line WL of the selection transistor_S(WL_SA, WL_SB), Plate wire PL_{(n-1) M + m}For a plurality of access unit units sharing the data, data writing or data reading and rewriting is performed in a lump. That is, in the memory array, all the non-volatile memories are collectively turned on sequentially, or are collectively turned off (standby).
[0148]
A pair of selection transistors TR in a paired nonvolatile memory_SAAnd TR_SBIs the word line WL_SAnd paired bit lines BL_A, BL_BOccupies the area surrounded by. Accordingly, if the word lines and the bit lines are arranged at the shortest pitch, a pair of selection transistors TR in the paired nonvolatile memory is assumed._SAAnd TR_SBThe minimum area is 8F²It is. However, transistor TR_SA, TR_SB, TR_W, TR_R, TR_DM pairs of memory cells MC_A1m, MC_A2m, MC_B1m, MC_B2m(M = 1, 2,..., M), and therefore, a selection transistor TR per bit._SA, TR_SBAnd the word line WL_SSince the arrangement of the non-volatile memory is also gradual, it is easy to reduce the size of the nonvolatile memory. In addition, for the peripheral circuit, M bits can be selected by one word line decoder / driver WD and M plate line decoder / driver PD. Therefore, by adopting such a configuration, the cell area is 8F.²A layout close to that of a DRAM can be realized, and a chip size comparable to that of a DRAM can be realized.
[0149]
(Embodiment 3)
The third embodiment relates to a gain cell type nonvolatile memory according to the fifth and sixth aspects of the present invention. FIG. 14 shows a circuit diagram of the nonvolatile memory according to the third embodiment, and FIG. 15 shows a more specific circuit diagram of the memory unit in FIG. FIG. 16 is a schematic partial cross-sectional view of the nonvolatile memory according to the third embodiment parallel to the direction in which the bit line extends when the nonvolatile memory is cut. In the figure, two memory unit blocks (which constitute one nonvolatile memory) adjacent to each other in the bit line direction are illustrated, but a reference numeral of one component of the memory unit block is denoted by “′”. Since the two memory unit blocks have the same configuration, only one memory unit block will be described below. Here, FIG. 15 shows another nonvolatile memory M adjacent in the direction in which the plate line extends._BOne memory unit block MB in_BThis memory unit block MB_BIs memory unit block MB_AHas the same configuration.
[0150]
Nonvolatile Memory M of Embodiment 3_AIs
(A) a signal detection circuit;
(B) Multiple memory unit blocks MB_A, MB_A’,
Consisting of
For example, memory unit block MB_AIs
(B-1) N transistors N (where N ≧ 2, N = 2 in the third embodiment)._SANWhen,
(B-2) M memory cells MC each (where M ≧ 2 and M = 8 in the third embodiment)_ANMN memory units MU composed of_ANWhen,
(B-3) M plate lines PL_M,
Consists of.
[0151]
And memory unit block MB_AN memory units MU in_ANAre stacked via an insulating layer (interlayer insulating layer 26). Each memory cell MC_AnmIs composed of first electrodes 21, 31, ferroelectric layers 22, 32, and second electrodes 23, 33, and includes a memory unit block MB._AEach memory unit MU_AnMemory cell MC_AnmThe first electrodes 21 and 31 are common and the memory unit block MB_AN-th (where n = 1, 2,..., N) memory unit MU_AnThe common first electrode in the memory unit block MB_ANth selection transistor TR_SAnAnd connected to a signal detection circuit. Furthermore, the memory unit block MB_ANth memory unit MU_An, The mth memory cell MC (where m = 1, 2,..., M)_AnmThe second electrode of the memory unit block MB_AMemory unit MU_AnThe mth plate line PL common to all_mIt is connected to the. The signal detection circuit is connected to the memory unit block MB._AMemory unit MU_AnChange of the potential of the common first electrode in the memory cell MC_AnmBased on the data stored in the bit line BL)_AAs current or voltage. More specifically, this signal detection circuit includes a write transistor TR described below._WAnd reading transistor TR_RAnd detection transistor TR_DIt is composed of
[0152]
Alternatively, the nonvolatile memory M of the third embodiment_AIs
(A) Bit line BL_AWhen,
(B) Write transistor TR_WWhen,
(C) Reading transistor TR_RWhen,
(D) Detection transistor TR_DWhen,
(E) Multiple memory unit blocks MB_A, MB_A’,
Consisting of
For example, memory unit block MB_AIs
(E-1) N transistors N (where N ≧ 2 and M = 2 in the third embodiment)._SANWhen,
(E-2) Each of M memory cells MC (where M ≧ 2 and M = 8 in the third embodiment)_ANMN memory units MU composed of_ANWhen,
(E-3) M plate lines PL_M,
Consists of.
[0153]
And memory unit block MB_AN memory units MU in_ANAre stacked via an insulating layer (interlayer insulating layer 26). Each memory cell includes a first electrode, a ferroelectric layer, and a second electrode. Specifically, the first (hereinafter referred to as the first layer) memory unit MU_A1Each memory cell MC comprising_A1MIncludes a first electrode 21, a ferroelectric layer 22, and a second electrode 23, and a second (hereinafter referred to as a second layer) memory unit MU._A2Each memory cell MC comprising_A2MConsists of a first electrode 31, a ferroelectric layer 32 and a second electrode 33. Furthermore, each memory unit MU_AnMemory cell MC_AnmThe first electrodes 21 and 31 are common. Specifically, the memory unit MU in the first layer_A1Memory cell MC_A1MThe first electrode 21 is common. The common first electrode 21 is connected to the first common node CN._A1Sometimes called. In addition, the second layer memory unit MU_A2Memory cell MC_A2MThe first electrode 31 is common. The common first electrode 31 is connected to the second common node CN._A2Sometimes called. Furthermore, the nth memory unit MU (where n = 1, 2,..., N, which is called the nth layer)_An, The second electrodes 23 and 33 of the mth memory cell (where m = 1, 2,..., M) are connected to the memory unit MU._AnThe mth plate line PL common to all_mIt is connected to the. In the third embodiment, more specifically, each plate line extends from the second electrodes 23 and 33.
[0154]
Memory unit MU in the nth layer (where n = 1, 2,..., N)_AnThe common first electrode of the nth selection transistor TR is the nth selection transistor TR._SAnAnd the writing transistor TR_WVia the bit line BL_AIt is connected to the. Specifically, each selection transistor TR_SA1, TR_SA2One source / drain region 14 includes a connection hole 18C, a sub bit line 19, a connection hole 18B, and a writing transistor TR._WVia the bit line BL_AIt is connected to the. On the other hand, the first selection transistor TR_SA1The other source / drain region 14 is connected to the first layer memory unit MU via a connection hole 17 provided in the insulating layer 16._A1First electrode 21 (first common node CN)_A1)It is connected to the. The second selection transistor TR_SA2The other source / drain region 14 is connected to the second layer memory unit MU via a connection hole 17 provided in the insulating layer 16, a pad portion 25, and a connection hole 27 provided in the interlayer insulating layer 26._A2First electrode 31 (second common node CN)_A2)It is connected to the.
[0155]
Bit line BL_AAre connected to the sense amplifier SA. Plate wire PL_MAre connected to a plate line decoder / driver PD. Furthermore, the word line WL_S1, WL_S2Are connected to a word line decoder / driver WD. Word line WL_S1, WL_S2Extends in the direction perpendicular to the paper surface of FIG. Nonvolatile memory M_AMemory cell MC constituting_A1mThe second electrode 23 of the non-volatile memory M adjacent in the direction perpendicular to the paper surface of FIG._BMemory cell MC constituting_B1mCommon to the second electrode 23 of the plate line PL_mDoubles as Furthermore, the non-volatile memory M_AMemory cell MC constituting_A2MThe second electrode 33 of the non-volatile memory M adjacent in the direction perpendicular to the paper surface of FIG._BMemory cell MC constituting_B2mThe second electrode 33 is common to the plate line PL_mDoubles as These plate lines PL_mAre connected in a region not shown. Also, the word line WL_S1Is a non-volatile memory M_ATransistor TR for configuring_SA1And a non-volatile memory M adjacent in the direction perpendicular to the sheet of FIG._BTransistor TR for configuring_SB1And is common. Furthermore, the word line WL_S2Is a non-volatile memory M_ATransistor TR for configuring_SA2And a non-volatile memory M adjacent in the direction perpendicular to the sheet of FIG._BTransistor TR for configuring_SB2And is common.
[0156]
Detection transistor TR_DIs connected to a predetermined potential (for example, power supply V_cc), And the other end is connected to the read transistor TR._RVia the bit line BL_AIt is connected to the. Write transistor TR_WRead transistor TR_RAnd detection transistor TR_DSince the configuration, the operation thereof, and the relationship between these and the memory unit block can be substantially the same as those in the first embodiment, detailed description thereof is omitted.
[0157]
For example, the memory unit block MB_ANth memory unit MU_AnMemory cell MC_AnmWhen writing data to
(1) Writing transistor TR_W,as well as,
(2) Memory unit block MB_ANth selection transistor TR_SAn, Is turned on,
(3) Reading transistor TR_R,
(4) Memory unit block MB_ANth selection transistor TR_SAnA selection transistor other than
(5) Memory unit block MB_AMemory unit block MB other than_A′ Selection transistor TR_SAN’,
Is turned off,
Memory unit block MB_ANth memory unit MU_AnMemory cell MC_AnmWhen reading the data stored in
(1) Writing transistor TR_W,
(2) Memory unit block MB_ANth selection transistor TR_SAnA selection transistor other than
(3) Memory unit block MB_AMemory unit block MB other than_A′ Selection transistor TR_SAN’,
Is turned off,
(4) Reading transistor TR_R,as well as,
(5) Memory unit block MB_ANth selection transistor TR_SAn, Is rendered conductive, and the memory unit block MB_ANth memory unit MU_AnMemory cell MC_AnmBased on the data stored in the common first electrode (common node CN_An), The detection transistor TR_DIs controlled.
[0158]
The nonvolatile memory M whose circuit diagram is shown in FIG._A, M_BThe transistor for selection TR_SAn, TR_SBnIs the same word line WL_SnIt is connected to the. The paired memory cells MC_Anm, MC_BnmComplementary data is stored (n = 1, 2,..., N and m = 1, 2,..., M). For example, the memory cell MC_Anm, MC_BnmWhen reading data stored in (where m is any one of 1, 2,..., 8), the word line WL_SnSelect the plate line PL_j(M ≠ j) includes, for example, (1/2) V_ccWith the voltage of_mDrive. Where V_ccIs, for example, a power supply voltage. As a result, the potential corresponding to the complementary data becomes a pair of memory cells MC._Anm, MC_BnmTo common node CN_An, CN_BnAs a result, the detection transistor TR_D, Detection transistor TR_BD(This detection transistor TR_BDIs a non-volatile memory M_BThe potential corresponding to the complementary data is detected by the detection transistor TR._DRead transistor TR_RAnd detection transistor TR_BDRead transistor TR_BR(This reading transistor TR_BRIs a non-volatile memory M_BBit line BL paired via a read transistor constituting_A, BL_BAppears as a voltage (bit line potential). The paired bit lines BL_A, BL_BIs detected by the sense amplifier SA.
[0159]
Hereinafter, a method for reading and rewriting data from the nonvolatile memory according to Embodiment 3 will be described. As an example, a pair of nonvolatile memories M_A, M_BPaired memory cells MC (ie, plate lines are common)_A11, MC_{B 11}Data is read from the memory cell MC_A11The data “1” is stored in the memory cell MC._B11Assume that data “0” is stored in. FIG. 17 shows operation waveforms. In FIG. 17, the numbers in parentheses correspond to the numbers of the steps described below.
[0160]
(1D) In the standby state, the bit lines, word lines, and all plate lines are at 0 volts. Furthermore, the common node CN is also floating at 0 volts. When reading and rewriting data, memory unit block MB_A, MB_BMemory unit block MB other than_A', MB_BThe selection transistor of 'is always in an off state.
[0161]
(2D) When data reading is started, first, all plate lines PL in the selected memory unit (access unit unit)_m(M = 1, 2,..., 8) to (1/2) V_cc(However, V_ccIs precharged to the power supply voltage), and the bit line BL_A, BL_B(1/2) V_ccTo precharge. Then, word line WL_W, Word line WL_S1, WL_S2Is set to a high level, thereby writing transistor TR_W, TR_BW(This writing transistor TR_BWIs a non-volatile memory M_BAnd the transistor for selection TR_SA1, TR_SA2, TR_SB1, TR_SB2Is turned on. As a result, the common first electrode 21 (common node CN_A1, CN_A2, CN_B1, CN_B2) Is the bit line BL_A, BL_BConnected to the common node CN_A1, CN_A2, CN_B1, CN_B2Potential is (1/2) V_ccIt becomes.
[0162]
(3D) Next, a non-selected word line WL_S2Is set to a low level to select transistor TR_SA2, TR_SB2Is turned off. As a result, the non-selected common node CN_A2, CN_B2Has a potential of (1/2) V_ccIt will be in a floating state.
[0163]
(4D) Then, the selected plate line PL₁And bit line BL_A, BL_BIs discharged to 0 volts through a ground line (not shown). At this time, the bit line BL_A, BL_BCommon node CN connected to_A1, CN_B1Is also 0 volts. Bit line BL_A, BL_BWhen the discharge of the ground is completed, the ground line and the bit line BL_A, BL_BThe bit line BL_A, BL_BIs in a floating state.
[0164]
(5D) Next, the word line WL_WIs set to a low level, thereby writing transistor TR_W, TR_BWOff, and then the word line WL_RIs set to the high level to thereby read the transistor TR_R, TR_BR(This reading transistor TR_BRIs a non-volatile memory M_BIs turned on. On the other hand, the selected plate line PL₁V_ccApply. As a result, the memory cell MC storing the data “1” is stored._A11, Inversion charges are released, and as a result, the detection transistor TR_DTurns on and the wiring (potential: V_cc) To detection transistor TR_DAnd reading transistor TR_RVia the bit line BL_ACurrent flows through the bit line BL_AThe potential increases. On the other hand, the selected memory cell MC_B11Since data “0” is stored in the detection transistor TR_BD(This detection transistor TR_BDIs a non-volatile memory M_BAre in the off state, and the bit line BL_BThe potential of does not rise. In this way, the bit line BL_A, BL_BA potential difference occurs between the two. Next, the sense amplifier SA is activated and the bit line BL is activated._A, BL_BThe potential difference between is read as data.
[0165]
(6D) Next, the reading transistor TR_R, TR_BRIs turned off.
[0166]
(7D) After that, the bit line BL_A, BL_BIs charged / discharged by the sense amplifier SA, and the bit line BL_AV_ccBit line BL_BIs applied with 0 volts.
[0167]
(8D) Next, the writing transistor TR_W, TR_BWIs turned on. As a result, the memory cell MC_B11The data “0” is written again in.
[0168]
(9D) Then, the selected plate line PL₁By setting the voltage to 0 volts, the memory cell MC_A11The data “1” is written again in.
[0169]
(10D) To finish reading data, the bit line BL_A, BL_BIs discharged to 0 volts. Next, plate line PL_mAfter discharging (m = 1, 2,..., 8) to 0 volts, the unselected word line WL_S2Is again set to the high level, and the selection transistor TR_SA2, TR_SB2All the common nodes CN of the memory unit (access unit unit)_A1, CN_A2, CN_B1, CN_B2Is 0 volts.
[0170]
If the data of the next memory cell in the pair continues to be read, all the plate lines PL are again read._m(M = 1, 2,..., 8) to (1/2) V_ccThe above operations (2D) to (9D) are repeated.
[0171]
According to the above sequence, the disturbance applied to the non-selected memory cell is always (1/2) V._ccIt is suppressed to the following.
[0172]
Note that the common node CN is in a non-selected state and in a floating state._B1, CN_B2Is the selected plate line PL₁And (1/2) V_ccUnselected plate line PL fixed to_jAlthough it fluctuates according to the coupling ratio with (j = 2,..., 8), the coupling capacitance on the non-selected plate line side is larger. Therefore, the common node CN_A2, CN_B2The potential fluctuation of (1/2) V_cc~ V_ccMemory cell MC_A2m, MC_B2mThe disturbance added to (m = 1-8) is (1/2) V_ccIt is as follows.
[0173]
In such a circuit configuration, in order to limit the number of disturbances to a finite number of times, all the memory cells sharing the plate line or the common node should be collectively and continuously accessed serially. Is desirable. That is, the word line WL_S1When accessing the common node CN_A1, CN_B1Memory cells related to_A1m, MC_B1mAll of (m = 1, 2,..., 8) are sequentially accessed. Subsequently, the word line WL_S2To the common node CN_A2, CN_B2Memory cell MC related to_A2m, MC_B2mAll of (m = 1, 2,..., 8) are sequentially accessed. As a result, data is read from all of the memory cells in the memory unit (access unit unit), and then rewritten to restore degradation due to disturbance. In this way, the upper limit of the number of disturbances is the number obtained by subtracting 1 from the number of bits stored in the memory unit (access unit unit), and the reliability can be guaranteed. In the third embodiment described above, the number of disturbances is seven.
[0174]
Non-volatile memory M_A, M_BTransistor TR for configuring_SAn, TR_SBn, Different word lines WL_SAn, WL_SBnConnected to the memory cell MC_Anm, MC_BnmAre controlled independently, for example, by using a dummy cell, etc._A, BL_BA reference voltage (a reference potential intermediate between a read potential of data “1” and a read potential of data “0”) is applied to one of the memory cells MC_Anm, MC_BnmData can also be read from each of the above. Refer to FIG. 18 for a circuit diagram when such a configuration is adopted. The selection transistor TR_SAn, TR_SBnAre simultaneously equivalent to the circuit shown in FIG.
[0175]
Thus, each memory cell MC_Anm, MC_Bnm1 bit is stored as data in each of (n = 1, 2 and m = 1, 2,..., 8) (see FIG. 18), or a pair of memory cells MC_Anm, MC_BnmIs stored as one bit (see FIG. 15). In an actual nonvolatile memory, a set of memory units storing 16 bits or 8 bits is arranged in an array as an access unit unit. The word line WL of the selection transistor_Sn(WL_SAn, WL_SBn), Plate wire PL_mFor a plurality of access unit units sharing the data, data writing or data reading and rewriting is performed in a lump. That is, in the memory array, all the non-volatile memories are collectively turned on sequentially, or are collectively turned off (standby).
[0176]
(Embodiment 4)
The fourth embodiment relates to a gain cell type nonvolatile memory according to the seventh and eighth aspects of the present invention. FIG. 19 shows a circuit diagram of the nonvolatile memory according to the fourth embodiment. A more specific circuit diagram of the memory unit in FIG. 19 is shown in FIG. Further, a schematic partial cross-sectional view of the nonvolatile memory according to the fourth embodiment parallel to the extending direction of the bit line when the nonvolatile memory is cut is substantially the same as that shown in FIG. In FIG. 19, a part of two memory unit blocks (which constitute one nonvolatile memory) adjacent in the bit line direction is illustrated, but “′” is used as a reference number of one component of the memory unit block. It was attached. Since the two memory unit blocks have the same configuration, only one memory unit block will be described below. Here, FIG. 20 shows another nonvolatile memory M adjacent in the direction in which the plate line extends._BOne memory unit block MB in_BThis memory unit block MB_BIs memory unit block MB_AHas the same configuration.
[0177]
FIG. 19 shows the bit line BL._An, Writing transistor TR_WnRead transistor TR_Rn, Detection transistor TR_DnTwo selection transistors TR_SAn, TR_SAn'And two memory units MU_An, MU_AnAlthough 'is shown as one set, in practice, one non-volatile memory includes N sets.
[0178]
Nonvolatile Memory M of Embodiment 4_AIs
(A) N signal detection circuits (where N ≧ 2, N = 2 in the fourth embodiment);
(B) Multiple memory unit blocks MB_A, MB_A’,
Consisting of
For example, memory unit block MB_AIs
(B-1) N selection transistors TR_SANWhen,
(B-2) Each of M memory cells MC (where M ≧ 2 and M = 8 in the fourth embodiment)._ANMN memory units MU composed of_ANWhen,
(B-3) M plate lines PL_M,
Consists of.
[0179]
And memory unit block MB_AN memory units MU_ANAre stacked via an insulating layer (interlayer insulating layer 26). Each memory cell MC_AnmConsists of first electrodes 21, 31, ferroelectric layers 22, 32 and second electrodes 23, 33. Memory unit block MB_AEach memory unit MU_AnMemory cell MC_AnmThe first electrodes 21 and 31 are common and the memory unit block MB_AN-th (n-th layer) (where n = 1, 2,..., N) memory unit MU_AnThe common first electrode in the memory unit block MB_ANth selection transistor TR_SAnTo the nth signal detection circuit. Furthermore, the memory unit block MB_AN-th (n-th layer) memory unit MU_An, The mth memory cell MC (where m = 1, 2,..., M)_AnmThe second electrode of the memory unit block MB_AMemory unit MU_AnThe mth plate line PL common to all_mIt is connected to the. The nth signal detection circuit is connected to the memory unit block MB._AN-th layer memory unit MU_AnChange of the potential of the common first electrode in the memory cell MC_AnmBased on the data stored in the nth bit line BL)._AnAs current or voltage. Specifically, the nth signal detection circuit includes a write transistor TR described below._WnAnd reading transistor TR_RnAnd detection transistor TR_DnIt is composed of
[0180]
Alternatively, the nonvolatile memory M of the fourth embodiment_AIs
(A) N number of bit lines BL (where N ≧ 2 and N = 2 in the fourth embodiment)_ANWhen,
(B) N write transistors TR_WNWhen,
(C) N read transistors TR_RNWhen,
(D) N detection transistors TR_DNWhen,
(E) Multiple memory unit blocks MB_A, MB_A’,
Consisting of
For example, memory unit block MB_AIs
(E-1) N selection transistors TR_SANWhen,
(E-2) Each of M memory cells MC (where M ≧ 2 and M = 8 in the fourth embodiment)_ANMN memory units MU composed of_ANWhen,
(E-3) M plate lines PL_M,
Consists of.
[0181]
And memory unit block MB_AThe N memory units are stacked via an insulating layer (interlayer insulating layer 26). Each memory cell includes a first electrode, a ferroelectric layer, and a second electrode. Specifically, the first (first layer) memory unit MU_A1Each memory cell MC comprising_A1MIncludes a first electrode 21, a ferroelectric layer 22, and a second electrode 23, and a second (second layer) memory unit MU._A2Each memory cell MC comprising_A2MConsists of a first electrode 31, a ferroelectric layer 32 and a second electrode 33. Memory unit block MB_AEach memory unit MU_AnMemory cell MC_AnmThe first electrode is common. Specifically, the memory unit MU in the first layer_A1Memory cell MC_A1MThe first electrode 21 is common. The common first electrode 21 is connected to the first common node CN._A1Sometimes called. In addition, the second layer memory unit MU_A2Memory cell MC_A2MThe first electrode 31 is common. The common first electrode 31 is connected to the second common node CN._A2Sometimes called. Furthermore, the memory unit block MB_AN-th (n-th layer) (where n = 1, 2,..., N) memory unit MU_An, The second electrodes 23 and 33 of the mth memory cell (where m = 1, 2,..., M) are connected to the memory unit MU._AnThe mth plate line PL common to all_mIt is connected to the. In the fourth embodiment, more specifically, each plate line extends from the second electrodes 23 and 33. These plate lines PL_mAre connected in a region not shown.
[0182]
Memory unit block MB_AN-th memory unit MU (where n = 1, 2,..., N)_AnThe common first electrode of the nth selection transistor TR is the nth selection transistor TR._SAnAnd the nth write transistor TR_WnThrough the nth bit line BL_AnIt is connected to the. Specifically, the nth selection transistor TR_SAnOne source / drain region 14 includes a connection hole 18C, a sub-bit line 19, a connection hole 18B, and an nth write transistor TR._WnThrough the nth bit line BL_AnIt is connected to the. On the other hand, the first selection transistor TR_SA1The other source / drain region 14 is connected to the first layer memory unit MU via a connection hole 17 provided in the insulating layer 16._A1First electrode 21 (first common node CN)_A1)It is connected to the. The second selection transistor TR_SA2The other source / drain region 14 is connected to the second layer memory unit MU via a connection hole 17 provided in the insulating layer 16, a pad portion 25, and a connection hole 27 provided in the interlayer insulating layer 26._A2First electrode 31 (second common node CN)_A2)It is connected to the.
[0183]
Bit line BL_A1Sense amplifier SA₁Connected to the bit line BL_A2Sense amplifier SA₂It is connected to the. Plate wire PL_MAre connected to a plate line decoder / driver PD. Furthermore, the word line WL_SnAre connected to a word line decoder / driver WD. Nonvolatile memory M_AMemory cell MC constituting_A1mThe second electrode 23 is connected to another nonvolatile memory M adjacent in the direction in which the plate line extends._BMemory cell MC constituting_B1mCommon to the second electrode 23 of the plate line PL_mDoubles as Furthermore, the non-volatile memory M_AMemory cell MC constituting_A2MThe second electrode 33 is connected to another nonvolatile memory M adjacent in the direction in which the plate line extends._BMemory cell MC constituting_B2mThe second electrode 33 is common to the plate line PL_mDoubles as These plate lines PL_mAre connected in a region not shown. Also, the word line WL_SnIs a non-volatile memory M_ATransistor TR for configuring_SAnAnd another non-volatile memory M adjacent in the extending direction of the word line_BTransistor TR for configuring_SBnAnd is common.
[0184]
Nth detection transistor TR_DnIs connected to a predetermined potential (for example, power supply V_cc), And the other end is connected to the nth read transistor TR._RnThrough the nth bit line BL_AnIt is connected to the. Write transistor TR_WnRead transistor TR_RnAnd detection transistor TR_DnSince the configuration, the operation thereof, and the relationship between these and the memory unit block can be substantially the same as those in the first embodiment, detailed description thereof is omitted.
[0185]
For example, the memory unit block MB_AN-th (n-th layer) memory unit MU_AnMemory cell MC_AnmWhen writing data to
(1) nth write transistor TR_Wn,as well as,
(2) Memory unit block MB_ANth selection transistor TR_SAn, Is turned on,
(3) nth write transistor TR_WnWriting transistors other than
(4) Reading transistor TR_RN,
(5) Memory unit block MB_ANth selection transistor TR_SAnA selection transistor other than
(6) Memory unit block MB_AMemory unit block MB other than_A′ Selection transistor TR_SAN’,
Is turned off,
For example, memory unit block MB_AN-th (n-th layer) memory unit MU_AnMemory cell MC_AnmWhen reading the data stored in
(1) Writing transistor TR_WN,
(2) Memory unit block MB_AN-th reading transistor TR_RnA reading transistor other than
(3) Memory unit block MB_ANth selection transistor TR_SAnNon-selection transistor,
(4) Memory unit block MB_AMemory unit block MB other than_A′ Selection transistor TR_SAn’,
Is turned off,
(5) nth read transistor TR_Rn,as well as,
(6) Memory unit block MB_ANth selection transistor TR_SAn, Is rendered conductive, and the memory unit block MB_AN-th layer memory unit MU_AnMemory cell MC_AnmBased on the data stored in the common first electrode (common node CN_An), The nth detection transistor TR_DnIs controlled.
[0186]
Since the data write operation and the data read and rewrite operations in the nonvolatile memory in the fourth embodiment can be substantially the same as the operations described in the second embodiment, a detailed description will be given. Omitted.
[0187]
Non-volatile memory M whose circuit diagram is shown in FIG._A, M_BIn the selection transistor TR_SA1, TR_SB1Is the same word line WL_S1Connected to the transistor for selection TR_SA2, TR_SB2Is the same word line WL_S2It is connected to the. The paired memory cells MC_Anm, MC_BnmComplementary data is stored in (n = 1, 2, and m = 1, 2,..., M). For example, the memory cell MC_A1m, MC_B1mWhen reading data stored in (where m is any one of 1, 2,..., 8), the word line WL_S1Select the plate line PL_j(M ≠ j) includes, for example, (1/2) V_ccWith the voltage of_mDrive. As a result, the potential corresponding to the complementary data becomes a pair of memory cells MC._Anm, MC_BnmTo common node CN_An, CN_BnAs a result, the detection transistor TR_Dn, Detection transistor TR_BDn(This detection transistor TR_BDnIs a non-volatile memory M_BThe potential corresponding to the complementary data is detected by the detection transistor TR._DnRead transistor TR_RnAnd detection transistor TR_BDnRead transistor TR_BRn(This reading transistor TR_BRnIs a non-volatile memory M_BBit line BL paired via a read transistor constituting_An, BL_BnAppears as a voltage (bit line potential). The paired bit lines BL_An, BL_BnVoltage (bit line potential) of the sense amplifier SA_nDetect with.
[0188]
Non-volatile memory M_A, M_BTransistor TR for configuring_SAn, TR_SBn, Different word lines WL_SAn, WL_SBnConnected to the memory cell MC_Anm, MC_BnmAre controlled independently, for example, by using a dummy cell, etc._An, BL_BnA reference voltage (a reference potential intermediate between a read potential of data “1” and a read potential of data “0”) is applied to one of the memory cells MC_Anm, MC_BnmData can also be read from each of the above. Refer to FIG. 21 for a circuit diagram when such a configuration is adopted. The selection transistor TR_SAn, TR_SBnAre simultaneously equivalent to the circuit shown in FIG.
[0189]
Thus, each memory cell MC_Anm, MC_Bnm1 bit is stored as data in each of (n = 1, 2 and m = 1, 2,..., 8) (see FIG. 21), or a pair of memory cells MC_Anm, MC_BnmIs stored as one bit (see FIG. 20). In an actual nonvolatile memory, a set of memory units storing 16 bits or 8 bits is arranged in an array as an access unit unit. The word line WL of the selection transistor_Sn(WL_SAn, WL_SBn), Plate wire PL_mFor a plurality of access unit units sharing the data, data writing or data reading and rewriting is performed in a lump. That is, in the memory array, all the non-volatile memories are collectively turned on sequentially, or are collectively turned off (standby).
[0190]
(Embodiment 5)
Embodiment 5 relates to a gain cell type nonvolatile memory according to the ninth and tenth aspects of the present invention. A circuit diagram of the nonvolatile memory of Embodiment 5 is shown in FIG. 22, and a more specific circuit diagram of the memory unit in FIG. 22 is shown in FIG. Further, a schematic partial cross-sectional view of the nonvolatile memory according to the fifth embodiment in parallel to the extending direction of the bit line when the nonvolatile memory is cut is substantially the same as that shown in FIG. In FIG. 22, two memory unit blocks (constituting one nonvolatile memory) adjacent to each other in the bit line direction are illustrated, but “′” is attached to the reference number of one component of the memory unit block. . Since the two memory unit blocks have the same configuration, only one memory unit block will be described below. Here, FIG. 23 shows another nonvolatile memory M adjacent in the direction in which the plate line extends._BOne memory unit block MB in_BThis memory unit block MB_BHas the same configuration as the memory unit block MB.
[0191]
FIG. 22 shows the bit line BL._An, Writing transistor TR_WnRead transistor TR_Rn, Detection transistor TR_DnTwo selection transistors TR_SAn, TR_SAn'And two memory units MU_An, MU_AnAlthough 'is shown as one set, in practice, one non-volatile memory includes N sets.
[0192]
The nonvolatile memory M of the fifth embodiment is
(A) 2N signal detection circuits (where N ≧ 1, N = 1 in the fifth embodiment),
(B) A plurality of memory unit blocks MB, MB ′,
Consisting of
For example, the memory unit block MB is
(B-1) 2N selection transistors TR_SWhen,
(B-2) Each of M memory cells MC (where M ≧ 2)_NM2N memory units MU composed of_NWhen,
(B-3) M plate lines PL_M,
Consists of.
[0193]
And 2N memory units MU of the memory unit block MB_nAre stacked via an insulating layer (interlayer insulating layer 26). Each memory cell MC_nmConsists of first electrodes 21, 31, ferroelectric layers 22, 32 and second electrodes 23, 33. And each memory unit MU of the memory unit block MB_nMemory cell MC_nmThe first electrodes 21 and 31 are common, and the memory unit MU of the nth layer (where n = 1, 2,..., 2N) of the memory unit block MB._nThe common first electrodes 21 and 31 in the n are the nth selection transistors TR of the memory unit block MB._SnThrough the nth bit line BL_nIt is connected to the. Furthermore, the memory unit MU of the nth layer of the memory unit block MB_n, The mth memory cell MC (where m = 1, 2,..., M)_nmThe second electrodes 23 and 33 are connected to the memory unit MU of the memory unit block MB._nThe mth plate line PL common to all_mIt is connected to the. Then, the memory unit MU of the (2n′−1) th layer and the second n′th layer (where n ′ = 1, 2,..., N) of the memory unit block MB._(2n'-1), MU_{2n '}Memory cells MC having a common plate line_{(2n'-1), m}, MC_{2n ', m}Data is written to and read from the data. The (2n′−1) th and 2n′th signal detection circuits are connected to the (2n′−1) th and second n′th layer memory units MU of the memory unit block MB._(2n'-1), MU_{2n '}Change of the potential of the common first electrode in the memory cell MC_{(2n'-1), m}, MC_{2n ', m}And (2n′−1) th and 2n′th bit lines BL are detected based on the detection results._(2n'-1), BL_{2n '}As current or voltage. Specifically, each signal detection circuit includes a write transistor TR described below._WnAnd reading transistor TR_RnAnd detection transistor TR_DnIt is composed of
[0194]
Alternatively, the nonvolatile memory M of the fifth embodiment is
(A) 2N bit lines BL (where N ≧ 1, N = 1 in the fifth embodiment)_NWhen,
(B) 2N write transistors TR_WNWhen,
(C) 2N read transistors TR_RNWhen,
(D) 2N detection transistors TR_DNWhen,
(E) a plurality of memory unit blocks MB, MB ′,
Consisting of
For example, the memory unit block MB is
(E-1) 2N selection transistors TR_SNWhen,
(E-2) Each of M memory cells MC (where M ≧ 2 and M = 8 in the fifth embodiment)_NM2N memory units MU composed of_NWhen,
(E-3) M plate lines PL_M,
Consists of.
[0195]
The N memory units of the memory unit block MB are stacked via an insulating layer (interlayer insulating layer 26). Each memory cell includes a first electrode, a ferroelectric layer, and a second electrode. Specifically, the memory unit MU in the first layer₁Each memory cell MC comprising_1MIncludes a first electrode 21, a ferroelectric layer 22, and a second electrode 23, and the second layer memory unit MU.₂Each memory cell MC comprising_2MConsists of a first electrode 31, a ferroelectric layer 32 and a second electrode 33. Each memory unit MU of the memory unit block MB_nMemory cell MC_nmThe first electrode is common. Specifically, the memory unit MU in the first layer₁Memory cell MC_1MThe first electrode 21 is common. The common first electrode 21 is connected to the first common node CN.₁Sometimes called. In addition, the second layer memory unit MU₂Memory cell MC_2MThe first electrode 31 is common. The common first electrode 31 is connected to the second common node CN.₂Sometimes called. Further, the memory unit MU in the nth layer (where n = 1, 2,..., N) of the memory unit block MB._n, The second electrodes 23 and 33 of the mth memory cell (where m = 1, 2,..., M) are connected to the memory unit MU._nThe mth plate line PL common to all_mIt is connected to the. In the fifth embodiment, more specifically, each plate line extends from the second electrodes 23 and 33. These plate lines PL_mAre connected in a region not shown.
[0196]
Memory unit MU in the nth layer (where n = 1, 2,..., N) of the memory unit block MB_nThe common first electrode of the nth selection transistor TR is the nth selection transistor TR._SnAnd the nth write transistor TR_WnThrough the nth bit line BL_nIt is connected to the. Specifically, the nth selection transistor TR_SnOne source / drain region 14 includes a connection hole 18C, a sub-bit line 19, a connection hole 18B, and an nth write transistor TR._WnThrough the nth bit line BL_nIt is connected to the. On the other hand, the first selection transistor TR_S1The other source / drain region 14 is connected to the first layer memory unit MU via a connection hole 17 provided in the insulating layer 16.₁First electrode 21 (first common node CN)₁)It is connected to the. The second selection transistor TR_S2The other source / drain region 14 is connected to the second layer memory unit MU via a connection hole 17 provided in the insulating layer 16, a pad portion 25, and a connection hole 27 provided in the interlayer insulating layer 26.₂First electrode 31 (second common node CN)₂)It is connected to the.
[0197]
Bit line BL₁, BL₂Sense amplifier SA₁It is connected to the. Plate wire PL_MAre connected to a plate line decoder / driver PD. Furthermore, the word line WL_SnAre connected to a word line decoder / driver WD. Further, the memory cell MC constituting the nonvolatile memory M_1mThe second electrode 23 is connected to another nonvolatile memory M adjacent in the direction in which the plate line extends._BMemory cell MC constituting_B1mCommon to the second electrode 23 of the plate line PL_mDoubles as Further, the memory cell MC constituting the nonvolatile memory M_2MThe second electrode 33 is connected to another nonvolatile memory M adjacent in the direction in which the plate line extends._BMemory cell MC constituting_B2mThe second electrode 33 is common to the plate line PL_mDoubles as These plate lines PL_mAre connected in a region not shown. Also, the word line WL_SnIs a transistor for selection TR constituting the nonvolatile memory M_SnAnd another non-volatile memory M adjacent in the extending direction of the word line_BTransistor TR for configuring_SBnAnd is common.
[0198]
Nth detection transistor TR_DnIs connected to a predetermined potential (for example, power supply V_cc), And the other end is connected to the nth read transistor TR._RnThrough the nth bit line BL_nIt is connected to the. Write transistor TR_WnRead transistor TR_RnAnd detection transistor TR_DnSince the configuration, the operation thereof, and the relationship between these and the memory unit block can be substantially the same as those in the first embodiment, detailed description thereof is omitted.
[0199]
Then, for example, the memory unit MU of the (2n′−1) th layer and the second n′th layer (where n ′ = 1, 2,..., N) of the memory unit block MB._(2n'-1), MU_{2n '}Plate line at_MTwo memory cells MC_{(2n'-1), m}, MC_{2n ', m}When writing data to
(1) The (2n'-1) th and 2n'th write transistors TR_{W, (2n'-1)}, TR_{W, 2n '},as well as,
(2) The (2n'-1) th and 2n'th selection transistors TR of the memory unit block MB_{S, (2n'-1)}, TR_{S, 2n '},
Is turned on,
(3) (2n'-1) th and 2n'th write transistors TR_{W, (2n'-1)}, TR_{W, 2n '}Writing transistors other than
(4) Reading transistor TR_Rn,
(5) The (2n'-1) th and 2n'th selection transistors TR of the memory unit block MB_{S, (2n'-1)}, TR_{S, 2n '}A selection transistor other than
(6) Selection transistor TR of memory unit block MB 'other than memory unit block MB_SN’,
Is turned off,
Memory units MU in the (2n′−1) th layer and the second n′th layer of the memory unit block MB_(2n'-1), MU_{2n '}Plate line at_mTwo memory cells MC_{(2n'-1), m}, MC_{2n ', m}When reading the data stored in
(1) Writing transistor TR_WN,
(2) (2n'-1) th and 2n'th read transistors TR of the memory unit block MB_{R, (2n'-1)}, TR_{R, 2n '}A reading transistor other than
(3) (2n'-1) th and 2n'th selection transistors TR of the memory unit block MB_{S, (2n'-1)}, TR_{S, 2n '}A selection transistor other than
(4) Transistor TR for selection of memory unit block MB 'other than memory unit block MB_SN’,
Is turned off,
(5) The (2n′−1) th and 2n′th read transistors TR_{R, (2n'-1)}, TR_{R, 2n '},as well as,
(6) The (2n'-1) th and 2n'th selection transistors TR of the memory unit block MB_{S, (2n'-1)}, TR_{S, 2n '},
Is made conductive, and the memory unit MU in the (2n′−1) th layer and the second n′th layer of the memory unit block MB._(2n'-1), MU_{2n '}Plate line at_mTwo memory cells MC_{(2n'-1), m}, MC_{2n ', m}Based on the data stored in the common first electrode (common node CN_(2n'-1), CN_{2n '}), The (2n′−1) th and second n′th detection transistors TR_{D, (2n'-1)}, TR_{D, 2n '}Is controlled.
[0200]
Since the data write operation and the data read and rewrite operations in the nonvolatile memory M in the fifth embodiment can be substantially the same as the operations described in the second embodiment, a detailed description will be given. Is omitted.
[0201]
In the nonvolatile memory M whose circuit diagram is shown in FIG. 23, the selection transistor TR constituting the nonvolatile memory M_S1, TR_S1Are different word lines WL_S1, WL_S2It is connected to the. The paired memory cells MC_1m, MC_2mComplementary data is stored. For example, the memory cell MC_1m, MC_2mWhen reading data stored in (where m is any one of 1, 2,..., 8), the word line WL_S1And word line WL_S2Select the plate line PL_j(M ≠ j) includes, for example, (1/2) V_ccWith the voltage of_mDrive. As a result, the potential corresponding to the complementary data becomes a pair of memory cells MC._1m, MC_2mTo common node CN₁, CN₂As a result, the detection transistor TR_D1, Detection transistor TR_D2The potential corresponding to the complementary data is detected by the detection transistor TR._D1Read transistor TR_R1And detection transistor TR_D2Read transistor TR_R2Bit line BL paired via₁, BL₂Appears as a voltage (bit line potential). The paired bit lines BL₁, BL₂Voltage (bit line potential) of the sense amplifier SA₁Detect with.
[0202]
Thus, the paired memory cells MC_{(2n'-1), m}, MC_{2n ', m}Complementary data is stored as 1 bit. In an actual nonvolatile memory, a set of memory units for storing these 8 bits is arranged in an array as an access unit unit. The word line WL of the selection transistor_S1, WL_S2, Plate wire PL_mFor a plurality of access unit units sharing the data, data writing or data reading and rewriting is performed in a lump. That is, in the memory array, all the non-volatile memories are collectively turned on sequentially, or are collectively turned off (standby).
[0203]
Memory cell MC_1m, MC_2mAre controlled independently to form a pair of bit lines BL₁, BL₂By applying a reference voltage to one of the memory cells MC_1m, MC_2mData can also be read from each of the above. Such a configuration is substantially the same as the operation of the nonvolatile memory described in the fourth embodiment.
[0204]
As mentioned above, although this invention was demonstrated based on embodiment of this invention, this invention is not limited to these. The structure of the nonvolatile memory, the materials used, various formation conditions, the circuit configuration, the driving method, and the like described in the embodiment of the invention are examples, and can be changed as appropriate.
[0205]
The predetermined potential of the wiring to which one end of the detection transistor is connected is V_ccFor example, it may be grounded. That is, the predetermined potential of the wiring to which one end of the detection transistor is connected may be 0 volts. However, in this case, the potential (V_cc) Appears on the bit line, the potential of the bit line is set to 0 volt at the time of rewriting, and when 0 volt appears on the bit line at the time of reading data in the selected memory cell, the potential of the bit line is set to V at the time of rewriting._ccIt is necessary to. For this purpose, a transistor TR as illustrated in FIG._IV-1, TR_IV-2, TR_IV-3, TR_IV-4A kind of switch circuit (inversion circuit) composed of the above is arranged between the bit lines, and when reading data, the transistor TR_IV-2, TR_IV-4Is turned on, and the transistor TR_IV-1, TR_IV-3Can be turned on.
[0206]
The value of M is not limited to 8. The value of M only needs to satisfy M ≧ 2. As an actual value of M, for example, a power of 2 (2, 4, 8, 16...) Can be mentioned. In the first to fourth embodiments, the value of N only needs to satisfy N ≧ 2, and as a practical value of N, for example, a power of 2 (2, 4, 8,... ). Furthermore, in the fifth embodiment, the value of N only needs to satisfy N ≧ 1, and as a practical value of N, for example, a power of 1 or 2 (2, 4, 8,...) Is used. Can be mentioned. The number of memory unit blocks is not limited to two.
[0207]
In general, A = B + C, where A is the total number of signal lines for driving the unit units, B is the number of word lines, and C is the number of plate lines. Here, when the total number A is constant, in order to maximize the total number of addresses (= B × C) of the unit unit, it is sufficient to satisfy B = C. Therefore, in order to arrange peripheral circuits most efficiently, the number B of word lines and the number C of plate lines in the unit unit may be made equal. In addition, the number of word lines in the row address access unit unit is equal to, for example, the number of stacked memory cells (N), and the number of plate lines is equal to the number of memory cells (M) constituting the memory unit. As the number of these word lines and plate lines increases, the degree of integration of the substantial nonvolatile memory increases. The product of the number of word lines and the number of plate lines is the number of accessible addresses. Here, on the premise of continuous and continuous access, the value obtained by subtracting “1” from the product is the number of disturbances. Therefore, the value of the product of the number of word lines and the number of plate lines is determined from the disturbance tolerance of the memory cells, process factors, and the like. Here, the disturbance is a phenomenon in which an electric field is applied to the ferroelectric layer constituting a non-selected memory cell in a direction in which polarization is reversed, that is, in a direction in which stored data is deteriorated or destroyed. Point to.
[0208]
The nonvolatile memory described in Embodiment 3 can be modified as in the structure shown in FIG. A circuit diagram is shown in FIG. 25 and 26, the writing transistor, the reading transistor, and the detection transistor are not shown.
[0209]
This nonvolatile memory includes a bit line BL connected to the sense amplifier SA._AN transistors (where N ≧ 2, N = 4 in this example) made up of MOS FETs are selected._S1, TR_S2, TR_S3, TR_S4And N memory units MU_A1, MU_A2, MU_A3, MU_A4And a plate wire. First layer memory unit MU_A1Is M memory cells (where M ≧ 2 and M = 8 in this example)._A1m(M = 1, 2,..., 8). In addition, the second layer memory unit MU_A2M memory cells MC (M = 8)_A2m(M = 1, 2,..., 8). Furthermore, the third layer memory unit MU_A3M memory cells MC (M = 8)_A3m(M = 1, 2,..., 8) and the fourth layer memory unit MU_A4M memory cells MC (M = 8)_A4m(M = 1, 2,..., 8). The number of plate lines is M (8 in this example), and PL_m(M = 1, 2,..., 8). Selection transistor TR_SnWord line WL connected to the gate electrode of_SnAre connected to a word line decoder / driver WD. On the other hand, each plate line PL_mAre connected to a plate line decoder / driver PD.
[0210]
Also, the memory unit MU in the first layer_A1Each memory cell MC comprising_A1mIs composed of a first electrode 21A, a ferroelectric layer 22A, and a second electrode 23, and the second layer memory unit MU._A2Each memory cell MC comprising_A2mConsists of a first electrode 21B, a ferroelectric layer 22B, and a second electrode 23, and a third-layer memory unit MU._A3Each memory cell MC comprising_A3mIs composed of a first electrode 31A, a ferroelectric layer 32A, and a second electrode 33, and a fourth layer memory unit MU._A4Each memory cell MC comprising_A4mConsists of a first electrode 31B, a ferroelectric layer 32B, and a second electrode 33. And each memory unit MU_A1, MU_A2, MU_A3, MU_A4, The first electrodes 21A, 21B, 31A, 31B of the memory cells are common. For the sake of convenience, the common first electrodes 21A, 21B, 31A, 31B are connected to the common node CN._A1, CN_A2, CN_A3, CN_A4Call it.
[0211]
Here, the memory unit MU of the first layer_A1First electrode 21A (first common node CN)_A1) Is the first selection transistor TR_S1And, for example, a writing transistor TR_WVia the bit line BL_AIt is connected to the. In addition, the second layer memory unit MU_A2First electrode 21B (second common node CN)_A2) Is the second selection transistor TR_S2And, for example, a writing transistor TR_WVia the bit line BL_AIt is connected to the. Furthermore, the third layer memory unit MU_A3First electrode 31A (third common node CN)_A3) Is the third selection transistor TR_S3And, for example, a writing transistor TR_WVia the bit line BL_AIt is connected to the. Also, the fourth layer memory unit MU_A4Common electrode 31B (fourth common node CN)_A4) Is the fourth selection transistor TR_S4And, for example, a writing transistor TR_WVia the bit line BL_AIt is connected to the.
[0212]
Also, the memory unit MU in the first layer_A1Memory cell MC constituting_A1mAnd the second layer memory unit MU_A2Memory cell MC constituting_A2mShare the second electrode 23, and the shared m-th second electrode 23 is the plate line PL._mIt is connected to the. Furthermore, the third layer memory unit MU_A3Memory cell MC constituting_A3mAnd the fourth layer memory unit MU_A4Memory cell MC constituting_A4mShare the second electrode 33, and the shared m-th second electrode 33 is the plate line PL._mIt is connected to the. Specifically, the plate line PL extends from the extended portion of the m-th second electrode 23 shared._mAnd the plate line PL extends from the extended portion of the shared m th second electrode 33._mEach plate line PL_mAre connected in a region not shown.
[0213]
In this nonvolatile memory, the memory unit MU_A1, MU_A2And memory unit MU_A3, MU_A4Are stacked via an insulating layer (interlayer insulating layer 26). Memory unit MU_A4Is covered with an insulating film 36A. In addition, the memory unit MU_A1Is formed above the semiconductor substrate 10 via an insulating layer 16. An element isolation region 11 is formed in the semiconductor substrate 10. The selection transistor TR_S1, TR_S2, TR_S3, TR_S4Consists of a gate insulating film 12, a gate electrode 13, and source / drain regions 14. The first selection transistor TR_S1, Second selection transistor TR_S2, Third selection transistor TR_S3, Fourth selection transistor TR_S4One source / drain region 14 has a connection hole, a sub bit line, for example, a write transistor TR._WnVia the bit line BL_AIt is connected to the. The first selection transistor TR_S1The other source / drain region 14 is connected to the first common node CN via a connection hole 17 provided in an opening formed in the insulating layer 16._A1It is connected to the. Further, the second selection transistor TR_S2The other source / drain region 14 is connected to the second common node CN via the connection hole 17._A2It is connected to the. The third selection transistor TR_S3The other source / drain region 14 of the third common node CN is connected to the third common node CN via a connection hole 27 provided in an opening formed in the connection hole 17, the pad portion 25, and the interlayer insulating layer 26._A3It is connected to the. Furthermore, the fourth selection transistor TR_S4The other source / drain region 14 is connected to the fourth common node CN via the connection hole 17, the pad portion 25, and the connection hole 27._A4It is connected to the.
[0214]
The structure of the non-volatile memory described above can be applied as appropriate to the non-volatile memory in other embodiments.
[0215]
For example, as shown in FIG. 27, as a modification of the nonvolatile memory according to the third embodiment, the first electrodes 21 ′ and 31 ′ are upper electrodes and the second electrodes 23 ′ and 33 ′ are lower electrodes. It can also be. Such a structure can be applied as appropriate to the non-volatile memory in other embodiments. In FIG. 27, the writing transistor, the reading transistor, and the detecting transistor are not shown.
[0216]
【The invention's effect】
In the ferroelectric nonvolatile semiconductor memory of the present invention, since a plurality of memory cells are provided, the cell area per bit can be reduced, and further, a plurality of memory unit blocks are provided. Therefore, the cell area per bit can be further reduced. In addition, since the first electrode is common to the first electrodes of the plurality of memory cells constituting the memory unit, a kind of additional load capacitance is added to the first electrode, When a voltage is applied to the plate line during reading, an increase in potential of the first electrode in a floating state can be suppressed, and a sufficient potential difference is generated between the first electrode and the second electrode. Therefore, it is possible to reliably generate polarization inversion in the ferroelectric layer. In addition, a writing transistor, a reading transistor, and a detecting transistor are provided, but the area overhead of these transistors is very small. In addition, even if the scaling is improved and the memory cell is reduced, it is possible to ensure almost the same amount of sense signal.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a ferroelectric nonvolatile semiconductor memory according to a first embodiment of the invention.
FIG. 2 is a more specific circuit diagram of a memory unit portion in the ferroelectric nonvolatile semiconductor memory according to the first embodiment of the present invention.
FIG. 3 is a diagram showing a schematic layout of various transistors constituting the ferroelectric nonvolatile semiconductor memory according to the first embodiment of the invention.
4 is a schematic partial cross-sectional view in parallel with the extending direction of the bit line when the ferroelectric nonvolatile semiconductor memory according to the first embodiment of the invention is cut along the arrow AA in FIG. 3; FIG. is there.
5 is a schematic partial cross-sectional view in parallel with the extending direction of the bit line when the ferroelectric nonvolatile semiconductor memory according to the first embodiment of the present invention is cut along the arrow BB in FIG. 3; is there.
6 is a diagram showing operation waveforms in a data write operation of the ferroelectric nonvolatile semiconductor memory according to the first embodiment of the present invention; FIG.
7 is a diagram showing operation waveforms in data read and rewrite operations of the ferroelectric nonvolatile semiconductor memory according to the first embodiment of the present invention; FIG.
FIG. 8 is a graph showing the result of simulating the relationship between the value of the number (M) of memory cells constituting the memory unit and the signal potential in the first embodiment of the invention.
FIG. 9 is a circuit diagram of a ferroelectric nonvolatile semiconductor memory according to a second embodiment of the invention.
FIG. 10 is a more specific circuit diagram of a memory unit portion in the ferroelectric nonvolatile semiconductor memory according to the second embodiment of the present invention.
FIG. 11 is a schematic partial cross-sectional view in parallel with the direction in which a bit line extends in the ferroelectric nonvolatile semiconductor memory according to the second embodiment of the present invention;
12 is a diagram showing operation waveforms in data read and rewrite operations of the ferroelectric nonvolatile semiconductor memory according to the second embodiment of the present invention; FIG.
FIG. 13 is a more specific circuit diagram of a memory unit portion in a modification of the ferroelectric nonvolatile semiconductor memory according to the second embodiment of the present invention.
FIG. 14 is a circuit diagram of a ferroelectric nonvolatile semiconductor memory according to a third embodiment of the invention.
FIG. 15 is a more specific circuit diagram of a memory unit portion in the ferroelectric nonvolatile semiconductor memory according to the third embodiment of the present invention.
FIG. 16 is a schematic partial cross-sectional view in parallel with the direction in which a bit line extends in a ferroelectric nonvolatile semiconductor memory according to a third embodiment of the present invention;
FIG. 17 is a diagram showing operation waveforms in a data read and rewrite operation of the ferroelectric nonvolatile semiconductor memory according to the third embodiment of the present invention;
FIG. 18 is a more specific circuit diagram of a memory unit portion in a modification of the ferroelectric nonvolatile semiconductor memory according to the third embodiment of the present invention.
FIG. 19 is a circuit diagram of a ferroelectric nonvolatile semiconductor memory according to a fourth embodiment of the invention.
FIG. 20 is a more specific circuit diagram of the memory unit portion in the ferroelectric nonvolatile semiconductor memory according to the fourth embodiment of the present invention.
FIG. 21 is a more specific circuit diagram of a memory unit portion in a modification of the ferroelectric nonvolatile semiconductor memory according to the fourth embodiment of the present invention.
FIG. 22 is a circuit diagram of a ferroelectric nonvolatile semiconductor memory according to a fifth embodiment of the present invention.
FIG. 23 is a more specific circuit diagram of the memory unit portion in the ferroelectric nonvolatile semiconductor memory according to the fifth embodiment of the present invention.
FIG. 24 is a circuit diagram showing a kind of switch circuit arranged between bit lines when a predetermined potential of a wiring to which one end of a detection transistor is connected is 0 volt.
FIG. 25 is a schematic partial cross-sectional view showing a modification of the ferroelectric nonvolatile semiconductor memory described in the third embodiment of the present invention.
26 is a circuit diagram of the ferroelectric nonvolatile semiconductor memory shown in FIG. 25. FIG.
FIG. 27 is a schematic partial cross-sectional view of another modified example of the ferroelectric nonvolatile semiconductor memory according to the third embodiment of the present invention.
FIG. 28 is a PE hysteresis loop diagram of a ferroelectric.
FIG. 29 is a circuit diagram of a ferroelectric nonvolatile semiconductor memory disclosed in US Pat. No. 4,873,664.
FIG. 30 is a circuit diagram of a ferroelectric nonvolatile semiconductor memory disclosed in Japanese Patent Laid-Open No. 9-121032.
FIG. 31 is an equivalent circuit diagram of a gain cell in a DRAM, and an equivalent circuit diagram when this gain cell is applied to a nonvolatile memory disclosed in conventional US Pat. No. 4,873,664.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Silicon semiconductor substrate, 11 ... Element isolation region, 12 ... Gate insulating film, 13 ... Gate electrode, 14 ... Source / drain region, 15, 17, 18A, 18B, 18C, 27 ... connection hole (contact hole), 16 ... insulating layer, 21, 21A, 21B, 21 ', 31, 31A, 31B, 31' ... first electrode, 22, 22A, 22B, 32 32A, 32B ... ferroelectric layer, 23, 23 ', 33, 33' ... second electrode, 25 ... pad portion, 26 ... insulating layer (interlayer insulating layer), 26A, 36A ... Insulating film, M ... Ferroelectric nonvolatile semiconductor memory, MB ... Memory unit block, MC ... Memory cell, TR_S... Selection transistors, TR_W... Write transistors, TR_R... Reading transistors, TR_D... Detection transistor, WL ... Word line, BL ... Bit line, PL ... Plate line, WD ... Word line decoder / driver, SA ... Sense amplifier, PD ... Plate Line decoder / driver, CN ... Common node

Claims (4)

(A) a signal detection circuit;
(B) a plurality of memory unit blocks;
Consisting of
Each memory unit block
(B-1) a selection transistor;
(B-2) N (where N ≧ 2) memory units each composed of M (where M ≧ 2) memory cells;
(B-3) M × N plate wires,
Consisting of
N memory units of each memory unit block are stacked via an insulating layer,
Each memory cell includes a first electrode, a ferroelectric layer, and a second electrode,
In each memory unit of each memory unit block, the first electrode of the memory cell is common, and the common first electrode is connected to the signal detection circuit via the selection transistor of the memory unit block. And
In the memory unit in the nth layer (where n = 1, 2,..., N) of each memory unit block, the mth (where m = 1, 2,..., M) memory cells The second electrode is a ferroelectric nonvolatile semiconductor memory connected to the [(n−1) M + m] th plate line of the memory unit block,
The signal detection circuit detects a potential change of a common first electrode in a memory unit of each memory unit block, and transmits the detection result as a current or a voltage to a bit line. Semiconductor memory. (A) a bit line;
(B) a writing transistor;
(C) a reading transistor;
(D) a detection transistor;
(E) a plurality of memory unit blocks;
Consisting of
Each memory unit block
(E-1) a selection transistor;
(E-2) N (where N ≧ 2) memory units each composed of M (where M ≧ 2) memory cells;
(E-3) M × N plate wires,
Consisting of
N memory units of each memory unit block are stacked via an insulating layer,
Each memory cell includes a first electrode, a ferroelectric layer, and a second electrode,
In each memory unit of each memory unit block, the first electrode of the memory cell is common, and the common first electrode is connected via the selection transistor and the write transistor of the memory unit block. Connected to the bit line,
In the memory unit in the nth layer (where n = 1, 2,..., N) of each memory unit block, the mth (where m = 1, 2,..., M) memory cells The second electrode is connected to the [(n−1) M + m] th plate line of the memory unit block,
One end of the detection transistor is connected to a wiring having a predetermined potential, and the other end is connected to the bit line via the reading transistor,
When writing data to memory cells in the memory unit block,
(1) a writing transistor, and
(2) a transistor for selecting the memory unit block;
Is turned on,
(3) a reading transistor, and
(4) a transistor for selecting a memory unit block other than the memory unit block;
Is turned off,
When reading the data stored in the memory cells of the memory unit block,
(1) a writing transistor, and
(2) a transistor for selecting a memory unit block other than the memory unit block;
Is turned off,
(3) a reading transistor, and
(4) a transistor for selecting the memory unit block;
Is made conductive, and the operation of the detection transistor is controlled by the potential generated at the common first electrode based on the data stored in the memory cell of the memory unit block. Non-volatile semiconductor memory. (A) a signal detection circuit;
(B) a plurality of memory unit blocks;
Consisting of
Each memory unit block
(B-1) N selection transistors (where N ≧ 2),
(B-2) N memory units each composed of M (where M ≧ 2) memory cells;
(B-3) M plate wires,
Consisting of
Each memory cell includes a first electrode, a ferroelectric layer, and a second electrode,
In each memory unit of each memory unit block, the first electrode of the memory cell is common,
The common first electrode in the nth (where n = 1, 2,..., N) memory unit of each memory unit block is connected via the nth selection transistor of the memory unit block. Connected to the signal detection circuit,
In the nth memory unit of each memory unit block, the second electrode of the mth memory cell (where m = 1, 2,..., M) is common among the memory units of the memory unit block. A ferroelectric nonvolatile semiconductor memory connected to the m-th plate line,
The signal detection circuit detects a potential change of the common first electrode in the nth memory unit of each memory unit block, and transmits the detection result to the bit line as a current or a voltage. Dielectric type nonvolatile semiconductor memory. (A) a bit line;
(B) a writing transistor;
(C) a reading transistor;
(D) a detection transistor;
(E) a plurality of memory unit blocks;
Consisting of
Each memory unit block
(E-1) N selection transistors (where N ≧ 2),
(E-2) N memory units each composed of M (where M ≧ 2) memory cells;
(E-3) M plate wires,
Consisting of
Each memory cell includes a first electrode, a ferroelectric layer, and a second electrode,
In each memory unit of each memory unit block, the first electrode of the memory cell is common,
The common first electrode in the nth (where n = 1, 2,..., N) memory unit of each memory unit block is the nth selection transistor in the memory unit block and the write It is connected to the bit line through the embedded transistor,
In the nth memory unit of each memory unit block, the second electrode of the mth memory cell (where m = 1, 2,..., M) is common among the memory units of the memory unit block. Connected to the m-th plate wire,
One end of the detection transistor is connected to a wiring having a predetermined potential, and the other end is connected to the bit line via the reading transistor,
When writing data to the memory cell of the nth memory unit in the memory unit block,
(1) a writing transistor, and
(2) the nth selection transistor of the memory unit block;
Is turned on,
(3) a reading transistor;
(4) a selection transistor other than the nth selection transistor in the memory unit block; and
(5) a transistor for selecting a memory unit block other than the memory unit block;
Is turned off,
When reading the data stored in the memory cell of the nth memory unit of the memory unit block,
(1) Write transistor,
(2) a selection transistor other than the nth selection transistor of the memory unit block; and
(3) a transistor for selecting a memory unit block other than the memory unit block;
Is turned off,
(4) a reading transistor, and
(5) the nth selection transistor of the memory unit block;
Is made conductive, and the operation of the detection transistor is controlled by the potential generated at the common first electrode based on the data stored in the memory cell of the nth memory unit of the memory unit block. A ferroelectric-type nonvolatile semiconductor memory characterized by the above.

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