JP2003123467A - Ferroelectric type nonvolatile semiconductor memory array and driving method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a ferroelectric type nonvolatile semiconductor memory array permitting its application to random access use. SOLUTION: The ferroelectric type nonvolatile semiconductor memory array consists of a plurality of ferroelectric type nonvolatile semiconductor memory Mk , and a flag circuit consisting of at least one flag storing semiconductor memory F, and the memory comprises a bit line BLk , a memory unit MUk selection transistor TRk , M pieces (M>=2) of memory cells, and M pieces of plate lines, and when data reading and data rewriting from/to any memory cell sharing a certain plate line among the memory cells are performed predetermined times, the memory cells of the flag storing semiconductor memory F are initialized, and the memory cells forming each ferroelectric type nonvolatile semiconductor memory are refreshed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric non-volatile semiconductor memory array including a plurality of ferroelectric non-volatile semiconductor memories (so-called FERAM) and a driving method thereof.

[0002]

2. Description of the Related Art In recent years, much research has been conducted on large-capacity ferroelectric non-volatile semiconductor memories. A ferroelectric non-volatile semiconductor memory (hereinafter, may be abbreviated as a non-volatile memory) can be accessed at high speed and
It is non-volatile, small in size, low in power consumption, and resistant to shocks. It is expected to be used as a storage device or a recording medium for recording audio and video.

This non-volatile memory utilizes a high-speed polarization reversal of a ferroelectric thin film and its residual polarization to detect a change in the amount of accumulated charge in a capacitor section having a ferroelectric layer.
It is a high-speed rewritable non-volatile memory, and basically includes a memory cell (capacitor portion) and a selection transistor. Memory cell (capacitor section)
Is composed of, for example, a lower electrode, an upper electrode, and a ferroelectric layer sandwiched between these electrodes. Writing and reading of data in this non-volatile memory is performed by using FIG.
This is performed by applying the PE hysteresis loop of the ferroelectric substance shown in FIG. That is, when the external electric field is removed after applying the external electric field to the ferroelectric layer, the ferroelectric layer exhibits spontaneous polarization. The remanent polarization of the ferroelectric layer becomes + P _r when an external electric field in the positive direction is applied, and −P _r when an external electric field in the negative direction is applied. Here, the case where the remanent polarization is + P _r (see “D” in FIG. 52) is “0”, and the case where the remanent polarization is −P _r (see “A” in FIG. 52) is “1”. And

In order to determine the state of "1" or "0", an external electric field in the positive direction, for example, is applied to the ferroelectric layer. As a result, the polarization of the ferroelectric layer becomes the state of "C" in FIG. At this time, if the data is "0", the polarization state of the ferroelectric layer changes from "D" to "C". On the other hand, if the data is “1”, the polarization state of the ferroelectric layer changes from “A” to “C” via “B”. When the data is "0", polarization inversion of the ferroelectric layer does not occur. On the other hand, when the data is "1", polarization inversion occurs in the ferroelectric layer. As a result, a difference occurs in the amount of charge stored in the memory cell (capacitor section). By turning on the selection transistor of the selected nonvolatile memory, this accumulated charge is detected as a signal current.
When the external electric field is set to 0 after reading the data, the polarization state of the ferroelectric layer becomes the state of “D” in FIG. 52 regardless of whether the data is “0” or “1”. That is, at the time of reading, the data “1” is once destroyed. Therefore, when the data is "1", an external electric field in the negative direction is applied to bring the state of "A" through the paths "D" and "E", and the data "1" is written again.

The structure and operation of a non-volatile memory, which is currently the mainstream, is described in US Pat. No. 4,873,664. It was proposed by Sheffiled et al.
This non-volatile memory has a circuit diagram shown in FIG.
It is composed of two non-volatile memory cells. In addition, in FIG. 53, one nonvolatile memory is surrounded by a dotted line.
Each nonvolatile memory has, for example, a selection transistor TR.
₁₁ , TR ₁₂ , memory cell (capacitor part) FC ₁₁ , FC
_It consists of ₁₂ .

The two-digit subscript, for example, the subscript "11" is
Originally, the subscript should be displayed as "1,1", but it may be displayed as a two-digit subscript for the sake of simplicity of display. Three
The same applies to digit subscripts. The subscript "M" is used, for example, to collectively display a plurality of memory cells or plate lines, and the subscript "m" is used, for example, to display a plurality of memory cells or plate lines individually. , Subscript “N”,
For example, it is used to collectively display the selection transistors and the memory units, and the subscript “n” is used to individually display the selection transistors and the memory units, for example. Further, the subscript "K" is used to collectively display the ferroelectric non-volatile semiconductor memory arrays, and the subscript "k" is used to individually display the ferroelectric non-volatile semiconductor memory arrays. To do.

Then, one bit is stored by writing complementary data in each memory cell. In FIG. 53, reference numeral “WL” indicates a word line, reference numeral “BL” indicates a bit line, and reference numeral “PL” indicates a plate line. Focusing on one nonvolatile memory, the word line WL ₁ is connected to the word line decoder / driver WD. The bit lines BL ₁ and BL ₂ are connected to the sense amplifier SA. Furthermore, the plate line PL ₁
Are connected to the plate line decoder / driver PD.

In the nonvolatile memory having such a structure, when reading the stored data, the word line W
When L ₁ is selected and the plate line PL ₁ is driven,
Complementary data is transmitted from the paired memory cells (capacitor sections) FC ₁₁ and FC ₁₂ to the selection transistors TR ₁₁ and T.
It appears as a voltage (bit line potential) on the paired bit lines BL ₁ and BL ₂ via R ₁₂ . The voltage (bit line potential) of the paired bit lines BL ₁ and BL ₂ is detected by the sense amplifier SA.

One nonvolatile memory is a word line W.
It occupies a region surrounded by L ₁ and the paired bit lines BL ₁ and BL ₂ . Therefore, if the word lines and the bit lines are arranged at the shortest pitch, the minimum area of one nonvolatile memory is 8F ^2, where F is the minimum processing size. Therefore, the minimum area of the nonvolatile memory having such a structure is 8F ² .

When it is attempted to increase the capacity of the nonvolatile memory having such a structure, its realization can only depend on the miniaturization of the processing size. Further, two selection transistors and two memory cells (capacitor section) are required to form one nonvolatile memory. Furthermore, it is necessary to arrange the plate lines at the same pitch as the word lines. Therefore, it is almost impossible to arrange the non-volatile memory at the minimum pitch, and in reality, the area occupied by one non-volatile memory is significantly larger than 8F ² .

Moreover, it is necessary to dispose the word line decoder / driver WD and the plate line decoder / driver PD at the same pitch as that of the nonvolatile memory. In other words, two decoders / drivers are needed to select one row address. Therefore, the layout of the peripheral circuit becomes difficult, and the area occupied by the peripheral circuit becomes large.

One of means for reducing the area of a non-volatile memory
One is known from JP-A-9-121032.
As shown in the equivalent circuit of FIG.
The nonvolatile memory shown is a single selection transistor.
TR_k1Each lower electrode was connected in parallel to one end of
Multiple memory cells MC_k1M(Eg M = 4)
Has been done. In addition, the nonvolatile memory paired with this non-volatile memory
Volatile memory also has one selection transistor TR_k2One
Multiple notes with each bottom electrode connected in parallel to the end
Resel MC_k2M(For example, M = 4)
It Selection transistor TR_k1, TR_k2The other end of it
Bit line BL_k1, BL_k2It is connected to the. Pair
Bit line BL_k1, BL_k2Is the sense amplifier SA_k
It is connected to the. Also, the memory cell MC_k1m, MC_k2m
(M = 1, 2 ... M) upper electrode is a common plate line
PL_mConnected to the plate line PL_mIs the plate line
It is connected to the decoder / driver PD. In addition,
The word line WL is connected to the word line decoder / driver WD.
Has been done. Furthermore, a large number of non-volatile
The nonvolatile memory is arranged in the plate line direction,
It constitutes a moly array. Construct a non-volatile memory array
Memory cell MC in nonvolatile memory _knm(K
Is the number of non-volatile memories that make up the non-volatile memory array
Is 1/2, and n = 1, 2),
Plate line PL_mAre common.

Then, a pair of memory cells MC _k1m ,
Data complementary to MC _k2m (m = 1, 2 ... M) is stored. For example, when reading the data stored in the memory cells MC _k1m and MC _k2m (where m is 1, 2, 3, or 4), the word line WL is selected and the plate line PL _j (m ≠ j ), The plate line PL _m is driven with a voltage of (1/2) V _cc applied. Where V
_cc is, for example, a power supply voltage. As a result, complementary data is _{supplied as} a voltage (bit line potential) from the _paired memory cells MC _k1m and MC _k2m to the paired bit lines BL _k1 and BL _k2 via the selection transistors TR _k1 and TR _k2. Appears as. Then, the paired bit lines BL _k1 ,
The voltage of BL _k2 (bit line potential) is supplied to the sense amplifier SA _k.
Detect with.

A pair of non-volatile memories in a pair
Selection transistor TR_k1And TR _k2Is the word line W
L and the paired bit line BL_k1, BL_k2By
Occupies the enclosed area. Therefore, if the word line and
And the bit lines are arranged at the shortest pitch, they are paired.
Pair of select transistors in a non-volatile memory
TR_k1And TR_k2Area is 8F²Is. However
While a pair of selection transistors TR_k1, TR_k2To
M sets of memory cells MC as a pair_k1m, MC_k2m(M =
1, 2, ... M)
Selection transistor TR_k1, TR_k2The number of
In addition, since the arrangement of the word lines WL is loose,
It is easy to reduce the size of the memory. Moreover, the peripheral circuits
However, one word line decoder / driver WD and M
Select M bit with plate line decoder / driver PD
You can Therefore, such a configuration may be adopted.
And the cell area is 8F²It is possible to realize a layout close to
Yes, it is possible to realize a chip size comparable to DRAM
It

When reading the data stored in the memory cells MC _k1m and MC _k2m , at the same time, a pair of memory cells MC _k′1m and MC _k′2m (the plate line is common in k ′ ≠ k). The data stored in () is also read. Memory cells MC _k1m , MC _k2m , memory cells MC _k'1m , MC
After reading the data stored in _k'2m , the data is rewritten. That is, a so-called refresh operation is executed. Alternatively, the data read by the sense amplifier SA _k is output to the outside randomly or sequentially.

[0016]

By the way, JP-A-9-
The method of reducing the area of the non-volatile memory disclosed in Japanese Patent No. 121032 is a very effective method, but has the following problems.

That is, for example, a pair of memory cells MC
_{In k1m} and MC _k2m , when the data “1” is _rewritten in the memory cell MC _k1m , the plate line PL _{m is set} to the ground level (0 volt) and the bit line BL _{k1 is set} to V _cc , so that the ferroelectric layer is formed. Is polarized, but at this time, in order to hold the data “0” in the memory cell MC _k2m , the bit line BL _{k2 is set} to the ground level (0 volt).
And need to.

On the other hand, non-selected plate lines PL _j (j ≠
In order to prevent the data stored in the memory cells MC _k1j and MC _k2j connected to m) from being destroyed, the non-selected plate line PL _{j m} is an intermediate voltage between the bit lines BL _k1 and BL _k2 ( 1/2) Fixed to V _cc and unselected memory cell MC
_The electric field applied to the ferroelectric layers forming the memory cells _k1j and _MCk2j is relaxed. That is, unselected memory cells M
A disturbance of (1/2) V _cc is added to C _k1j and MC _k2j . Here, the disturb refers to a phenomenon in which an electric field is applied to a ferroelectric layer of a non-selected memory cell in a direction in which polarization is inverted, that is, in a direction in which stored data is deteriorated or destroyed. .

Therefore, if the number of times of reading and rewriting data from the memory cell is unlimited, there is a problem that the data stored in the memory cell is destroyed by the disturb. As one of the measures for solving such a problem, at the time when the data reading and _rewriting in the memory cells MC _k1m and MC _k2m are completed, the data reading and the rewriting are _performed to all the other memory cells MC _k1j and MC _k2j. A method of writing (refresh operation) can be considered. As a result, the number of disturbs received by the memory cell is (M-1).

However, in such a measure, in the pair of non-volatile memories among the plurality of non-volatile memories forming the non-volatile memory array, data is read and rewritten from the pair of memory cells once each time. In addition, there is a problem in that the refresh operation must be performed on all the remaining memory cells, and the operation speed of the entire nonvolatile memory array cannot be improved. Also,
There is also a problem that the non-volatile memory array cannot be accessed until the refresh operation in the plurality of non-volatile memories constituting the non-volatile memory array is not completed. Therefore, application to random access such as DRAM is basically extremely difficult, or even if possible, the access speed becomes very slow.

Therefore, an object of the present invention is to provide a ferroelectric non-volatile semiconductor memory array which can be applied to random access and can solve the problem that the access speed becomes very slow, and a driving method thereof. To do.

[0022]

A ferroelectric non-volatile semiconductor memory array according to a first aspect of the present invention for achieving the above object is a plurality of ferroelectric non-volatile semiconductor memories and at least one ferroelectric non-volatile semiconductor memory. A ferroelectric non-volatile semiconductor memory array comprising a flag circuit composed of a flag storing semiconductor memory, wherein the ferroelectric non-volatile semiconductor memory and the flag storing semiconductor memory are (A) bit lines and (B) ) A selection transistor, (C) a memory unit composed of M (where M ≧ 2) memory cells, and (D) M plate lines, each memory cell having a first electrode. And a ferroelectric layer and a second electrode, the first electrode of the memory cell is common in the memory unit, and the common first electrode is connected to the bit through the selection transistor. In the memory unit, the second electrode of the m-th (where m = 1, 2 ..., M) memory cell is connected to the m-th plate line, and is of the ferroelectric type. In the nonvolatile semiconductor memory and the flag storage semiconductor memory, the M plate lines are common, and in a certain plate line, data reading and data re-reading from any memory cell in which the plate line is common. When the writing is performed a predetermined number of times, the memory cells of the flag storing semiconductor memory forming the flag circuit are initialized, and the refresh operation of the memory cells forming each ferroelectric non-volatile semiconductor memory is performed. Characterize.

Second aspect of the present invention for achieving the above object
A ferroelectric non-volatile semiconductor memory array according to another aspect is a ferroelectric non-volatile semiconductor memory array including a plurality of ferroelectric non-volatile semiconductor memories and a flag circuit including at least one flag storing semiconductor memory. The ferroelectric non-volatile semiconductor memory and the flag storage semiconductor memory are (A) bit lines and (B)
The selection transistors and (C) are each M (however,
N (where N ≧ 2) memory cells each having M ≧ 2
≧ 2) memory units and (D) M × N plate lines, N memory units are stacked with an insulating layer in between, and each memory cell has a first electrode and a strong electrode. In each memory unit, the first electrode of the memory cell is common, and the common first electrode is connected to the bit line via the selection transistor, and comprises a dielectric layer and a second electrode. In the n-th layer (however, n = 1, 2, ..., N) memory unit, the mth (however, m = 1, 2)
The second electrode of the memory cell of ...
1) M + m] th plate line, and in the ferroelectric type nonvolatile semiconductor memory and the flag storage semiconductor memory, the M × N plate lines are common, and in a certain plate line, When data reading and data rewriting from any memory cell having the common plate line are performed a predetermined number of times, the memory cell of the flag storing semiconductor memory forming the flag circuit is initialized and It is characterized in that a refresh operation is performed on a memory cell forming a dielectric non-volatile semiconductor memory.

A third aspect of the present invention for achieving the above object.
A ferroelectric non-volatile semiconductor memory array according to another aspect is a ferroelectric non-volatile semiconductor memory array including a plurality of ferroelectric non-volatile semiconductor memories and a flag circuit including at least one flag storing semiconductor memory. The ferroelectric non-volatile semiconductor memory and the flag storage semiconductor memory are (A) bit lines and (B)
N (where N ≧ 2) selection transistors and (C)
Each memory cell is composed of N memory units each composed of M memory cells (where M ≧ 2) and (D) M plate lines. Each memory cell has a first electrode and a ferroelectric layer. The memory cell includes a body layer and a second electrode, and in each memory unit, the first electrode of the memory cell is common and common in the n-th (where n = 1, 2, ..., N) memory unit. Is connected to the bit line through the n-th selection transistor, and in the n-th memory unit, the m-th (where m = 1, 2 ...
The second electrode of the memory cell of M) is connected to the m-th plate line common to the memory units,
In the ferroelectric non-volatile semiconductor memory and the flag storage semiconductor memory, the M plate lines are common, and in a certain plate line, data read from any memory cell in which the plate line is common. When the data rewriting is performed a predetermined number of times, the memory cells of the flag storing semiconductor memory that configure the flag circuit are initialized, and the refresh operation of the memory cells that configure each ferroelectric non-volatile semiconductor memory is performed. It is characterized by being called.

A fourth aspect of the present invention for achieving the above object.
A ferroelectric non-volatile semiconductor memory array according to another aspect is a ferroelectric non-volatile semiconductor memory array including a plurality of ferroelectric non-volatile semiconductor memories and a flag circuit including at least one flag storing semiconductor memory. Therefore, the ferroelectric non-volatile semiconductor memory is
(A) bit lines, (B) N (where N ≧ 2) selection transistors, and (C) each for M (where M ≧)
2) N memory units composed of memory cells and (D) M plate lines, each memory cell comprising a first electrode, a ferroelectric layer and a second electrode. In each memory unit, the first electrode of the memory cell is common, and the n-th (where n = 1, 2, ...,
The common first electrode in the memory unit N) is connected to the bit line via the nth selection transistor, and the mth memory unit (where m = 1, 2, ...) In the nth memory unit. .., M), the second electrode of the memory cell is connected to the m-th plate line common to the memory units, and the flag storing semiconductor memory is
(E) a bit line, (F) N selection transistors, (G) a memory unit composed of M (where M ≧ 2) memory cells, and (H) M plates. Line, each memory cell comprises a first electrode, a ferroelectric layer and a second electrode, and in the memory unit, the first electrode of the memory cell is common and the first common electrode of the memory unit is common. The electrode No. 1 is connected to the bit line via each selection transistor, and the M plate lines are common in the ferroelectric type nonvolatile semiconductor memory and the flag storage semiconductor memory, and a certain plate line In the memory of the semiconductor memory for storing flags, which constitutes a flag circuit, when data reading and data rewriting from any memory cell having a common plate line are performed a predetermined number of times. Le is initialized, and, wherein the refresh operation of the memory cells constituting each type nonvolatile semiconductor memory.

A fifth aspect of the present invention for achieving the above object.
A ferroelectric non-volatile semiconductor memory array according to another aspect is a ferroelectric non-volatile semiconductor memory array including a plurality of ferroelectric non-volatile semiconductor memories and a flag circuit including at least one flag storing semiconductor memory. Therefore, the ferroelectric non-volatile semiconductor memory and the flag storage semiconductor memory are (A) N (where N ≧
2) bit lines, (B) N selection transistors, and (C) N memory units each composed of M memory cells (where M ≧ 2), and (D). M
Book plate lines, each memory cell comprises a first electrode, a ferroelectric layer and a second electrode, and in each memory unit, the first electrode of the memory cell is common,
The common first electrode in the n-th (where n = 1, 2, ..., N) memory unit is connected to the n-th bit line via the n-th selection transistor, In the nth memory unit, the mth (however, m
, 1, ..., M), the second electrode of the memory cell is connected to the m-th plate line that is common between the memory units, and the ferroelectric type nonvolatile semiconductor memory and the flag storage are stored. In the semiconductor memory for use, the M plate lines are made common, and the data read and the data rewrite from a memory cell having a common plate line on a certain plate line are performed a predetermined number of times. At this time, the memory cells of the flag storing semiconductor memory forming the flag circuit are initialized, and the refresh operation of the memory cells forming each ferroelectric non-volatile semiconductor memory is performed.

A sixth aspect of the present invention for achieving the above object.
A ferroelectric non-volatile semiconductor memory array according to another aspect is a ferroelectric non-volatile semiconductor memory array including a plurality of ferroelectric non-volatile semiconductor memories and a flag circuit including at least one flag storing semiconductor memory. Therefore, the ferroelectric non-volatile semiconductor memory is
(A) N (where N ≧ 2) bit lines, (B) N selection transistors, and (C) each consisting of M (where M ≧ 2) memory cells, Each of the memory cells includes N memory units and (D) M plate lines. Each memory cell includes a first electrode, a ferroelectric layer, and a second electrode. The first electrode is common, and is the n-th (where n = 1, 2 ,.
.., N) is connected to the n-th bit line through the n-th selection transistor, and the common first electrode is connected to the n-th memory unit. , M = 1, 2, ..., M), the second electrode of the memory cell is connected to the m-th plate line common to the memory units, and the flag storage semiconductor memory is ( E) bit line, (F) N selection transistors, and (G) M pieces (where M ≧
A memory unit composed of the memory cells of 2),
(H) M plate lines, each memory cell
It is composed of a first electrode, a ferroelectric layer, and a second electrode, the first electrode of the memory cell is common in the memory unit, and the common first electrode of the memory unit is a selection transistor. Which are connected to a bit line through the M type plate lines, and the ferroelectric non-volatile semiconductor memory and the flag storage semiconductor memory share the M plate lines in common. When the data reading and the data rewriting from the memory cell are performed a predetermined number of times, the memory cell of the flag storing semiconductor memory forming the flag circuit is initialized and each ferroelectric non-volatile semiconductor memory is formed. The refresh operation of the memory cell is performed.

The first aspect of the present invention for achieving the above object
A method of driving a ferroelectric non-volatile semiconductor memory array according to another aspect of the present invention is a ferroelectric non-volatile memory including a plurality of ferroelectric non-volatile semiconductor memories and a flag circuit including at least one flag storing semiconductor memory. The semiconductor memory array, which is a ferroelectric non-volatile semiconductor memory and a flag storage semiconductor memory, includes (A) bit lines, (B) selection transistors, and (C) M (however,
(M ≧ 2), a memory unit including memory cells, and (D) M plate lines, each memory cell including a first electrode, a ferroelectric layer, and a second electrode.
In the memory unit, the first electrode of the memory cell is common, and the common first electrode is connected to the bit line through the selection transistor, and in the memory unit, the m-th electrode (where m = 1 , 2 ..., M) of the memory cell is connected to the m-th plate line, and in the ferroelectric non-volatile semiconductor memory and the flag storing semiconductor memory, the M plates are connected. A method of driving a ferroelectric non-volatile semiconductor memory array in which lines are common, and in a certain plate line, data read and data rewrite from any memory cell in which the plate line is common are predetermined. A memory that initializes the memory cells of the flag storage semiconductor memory that configures the flag circuit when the number of times is performed and configures each ferroelectric non-volatile semiconductor memory And performing a refresh operation of Le.

Second aspect of the present invention for achieving the above object
A method of driving a ferroelectric non-volatile semiconductor memory array according to another aspect of the present invention is a ferroelectric non-volatile memory including a plurality of ferroelectric non-volatile semiconductor memories and a flag circuit including at least one flag storing semiconductor memory. The ferroelectric memory nonvolatile semiconductor memory and the flag storage semiconductor memory, which are semiconductor memory arrays, include (A) bit lines, (B) selection transistors, and (C) M.
Each of the N memory units is composed of N (however, M ≧ 2) memory cells and (D) M × N plate lines composed of N (where M ≧ 2) memory cells. , Stacked via an insulating layer, each memory cell includes a first electrode, a ferroelectric layer, and a second electrode. In each memory unit, the first electrode of the memory cell is common. , The common first electrode is connected to the bit line via the selection transistor, and the nth layer (where n = 1, 2 ,.
.., N), the second electrode of the m-th (where m = 1, 2 ..., M) memory cell is the [(n-1) M + m] -th plate line. And a ferroelectric non-volatile semiconductor memory and a flag storing semiconductor memory, the method of driving a ferroelectric non-volatile semiconductor memory array in which the M × N plate lines are common. At a plate line,
When data reading and data rewriting from any of the memory cells having the common plate line are performed a predetermined number of times, the memory cells of the flag storing semiconductor memory forming the flag circuit are initialized, and each ferroelectric type A feature is that a refresh operation is performed on a memory cell included in the nonvolatile semiconductor memory.

A third aspect of the present invention for achieving the above object.
A method of driving a ferroelectric non-volatile semiconductor memory array according to another aspect of the present invention is a ferroelectric non-volatile memory including a plurality of ferroelectric non-volatile semiconductor memories and a flag circuit including at least one flag storing semiconductor memory. The semiconductor memory array, which is a ferroelectric non-volatile semiconductor memory and a flag storage semiconductor memory, includes (A) bit lines, (B) N (where N ≧ 2) selection transistors, and (C). N memory units each composed of M (where M ≧ 2) memory cells, and (D) M
Book plate lines, each memory cell comprises a first electrode, a ferroelectric layer and a second electrode, and in each memory unit, the first electrode of the memory cell is common,
The common first electrode in the n-th (where n = 1, 2, ..., N) memory unit is connected to the bit line via the n-th selection transistor, and the n-th memory In the unit, the m-th unit (however, m = 1, 2 ·
.., M), the second electrode of the memory cell is connected to the m-th plate line common to the memory units, and in the ferroelectric nonvolatile semiconductor memory and the flag storage semiconductor memory, A method of driving a ferroelectric non-volatile semiconductor memory array in which the M plate lines are commonly used, in which data is read from any memory cell having a common plate line in a certain plate line. When data rewriting is performed a predetermined number of times, the memory cells of the flag storing semiconductor memory that configure the flag circuit are initialized, and the refresh operation of the memory cells that configure each ferroelectric non-volatile semiconductor memory is performed. And

A fourth aspect of the present invention for achieving the above object.
A method of driving a ferroelectric non-volatile semiconductor memory array according to another aspect of the present invention is a ferroelectric non-volatile memory including a plurality of ferroelectric non-volatile semiconductor memories and a flag circuit including at least one flag storing semiconductor memory. A ferroelectric non-volatile semiconductor memory, which is a semiconductor memory array, includes (A) bit lines and (B) N pieces (where N ≧
2) selection transistors, (C) N memory units each composed of M memory cells (where M ≧ 2), and (D) M plate lines. The memory cell includes a first electrode, a ferroelectric layer, and a second electrode. In each memory unit, the first electrode of the memory cell is common and the n-th (where n =
The common first electrode in the memory units 1, 2, ..., N) is connected to the bit line via the nth selection transistor, and in the nth memory unit, the mth (however, , M = 1, 2, ..., M), the second electrode of the memory cell is connected to the m-th plate line common to the memory units, and the flag storage semiconductor memory is ( E) bit line, (F) N selection transistors, and (G) M pieces (where M ≧
A memory unit composed of the memory cells of 2),
(H) M plate lines, each memory cell
It is composed of a first electrode, a ferroelectric layer, and a second electrode, the first electrode of the memory cell is common in the memory unit, and the common first electrode of the memory unit is a selection transistor. A method for driving a ferroelectric non-volatile semiconductor memory array, wherein the M plate lines are connected in common in a ferroelectric non-volatile semiconductor memory and a flag storing semiconductor memory. In the plate line to be read, when data reading and data rewriting from any memory cell having the common plate line are performed a predetermined number of times, the memory cell of the flag storing semiconductor memory forming the flag circuit is initialized, and It is characterized in that a refresh operation of a memory cell constituting each ferroelectric non-volatile semiconductor memory is performed.

A fifth aspect of the present invention for achieving the above object.
A method of driving a ferroelectric non-volatile semiconductor memory array according to another aspect of the present invention is a ferroelectric non-volatile memory including a plurality of ferroelectric non-volatile semiconductor memories and a flag circuit including at least one flag storing semiconductor memory. The semiconductor memory array, which is a ferroelectric non-volatile semiconductor memory and a flag storage semiconductor memory, includes (A) N (where N ≧ 2) bit lines, and (B) N selection transistors. (C) N memory units each composed of M memory cells (where M ≧ 2),
(D) consists of M plate lines, and each memory cell is
It is composed of a first electrode, a ferroelectric layer, and a second electrode, and in each memory unit, the first electrode of the memory cell is common and the n-th (where n = 1, 2, ..., The common first electrode in the N) th memory unit is connected to the nth bit line through the nth selection transistor, and in the nth memory unit, the mth (where m = The second electrode of each of the memory cells (1, 2, ..., M) is connected to the m-th plate line common to the memory units, and is used for storing the ferroelectric type nonvolatile semiconductor memory and the flag. In a semiconductor memory, the M
A method of driving a ferroelectric non-volatile semiconductor memory array in which one plate line is common, in which data read and data recovery from any memory cell in which one plate line is common When writing is performed a predetermined number of times, the memory cells of the flag storage semiconductor memory that configure the flag circuit are initialized, and the memory cells that configure each ferroelectric non-volatile semiconductor memory are refreshed. .

A sixth aspect of the present invention for achieving the above object.
A method of driving a ferroelectric non-volatile semiconductor memory array according to another aspect of the present invention is a ferroelectric non-volatile memory including a plurality of ferroelectric non-volatile semiconductor memories and a flag circuit including at least one flag storing semiconductor memory. A ferroelectric non-volatile semiconductor memory, which is a semiconductor memory array, includes (A) N (where N ≧ 2) bit lines,
(B) N selection transistors and (C) each of M memory cells (where M ≧ 2)
Memory cells and (D) M plate lines, each memory cell including a first electrode, a ferroelectric layer, and a second electrode.
In each memory unit, the first electrode of the memory cell is common, and the n-th electrode (where n =
1, 2, ..., N) are connected to the n-th bit line via the n-th selection transistor, and the common first electrode is connected to the n-th memory unit. m-th (however, m = 1, 2, ..., M)
The second electrode of the memory cell is connected to the m-th plate line common to the memory units, and the flag storing semiconductor memory includes the (E) bit line and the (F) N line.
Number of selection transistors, (G) M memory cells (where M ≧ 2) each, and (H) M plate lines. One electrode, a ferroelectric layer, and a second electrode, the first electrode of the memory cell is common in the memory unit, and the common first electrode of the memory unit is through each selection transistor. A ferroelectric non-volatile semiconductor memory and a flag storing semiconductor memory, the M plate lines are shared by the ferroelectric non-volatile semiconductor memory and the flag storing semiconductor memory. In the plate line, when data reading and data rewriting from one of the memory cells having the common plate line is performed a predetermined number of times, the flag storage that constitutes the flag circuit is stored. The memory cell of the semiconductor memory is initialized, and, and performing a refresh operation of the memory cells constituting each type nonvolatile semiconductor memory.

A ferroelectric non-volatile semiconductor memory array or a driving method thereof according to the first to sixth aspects of the present invention (hereinafter, these may be collectively referred to as the present invention). A pair of ferroelectric non-volatile semiconductor memories, one bit is stored in each of a pair of memory cells having a common plate line, and a pair of flag storing semiconductor memories is formed. ,and,
One bit can be stored in each of a pair of memory cells having a common plate line. In this case, for example, a pair of ferroelectric non-volatile semiconductor memory or flag storage semiconductor memory (for convenience, referred to as non-volatile memory-A, non-volatile memory-B), a pair of non-volatile memory-A and non-volatile memory The bit lines forming -B may be connected to the same sense amplifier, but the configuration is not limited to this. Then, in this case, the selection transistor forming the non-volatile memory-A and the selection transistor forming the non-volatile memory-B are connected to different word lines.
A pair of the non-volatile memory-A and the non-volatile memory-B is used to store 1-bit data in each of the paired memory cells. In this case, the number of flag storage semiconductor memories is 2L (however, L = 1, 2, 3, ...
.), The predetermined number of times is 2 ^L.

Alternatively, according to the present invention, a pair of ferroelectric non-volatile semiconductor memories are formed, and one bit is stored complementarily in a pair of memory cells having a common plate line. It is possible to configure the semiconductor memory for storing the flag and to store 1 bit complementarily in a pair of memory cells having a common plate line. That is, the ferroelectric type nonvolatile semiconductor memory or the flag storing semiconductor memory is paired (for convenience, referred to as nonvolatile memory-A and nonvolatile memory-B), and the pair of nonvolatile memory-A and nonvolatile memory-B is used. The constituent bit lines can be connected to the same sense amplifier. In this case, the non-volatile memory
Selection transistor forming A and non-volatile memory-
The selection transistor forming B may be connected to the same word line or different word lines. However, in the latter case, the non-volatile memory-A
Selection transistor and a non-volatile memory-B
And the selection transistor constituting the above are simultaneously driven.
Then, the nonvolatile memory-A and the nonvolatile memory-B are paired, and complementary data is stored in the paired memory cells. In this case, the number of flag storage semiconductor memories is 2L (however, L = 1, 2, 3, ...)
The predetermined number of times is 2 ^L.

In the present invention, the data stored in the memory cell of the flag storing semiconductor memory in the initialized flag circuit is the data from any memory cell having a common plate line in a certain plate line. When reading and rewriting data, the value changes in the memory cell formed from the plate line.
Then, the number of times of data reading and data rewriting from any of the memory cells having the common plate line until the changed value reaches a certain value corresponds to a predetermined number. For example, when the data stored in the flag storing semiconductor memory (the number is L) in the initialized flag circuit is “0” and the flag circuit has a 2 ^L- bit configuration, and when the data is incremented. , A certain value when the changed value becomes a certain value is (2 ^L −1)
Is a value corresponding to.

In the present invention, the disturbance tolerance of the memory cells forming the ferroelectric non-volatile semiconductor memory and the flag storing semiconductor memory is evaluated, and the upper limit of the number of times of disturb that the data stored in the memory cells is not destroyed is evaluated. The values of N, M, and L may be determined based on the value.

In the ferroelectric non-volatile semiconductor memory array or the method of driving the same according to the first aspect of the present invention, a plurality of memory units of ferroelectric non-volatile semiconductor memories may be laminated via an insulating layer. . In the ferroelectric non-volatile semiconductor memory array or the driving method thereof according to the third to sixth aspects of the present invention, N
The individual memory units may be formed on the same insulating layer, or may be stacked via the insulating layer.

In the present invention, it is only necessary to satisfy M ≧ 2, and as a practical value of M, for example, a power of 2 (2,
4, 8, 16 ...). In the ferroelectric non-volatile semiconductor memory array or the driving method thereof according to the second to sixth aspects of the present invention, it is sufficient that N ≧ 2 is satisfied, and as a practical value of N,
For example, a power of 2 (2, 4, 8 ...) Can be mentioned. Furthermore, in the present invention, as the number of ferroelectric non-volatile semiconductor memories, 2 ^p (p is, for example,
7,8,9,10,11,12 ...) can be illustrated.

The refresh operation in the present invention means an operation of reading data from the memory cell and rewriting the data. The read data is output to the outside of the ferroelectric non-volatile semiconductor memory array. Instead, it is simply used for rewriting. In some cases, the data read by the sense amplifier at the time of refreshing may be appropriately output to the outside.

In the ferroelectric non-volatile semiconductor memory array or the driving method thereof according to the second aspect of the present invention, or alternatively, the ferroelectric non-volatile semiconductor according to the third to sixth aspects of the present invention. In a preferred form of the memory array or the driving method thereof, the memory unit has a three-dimensional laminated structure, so that the number of transistors occupying the surface of the semiconductor substrate is not restricted.
The storage capacity can be dramatically increased as compared with the conventional ferroelectric non-volatile semiconductor memory, and the effective occupied area of the bit storage unit can be significantly reduced.

In the ferroelectric non-volatile semiconductor memory array or the driving method thereof according to the second to sixth aspects of the present invention, further, the address selection in the row direction is constituted by the selection transistor and the plate line. The two-dimensional matrix is used. For example, if a row address selection unit is made up of eight selection transistors and eight plate lines, 16 decoder / driver circuits can select, for example, 64-bit or 32-bit memory cells. it can. Therefore, the storage capacity can be quadrupled or doubled even if the degree of integration of the ferroelectric non-volatile semiconductor memory is the same as the conventional one. In addition, the number of peripheral circuits and drive wiring in address selection can be reduced.

In the ferroelectric non-volatile semiconductor memory array or the driving method thereof according to the second aspect of the present invention, or alternatively, the ferroelectric non-volatile semiconductor according to the third to sixth aspects of the present invention. In a preferred form of the memory array or its driving method, the crystallization temperature of the ferroelectric layer forming the memory cell of the memory unit located above is the ferroelectric layer forming the memory cell of the memory unit located below. Is preferably lower than the crystallization temperature of. Here, the crystallization temperature of the ferroelectric layer forming the memory cell can be examined by using, for example, an X-ray diffractometer or a surface scanning electron microscope. Specifically, for example, after the ferroelectric material layer is formed, the heat treatment temperature for performing crystallization of the ferroelectric material layer is variously changed to perform heat treatment for promoting crystallization, and The crystallization temperature of the ferroelectric layer can be obtained by performing X-ray diffraction analysis of the body material layer and evaluating the diffraction pattern intensity (diffraction peak height) peculiar to the ferroelectric material.

By the way, in the case of manufacturing a ferroelectric type nonvolatile semiconductor memory having a structure in which memory units are laminated, in order to crystallize the ferroelectric layer or the ferroelectric thin film forming the ferroelectric layer. , Heat treatment (referred to as crystallization heat treatment) must be performed by the number of stacked memory units. Therefore, the lower memory unit is subjected to the crystallization heat treatment for a longer time, and the upper memory unit is subjected to the crystallization heat treatment for a shorter time. Therefore, when the optimum crystallization heat treatment is performed on the memory unit located on the upper stage, the memory unit located on the lower stage may be subjected to an excessive heat load, and the characteristics of the memory unit located on the lower stage may deteriorate. There is. Although it is possible to perform a crystallization heat treatment at once after manufacturing a multi-stage memory unit, a large volume change occurs in the ferroelectric layer during crystallization, and degassing from each ferroelectric layer occurs. It is likely to occur, and problems such as cracks and peeling of the ferroelectric layer are likely to occur. If the crystallization temperature of the ferroelectric layer forming the memory unit located above is set lower than the crystallization temperature of the ferroelectric layer forming the memory unit located below, only the number of stacked memory units will be increased. Even if the crystallization heat treatment is performed, there is no problem such as characteristic deterioration of the memory cells forming the memory unit located below. Further, the crystallization heat treatment under the optimum conditions can be performed on the memory cells forming the memory unit in each stage, and the ferroelectric non-volatile semiconductor memory having excellent characteristics can be obtained. Table 1 below shows crystallization temperatures of typical materials constituting the ferroelectric layer.
The material forming the ferroelectric layer is not limited to such a material.

[Table 1] Material name Crystallization temperature Bi ₂ SrTa ₂ O ₉ 700 to 800 ° C Bi ₂ Sr (Ta _1.5 , Nb _0.5 ) O ₉ 650 to 750 ° C Bi ₄ Ti ₃ O ₁₂ 600 to 700 ° _{C Pb (Zr 0.48, Ti 0.52} ) O 3 550~650 ° C PbTiO ₃ 500 to 600 ° C

Examples of the material constituting the ferroelectric layer in the present invention include a bismuth layered compound, more specifically, a Bi-based layered structure perovskite type ferroelectric material. The Bi-based layered structure perovskite type ferroelectric material belongs to a so-called non-stoichiometric compound, and is tolerant of composition shifts at both sites of a metal element and an anion (O etc.) element. In addition, it is not uncommon to show optimum electrical characteristics when the composition deviates slightly from the stoichiometric composition. The Bi-based layered structure perovskite type ferroelectric material can be represented by, for example, the general formula (Bi ₂ O ₂ ) ²⁺ (A _m-1 B _m O _{3m + 1} ) ^2- . Here, “A” means Bi, Pb, Ba, Sr,
Represents one kind of metal selected from the group consisting of metals such as Ca, Na, K and Cd, and “B” represents Ti, Nb,
It represents a combination of one kind or a plurality of kinds selected from the group consisting of Ta, W, Mo, Fe, Co and Cr at an arbitrary ratio. Further, m is an integer of 1 or more.

Alternatively, the material forming the ferroelectric layer is (Bi _X , Sr _1-X ) ₂ (Sr _Y , Bi _1-Y ) (Ta _Z , Nb _1-Z ) ₂ O _d formula (1 (However, 0.9 ≦ X ≦ 1.0, 0.7 ≦ Y ≦ 1.0, 0
≦ Z ≦ 1.0, 8.7 ≦ d ≦ 9.3) is preferably contained as the main crystal phase. Alternatively, the material forming the ferroelectric layer is Bi _X Sr _Y Ta ₂ O _d formula (2) (where X + Y = 3, 0.7 ≦ Y ≦ 1.3, 8.7 ≦ d
It is preferable that the crystal phase represented by ≦ 9.3) is contained as a main crystal phase. In these cases, the crystal phase represented by the formula (1) or (2) is used as the main crystal phase.
% Or more is more preferable. The formula (1)
In the meaning, (Bi _X , Sr _1-X ) means that Sr occupies the site originally occupied by Bi in the crystal structure, and the ratio of Bi and Sr at this time is X: (1-X). . Further, the meaning of (Sr _Y , Bi _{1 -Y} ) means that Bi occupies the site originally occupied by Sr in the crystal structure, and the ratio of Sr and Bi at this time is Y: (1-Y). . Examples of the material forming the ferroelectric layer containing the crystal phase represented by the formula (1) or (2) as a main crystal phase include Bi oxide, Ta or Nb oxide, and Bi, Ta or Nb oxide. In some cases, a small amount of complex oxide may be contained.

Alternatively, the material forming the ferroelectric layer is as follows: Bi _X (Sr, Ca, Ba) _Y (Ta _Z , Nb _{1 -Z} ) ₂ O _d Formula (3) (provided that 1.7 ≦ X ≤2.5, 0.6≤Y≤1.2,0
≦ Z ≦ 1.0, 8.0 ≦ d ≦ 10.0) may be included. In addition, "(Sr, Ca, Ba)"
Means one kind of element selected from the group consisting of Sr, Ca and Ba. When the composition of the material forming the ferroelectric layer represented by each of these formulas is represented by a stoichiometric composition, for example, Bi ₂ SrTa ₂ O ₉ , Bi ₂ SrNb ₂ O ₉ ,
_{Bi 2 BaTa 2 O 9, Bi} 2 Sr (Ta, Nb) can be exemplified ₂ O _9, or the like. Alternatively, as a material for forming the ferroelectric layer, Bi ₄ SrTi ₄ O ₁₅ , Bi ₃ TiNb is used.
O ₉ , Bi ₃ TiTaO ₉ , Bi ₄ Ti ₃ O ₁₂ , Bi ₂ PbT
can be exemplified a ₂ O _9, etc., even in these cases, the ratio of the respective metal elements may change to the extent that the crystal structure does not change. That is, there may be a compositional shift at both the metal element and oxygen element sites.

Alternatively, as a material forming the ferroelectric layer, PbTiO ₃ or P having a perovskite structure is used.
Lead zirconate titanate [PZT, Pb (Zr _{1 -y} , Ti _y ) O ₃ (provided that bZrO ₃ and PbTiO ₃ are solid solutions.
0 <y <1)], PLZT which is a metal oxide obtained by adding La to PZT, or PZT compound such as PNZT which is a metal oxide obtained by adding Nb to PZT.

In the materials constituting the ferroelectric layer explained above, the crystallization temperature can be changed by removing these compositions from the stoichiometric composition.

In order to obtain the ferroelectric layer, the ferroelectric thin film may be patterned in a step after the ferroelectric thin film is formed. In some cases, patterning of the ferroelectric thin film is unnecessary. The ferroelectric thin film can be appropriately formed by a method suitable for the material forming the ferroelectric thin film, such as MOCVD, pulse laser ablation, sputtering, and sol-gel method. Also,
The ferroelectric thin film can be patterned by, for example, anisotropic ion etching (RIE) method.

In the present invention, the first layer is formed under the ferroelectric layer.
The second electrode may be formed on the ferroelectric layer by forming the second electrode (that is, the first electrode corresponds to the lower electrode and the second electrode corresponds to the upper electrode). A structure in which the first electrode is formed on the ferroelectric layer and the second electrode is formed under the ferroelectric layer (that is, the first electrode corresponds to the upper electrode and the second electrode The electrode may correspond to the lower electrode). The plate line preferably extends from the second electrode from the viewpoint of simplifying the wiring structure. As a structure in which the first electrode is common, specifically, a structure is such that a stripe-shaped first electrode is formed and a ferroelectric layer is formed so as to cover the entire surface of the stripe-shaped first electrode. Can be mentioned. In such a structure, the overlapping region of the first electrode, the ferroelectric layer and the second electrode corresponds to the memory cell. As a structure in which the first electrode is common, in addition, a structure in which each ferroelectric layer is formed in a predetermined region of the first electrode and a second electrode is formed on the ferroelectric layer, or Further, each first electrode is formed on a predetermined surface region of the wiring layer, and a ferroelectric layer is formed on each of the first electrodes,
A structure in which the second electrode is formed on the ferroelectric layer can be mentioned, but the structure is not limited to these.

Furthermore, in the present invention, when the first electrode is formed below the ferroelectric layer and the second electrode is formed above the ferroelectric layer, the first electrode forming the memory cell is formed. Has a so-called damascene structure. When the first electrode is formed on the ferroelectric layer and the second electrode is formed under the ferroelectric layer, a memory cell is formed. It is preferable that the second electrode has a so-called damascene structure from the viewpoint that the ferroelectric layer can be formed on a flat base.

In the present invention, the first electrode or the second electrode
Examples of the material forming the electrodes of Ir include Ir and IrO.
_2-X , Ir / IrO _2-X , SrIrO ₃ , Ru, Ru
_{O 2-X, SrRuO 3,} Pt, Pt / IrO 2-X, Pt /
RuO _2-X , Pd, Pt / Ti laminated structure, Pt / Ta
Laminated structure, Pt / Ti / Ta laminated structure, La _0.5 S
Examples thereof include r _0.5 CoO ₃ (LSCO), a Pt / LSCO laminated structure, and YBa ₂ Cu ₃ O ₇ . here,
The value of X is 0 ≦ X <2. In the laminated structure, the material described after "/" is in contact with the ferroelectric layer. The first electrode and the second electrode may be made of the same material, may be made of the same kind of material, or may be made of different materials. In order to form the first electrode or the second electrode, the conductive material layer is patterned in a step after forming the conductive material layer forming the first electrode or the conductive material layer forming the second electrode. do it. The conductive material layer is formed by, for example, a sputtering method, a reactive sputtering method, an electron beam evaporation method, a MO method.
This can be appropriately performed by a method suitable for the material forming the conductive material layer, such as a CVD method or a pulse laser ablation method. In addition, the patterning of the conductive material layer is
For example, the ion milling method or the RIE method can be used.

The selection transistor and various types of transistors can be composed of, for example, a well-known MIS type FET or MOS type FET. Examples of the material forming the bit line include polysilicon doped with impurities and a refractory metal material. The connection between the selection transistor and the common first electrode, and the connection between the selection transistor and the bit line may be performed through the connection hole.
For example, it can be obtained by embedding a tungsten plug or polysilicon doped with impurities.

In the present invention, silicon oxide (SiO ₂ ), silicon nitride (Si
N), SiON, SOG, NSG, BPSG, PSG,
BSG or LTO can be exemplified.

In the present invention, in a certain plate line, data read and data rewrite from any memory cell having the common plate line (hereinafter, sometimes referred to as memory cell access) are predetermined. When the operation is performed a number of times, the memory cells of the flag storage semiconductor memory that configure the flag circuit are initialized, and the refresh operation of the memory cells that configure each ferroelectric non-volatile semiconductor memory is performed. As a result, the number of refresh operations of the ferroelectric non-volatile semiconductor memory array can be dramatically reduced, while the number of disturbs received by the memory cells can be reliably managed. Furthermore, random access to the memory cells becomes possible.

[0058]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below with reference to the drawings on the basis of an embodiment of the invention (hereinafter, simply referred to as an embodiment).

(Embodiment 1) Embodiment 1 relates to a ferroelectric non-volatile semiconductor memory array (hereinafter abbreviated as non-volatile memory array) according to the first aspect of the present invention and a driving method thereof. A schematic view of a ferroelectric non-volatile semiconductor memory (hereinafter, abbreviated as non-volatile memory) that constitutes the non-volatile memory array of the first embodiment taken along a virtual vertical plane parallel to the extending direction of the bit line. FIG. 1 is a partial cross-sectional view, and FIG. 2 is a schematic partial cross-sectional view when the flag storing semiconductor memory is cut. Further, a conceptual circuit diagram of the nonvolatile memory array of the first embodiment is shown in FIG. 3, and a more specific nonvolatile memory circuit diagram of the conceptual circuit diagram of FIG. 3 is shown in FIG. A more specific circuit diagram of the circuit is shown in FIG. Note that, in FIGS. 1 and 2, two non-volatile memories and a flag storage semiconductor memory which are adjacent to each other in the bit line direction are illustrated. Then, the reference number of one of the constituent elements of the non-volatile memory and the flag storage semiconductor memory which are adjacent to each other is denoted by "'". The nonvolatile memory and the flag storage semiconductor memory which are adjacent to each other in the extending direction of the bit line belong to different nonvolatile memory arrays.

This non-volatile memory array includes a plurality of (for example, K = 2 ⁷ ) non-volatile memories and at least one (1 in the first embodiment, L = 1) semiconductor memory for storing flags. Flag circuit (2 ^L-1 bit = 1 bit flag circuit). still,
The nonvolatile memory and the flag storage semiconductor memory have the same structure and configuration. In the drawing, in the k-th (k is any of 1, 2, 3 ... K) nonvolatile memory,
The subscript "k" was added.

The k-th non-volatile memory M _k includes (A) bit line BL _k , (B) selection transistor TR _k ,
(C) M (where M ≧ 2, M = 8 in the first embodiment) memory units MU _k configured of memory cells MC _kM and (D) M plate lines PL _M , Consists of.

On the other hand, the flag storing semiconductor memory F is
(A) Bit line FBL and (B) selection transistor F
TR, (C) M memory cells (where M ≧ 2, and M = 8 in the first embodiment), a memory unit FU including memory cells FC _M , and (D) M plate lines. P
L _M, consisting of.

Here, each memory cell MC _km , FC _m is
It is composed of a first electrode 21, a ferroelectric layer 22 and a second electrode 23, and in the memory units MU _k , FU, the first electrodes 21 of the memory cells MC _kM , FC _M are common and have a common first. One electrode (called common node CN _k , FCN)
Is connected to the bit lines BL _k , FBL via the selection transistors TR _k , FTR, and the memory units MU _k , F
In U, m-th (however, m = 1, 2 ..., M)
The second electrode 23 of the memory cell MC _km , FC _m of
It is connected to the th plate line PL _m . Further, in the nonvolatile memory M _k and the flag storing semiconductor memory F, M plate lines PL _m are shared. Specifically, the memory cell M that constitutes the nonvolatile memory M _k
The second electrode 23 of C _km and the semiconductor memory F for storing the flag
Is connected to the same plate line PL _m as the second electrode 23 of the memory cell FC _m constituting the memory cell FC _m , or the plate line PL _m extends from the second electrode 23.

One of the source / drain regions 14A of the selecting transistors TR _k , FTR is connected to the bit lines BL _k , FBL via the connection hole 15, and the other source / drain regions 14B of the selecting transistors TR _k , FTR are connected.
Via the connection hole 18 formed in the opening 17 provided in the insulating layer 16 to the common first electrode 21 (first common node CN _k , in the memory units MU _k , FU).
FCN). In addition, the bit lines BL _k , F
BL is connected to the sense amplifiers SA _k and FSA. The plate line PL _M is connected to the plate line decoder / driver PD. Furthermore, the selection transistor T
The word line WL which controls the operation of R _k and FTR is connected to the word line decoder / driver WD. The word line WL extends in the direction perpendicular to the paper surface of FIGS. 1 and 2. Word line WL is common in the selection transistor TR _k constituting the nonvolatile memory M _k, the selection transistor constituting a non-volatile memory adjacent in the direction perpendicular to the paper surface in FIG. 1, moreover, the semiconductor flag storage It is also common to the selection transistor FTR forming the memory F. The second electrode 23 of the memory cell MC _m forming the non-volatile memory M is common to the second electrode of the memory cell forming the non-volatile memory adjacent in the direction perpendicular to the paper surface of FIG. The plate line P which also serves as PL _m and which constitutes the memory cell FC _m of the flag storing semiconductor memory F
It is also common to L _m .

The flag circuit further includes a sense amplifier FSA.
Determination circuit FG for deciding the output from the sense amplifier FSA, and inverting circuit IN for inverting the output from the sense amplifier FSA
Register RS that stores V and the output from the inverting circuit
It consists of The flag determination circuit FG, the inverting circuit INV, and the register RS may be composed of known circuits.

Then, in a certain plate line, for example,
For example, plate line PL_mOne of the memories that was common to
Cell MC_kmRead data from and rewrite data (
A certain number of times (2)^LAnd the first embodiment
(2 times).
The memory cell of the semiconductor memory for storing lag is initialized and
Remaining part of each ferroelectric non-volatile semiconductor memory
All memory cells MC _Kj(J ≠ m) refresh motion
The work is done.

The method of driving the nonvolatile memory array of the first embodiment will be specifically described below.

First, an operation (access operation) of reading data from the nonvolatile memory of the first embodiment and rewriting the data will be described below. As an example, it is assumed that the data is read from the memory cell MC _km connected to the plate line PL _m and the data is rewritten. Figure 6
Shows the operation waveform. In addition, in FIG. 6, the numbers in parentheses correspond to the numbers of the steps described below.

(1) In the standby state, all bit lines, word lines, and all plate lines are at 0 volt. Furthermore, all common nodes are also floating at 0 volts.

(2) When reading data, the selected plate line P
Applying a V _cc to L _m. At this time, the selected memory cell MC
_If data “1” is stored in _km , polarization inversion occurs in the ferroelectric layer, the amount of accumulated charge increases, and the common node CN _k
The potential of rises. On the other hand, if the data “0” is stored in the selected memory cell MC _km , polarization inversion does not occur in the ferroelectric layer and the potential of the common node CN _k hardly rises. That is, since the common node CN _k is coupled to the plurality of non-selected plate lines PL _j (j ≠ m) via the ferroelectric layer of the non-selected memory cell, the potential of the common node CN _k is 0 volt. Maintained at a level relatively close to. In this way, the potential of the common node CN _k changes depending on the data stored in the selected memory cell MC _km .

(3) Next, the bit line BL _k is brought into a floating state, and the selection transistor TR _k is turned on. As a result, the potential generated on the common first electrode (common node CN _k ) based on the data stored in the selected memory cell MC _km causes a potential on the bit line BL _k .

(4) Next, the selection transistor TR _k
Is turned off. Then, the potential of the bit line BL _k is latched by the sense amplifier SA _k ,
A _k is activated to amplify the data, and the data read operation is completed. The data is output to the outside.

By the above operation, the selected memory cell MC
_Since the data stored in _km is once destroyed, the data is rewritten.

(5) Therefore, first, the bit line BL _k
Are charged and discharged by the sense amplifier SA _k , and V _cc or 0 volt is applied to the bit line BL _k depending on the data stored in the selected memory cell MC _km .

(6) Then, the potential of the non-selected plate line PL _j is set to (1/2) V _cc . As a result, the unselected memory cells are in a state in which the disturb is added.

(7) After that, the selection transistor TR_k
Is turned on. As a result, the common node CN_kof
The potential is the bit line BL_kIs equal to the potential of. That is, selection
Memory cell MC_kmIf the data stored in is "1"
Common node CN_kPotential is V_ccNext, select
Morisell MC_kmIf the data stored in is "0"
Common node CN_kHas a potential of 0 volt. Choice
Plate line PL_mPotential is V _ccBecause it remains
Communication node CN_kIf the potential of the
Le MC_kmThe data “0” is rewritten in the memory.

(8) Next, the potential of the selected plate line PL _m is set to 0 volt. As a result, the selected memory cell MC
_When the data stored in _km is "1", the data of "1" is rewritten because the potential of the common node CN _k is V _cc . If the data "0" has been re-written already to the selected memory cell MC _km is, there is no change to the selected memory cell MC _km.

(9) After that, the bit line BL _{k is set} to 0 volt.

(10) Finally, the non-selected plate line PL _j
Is set to 0 V, and the selection transistor TR _k is turned off.

The k-th plate line PL _m is commonly used.
Data is also read and _rewritten in the memory cells MC _{k ′ m} in all the non-volatile memories M _{k ′} other than the second one. In this memory cell MC _k'm , no data is sent to the outside, which is a kind of refresh operation. Depending on the case, the read data may be sequentially output to the outside.

In the initial state, data "0" is stored in all the memory cells FC _M in the flag storage semiconductor memory F. The k-th column address and the m-th row address are selected, a pulse is applied to the plate line PL _m , and stored in the m-th memory cell MC _km of the k-th nonvolatile memory M _k . When the read data is read by the sense amplifier SA _k , at the same time, the data stored in the memory cell FC _m in the flag storing semiconductor memory F is read by the sense amplifier FSA. Here, the m-th plate line corresponds to a “certain plate line”. Then, the data read by the sense amplifier FSA is sent to the flag determination circuit FG, and the flag determination is performed. Since the data stored in the memory cell FC _m is “0”, in the flag determination circuit FG, it is determined that the memory cell of the flag storage semiconductor memory forming the flag circuit does not need to be initialized. The data read by the sense amplifier FSA is simultaneously sent to the inverting circuit INV composed of the combinational logic circuit. Since the data input to the inverting circuit INV is "0", the data output from the inverting circuit INV is "1". This data "1" is held in the register RS.

[0082] Then, when data rewriting in the memory cell MC _miles, data "1" held in the register RS, and written into the memory cell FC _m in the semiconductor memory F for flags stored by the sense amplifier FSA. When the m-th row address is selected by the above operation, the data stored in the memory cell FC _m in the flag storing semiconductor memory F related to this row address is changed from the initial state “0” to “1”. And changes.

For example, next, when the m'th (m '≠ m) row address is selected, the data of the memory cell FC _{m'in the} flag storing semiconductor memory F relating to this row address is in the initial state. Changes from "0" to "1". That is, any row address can be randomly accessed.

When the mth row address is selected again (the column address may be any value, the column address is k'in the following description),
At the same time when a pulse is applied to the plate line PL _m and the data stored in the m-th memory cell MC _{k ′} m of the _k′- th nonvolatile memory M _{k ′} is read by the sense amplifier SA _k. , The data stored in the memory cell FC _m in the flag storing semiconductor memory F is also sense amplifier FSA.
Read out. Then, the data read by the sense amplifier FSA is sent to the flag determination circuit FG, and the flag determination is performed. Since the data stored in the memory cell FC _m is “1”, the flag determination circuit FG determines that the memory cell of the flag storage semiconductor memory forming the flag circuit needs to be initialized.

Then, the k'th non-volatile memory M _{k '}
When the _rewriting of the data to the m-th memory cell MC _k'm is completed, all the memory cells in all the non-volatile memories constituting the non-volatile memory array (excluding the m-th memory cell) Refresh operation is performed. Specifically, the above operations (1) to (10) are sequentially performed on all memory cells in the nonvolatile memory array except the m-th memory cell of all nonvolatile memories.

On the other hand, in the flag circuit, the m-th memory cell MC _{k'm of the k'-} th non-volatile memory M _{k '} .
At the time of rewriting the data in the register RS, the data “0” held in the register RS is written in the memory cell FC _m in the flag storing semiconductor memory F by the sense amplifier FSA. Further, when the refresh operation of all the memory cells (excluding the m-th memory cell) in all the non-volatile memories forming the non-volatile memory array is performed, the memory cells F in the flag storing semiconductor memory F are
The initial value data “0” is written in all the memory cells other than C _m via the sense amplifier FSA. As a result, the memory cells of the flag storing semiconductor memory forming the flag circuit are initialized.

When the memory cell of the flag storing semiconductor memory is in the initialized state, the data stored in the memory cell is "1", and when the data of the memory cell is "0", the flag circuit is formed. The memory cells of the flag storing semiconductor memory may be initialized. The same applies to each of the following embodiments.

In the conventional technique, the m-th row
When the address is selected, the memory cells (mth m) in all the nonvolatile memories that constitute the nonvolatile memory array are selected.
(Except the second memory cell) is immediately performed. On the other hand, in the nonvolatile memory array according to the first embodiment, after the m-th row address is selected twice, the memory cells (m-th memory cell) in all the nonvolatile memories forming the nonvolatile memory array are selected. (Excluding cells) is refreshed. That is, in the nonvolatile memory array according to the first embodiment, the refresh operation is performed at the shortest, when the row address is selected twice, at the longest, the row address is selected (M + 1) times. This is the case. Further, the maximum number of disturbs received by the memory cells forming the non-volatile memory is (M-1) times after completion of the last refresh operation and before the start of this refresh operation, and (M-1) during the refresh operation. This is a maximum of 2 (M-1) times.

The method of manufacturing the nonvolatile memory in the nonvolatile memory array of the first embodiment will be described below. The semiconductor memory for flag storage, or the nonvolatile memory and flag storage in another embodiment or a modification thereof. The semiconductor memory can be manufactured by a substantially similar method.

[Step-100] First, a MOS transistor functioning as a selection transistor TR in a nonvolatile memory is formed on the semiconductor substrate 10. Therefore, the element isolation region 11 having, for example, a LOCOS structure is formed by a known method. The element isolation region may have a trench structure or a combination of a LOCOS structure and a trench structure. Then, the surface of the semiconductor substrate 10 is oxidized by, for example, a pyrogenic method,
The gate insulating film 12 is formed. Next, a polysilicon layer doped with impurities is formed on the entire surface by a CVD method, and then the polysilicon layer is patterned to form the gate electrode 1
3 is formed. The gate electrode 13 also serves as a word line. The gate electrode 13 may be made of polycide or metal silicide instead of being made of a polysilicon layer. Next, the semiconductor substrate 10 is ion-implanted to form an LDD structure. After that, a SiO ₂ layer is formed on the entire surface by a CVD method, and then the SiO ₂ layer is etched back to form a gate sidewall (not shown) on the side surface of the gate electrode 13. Next, after ion-implanting the semiconductor substrate 10, activation / annealing treatment of the ion-implanted impurities is performed to form the source / drain regions 14A and 14B.

[Step-110] Next, a lower insulating layer made of SiO _{2 is} formed by a CVD method, and then an opening is formed in the lower insulating layer above one of the source / drain regions 14A by R.
It is formed by the IE method. Then, a polysilicon layer doped with impurities is formed on the lower insulating layer including the inside of the opening by a CVD method. As a result, the connection hole (contact plug) 15 is formed. Next, a bit line is formed by patterning the polysilicon layer on the lower insulating layer. After that, an upper insulating layer made of BPSG is formed on the entire surface by the CVD method. After forming the upper insulating layer made of BPSG, for example, in a nitrogen gas atmosphere,
It is preferable to reflow the upper insulating layer at 0 ° C. for 20 minutes. Further, if necessary, it is desirable to planarize the upper insulating layer by chemically and mechanically polishing the top surface of the upper insulating layer by, for example, a chemical mechanical polishing method (CMP method). The lower insulating layer and the upper insulating layer are collectively referred to as the insulating layer 16
Call.

[Step-120] Next, an opening 17 is formed in the insulating layer 16 above the other source / drain region 14B by R.
After the formation by the IE method, the inside of the opening 17 is filled with impurity-doped polysilicon to complete the connection hole (contact plug) 18. The bit line extends on the lower insulating layer in the left-right direction in FIG. 1 so as not to come into contact with the connection hole 18.

The connection hole 18 is formed in the opening 17 formed in the insulating layer 16 by, for example, tungsten, Ti, P or the like.
t, Pd, Cu, TiW, TiNW, WSi ₂ , MoS
It can also be formed by embedding a metal wiring material made of a refractory metal such as i ₂ or metal silicide. The top surface of the connection hole 18 may exist on the same plane as the surface of the insulating layer 16, or the top portion of the connection hole 18 may extend to the surface of the insulating layer 16. Opening 17 with tungsten
Table 2 below shows the conditions under which the contact holes 18 are embedded and the connection holes 18 are formed.
For example. Before the opening 17 is filled with tungsten, it is preferable that a Ti layer and a TiN layer are sequentially formed on the insulating layer 16 including the inside of the opening 17 by, for example, a magnetron sputtering method. Here, the reason for forming the Ti layer and the TiN layer is to obtain an ohmic low contact resistance, prevent damage to the semiconductor substrate 10 in the blanket tungsten CVD method, and improve the adhesion of tungsten.

[Table 2] Sputtering conditions of Ti layer (thickness: 20 nm) Process gas: Ar = 35 sccm Pressure: 0.52 Pa RF power: 2 kW Substrate heating: None Sputtering conditions of TiN layer (thickness: 100 nm) Process Gas: N ₂ / Ar = 100/35 sccm Pressure: 1.0 Pa RF power: 6 kW Substrate heating: None Tungsten CVD forming conditions Working gas: WF ₆ / H ₂ / Ar = 40/400/2250 sccm Pressure: 10.7 kPa Forming temperature: 450 ° C. Etching conditions for tungsten layer, TiN layer, and Ti layer First-stage etching: Etching tungsten layer Gas used: SF ₆ / Ar / He = 110: 90: 5 sccm Pressure: 46 Pa RF power: 275 W two-step etching: etching gas used in TiN layer / Ti layer: Ar / Cl ₂ 75 / 5sccm pressure: 6.5Pa RF power: 250W

[Step-130] Next, on the insulating layer 16,
It is desirable to form an adhesion layer (not shown) made of titanium oxide. Then, a first electrode material layer that forms the first electrode (lower electrode) 21 made of Ir is formed on the adhesion layer by, for example, a sputtering method, and the first electrode material layer and the adhesion layer are formed by a photolithography technique. And the first electrode 2 by patterning based on the dry etching technique.
1 can be obtained.

[Step-140] Thereafter, for example, MOC
By the VD method, a Bi-based layered structure perovskite-type strong
Dielectric material (specifically, for example, crystallization temperature 750 °
Bi of C₂SrTa₂O ₉) Ferroelectric thin film consisting of
To form. After that, dry in 250 ° C air
After that, heat treatment for 1 hour in an oxygen gas atmosphere at 750 ° C.
After applying heat treatment to promote crystallization, if necessary,
Strong based on lithographic technology and dry etching technology
The dielectric thin film is patterned to obtain the ferroelectric layer 22.
It

[Step-150] Next, IrO _2-X layer, P
After the t layer is sequentially formed on the entire surface by the sputtering method, the Pt layer and the IrO _2-X layer are sequentially patterned based on the photolithography technology and the dry etching technology.
The second electrode 23 is formed. When the ferroelectric layer 22 is damaged by the etching, the heat treatment may be performed at the temperature required to recover the damage.

[Step-160] After that, the insulating film 2 is formed on the entire surface.
6A is formed.

In manufacturing a nonvolatile memory array having a structure in which memory cells are laminated, which will be described later, for example, the following steps are performed: Formation / First electrode 31, Bi ₂ Sr with crystallization temperature 700 ° C
The ferroelectric layer 32 made of (Ta _1.5 Nb _0.5 ) O ₉ , the second electrode 33, and the insulating film 36A may be sequentially formed. In addition, Bi ₂ Sr (Ta _1.5 Nb
_The ferroelectric layer 32 made of _0.5 ) O ₉ may be subjected to a heat treatment for promoting crystallization in an oxygen gas atmosphere at 700 ° C. for 1 hour.

Each second electrode may not also serve as a plate line. In this case, after the formation of the insulating films 26A and 36A is completed, the second electrode 23 and the second electrode 33 are connected by a connection hole (via hole).
A plate wire connected to the connection hole may be formed on 6A.

For example, Table 3 below shows conditions for forming a ferroelectric thin film made of Bi ₂ SrTa ₂ O ₉ . Table 3
In the above, “thd” is an abbreviation for tetramethylheptanedionate. The source materials shown in Table 3 are dissolved in a solvent containing tetrahydrofuran (THF) as a main component.

[Table 3] Formation by MOCVD Source material: Sr (thd) ₂ -tetraglyme Bi (C ₆ H ₅ ) ₃ Ta (O-iC ₃ H ₇ ) ₄ (thd) Formation temperature: 400 to 700 ° C Process gas: Ar / O ₂ = 1000/1000 cm ³ Formation rate: 5 to 20 nm / min

Alternatively, a ferroelectric thin film made of Bi ₂ SrTa ₂ O _{9 is} prepared by pulse laser ablation method, sol-
It can also be formed on the entire surface by a gel method or an RF sputtering method. The formation conditions in these cases are illustrated below. When forming a thick ferroelectric thin film by the sol-gel method, spin coating and drying, or spin coating and baking (or annealing treatment) may be repeated a desired number of times.

[Table 4] Target formed by pulse laser ablation method: Bi ₂ SrTa ₂ O ₉ Laser used: KrF excimer laser (wavelength 248 nm,
Pulse width 25 nsec, 5 Hz) Forming temperature: 400 to 800 ° C Oxygen concentration: 3 Pa

[0105] [Table 5] sol - gel method by forming _{ingredients: Bi (CH 3 (CH 2} ) 3 CH (C 2 H 5) COO) 3 [ bismuth _{2-ethylhexanoate, Bi (OOc) 3] Sr} ( CH ₃ (CH ₂ ) ₃ CH (C ₂ H ₅ ) COO) ₂ [strontium diethylhexanoate, Sr (OO
c) ₂ ] Ta (OEt) ₅ [tantalum ethoxide] Spin coating conditions: 3000 rpm x 20 seconds Drying: 250 ° C x 7 minutes Firing: 700 to 800 ° C x 1 hour (RT if necessary
A processing is added)

[Table 6] Target formed by RF sputtering method: Bi ₂ SrTa ₂ O ₉ ceramic target RF power: 1.2 W to 2.0 W / target 1 cm ² Atmospheric pressure: 0.2 to 1.3 Pa Formation temperature: Room temperature ˜600 ° C. Process gas: Ar / O ₂ flow rate ratio = 2/1 to 9/1

When the ferroelectric layer is made of PZT or PLZT, PZ by magnetron sputtering method
The conditions for forming T or PLZT are shown in Table 7 below. Alternatively, PZT or PLZT may be formed by reactive sputtering, electron beam evaporation, sol-gel method, or MOCVD.
It can also be formed by a method.

[Table 7] Target: PZT or PLZT Process gas: Ar / O ₂ = 90% by volume / 10% by volume Pressure: 4 Pa Power: 50 W Formation temperature: 500 ° C

Further, PZT or PLZT can be formed by the pulse laser ablation method. The forming conditions in this case are illustrated in Table 8 below.

[Table 8] Target: PZT or PLZT Laser used: KrF excimer laser (wavelength 248 nm,
Pulse width 25 nsec, 3 Hz) Output energy: 400 mJ (1.1 J / cm ² ) Formation temperature: 550 to 600 ° C Oxygen concentration: 40 to 120 Pa

(Embodiment 2) Embodiment 2 is a modification of Embodiment 1. In the first embodiment, one flag storage semiconductor memory (= L) is used. On the other hand, in the second embodiment, two flag storing semiconductor memories (= L) are used to configure a flag circuit of 2 ^L-1 bits = 2 bits. The predetermined number of times is 2 ^L times = 4 times. FIG. 7 shows a conceptual circuit diagram of the nonvolatile memory array of the second embodiment, and FIG. 8 shows a more specific circuit diagram of the flag circuit.
The structures of the nonvolatile memory and the flag storage semiconductor memory are substantially the same as the structures of the nonvolatile memory and the flag storage semiconductor memory according to the first embodiment described with reference to FIGS. 1 and 2. Therefore, detailed description will be omitted.

[0112] Memorise in the initial state, the semiconductor memory F _A flag stored in the F _B (Le FC _AM, FC _BM)
Data “0” is stored in each of the. still,
Such a state is expressed as storing data (0,0).

Then, the kth column address and the mth row address are selected, and the plate line PL
pulse is applied to _m, when the data from the m-th memory cell MC _miles of the k-th non-volatile memory M _k is read out to the sense amplifier SA _k, at the same time, the semiconductor memory F _A flag storing, F _The data stored in the memory cells FC _Am and FC _Bm in _B are also read by the sense amplifiers FSA _A and FSA _B. Here, the m-th plate line corresponds to a “certain plate line”. And the sense amplifier FS
The data read to A _A and FSA _B are sent to the flag determination circuit FG and flag determination is performed. Memory cell (F
Since the data stored in C _Am , FC _Bm ) is (0, 0), in the flag determination circuit FG, it is determined that the initialization of the memory cell of the flag storage semiconductor memory forming the flag circuit is unnecessary. It Sense amplifier FSA _A , FSA _B
At the same time, the data read out is sent to the increment circuit INC, where the data is incremented by 1,
It becomes (0, 1). This data (0, 1) is stored in the register R
Hold at S.

[0114] Then, when data rewriting in the memory cell MC _miles, data held in the register RS (0, 1) is a semiconductor memory for storing a flag F _A, the memory cells in _{F B (FC Am, FC Bm} ) Written in. When the m-th row address is selected by the above operation, the memory cells (FC _Am , FC) in the flag storing semiconductor memories F _A , F _B relating to this row address
_The data stored in _Bm ) changes from the initial state (0,0) to (0,1).

For example, next, when the m'th (m '≠ m) row address is selected, the memory cell FC _Am' in the flag storing semiconductor memories F _A , F _B relating to this row address is selected. FC _{Bm '} changes from the initial state. That is, any row address can be randomly accessed.

If the m-th row address is selected again (the column address may be any value, it is the second row address selection at the m-th row address), the data (1,0) is a memory cell (FC) in the flag storing semiconductor memories F _A and F _B.
Am , FC _Bm ). If the m-th row address is further selected again (the column address may have any value and is the third row address selection in the m-th row address), the data (1 , 1) are written in the memory cells (FC _Am , FC _Bm ) in the flag storing semiconductor memories F _A , F _B. When the m-th row address is further selected again (the column address may be any value and is the fourth row address selection at the m-th row address), that is, When the mth row address is selected 2 ^L times (specifically 4 times), the memory cell (FC
_Since the data stored in ( _Am , FC _Bm ) is (1, 1), in the flag determination circuit FG, it is determined that the memory cells of the flag storage semiconductor memory forming the flag circuit need to be initialized. . The data (1,1) is sent to the increment circuit INC, and the data is incremented by 1 to become (0,0). This data (0,0)
Are held in the register RS.

Then, when the rewriting of data to the memory cells in the non-volatile memory in which the column address is selected is completed, all the memory cells in all the non-volatile memories constituting the non-volatile memory array (m-th (Except the second memory cell) is performed. Specifically, the operations (1) to (10) of the first embodiment are sequentially performed on all the memory cells except the mth memory cell.

On the other hand, in the flag circuit, the fourth row address selection at the m-th row address is performed, and the data is held in the register RS when data is rewritten to the memory cells forming the nonvolatile memory. The existing data (0, 0) is written in the memory cells (FC _Am , FC _Bm ) in the flag storing semiconductor memories F _A , F _B by the sense amplifiers FSA _A , FSA _B. In addition, when the refresh operation of all the memory cells (excluding the m-th memory cell) in all the nonvolatile memories configuring the nonvolatile memory array is performed, the memory cells in the flag storing semiconductor memories F _A and F _B are Data (0, 0) which is the initial value in all memory cells except (FC _Am , FC _Bm )
Are written via the sense amplifiers FSA _A and FSA _B. As a result, the memory cells of the flag storing semiconductor memory forming the flag circuit are initialized.

In the nonvolatile memory array according to the second embodiment, the refresh operation is performed at the shortest, and when the row address is selected four times (= 2 ^L times), the longest address is the row address. (3M + 1) times, in general,
This is the case where the selection is performed {(2 ^L −1) M + 1} times. In addition, the maximum number of disturbances received by the memory cells forming the non-volatile memory is 3 (M−M) from the completion of the previous refresh operation to the start of this refresh operation.
1) times, generally (2 ^L -1) (M-1) times, and (M-1) times during the refresh operation, a maximum of 4 in total.
(M-1) times, typically 2 ^L (M-1) times.

The flag determination may be performed after the increment, or may be decremented instead of the increment. Further, the flag circuit is not limited to the 2-bit configuration, and may have a 3-bit configuration or more. The same applies to the following embodiments. Further, in the memory cell of the flag storing semiconductor memory, arbitrary data can be stored in the initial state. When the data is incremented or decremented and the arbitrary data is returned, the memory cells of the flag storing semiconductor memory forming the flag circuit may be initialized.
The same applies to each of the following embodiments.

(Third Embodiment) The third embodiment is also a modification of the first embodiment. In the third embodiment, organic memory cell MC _kM constituting the nonvolatile memory M _k having the same structure as the nonvolatile memory M _k explained in the first embodiment, and the same structure as the nonvolatile memory M _k Bit line B
Memory cells MC _kM ′ forming a non-volatile memory M _k ′ sharing L are stacked via an insulating layer (for convenience, referred to as an interlayer insulating layer 26). The nonvolatile memory M _k
And belongs to a non-volatile memory array different from the non-volatile memory M _k ′. FIG. 9 shows a schematic partial cross-sectional view when two non-volatile memories according to a virtual vertical plane parallel to the extending direction of the bit line are cut, and FIG. 10 shows a conceptual circuit diagram of the non-volatile memory. FIG. 11 shows a more specific circuit diagram of the circuit diagram of the conceptual nonvolatile memory shown in FIG.

[0122] 'a memory cell MC _kM constituting the' non-volatile memory M _k positioned above the memory cells MC _kM constituting the nonvolatile memory M _k is formed on the insulating layer (interlayer insulating layer 26), the The first electrode 31 includes a first electrode 31, a ferroelectric layer 32, and a second electrode 33. The first electrode 31 is a connection hole 2 formed in an opening 27 provided in the interlayer insulating layer 26.
8, pad portion 25 formed on insulating layer 16, insulating layer 1
6 is connected to the other source / drain region 14B of the selecting transistor TR _k ′ through the connection hole 18 formed in the opening 17 provided in No. 6. Also. The memory cell MC _kM 'is covered with the insulating film 36A. Except for these points, the structure of the non-volatile memory M _k 'has the same structure as the non-volatile memory M described in the first embodiment, and detailed description thereof will be omitted.

Similar to the nonvolatile memories M and M ′, the flag circuit is the same as the nonvolatile memory M and M ′ except that the memory cells FC _M and FC _M ′ forming the flag storing semiconductor memories F and F ′ are stacked. Since it can be the same as the flag circuit of No. 1, detailed description will be omitted. Incidentally, as in the second embodiment, the flag circuit can be a flag circuit having 2 bits or more bits.

(Embodiment 4) Embodiment 4 relates to a nonvolatile memory array according to the second aspect of the present invention and a driving method thereof. FIG. 12 is a schematic partial cross-sectional view of the nonvolatile memory that constitutes the nonvolatile memory array of the fourth embodiment, taken along a virtual vertical plane parallel to the direction in which the bit lines extend. FIG. 13 shows a schematic partial cross-sectional view when the is cut. Furthermore, FIG. 1 is a conceptual circuit diagram of the nonvolatile memory array according to the fourth embodiment.
4 and FIG. 15 shows a more specific non-volatile memory circuit diagram of the conceptual circuit diagram of FIG. 14, and FIG. 16 shows a more specific circuit diagram of the flag circuit.

The nonvolatile memory array according to the fourth embodiment is
A plurality of (for example, K = 2 ⁷ ) non-volatile memories and at least one (1 in the fourth embodiment, L =
The flag circuit ( ^2L-1 bit = 1 bit flag circuit) including the flag storing semiconductor memory of 1).

Further, in the fourth embodiment, a pair of nonvolatile memories M ₁ and M ₂ and a pair of flag storing semiconductor memories F ₁ and F ₂ are formed, and a pair of plate lines are commonly used. 1 bit is complementarily stored in the memory cell.
The number of flag storage semiconductor memories is a pair (2L = 2) with respect to a pair of nonvolatile memories M ₁ and M ₂ . In the fourth embodiment, N = 2 and M = 8. Further, the predetermined number of times is 2 ¹ = 2 times.

Hereinafter, the kth nonvolatile memory array will be described.
The second (k is one of 1, 2, 3, ..., K)
I will explain about the memory, but in the following explanation,
Is the number selected by the kth column address
The subscript “k” indicating the kth nonvolatile memory is omitted.
14 to 16 show a pair of non-volatile memories.
M ₁, M₂, A pair of flag storing semiconductor memories F₁, F₂To
As shown, these nonvolatile memories M₁, M₂,flag
Storage semiconductor memory F₁, F₂Have the same structure,
In the non-volatile memory M₁, Flag storage semiconductor
Memory F₁Will be explained.

The nonvolatile memory M ₁ of the fourth embodiment is
(A) Bit line BL ₁ and (B) selection transistor T
R ₁ and (C) are each M (provided that M ≧ 2,
In the fourth embodiment, N (where N ≧ 2 in the fourth embodiment, N = 2) memory units MU _N configured of M = 8 memory cells and (D )
It consists of M × N plate lines.

Further, in the flag storing semiconductor memory F ₁ of the fourth embodiment, (A) bit line FBL ₁ , (B) selecting transistor FTR ₁ and (C) are each M (where M ≧ 2 and M = 8 in the fourth embodiment)
Memory cells FU _1N (where N ≧ 2 and N = 2 in the fourth embodiment) composed of memory cells of (4) and (D) M × N plate lines. .

The nonvolatile memory M₁In
N memory units MU_1NIs an insulating layer (interlayer insulating layer 2
6) is stacked through each memory cell, and each memory cell is
Electrodes 21, 31 and ferroelectric layers 22, 32 and second electrode 2
3, 33, and each memory unit MU_1nsmell
Memory cell MC_1nMThe first electrode of the
The common first electrode is the selection transistor TR.₁Through
Bit line BL₁It is connected to the. Specifically, a memo
Reunit MU₁₁In the memory cell MC_11MFirst of
Electrode 21 is common (this common first electrode is
Common node CN₁₁Common first electrode 21
(First common node CN₁₁) Is a selection transistor T
R₁Via the bit line BL₁It is connected to the. In addition,
Mori unit MU₁₂In the memory cell MC_12MThe first
The first electrode 31 is common (this common first electrode is
2 common nodes CN₁₂Common) first electrode 31
(Second common node CN₁₂) Is a selection transistor T
R₁Via the bit line BL₁It is connected to the. Furthermore,
Memory unit of the nth layer (however, n = 1, 2, ..., N)
MU_1n, The m-th (however, m = 1, 2 ...
., M) memory cell MC _{1 nm}Second electrodes 23, 33 of
Is the [(n-1) M + m] th plate line PL_{(
n-1) M + m}It is connected to the. In addition, this plate line PL
_{(n-1) M + m}Is a non-volatile memory M₂Each memory cell that composes
Is also connected to the second electrodes 23, 33 of the battery.

Selection transistor TR₁One source
/ Drain region 14A is connected to bit line B through connection hole 15.
L₁Connected to the selection transistor TR₁The other saw
The source / drain region 14B is connected to the insulating layer 16.
The first layer memory unit MU is passed through the continuous hole 18.₁₁To
Common first electrode 21 (first common node C
N ₁₁)It is connected to the. Furthermore, the selection transistor
TR₁The other source / drain region 14B is an insulating layer.
16 to the connection hole 18 and the interlayer insulating layer 26.
The second layer memory unit is connected through the connection hole 28 provided.
MU₁₂Common first electrode 31 (second common
Node CN₁₂)It is connected to the. In the figure, reference numbers
36A is an insulating film.

The bit line BL ₁ is connected to the sense amplifier SA. The plate line PL _{(n-1) M + m} is connected to the plate line decoder / driver PD. Further, the word line WL is a word line decoder / driver WD.
It is connected to the. The word line WL extends in the direction perpendicular to the paper surface of FIG. Further, the second electrode 23 of the memory cell MC _11m forming the non-volatile memory M ₁ is common to the second electrode of the memory cell MC _21m forming the non-volatile memory M ₂ adjacent in the direction perpendicular to the paper surface of FIG. And also serves as the plate line PL _{(n-1) M + m} . Furthermore, the second electrode 33 of the memory cell MC _12m forming the nonvolatile memory M ₁ is
It is common with the second electrode of the memory cell MC _22m forming the non-volatile memory M ₂ adjacent in the direction perpendicular to the paper surface of FIG. 12, and also serves as the plate line PL _{(n-1) M + m} . The word line WL is common for selection transistors TR ₁ constituting the nonvolatile memory M _1, a selection transistor TR ₂ constituting the nonvolatile memory M ₂ adjacent in the direction perpendicular to the paper surface in FIG. 12.

Further, the flag storing semiconductor memory F₁To
In addition, N memory units FU_{1 N}Is an insulating layer (interlayer
Each memory cell is stacked via an insulating layer 26).
Is the first electrode 21, 31, the ferroelectric layer 22, 32, and
Each of the memory units FU is composed of two electrodes 23 and 33.
_1nIn memory cell FC_1nMThe first electrode of is common
And the common first electrode is a selection transistor FT
R₁Through the bit line FBL₁It is connected to the. concrete
The memory unit FU₁₁In memory cell FC
_11MThe first electrode 21 of the
The electrode is the first common node FCN₁₁Called), the first common
Electrode 21 (first common node FCN₁₁) Is for selection
Langista FTR₁Through the bit line FBL₁Connected to
ing. In addition, the memory unit FU₁₂At the memory
Cell FC_12MThe first electrode 31 of the
The first electrode of the second common node FCN₁₂Called)
Common first electrode 31 (second common node FCN₁₂) Is
Selection transistor FTR ₁Through the bit line FBL₁To
It is connected. Furthermore, the nth layer (however, n = 1, 2
..., N) memory unit FU_1nAt the number m
Memory cell FC of the eye (however, m = 1, 2, ..., M)
_{1 nm}Second electrodes 23 and 33 of the second electrode of [(n-1) M +
m] th plate line PL_{(n-1) M + m}It is connected to the.

Select transistor FTR₁One saw
The drain / series region 14A is connected to the bit line through the connection hole 15.
FBL₁Connected to the selection transistor FTR₁The other of
The source / drain region 14B of the
Through the connection hole 18 formed in the memory layer F of the first layer.
C₁₁Common first electrode 21 (first common node
FCN₁₁)It is connected to the. Furthermore, the transition for selection
Star FTR₁The other source / drain region 14B of
Connection hole 18 provided in insulating layer 16 and interlayer insulating layer
Through the connection hole 28 provided in 26, the memo of the second layer
Reunit FU ₁₂Common first electrode 31 (second
Common node FCN₁₂)It is connected to the.

In the flag storing semiconductor memory F ₁ ,
The bit line FBL ₁ is connected to the sense amplifier FSA. The plate line PL _{(n-1) M + m} is connected to the plate line decoder / driver PD. The second electrode 23 of the memory cell FC _11m that constitutes the flag storage semiconductor memory F ₁ is the second electrode of the memory cell FC _21m that constitutes the flag storage semiconductor memory F ₂ that is adjacent in the direction perpendicular to the paper surface of FIG.
, And also serves as the plate line PL _{(n-1) M + m} . Further, the second electrode 33 of the memory cell MC _12m forming the flag storing semiconductor memory F ₁ is the second electrode 33 of the memory cell FC _22m forming the flag storing semiconductor memory F ₂ adjacent in the direction perpendicular to the paper surface of FIG. It is common to the second electrode and also serves as the plate line PL _{(n-1) M + m} . Moreover, the plate line PL _{(n-1) M + m} is connected to the nonvolatile memories M ₁ and M ₂
Is also connected to the second electrodes 23 and 33 of each memory cell constituting the. In the fourth embodiment, more specifically, each plate line extends from the second electrodes 23 and 33. In addition, the word line WL includes a selection transistor FTR ₁ included in the flag storage semiconductor memory F ₁ , and
3 is also common to the selection transistor FTR ₂ forming the flag storage semiconductor memory F ₂ adjacent in the direction perpendicular to the paper surface.

In the nonvolatile memory arrays whose circuit diagrams are shown in FIGS. 14 to 16, in the nonvolatile memories M ₁ and M ₂ and the flag storing semiconductor memories F ₁ and F ₂ , the nonvolatile memories M ₁ and M ₂ and selection transistor TR ₁ constituting the semiconductor memory F _1, F ₂ flag storing, TR _2, FTR _1,
FTR ₂ is connected to the same word line WL. Then, the paired memory cells MC _1nm and MC _2nm (n = 1,
2 ..., N, and m = 1, 2 ..., M) and 1-bit data complementary to the memory cells FC _1nm and FC _2nm are stored.

A method of reading data from the nonvolatile memory according to the fourth embodiment and rewriting the data will be described below. As an example, data is read from the paired memory cells MC ₁₁₁ and MC ₂₁₁ , and the data “1” is stored in the memory cell MC _111.
It is assumed that the data “0” is stored in ₂₁₁ . FIG. 17
Shows the operation waveform. In addition, in FIG. 17, the numbers in parentheses correspond to the numbers of the steps described below.

(1) In the standby state, all bit lines, word lines and all plate lines are at 0 volt. Furthermore, all common nodes are also floating at 0 volts.

(2) When reading data, the selected plate line P
Applying a V _cc to L _1. At this time, the selected memory cell MC
_Since the data “1” is stored in ₁₁₁ , polarization inversion occurs in the ferroelectric layer, the amount of accumulated charge increases, and the common node C
The potential of N ₁₁ rises. On the other hand, the selected memory cell MC ₂₁₁
Since the data "0" is stored in, the polarization inversion does not occur in the ferroelectric layer, and the potential of the common node CN ₂₁ hardly rises. That is, the common node CN ₂₁ has a plurality of non-selected plate lines PL via the ferroelectric layers of the non-selected memory cells.
Since it is coupled to _j (j ≠ 1), the potential of the common node CN ₂₁ is maintained at a level relatively close to 0 volt. In this way, the selected memory cells MC ₁₁₁ , MC ₂₁₁
Common nodes CN ₁₁ , CN depending on the data stored in
The potential of ₂₁ changes.

(3) Next, the bit lines BL ₁ and BL ₂ are brought into a floating state, and the selection transistors TR ₁ and TR ₂ are turned on. As a result, the selected memory cells MC ₁₁₁ , MC
_The potential generated on the common first electrodes (common nodes CN ₁₁ and CN ₂₁ ) based on the data stored in ₂₁₁ causes potentials on the bit lines BL ₁ and BL ₂ .

(4) Next, the selection transistor T
R ₁ and TR ₂ are turned off. Then, the potentials of the bit lines BL ₁ and BL ₂ are latched by the sense amplifier SA,
The sense amplifier SA is activated to amplify the data, and the data read operation is completed. This 1-bit data is output to the outside.

By the above operation, the selected memory cell MC
_Since the data stored in ₁₁₁ and MC ₂₁₁ are once destroyed, the data rewriting operation is performed.

(5) Therefore, first, the bit line B
L ₁ and BL ₂ are charged and discharged by the sense amplifier SA, and V _cc is applied to the bit line BL ₁ depending on the data stored in each memory cell MC ₁₁₁ and MC ₂₁₁ , and the bit line B 1
Apply 0 volts to L ₂ .

(6) Then, the potential of the non-selected plate line PL _j is set to (1/2) V _cc . As a result, the unselected memory cells are in a state in which the disturb is added.

(7) After that, the selection transistor T
The R _1, TR ₂ is turned on. As a result, the potentials of the common nodes CN ₁₁ and CN ₂₁ become equal to the potentials of the bit lines BL ₁ and BL ₂ . That is, since the data stored in the selected memory cell MC ₁₁₁ is “1”, the common node CN
The potential of ₁₁ becomes V _cc , and since the data stored in the selected memory cell MC ₂₁₁ is “0”, the common node C
The potential of N ₂₁ becomes 0 volt. Since the potential of the selected plate line PL ₁ remains V _cc , the potential of the common node CN ₂₁ is 0 volt, and the data “0” is rewritten in the selected memory cell MC ₂₁₁ .

(8) Next, the potential of the selected plate line PL ₁ is set to 0 volt. As a result, the selected memory cell MC
₁₁₁ data stored in the is "1", the potential of the common node CN _{1 1} is V _cc thus, data "1" is rewritten. Since data "0" into the selected memory cell MC ₂₁₁ has already been rewritten, there is no change to the selected memory cell MC _211.

(9) After that, the bit lines BL ₁ and BL ₂ are set to 0.
Let it be a bolt.

(10) Finally, the non-selected plate line PL _j
Is set to 0 volt, and the selection transistors TR ₁ and TR ₂ are turned off.

A pair of flag storing semiconductor memories F₁, F₂
Even in, 1 bit is stored complementarily, and in the initial state
Stores data "0". The kth column
Address and the first row address are selected and
Rate line PL₁Pulsed to the non-volatile memory
M₁, M₂First memory cell MC of₁₁₁, MC₂₁₁In
When the stored data is read by the sense amplifier SA
At the same time, the flag storing semiconductor memory F₁, F₂Oke
Memory cell FC₁₁, FC_{twenty one}Data stored in
It is read out by the amplifier FSA. Where the m-th
The rate line corresponds to "a certain plate line". And,
The data read by the sense amplifier FSA is flag-determined.
It is sent to the circuit FG, and a flag judgment is made. Memory cell
FC₁₁, FC _{twenty one}Because the data stored in is "0"
In addition, in the flag determination circuit FG, a flag circuit is configured.
The initialization of the memory cell of the flag storage semiconductor memory
Judged as unnecessary. Read to the sense amplifier FSA
The data is simultaneously inverted by the combinational logic circuit.
Sent to the circuit INV. The data input to the inverting circuit INV
Since the data is "0", it is output from the inverting circuit INV.
The data to be output is “1”. This data "1" is Regis
Held by the RS.

When data is rewritten in the memory cells MC ₁₁₁ and MC ₂₁₁ , the data “1” held in the register RS is stored in the memory cells FC ₁₁ and FC ₂₁ in the flag storing semiconductor memories F ₁ and F ₂ . Written. When the first row address is selected by the above operation, the data stored in the memory cells FC ₁₁ and FC ₂₁ in the flag storing semiconductor memories F ₁ and F ₂ related to this row address are in the initial state. It changes from "0" to "1".

For example, next, when the m'th (m '≠ m) row address is selected, the memory cells FC _1m' in the flag storing semiconductor memories F ₁ and F ₂ related to this row address are selected. FC _{2m '} changes from the initial state. That is, any row address can be randomly accessed.

When the first row address is selected again (the column address may have any value), the plate line PL ₁ is pulsed and the non-volatile memories M ₁ and M ₂ are read. First memory cell MC ₁₁₁ , MC
_When the data stored in ₂₁₁ is read by the sense amplifier SA, at the same time, the flag storing semiconductor memories F ₁ and F _{2 are} stored.
The data stored in the memory cells FC ₁₁ and FC ₂₁ in the above are also read by the sense amplifier FSA. Then, the data read by the sense amplifier FSA is sent to the flag determination circuit FG, and the flag determination is performed. Memory cell FC
₁₁ , because the data stored in FC ₂₁ is "1",
In the flag determination circuit FG, it is determined that the memory cells of the flag storage semiconductor memory forming the flag circuit need to be initialized. The data read by the sense amplifier FSA is simultaneously sent to the inverting circuit INV composed of the combinational logic circuit. Since the data input to the inverting circuit INV is "1", the data output from the inverting circuit INV is "0". This data “0” is registered in the register R
Hold at S.

Then, at the time when the rewriting of data to the first memory cells MC ₁₁₁ , MC _{211 of} the nonvolatile memories M ₁ , M ₂ is completed, in all the nonvolatile memories constituting the nonvolatile memory array. The refresh operation of all memory cells (except the first memory cell) is performed. Specifically, the above operations (1) to (10) are sequentially performed on all the memory cells except the first memory cell.

On the other hand, in the flag circuit, the second row address selection in the first row address is performed, and the memory cells MC of the nonvolatile memories M ₁ and M ₂ are selected.
_When data is rewritten to ₁₁₁ and MC ₂₁₁ , the data “0” held in the register RS is written to the memory cells FC ₁₁ and FC ₂₁ in the flag storing semiconductor memories F ₁ and F ₂ by the sense amplifier FSA. . In addition, when the refresh operation of all the memory cells (excluding the first memory cell) in all the nonvolatile memories forming the nonvolatile memory array is performed, the memory cells in the flag storing semiconductor memories F ₁ and F ₂ are FC _11, the data "0" is an initial value to all the memory cells other than FC ₂₁ is written via the sense amplifier FSA. As a result, the memory cells of the flag storing semiconductor memory forming the flag circuit are initialized.

In the nonvolatile memory array according to the fourth embodiment, the refresh operation is performed at the shortest, and when the row address is selected twice, at the longest, the row address is selected (MN + 1) times. That is the case. Also,
The maximum number of disturbs received by the memory cells constituting the nonvolatile memory is the maximum (MN-1) from the completion of the previous refresh operation to the start of the current refresh operation.
The number of refresh operations is (MN-1) times, which is a maximum of 2 (MN-1) times in total.

Also in the nonvolatile memory array of the fourth embodiment, as in the nonvolatile memory array of the second embodiment, a pair of flag storage semiconductor memories can be set in L groups, substantially as in the nonvolatile memory array of the second embodiment. In this case, the refresh operation is performed at the shortest, when the row address is selected 2 ^L times, and at the longest, {(2 ^L −1) MN + 1} times. In addition, the maximum number of disturbs received by the memory cells forming the nonvolatile memory is (2 ^L −1) (MN−1) times after the completion of the last refresh operation and before the start of the current refresh operation during the refresh operation. (MN-1) times, which is a maximum of 2 ^L (MN-1) times.

A pair of non-volatile memories in a pair
Selection transistor TR₁And TR₂Is the word line WL,
And a pair of bit lines BL₁, BL₂Surrounded by
Occupied area. Therefore, if the word line and bit
If the wires are placed at the shortest pitch, the
A pair of selection transistors TR in a volatile memory ₁
And TR₂Area is 8F²Is. However,
A pair of selection transistors TR₁, TR₂With M pairs
Memory cell MC_11m, MC_12m, MC_21m, MC_22m
1 bit because it is shared by (m = 1, 2, ..., M)
Per-selection transistor TR₁, TR₂The number of
In addition, since the arrangement of the word lines WL is loose,
It is easy to reduce the size of the volatile memory. Moreover, in the peripheral circuit
Even with one word line decoder / driver WD and M
Select M bit with book plate line decoder / driver PD
You can choose. Therefore, such a configuration is adopted.
As a result, the cell area is 8F²Realize a layout close to
It is possible to realize a chip size comparable to DRAM.
it can. The same applies to each of the following embodiments.

(Fifth Embodiment) The fifth embodiment is a modification of the fourth embodiment. In the fifth embodiment, a pair of non-volatile memories M ₁ and M ₂ and flag storing semiconductor memories F ₁ and F ₂ are formed, and 1 bit is provided to each of a pair of memory cells having a common plate line. Memorize Further, the number of flag storing semiconductor memories is one pair (2L) with respect to the pair of nonvolatile memories M ₁ and M ₂ . The value of L is specifically 1.

A conceptual circuit diagram of the non-volatile memory array of the fifth embodiment is shown in FIG. 18, and a more specific non-volatile memory circuit diagram of the conceptual circuit diagram of FIG. 18 is shown in FIG. A more specific circuit diagram of the circuit is shown in FIG.
In the nonvolatile memory array according to the fifth embodiment whose circuit diagrams are shown in FIGS. 18 to 20, a selecting transistor TR ₁ forming a nonvolatile memory M ₁ and a selecting transistor forming a flag storing semiconductor memory F ₁ are formed. The transistor FTR ₁ is
The selection transistor TR ₂ that is connected to the word line WL ₁ and that forms the nonvolatile memory M ₂ and the selection transistor FTR ₂ that forms the flag storage semiconductor memory F ₂ are
It is connected to the word line WL ₂ . Word lines WL ₁ , WL
₂ is connected to the word line decoder / driver WD. Then, the memory cells MC _1nm , FC _1nm and the memory cells MC _2nm , FC _2nm are independently controlled to form a pair of bit lines BL ₁ , BL ₂ and a pair of bit lines FBL ₁ , F.
By applying the reference voltage to one of the BL ₂ memory cells MC _1nm , MC _2nm , memory cells FC _1nm , FC _2nm
1-bit data is read from each. Except for this point, the configuration and structure of the non-volatile memory array can be the same as the configuration and structure of the non-volatile memory array according to the fourth embodiment, and detailed description thereof will be omitted.

A method of reading data from the nonvolatile memory according to the fifth embodiment and rewriting the data will be described below. As an example, it is assumed that data is read from the memory cell MC ₁₁₁ in the paired memory cells MC ₁₁₁ and MC ₂₁₁ . In the following description, the kth column address will be selected. Here, the first plate line corresponds to “a certain plate line”.

(1) In the standby state, all bit lines, word lines and all plate lines are at 0 volt. Furthermore, all common nodes are also floating at 0 volts.

(2) When reading data, the selected plate line P
L₁To V_ccIs applied. At this time, the selected memory cell MC
₁₁₁If the data “1” is stored in, the ferroelectric layer
Polarization inversion occurs, the accumulated charge amount increases, and the common node CN
₁₁The potential of rises. On the other hand, the selected memory cell MC₁₁₁To
If the data “0” is stored, the polarization reversal will occur in the ferroelectric layer.
No rolling occurs, common node CN₁₁Almost no increase in potential
Yes. That is, the common node CN ₁₁Is the strength of unselected memory cells
Plural non-selected plate lines PL via the dielectric layer_j(J ≠
Since it is coupled to 1), the common node CN₁₁
Potential is maintained at a level relatively close to 0 volts. this
In this way, the selected memory cell MC₁₁₁Memorized day
Common node CN depending on₁₁A change occurs in the potential of.

(3) Next, the bit line BL ₁ is brought into a floating state, and the bit line BL ₂ is supplied with a reference potential intermediate between the read potential of the data “1” and the read potential of the data “0”. Then, the selection transistor TR ₁ is turned on. As a result, the common first electrode (common node CN) based on the data stored in the selected memory cell MC _111.
The potential generated in ₁₁ ) causes a potential in the bit line BL ₁ .

(4) Next, the selection transistor TR ₁
Is turned off. Then, the potential of the bit line BL ₁ is latched by the sense amplifier SA,
_The data read operation is completed by activating ₁ to amplify the data. The data is output to the outside. This 1-bit data is output to the outside.

By the above operation, the selected memory cell MC
_Since the data stored in ₁₁₁ is once destroyed, the data rewriting operation is performed.

(5) Therefore, first, the bit line BL ₁
Are charged and discharged by the sense amplifier SA, and V _cc or 0 volt is applied to the bit line BL ₁ depending on the data stored in the selected memory cell MC ₁₁₁ .

(6) Then, the potential of the non-selected plate line PL _j is set to (1/2) V _cc . As a result, the unselected memory cells are in a state in which the disturb is added.

(7) After that, the selection transistor TR ₁
Is turned on. As a result, the potential of the common node CN ₁₁ becomes equal to the potential of the bit line BL ₁ . That is, when the data stored in the selected memory cell MC ₁₁₁ is “1”, the potential of the common node CN ₁₁ becomes V _cc , and the data stored in the selected memory cell MC ₁₁₁ is “0”. Therefore, the potential of the common node CN ₁₁ becomes 0 volt.
Since the potential of the selected plate line PL ₁ remains V _cc , when the potential of the common node CN ₁₁ is 0 V, the data “0” is rewritten in the selected memory cell MC ₁₁₁ .

(8) Next, the potential of the selected plate line PL ₁ is set to 0 volt. As a result, the selected memory cell MC
_When the data stored in ₁₁₁ is "1", the data of "1" is stored because the potential of the common node CN ₁₁ is V _cc.
Will be rewritten. If the data "0" into the selected memory cell MC ₁₁₁ had been rewritten already, no change in the selected memory cell MC _111.

(9) After that, the bit line BL _{1 is set} to 0 volt.

(10) Finally, the non-selected plate line PL _j
Is set to 0 V, and the selection transistor TR ₁ is turned off.

A pair of flag storing semiconductor memories F ₁ and F ₂
Also in the above, 1 bit is stored in each of the memory cells FC _1m and FC _2m , and data “0” is stored in the initial state. The kth column address and the first row address are selected, a pulse is applied to the plate line PL ₁ , and data is sensed from the first memory cell MC ₁₁₁ of the nonvolatile memory M ₁ by the sense amplifier SA.
At the same time, the data stored in the memory cell FC ₁₁ in the flag storing semiconductor memory F ₁ is also read by the sense amplifier FSA. Here, the first plate line corresponds to “a certain plate line”. At this time, the bit line FBL ₂ is supplied with a reference potential intermediate between the read potential of the data “1” and the read potential of the data “0”. Then, the data read by the sense amplifier FSA is sent to the flag determination circuit FG, and the flag determination is performed. Since the data stored in the memory cell FC ₁₁ is “0”, in the flag determination circuit FG,
It is determined that the initialization of the memory cell of the flag storage semiconductor memory forming the flag circuit is unnecessary. Sense amplifier FS
The data read by A is simultaneously sent to the inverting circuit INV composed of a combinational logic circuit. Inversion circuit IN
Since the data input to V is "0", the data output from the inverting circuit INV is "1". This data "1" is held in the register RS.

Then, at the time of rewriting data in the memory cell MC ₁₁₁ , the data “1” held in the register RS is written in the memory cell FC ₁₁ in the flag storing semiconductor memory F ₁ . If the first row address is selected by the above operation, this row
The data stored in the memory cell FC ₁₁ in the flag storage semiconductor memory F ₁ regarding the address changes from “0” in the initial state to “1”.

For example, next, when the m'th (m '≠ 1) row address is selected, the memory cell FC _1m' in the flag storing semiconductor memory F ₁ or F ₂ related to this row address, FC _{2m '} changes from the initial state. That is, any row address can be randomly accessed.

The first row address and the first nonvolatile memory M ₁ in the paired nonvolatile memory
Is selected again (the column address may have any value), the plate line PL ₁ is pulsed and the first memory cell MC ₁₁₁ of the nonvolatile memory M ₁ is selected.
When the data is read to the sense amplifier SA, the data stored in the memory cell FC ₁₁ in the flag storing semiconductor memory F ₁ is also read to the sense amplifier FSA. Then, the data read by the sense amplifier FSA is sent to the flag determination circuit FG, and the flag determination is performed. Since the data stored in the memory cell FC ₁₁ is “1”, in the flag determination circuit FG,
It is determined that the memory cell of the flag storage semiconductor memory that constitutes the flag circuit needs to be initialized. Sense amplifier FS
The data read by A is simultaneously sent to the inverting circuit INV composed of a combinational logic circuit. Inversion circuit IN
Since the data input to V is "1", the data output from the inverting circuit INV is "0". This data “0” is held in the register RS.

In reading and rewriting data from the _second non-volatile memory M ₂ in the pair of non-volatile memories, the flag storing semiconductor memory is accessed every time the non-volatile memory M ₂ is accessed. The data in the memory cell FC _2m in F ₂ is “0” → “1” →
It changes from "0" to "1". Then, when a certain row address is selected twice in the nonvolatile memory M ₂ , the flag determination circuit FG determines that the memory cell of the flag storage semiconductor memory forming the flag circuit needs to be initialized. It

Then, when the rewriting of data to the first memory cell forming the non-volatile memory is completed, all the memory cells in the non-volatile memory forming the non-volatile memory array (the first memory cell (Excluding the memory cell of) is performed. In particular,
The above operations (1) to (10) are sequentially performed on all the memory cells except the last rewritten memory cell.

On the other hand, in the flag circuit, the data "0" held in the register RS when the data is rewritten in the first memory cell is stored in the flag RS by the sense amplifiers FSA ₁ and FSA ₂ . _{First in the} semiconductor memory F ₁ and the flag storing semiconductor memory F ₂
The data is written in the th memory cells FC ₁₁ and FC ₂₁ . Further, when the refresh operation of all the memory cells (excluding the last rewritten memory cell) in all the non-volatile memories forming the non-volatile memory array is performed, the flag storing semiconductor memories F ₁ and F ₂ are The initial value data “0” is written in all the memory cells other than the first memory cells FC ₁₁ and FC ₂₁ via the sense amplifiers FSA ₁ and FSA ₂ . As a result, the memory cells of the flag storing semiconductor memory forming the flag circuit are initialized.

As described above, the refresh operation is performed at the shortest, and when the row address is selected twice,
The longest case is when the row address is selected (2MN + 1) times. Further, the maximum number of disturbs received by the memory cells constituting the nonvolatile memory is a maximum of (2MN-1) times after the completion of the last refresh operation and before the start of the current refresh operation, and (2M-1) during the refresh operation.
N-1) times, which is a maximum of 2 (2MN-1) times in total.

Also in the nonvolatile memory array of the fifth embodiment, as in the nonvolatile memory array of the second embodiment, a pair of flag storing semiconductor memories can be set in L groups. In this case, the refresh operation is performed at the shortest, when the row address is selected 2 ^L times, and at the longest, {(2 ^L −1) 2MN + 1} times. In addition, the maximum number of disturbs that the memory cells constituting the non-volatile memory receive is (2 ^L -1) (2 MN -1) times after the completion of the previous refresh operation and before the start of the current refresh operation during the refresh operation. is a (2MN-1) times, maximum, 2 ^L (2MN-
1) times.

If the selecting transistors TR ₁ , TR ₂ , FTR ₁ and FTR ₂ in the fifth embodiment are driven simultaneously, the circuit becomes equivalent to the circuit shown in FIGS. 14 to 16, and the same operation as in the fourth embodiment. Becomes

(Embodiment 6) Embodiment 6 relates to a nonvolatile memory array according to a third aspect of the present invention and a driving method thereof. FIG. 21 is a schematic partial cross-sectional view of the nonvolatile memory that constitutes the nonvolatile memory array of the sixth embodiment, taken along a virtual vertical plane parallel to the extending direction of the bit lines. FIG. 22 shows a schematic partial cross-sectional view when the is cut. Further, FIG. 2 is a conceptual circuit diagram of the nonvolatile memory array according to the sixth embodiment.
3 and the more specific non-volatile memory circuit diagram of the conceptual circuit diagram of FIG. 23 is shown in FIG. 24, and the more specific circuit diagram of the flag circuit is shown in FIG.

This non-volatile memory array is composed of a plurality (for example, K = 2 ⁷ ) of non-volatile memories and at least one (1 in the sixth embodiment, L = 1) flag storing semiconductor memory. Flag circuit (2 ^L-1 bit = 1 bit flag circuit).

In the sixth embodiment, a pair of nonvolatile memories M ₁ and M ₂ and a pair of flag storage semiconductor memories F are provided.
₁ bit and F ₂ are formed, and 1 bit is complementary stored in a pair of memory cells having a common plate line. The number of the semiconductor memory for storing a flag is 2L (L = 1), the predetermined number of times is 2 ^L.

Hereinafter, the kth nonvolatile memory array will be described.
Although the description will be given regarding the n-th (k is any of 1, 2, 3, ..., K) non-volatile memory, the subscript “k” representing the k-th non-volatile memory is omitted in the following description. To do. 23 to 25, a pair of non-volatile memories M ₁ and M ₂ and a pair of flag storage semiconductor memories F ₁ and F _{2 are shown.}
Although the nonvolatile memories M ₁ and M ₂ and the flag storing semiconductor memories F ₁ and F ₂ have the same structure, the nonvolatile memory M ₁ and the flag storing semiconductor memory F ₁ will be described below. Will be explained.

Nonvolatile memory M of the sixth embodiment₁Is
(A) Bit line BL₁And (B) N (however, if N ≧ 2,
Yes, in the sixth embodiment, N = 2)
Register TR₁₁, TR₁₂And (C) are each M (however
However, M ≧ 2, and in the sixth embodiment, M = 8)
Memory cell MC_11M, MC_12MConsists of N
Memory unit MU ₁₁, MU₁₂And (D) M plays
Line PL_M, Consists of.

The N memory units MU _1N are
They are stacked with an insulating layer (interlayer insulating layer 26) interposed therebetween. Each memory cell comprises a first electrode, a ferroelectric layer and a second electrode. Specifically, each of the memory cells MC _11M constituting the memory unit MU ₁₁ of the first (first layer) comprises a first electrode 21 and the ferroelectric layer 22 and a second electrode 23, each memory cell MC _12M constituting the memory unit MU ₁₂ of the second (second layer) comprises a first electrode 31 and the ferroelectric layer 32 and the second electrode 33. Further, in each memory unit MU _1n , the first electrodes 21 and 31 of the memory cell MC _1nm are common. Specifically, the first
In the memory unit MU ₁₁ of the layer, the memory cell MC
_{The 11M} first electrode 21 is common. This common first electrode 21 may be referred to as a first common node CN ₁₁ .
Further, in the memory unit MU ₁₂ of the second layer, the first electrode 31 of the memory cell MC _12M is common. This common first electrode 31 may be referred to as a second common node CN ₁₂ . Furthermore, the nth (nth layer) (where n =
1, 2, ..., N) in the memory unit MU _1n ,
The second electrodes 23 and 33 of the m-th (where m = 1, 2, ..., M) memory cells are connected to the m-th plate line PL _m that is common to the memory units MU _1n. Has been done. In the sixth embodiment, more specifically, each plate line extends from the second electrodes 23 and 33.

Nth (nth layer) (where n = 1, 2
..., N) memory unit MU _1nCommon first in
The first electrode is the nth selection transistor TR._1nThrough
Bit line BL₁It is connected to the. Specifically, each
Selection transistor TR₁₁, TR₁₂One source / do
The rain area 14A is the bit line BL₁Connected to the first
Eye selection transistor TR₁₁Other source / dray
The region 14B has a connection hole 18 formed in the insulating layer 16
Through the memory unit MU of the first layer₁₁Common in
Of the first electrode 21 (first common node CN₁₁) Connected to
Has been. In addition, the second selection transistor TR₁₂
The other source / drain region 14B of the
Provided connection hole 18, pad portion 25, and interlayer insulation
Through the connection hole 28 provided in the layer 26, the second layer
Mori unit MU₁₂Common first electrode 31 (first
2 common nodes CN₁₂)It is connected to the.

Bit line BL₁Is connected to the sense amplifier SA
Has been continued. Also, the plate line PL_MIs the plate line de
It is connected to the coder / driver PD. Furthermore,
Line WL₁, WL₂Is a word line decoder / driver WD
It is connected to the. Word line WL₁, WL₂21
It extends in the direction perpendicular to the page. In addition, the nonvolatile memory M ₁
Memory cell MC constituting the_11mThe second electrode 23 of FIG.
21 non-volatile memory M adjacent in the direction perpendicular to the paper surface₂Construct
Memory cell MC_21mCommon with the second electrode of
Plate line PL_mDoubles as Furthermore, non-volatile memo
Re M₁Memory cell MC constituting the_12mSecond electrode 33 of
Is a non-volatile memory M adjacent in the direction perpendicular to the paper surface of FIG.
₂Memory cell MC constituting the_22mCommon to the second electrode of
, Plate line PL_mDoubles as These plates
Line PL_mAre connected in a region not shown.
Also, the word line WL₁Is a non-volatile memory M₁Make up
Selection transistor TR₁₁And in the direction perpendicular to the paper surface of FIG.
Adjacent non-volatile memory M₂Selection transitions that make up
Star TR_{twenty one}And are common. Furthermore, the word line WL
₂Is a non-volatile memory M₁Selection transistor
TR₁₂24 and non-volatile memory adjacent in the direction perpendicular to the paper surface of FIG.
Mori M₂Selection transistor TR_{twenty two}Common with
Is.

Semiconductor memory for storing flags according to the sixth embodiment
F₁Is (A) bit line FBL₁And (B) N pieces (however,
N ≧ 2, and in the sixth embodiment, N = 2) is selected.
Selection transistor FTR₁₁, FTR₁₂And (C) That's right
These are M (provided that M ≧ 2, and in the sixth embodiment,
Is the memory cell FC of M = 8)_11M, FC_12MComposed of
N memory units FU ₁₁, FU₁₂And (D)
M plate lines PL_M, Consists of.

Then, N memory units FU_1NIs
They are stacked with an insulating layer (interlayer insulating layer 26) interposed therebetween. each
The memory cell has a first electrode, a ferroelectric layer, and a second electrode.
Consists of. Specifically, the first (first layer) memory
Unit FU₁₁Each memory cell FC that composes_11MIs the
From the first electrode 21, the ferroelectric layer 22, and the second electrode 23
And the second (second layer) memory unit FU₁₂To
Each memory cell FC_12MIs stronger than the first electrode 31.
It is composed of a dielectric layer 32 and a second electrode 33. Furthermore, each
Memory unit FU_1nIn memory cell FC_{1 nm}of
The first electrodes 21 and 31 are common. Specifically, the first
Layer memory unit FU₁₁In memory cell FC
_11MThe first electrode 21 of is common. This common first
The electrode 21 is connected to the first common node FCN₁₁Sometimes called
It In addition, the memory unit FU of the second layer₁₂At
Memory cell FC_12MThe first electrode 31 of is common. This
Of the common first electrode 31 of the second common node FCN₁₂When
May be called. Furthermore, the nth (nth layer) (however,
, N = 1, 2, ..., N) memory unit FU_1nTo
The m-th (however, m = 1, 2 ..., M) message
The second electrodes 23 and 33 of the memory cell are connected to the memory unit F.
U_1nThe m-th plate line PL that is common between _mContact
Has been continued. In the sixth embodiment, more specifically
Each plate line extends from the second electrode 23, 33
ing.

Nth (nth layer) (however, n = 1, 2
..., N) memory unit FU _1nCommon first in
The first electrode is the nth selection transistor FTR._1nTo
Through bit line FBL₁It is connected to the. Specifically
Is each selection transistor FTR₁₁, FTR₁₂One of
The source / drain region 14A is a bit line FBL₁Connected to
The first selection transistor FTR₁₁The other of
The source / drain region 14B is provided in the insulating layer 16.
The memory unit FU of the first layer is connected through the connection hole 18
₁₁Common first electrode 21 (first common node F
CN₁₁)It is connected to the. In addition, the second selection
Langista FTR₁₂The other source / drain region 14 of
B is a connection hole 18 and a pad portion 2 provided in the insulating layer 16.
5 and through the connection hole 28 provided in the interlayer insulating layer 26.
Then, the second layer memory unit FU₁₂Common in
The first electrode 31 (second common node FCN₁₂) Connected to
Has been.

The bit line FBL ₁ is connected to the sense amplifier FSA.
It is connected to the. Further, the plate line PL _M is connected to the plate line decoder / driver PD. Furthermore,
The word lines WL ₁ and WL ₂ are connected to the word line decoder / driver WD. The word lines WL ₁ and WL ₂ are shown in FIG.
2 extends in the direction perpendicular to the paper surface. The second electrode 23 of the memory cell FC _11m forming the flag storing semiconductor memory F ₁ is the second electrode of the memory cell FC _{2 1m} forming the flag storing semiconductor memory F ₂ which is adjacent in the direction perpendicular to the paper surface of FIG. Two
, And also serves as the plate line PL _m .
Further, the second electrode 33 of the memory cell FC _12m forming the flag storing semiconductor memory F ₁ is the second electrode 33 of the memory cell FC _22m forming the flag storing semiconductor memory F ₂ adjacent in the direction perpendicular to the paper surface of FIG. It is common to the second electrode and also serves as the plate line PL _m . These plate lines PL
_m is connected in a region not shown. Also,
The word line WL ₁ is shared by the selection transistor FTR ₁₁ that constitutes the flag storage semiconductor memory F ₁ and the selection transistor FTR ₂₁ that constitutes the flag storage semiconductor memory F ₂ that is adjacent in the direction perpendicular to the paper surface of FIG. Is. Furthermore, the word line WL ₂ includes a selection transistor FTR ₁₂ constituting the semiconductor memory F ₁ for flag storage, selection transistors constituting the flag storage semiconductor memory F ₂ adjacent in the direction perpendicular to the paper surface in FIG. 22 FTR ₂₂ And are common.

In the nonvolatile memory array whose circuit diagrams are shown in FIGS. 23 to 25, the selection transistor TR _1n forming the nonvolatile memory M ₁ , the selection transistor TR _2n forming the nonvolatile memory M ₂ , and the flag storage. The selection transistor FTR _1n forming the semiconductor memory F ₁ for selection and the selection transistor FTR _2n forming the semiconductor memory F ₂ for storing a flag are connected to the word line WL _n . And the paired memory cells MC _1nm , MC
_2nm (n = 1, 2 ..., N and m = 1, 2 ...
, M) and memory cells FC _1nm , FC _2nm , complementary 1
Bit data is stored.

The method of reading data from the non-volatile memory of the sixth embodiment and rewriting it can be substantially the same as that described in the fourth embodiment, and therefore detailed description thereof will be omitted. Only the operation of the flag circuit will be described below. In the description below, it is assumed that the mth row address and the first memory unit are selected. Here, the column address may have any value. Here, the m-th plate line corresponds to a “certain plate line”.

A pair of flag storing semiconductor memories F ₁ and F ₂
In, complementary one bit is stored, and data "0" is stored in the initial state. The kth column
Address, the mth row address, the first memory unit MU ₁₁ , MU ₂₁ are selected, and the plate line PL
_When a pulse is given to _m , the _m-th memory in the nonvolatile memories M ₁ and M ₂
When the data stored in the th memory cells MC _11m and MC _21m are read by the sense amplifier SA, the memory cells FC in the flag storing semiconductor memories F ₁ and F ₂ are simultaneously read.
_The data stored in _11m and FC _21m are also sense amplifier FSA.
Read out. Then, the data read by the sense amplifier FSA is sent to the flag determination circuit FG, and the flag determination is performed. Since the data stored in the memory cells FC _11m and FC _21m is “0”, the flag determination circuit FG
In the above, it is judged that the initialization of the memory cell of the flag storing semiconductor memory which constitutes the flag circuit is unnecessary. The data read by the sense amplifier FSA is simultaneously sent to the inverting circuit INV composed of the combinational logic circuit.
Since the data input to the inverting circuit INV is "0", the data output from the inverting circuit INV is "1". This data "1" is held in the register RS.

When data is rewritten in the memory cells MC _11m and MC _21m , the data “1” held in the register RS is stored in the memory cells FC _11m and FC _21m in the flag storing semiconductor memories F ₁ and F ₂ . Written. When the m-th row address is selected by the above operation, the memory cells FC _11m , FC in the flag storing semiconductor memories F ₁ , F ₂ related to this row address are selected.
_The data stored in _21m is from "0" to "1" in the initial state.
Changes to.

For example, next, when the m'th (m '≠ m) row address is selected, the memory cells FC _1nm' in the flag storing semiconductor memories F ₁ and F ₂ related to this row address are selected. FC _{2nm '} changes from the initial state.
That is, any row address can be randomly accessed.

When the m-th row address and the first memory units MU ₁₁ and MU ₂₁ are selected again (the column address may have any value), a pulse is applied to the plate line PL _m. When the data stored in the m-th memory cells MC _11m and MC _21m of the nonvolatile memories M ₁ and M ₂ are read by the sense amplifier SA, at the same time, the flag storing semiconductor memories F ₁ and F _{2 are} stored. data storage memory cell FC _11m, the FC _{2 1 m} in also read out to the sense amplifier FSA. The data read by the sense amplifier FSA is the flag determination circuit FG.
And the flag judgment is made. Memory cell F
Since the data stored in C _11m and FC _21m is “1”, in the flag determination circuit FG, it is determined that the memory cell of the flag storage semiconductor memory forming the flag circuit needs to be initialized. The data read by the sense amplifier FSA is simultaneously sent to the inverting circuit INV composed of the combinational logic circuit. Since the data input to the inverting circuit INV is "1", the data output from the inverting circuit INV is "0". This data “0” is held in the register RS.

In reading and rewriting data in the memory cells MC _12m and MC _22m forming the second memory units MU ₁₂ and MU ₂₂ in the paired nonvolatile memories M ₁ and M ₂ , the nonvolatile memory is used. The data in the memory cells FC _{12m and} FC _22m in the flag storing semiconductor memories F ₁ and F ₂ are _rewritten each time the specific memory M ₁ or M ₂ is accessed.
It changes in the order of “0” → “1” → “0” → “1” .... Then, in the flag storage semiconductor memories F ₁ and F ₂ , the data stored in a certain pair of memory cells is read out, and when this data is “1”, the flag determination circuit F
In G, it is determined that the memory cells of the flag storage semiconductor memory forming the flag circuit need to be initialized.

Then, at the time when the rewriting of data to the m-th memory cells MC _11m and MC _{21m of} the nonvolatile memories M ₁ and M ₂ is completed, all the nonvolatile memories constituting the nonvolatile memory array are The refresh operation of all memory cells (except the m-th memory cell) is performed. Specifically, the operations (1) to (10) of the fourth embodiment are sequentially performed on all memory cells except the m-th memory cell.

On the other hand, in the flag circuit, the second row address selection in the m-th row address is performed, and the memory cells MC of the nonvolatile memories M ₁ and M ₂ are selected.
At the time of rewriting data to _11m and MC _21m , the data "0" held in the register RS is written to the memory cells FC _11m and FC _21m in the flag storing semiconductor memories F ₁ and F ₂ by the sense amplifier FSA. . In addition, when the refresh operation of all the memory cells (excluding the first memory cell) in all the nonvolatile memories forming the nonvolatile memory array is performed, the memory cells in the flag storing semiconductor memories F ₁ and F ₂ are The initial value data "0" is written in all the memory cells other than FC _11m and FC _21m via the sense amplifier FSA. As a result, the memory cells of the flag storing semiconductor memory forming the memory cells of the flag storing semiconductor memory forming the flag circuit are initialized.

In the nonvolatile memory array of the sixth embodiment, the refresh operation is performed at the shortest, and when the row address is selected twice, at the longest, the row address is selected (2M + 1) times. That is the case. Also,
The maximum number of disturbances received by the memory cells constituting the non-volatile memory is the maximum (2M-1) from the completion of the last refresh operation to the start of this refresh operation.
The number of refresh operations is (2M-1) times, which is a maximum of 2 (2M-1) times.

Also in the non-volatile memory array of the sixth embodiment, a pair of flag storage semiconductor memories can be set to L sets, substantially as in the non-volatile memory array of the second embodiment. In this case, the refresh operation is performed at the shortest, when the row address is selected 2 ^L times, and at the longest, {(2 ^L −1) 2 M + 1} times. In addition, the maximum number of disturbs received by the memory cells constituting the non-volatile memory is (2 ^L -1) (2 M -1) times after the completion of the previous refresh operation and before the start of the current refresh operation during the refresh operation. a (2M-1) times the maximum, 2 ^L (2M-1) times.

(Embodiment 7) Embodiment 7 is a modification of Embodiment 6. In the seventh embodiment, a pair of non-volatile memories M ₁ and M ₂ and a pair of flag storing semiconductor memories F ₁ and F ₂ are formed, and each of a pair of memory cells having a common plate line. Store one bit. The number of the semiconductor memory for storing a flag is 2L (L = 1), the predetermined number of times is 2 ^L.

26 and 27 are conceptual circuit diagrams of the non-volatile memory array according to the seventh embodiment. More specific non-volatile memory circuit of the non-volatile memory conceptual circuit diagram shown in FIG. 28 is shown, and a more specific circuit diagram of the flag circuit shown in FIG. 27 is shown in FIG. In the nonvolatile memory array according to the seventh embodiment, the selection transistor TR _1n forming the nonvolatile memory M ₁ and the selection transistor FTR _1n forming the flag storing semiconductor memory F ₁ are connected to the word line WL _1n . A selection transistor TR _2n which is connected and constitutes the nonvolatile memory M ₂ , and
The selection transistor FTR _2n forming the flag storage semiconductor memory F ₂ is connected to the word line WL _2n .
The word lines WL _1n and WL _2n are connected to the word line decoder / driver WD. Then, the memory cell M
C _1nm , FC _1nm and memory cells MC _2nm , FC _2nm are independently controlled, and a reference voltage is applied to one of the paired bit lines BL ₁ and BL ₂ and the paired bit lines FBL ₁ and FBL _2. By doing so, 1-bit data is read from each of the memory cells MC _1nm and MC _2nm and the memory cells FC _1nm and FC _2nm . Except for this point, the configuration and structure of the non-volatile memory array can be the same as the configuration and structure of the non-volatile memory array according to the sixth embodiment, and detailed description thereof will be omitted.

The method of reading and rewriting data from the non-volatile memory of the seventh embodiment can be substantially the same as that described in the fifth embodiment, and therefore detailed description thereof will be omitted. Only the operation of the flag circuit will be described below. In the following description, the nonvolatile memory M ₁ is selected from the paired nonvolatile memories M ₁ and M ₂ .
Furthermore, it is assumed that the mth row address and the first memory unit are selected. That is, the memory cell MC
_{Suppose 11m} is selected. Here, the column address may have any value. Here, the m-th plate line corresponds to a “certain plate line”.

A pair of flag storing semiconductor memories F ₁ and F ₂
, 1 bit is stored in each of the memory cells FC _1nm and FC _2nm , and data “0” is stored in the initial state. The kth column address, the mth row address and the nth memory unit MU ₁₁ are selected, a pulse is applied to the plate line PL _m , and the mth memory cell of the nonvolatile memory M ₁ is selected. When the data is read from the MC _11m to the sense amplifier SA, at the same time, the data stored in the memory cell FC _11m in the flag storing semiconductor memory F ₁ is also read to the sense amplifier FSA. In this case, the bit line FBL
₂ has a read potential of data “1” and data “0”.
A reference potential in the middle of the read potential of is given. Then, the data read by the sense amplifier FSA is sent to the flag determination circuit FG, and the flag determination is performed. Since the data stored in the memory cell FC _11m is “0”, in the flag determination circuit FG, it is determined that initialization of the memory cell of the flag storage semiconductor memory forming the flag circuit is unnecessary. At the same time, the data read out to the sense amplifier FSA is inverted by an inverting circuit I composed of a combinational logic circuit.
Sent to NV. Since the data input to the inverting circuit INV is "0", the data output from the inverting circuit INV is "1". This data "1" is the register RS
Held in.

Then, at the time of rewriting data in the memory cell MC _11m , the data "1" held in the register RS is written in the memory cell FC _11m in the flag storing semiconductor memory F ₁ . By the above operation,
When the m-th row address is selected, the data stored in the memory cell FC _11m in the flag storing semiconductor memory F ₁ related to this row address changes from “0” in the initial state to “1”. .

For example, next, when the m'th (m '≠ m) row address is selected, the memory cell FC _1nm' in the flag storing semiconductor memory F ₁ related to this row address is changed from the initial state. Change. That is, any row address can be randomly accessed.

When the m-th row address and the first memory unit MU ₁₁ in the nonvolatile memory M ₁ are selected again (that is, the memory cell MC _11m ) (what value is the column address? , The pulse is applied to the plate line PL _m , and the nonvolatile memory M ₁
When the data is read from the mth memory cell MC _11m to the sense amplifier SA, the data stored in the memory cell FC _11m in the flag storing semiconductor memory F ₁ is also read to the sense amplifier FSA. And
The data read by the sense amplifier FSA is sent to the flag determination circuit FG and flag determination is performed. Since the data stored in the memory cell FC _11m is “1”,
In the flag determination circuit FG, it is determined that the memory cells of the flag storage semiconductor memory forming the flag circuit need to be initialized. The data read by the sense amplifier FSA is simultaneously sent to the inverting circuit INV composed of the combinational logic circuit. Since the data input to the inverting circuit INV is "1", the data output from the inverting circuit INV is "0". This data “0” is registered in the register R
Hold at S.

In reading and rewriting data from the _second non-volatile memory M ₂ in the pair of non-volatile memories, the flag storage semiconductor memory is accessed every time the non-volatile memory M ₂ is accessed. Data in the memory cell FC _2nm in F ₂ is “0” → “1” →
It changes from "0" to "1". Then, in the flag storage semiconductor memory F ₂ , the data stored in a certain memory cell is read out, and when this data is “1”, the flag determination circuit FG stores the flag in the flag circuit. It is determined that the memory cells of the semiconductor memory need to be initialized.

Then, when the rewriting of data to the memory cell MC _11m in the nonvolatile memory M ₁ is completed, all the memory cells in all the nonvolatile memories constituting the nonvolatile memory array (the m-th memory (Excluding cells) is refreshed. In particular,
The operations (1) to (10) of the fifth embodiment are sequentially performed on all the memory cells except the memory cell that was last rewritten.

On the other hand, in the flag circuit, when the data is rewritten to the mth memory cell, the data "0" held in the register RS is stored in the flag by the sense amplifier FSA ₁ and the sense amplifier FSA ₂ . The m-th memory in the semiconductor memory F ₁ and the flag storage semiconductor memory F ₂ .
The data is written in each of the th memory cells FC _11m and FC _21m . Further, when the refresh operation of all the memory cells (excluding the last rewritten memory cell) in all the non-volatile memories forming the non-volatile memory array is performed, the flag storing semiconductor memories F ₁ and F ₂ are The initial value data "0" is written to all the memory cells except the memory cells FC _11m and FC _21m via the sense amplifiers FSA ₁ and FSA ₂ . As a result, the memory cells of the flag storing semiconductor memory forming the flag circuit are initialized.

As described above, the refresh operation is performed at the shortest, and when the row address is selected twice,
The longest case is when the row address is selected (4M + 1) times. In addition, the maximum number of disturbs received by the memory cells forming the non-volatile memory is (4M-1) times after the completion of the previous refresh operation and before the start of the current refresh operation.
1) times, a maximum of 2 (4M-1) times in total.

Also in the non-volatile memory array of the seventh embodiment, a pair of flag storage semiconductor memories can be set in L groups, substantially as in the non-volatile memory array of the second embodiment. In this case, the refresh operation is performed at the shortest, when the row address is selected 2 ^L times, and at the longest, {(2 ^L −1) 4 M + 1} times. In addition, the maximum number of disturbs received by the memory cells constituting the non-volatile memory is (2 ^L -1) (4 M -1) N times after the completion of the last refresh operation and before the start of this refresh operation during the refresh operation. a There (4M-1) times the maximum, 2 ^L (4M-1) times.

If the selection transistors TR ₁ , TR ₂ , FTR ₁ and FTR ₂ in the seventh embodiment are driven at the same time, the circuit becomes equivalent to the circuit shown in FIGS. 23 to 25, and the same operation as in the sixth embodiment. Becomes

(Embodiment 8) Embodiment 8 relates to a nonvolatile memory array according to the fourth aspect of the present invention and a driving method thereof. The structure and configuration of the nonvolatile memory according to the eighth embodiment can be substantially the same as the structure and configuration of the nonvolatile memory according to the sixth embodiment.
Detailed description is omitted.

This non-volatile memory array includes a plurality of (for example, K = 2 ⁷ ) non-volatile memories and at least one (1 in the eighth embodiment, L = 1) semiconductor memory for storing flags. Flag circuit (2 ^L-1 bit = 1 bit flag circuit).

In the eighth embodiment, a pair of nonvolatile memories M ₁ and M ₂ and a pair of flag storage semiconductor memories F are provided.
₁ bit and F ₂ are formed, and 1 bit is complementary stored in a pair of memory cells having a common plate line. The number of the semiconductor memory for storing a flag is 2L (L = 1), the predetermined number of times is 2 ^L. The flag circuit has a 1-bit configuration.

FIG. 30 shows a conceptual circuit diagram of the non-volatile memory array in the eighth embodiment, and FIG. 31 shows a more specific circuit diagram of the flag circuit of the conceptual circuit diagram of FIG. 32 is a schematic partial cross-sectional view of the flag storage semiconductor memory of the eighth embodiment taken along a virtual vertical plane parallel to the extending direction of the bit lines. In FIG. 32, the flag storage semiconductor memory F is formed on the insulating layer 16.
₁ shows a state in which the memory cell FC _1M forming ₁ and the memory cell FC _2M forming the flag storing semiconductor memory F ₂ are formed on the insulating layer 26. However, the flag storing semiconductor memory F ₂ is formed. The memory cell FC _2M to be formed may be formed on the insulating layer 16.

Hereinafter, the kth nonvolatile memory array will be described.
Although the description will be given regarding the n-th (k is any of 1, 2, 3, ..., K) non-volatile memory, the subscript “k” representing the k-th non-volatile memory is omitted in the following description. To do. 30 to 32, a pair of non-volatile memories M ₁ and M ₂ and a pair of flag storage semiconductor memories F ₁ and F _{2 are shown.}
The structures of the nonvolatile memories M ₁ and M ₂ and the flag storing semiconductor memories F ₁ and F ₂ are substantially the same. In the following, the flag storage semiconductor memory F ₁
Will be explained.

The flag storing semiconductor memory F ₁ is (E)
Bit line FBL ₁ , (F) N (N = 2 in the eighth embodiment) selection transistors TR _1N , and (G)
A memory unit FU _{1 including M} memory cells (where M ≧ 2, and M = 8 in the eighth embodiment) FC _1M , and (H) M plate lines P.
L _M, consisting of.

Then, each memory cell FC_1mIs the first
It comprises a pole 21, a ferroelectric layer 22 and a second electrode 23.
Furthermore, the memory unit FU₁At memory cell F
C_1mThe first electrode 21 of is common. This common first
The electrode 21 is connected to the common node FCN. ₁Sometimes called. Well
Memory unit FU₁In the m-th (however,
m = 1, 2 ..., M) memory cell FC_1mSecond electric power
The pole 23 is the m-th plate line PL_mConnected to
It In the eighth embodiment, more specifically, the play
The wire extends from the second electrode 23.

Common _First in Memory Unit FU 1
Is connected to the bit line FBL ₁ via each selection transistor FTR _1n . Specifically, one source / drain region 14A of each of the selection transistors FTR ₁₁ and FTR ₁₂ is connected to the bit line FBL _1, and the other source / drain region 14B of the selection transistors FTR ₁₁ and FTR ₁₂ is insulated. Connection hole 18 provided in layer 16
Via a common first electrode 21 (common node FCN ₁ ) in the memory unit FU ₁ .
Incidentally, one of the source / drain region 14A of each selection transistor FTR _{2 1,} FTR ₂₂ constituting the flag storage semiconductor memory F ₂ is connected to the bit line FBL _2, of the selection transistor FTR _21, FTR ₂₂ other The source / drain region 14B is a connection hole 1 provided in the insulating layer 16.
It is connected to the common first electrode 31 (common node FCN ₂ ) in the memory unit FU ₂ via the connection hole 28 provided in the pad 8, the pad portion 25, and the interlayer insulating layer 26.

Bit line FBL₁Is the sense amplifier FSA
It is connected to the. Also, the plate line PL_MIs a plate
It is connected to the line decoder / driver PD. Furthermore,
Word line WL₁, WL₂Is a word line decoder / driver
It is connected to WD. In addition, in the example shown in FIG.
The flag storage semiconductor memory F₁The memory that makes up
Cell FC_1mThe second electrode 23 of the flag is located above
Storage semiconductor memory F ₂Memory cell FC_2mof
It is common to the second electrode 33, and the plate line PL_mDoubles as
ing. These plate lines PL_mIs not shown
Are connected in. Also, the word line WL₁Is
Semiconductor memory F for storing lag₁Selection transitions that make up
Star FTR₁₁32 and adjacent flas in the direction perpendicular to the paper surface of FIG.
Storage semiconductor memory F₂Transit for selection
FTR_{twenty one}And are common. Furthermore, the word line WL
₂Is a flag storing semiconductor memory F₁For selection
Langista FTR₁₂32 in the direction perpendicular to the paper surface of FIG.
Flag storing semiconductor memory F₂Selection tigers
Register FTR_{twenty two}And are common.

In the nonvolatile memory array whose circuit diagrams are shown in FIGS. 30 to 32, the selection transistor TR _1n forming the nonvolatile memory M ₁ , the selection transistor TR _2n forming the nonvolatile memory M ₂ , and the flag storage. The selection transistor FTR _1n forming the semiconductor memory F ₁ for selection and the selection transistor FTR _2n forming the semiconductor memory F ₂ for storing a flag are connected to the word line WL _n . And the paired memory cells MC _1nm , MC
_2nm (n = 1, 2 ..., N and m = 1, 2 ...
, M) and 1-bit data complementary to the memory cells FC _1m and FC _2m are stored.

The method of reading data from the non-volatile memory of the eighth embodiment and rewriting the data can be substantially the same as that described in the fourth embodiment, and therefore detailed description thereof will be omitted. Only the operation of the flag circuit will be described below. In the following description, the m-th row address and an arbitrary n-th memory unit (that is,
Memory cells MC _1nm , MC _2nm ) are selected. Here, the m-th plate line corresponds to a “certain plate line”. The column address can be any value.
Further, the following operation is performed regardless of whether the word line WL ₁ or WL ₂ is selected.

A pair of flag storing semiconductor memories F₁, F₂
, The complementary 1 bit is stored in the initial state.
Stores data "0". Any k th
RAM address, mth row address, any first address
nth memory unit MU _1n, MU_2nIs selected,
Rate line PL_mPulsed to the non-volatile memory
M₁, M₂M-th memory cell MC of_{1 nm}, MC_{2 nm}In
When the stored data is read by the sense amplifier SA
At the same time, the flag storing semiconductor memory F₁, F₂Oke
Memory cell FC_1m, FC_2mData stored in
It is read out by the amplifier FSA. And the sense amplifier
The data read by the FSA is sent to the flag determination circuit FG.
It is sent and flag determination is made. Memory cell FC_1m, F
C_2mSince the data stored in is 0, the flag
In the determination circuit FG, the flags forming the flag circuit
Judging that the memory cells of the storage semiconductor memory do not need to be initialized
To be done. The data read by the sense amplifier FSA is
At the same time, an inverting circuit INV composed of a combinational logic circuit
Sent to. The data input to the inverting circuit INV is
Since it is "0", the data output from the inverting circuit INV is
The data is "1". This data "1" is the register RS
Held in.

When data is rewritten in the memory cells MC _1nm and MC _2nm , the data "1" held in the register RS is stored in the memory cells FC _1m and FC _2m in the flag storing semiconductor memories F ₁ and F ₂ . Written. When the m-th row address is selected by the above operation, the data stored in the memory cells FC _1m and FC _2m in the flag storing semiconductor memories F ₁ and F ₂ related to this row address are in the initial state. It changes from "0" to "1".

For example, next, when the m'th (m '≠ m) row address is selected, the memory cells FC _1m' in the flag storing semiconductor memories F ₁ and F ₂ related to this row address are selected. FC _{2m '} changes from the initial state. That is, any row address can be randomly accessed. It does not depend on which of the word lines WL ₁ and WL ₂ is selected.

The mth row address and any nth row address
Th memory unit MU_1n, MU _2nWas selected again
If (column address can be any value
And word line WL₁, WL₂Depending on which was selected
Not exist), plate line PL_mPulse is given to the
Volatile memory M₁, M₂First memory cell M of
C_{1 nm}, MC_{2 nm}The data stored in the sense amplifier SA
At the same time, the semiconductor memory for flag storage
Li F₁, F₂Memory cell FC_1m, FC_2mRemembered by
The read data is also read by the sense amplifier FSA. That
The data read by the sense amplifier FSA is
Is sent to the flag determination circuit FG and flag determination is performed. Note
Resel FC_1m, FC_2mThe data stored in is "1"
Therefore, in the flag determination circuit FG, the flag circuit
The first memory cell of the flag storage semiconductor memory
It is judged that the period is necessary. Read to sense amplifier FSA
The combined data is composed of combinatorial logic circuits at the same time.
To the inverting circuit INV. Input to inverting circuit INV
Since the data obtained is "1",
The output data is “0”. This data “0”
It is held in the register RS.

Then, when the rewriting of the data to the memory cells MC _1nm and MC _{2nm of} the nonvolatile memories M ₁ and M ₂ is completed, all the memory cells in all the nonvolatile memories forming the nonvolatile memory array are completed. A refresh operation (excluding the mth memory cell) is performed. Specifically, the operations (1) to (10) of the fourth embodiment are sequentially performed on all memory cells except the m-th memory cell.

On the other hand, in the flag circuit, the second row address selection in the m-th row address is performed, and the memory cells MC of the nonvolatile memories M ₁ and M ₂ are selected.
At the time of rewriting data to _{1 nm} and MC _{2 nm} , the data “0” held in the register RS is written to the memory cells FC _1m and FC _2m in the flag storing semiconductor memories F ₁ and F ₂ by the sense amplifier FSA. . In addition, when the refresh operation of all the memory cells (excluding the first memory cell) in all the nonvolatile memories forming the nonvolatile memory array is performed, the memory cells in the flag storing semiconductor memories F ₁ and F ₂ are The initial value data "0" is written in all the memory cells other than FC _1m and FC _2m via the sense amplifier FSA. As a result, the memory cells of the flag storing semiconductor memory forming the flag circuit are initialized.

In the non-volatile memory array of the eighth embodiment, the refresh operation is performed at the shortest, and when the row address is selected twice, at the longest, the row address is selected (M + 1) times. That is the case. Further, the maximum number of disturbances received by the memory cells constituting the non-volatile memory is a maximum of M times after the completion of the previous refresh operation and before the start of this refresh operation, and (2M-1) times during the refresh operation, Maximum, total (3M
-1) times.

Also in the non-volatile memory array of the eighth embodiment, a pair of flag storing semiconductor memories can be set to L sets substantially like the non-volatile memory array of the second embodiment. In this case, the refresh operation is performed at the shortest, when the row address is selected 2 ^L times, and at the longest, {(2 ^L −1) M + 1} times. Further, the maximum number of disturbs received by the memory cells forming the nonvolatile memory is (2 ^L −1) M times after the completion of the previous refresh operation and before the start of the current refresh operation, and (2 M −1) during the refresh operation. )
The maximum number of times is {2 ^L −1) M + (2M−1)} times.

(Ninth Embodiment) The ninth embodiment is an embodiment.
It is a modification of state 8. In the ninth embodiment, a pair of mismatches is used.
Volatile memory M₁, M₂And a pair of semiconductor memory for storing flags.
Mori F₁, F₂And the plate line is common
One bit is stored in each of the pair of memory cells.
The number of flag storage semiconductor memories is 2L (L = 1).
The predetermined number of times is 2 ^LIs. Flag circuit consists of 1 bit
Is.

FIG. 33 shows a conceptual circuit diagram of the flag circuit in the non-volatile memory array according to the ninth embodiment, and FIG. 34 is a partial circuit diagram of a more specific flag circuit of the conceptual circuit diagram of FIG. Shown in. A schematic partial cross-sectional view of the flag storage semiconductor memory of the ninth embodiment taken along a virtual vertical plane parallel to the extending direction of the bit lines can be the same as that shown in FIG. , Detailed description is omitted. The conceptual circuit diagram of the nonvolatile memory in the nonvolatile memory array according to the ninth embodiment is similar to that shown in FIG.

Hereinafter, the kth nonvolatile memory array will be described.
Although the description will be given regarding the n-th (k is any of 1, 2, 3, ..., K) non-volatile memory, the subscript “k” representing the k-th non-volatile memory is omitted in the following description. To do. 33 and 34, a pair of non-volatile memories M ₁ and M ₂ , a pair of flag storage semiconductor memories F ₁ and
F ₂ is shown, but these nonvolatile memories M ₁ , M ₂ ,
The flag storage semiconductor memories F ₁ and F ₂ have the same structure. The semiconductor memory F ₁ for storing flags will be described below.

The flag storing semiconductor memory F ₁ is (E)
A bit line FBL ₁ and (F) N selection transistors TR _1N (N = 2 in the ninth embodiment);
(G) A memory unit FU _{1 including M} memory cells (where M ≧ 2, M = 8 in the ninth embodiment) FC _1M , and (H) M plate lines. PL _M.

Then, each memory cell FC_1mIs the first
It comprises a pole 21, a ferroelectric layer 22 and a second electrode 23.
Furthermore, the memory unit FU₁At memory cell F
C_1mThe first electrode 21 of is common. This common first
The electrode 21 is connected to the common node FCN. ₁Sometimes called. Well
Memory unit FU₁In the m-th (however,
m = 1, 2 ..., M) memory cell FC_1mSecond electric power
The pole 23 is the m-th plate line PL_mConnected to
It In the ninth embodiment, more specifically, the play
The wire extends from the second electrode 23.

Common _First in Memory Unit FU 1
Is connected to the bit line FBL ₁ via each selection transistor FTR _1n . Specifically, one source / drain region 14A of each of the selection transistors FTR ₁₁ and FTR ₁₂ is connected to the bit line FBL _1, and the other source / drain region 14B of the selection transistors FTR ₁₁ and FTR ₁₂ is insulated. Connection hole 18 provided in layer 16
Via a common first electrode 21 (common node FCN ₁ ) in the memory unit FU ₁ .

The bit line FBL ₁ is connected to the sense amplifier FSA.
It is connected to the. Further, the plate line PL _M is connected to the plate line decoder / driver PD. Furthermore,
The word lines WL ₁₁ , WL ₁₂ , WL ₂₁ , WL ₂₂ are connected to the word line decoder / driver WD. Second memory cell FC _1m forming the flag storing semiconductor memory F ₁
The electrode 23 is common to the second electrode of the memory cell FC _2m forming the flag storing semiconductor memory F ₂ and also serves as the plate line PL _m . These plate lines PL _m are
They are connected in a region not shown. The word line WL ₁₁ is common to the selection transistor FTR ₁₁ that constitutes the flag storage semiconductor memory F ₁ and the selection transistor TR ₁₁ that constitutes the nonvolatile memory M ₁ , and the word line WL ₁₂ is the flag. The selection transistor FTR ₁₂ forming the storage semiconductor memory F ₁ and the selection transistor TR ₁₂ forming the nonvolatile memory M ₁ are common, and the word line WL ₂₁ forms the flag storage semiconductor memory F ₂ . Selection transistor FTR ₂₁ and non-volatile memory M ₂
Common to the selection transistor TR ₂₁ that configures
The word line WL ₂₂ includes a selection transistor FTR ₂₂ and a non-volatile memory M that form the flag storage semiconductor memory F _2.
It is also common to the selection transistor TR ₂₂ that forms part ₂ . And the paired memory cells MC _1nm , MC
_2nm (n = 1, 2 ..., N and m = 1, 2 ...
., M) and memory cells FC _1m , FC _2m each 1
Bit data is stored.

The method of reading and rewriting data from the non-volatile memory of the ninth embodiment can be substantially the same as that described in the fifth embodiment, and therefore detailed description thereof will be omitted. Only the operation of the flag circuit will be described below. In the following description, the nonvolatile memory M ₁
It is assumed that the memory cell MC _{1 nm of} is selected. Here, the m-th plate line corresponds to a “certain plate line”.
The column address may have any value, and the value of n may be either 1 or 2. That is, the word line W
One of L _11, WL ₂ does not depend on whether the selected, also does not depend on whether one of the word lines WL _{2 1,} WL ₂₂ is selected.

A pair of flag storing semiconductor memories F ₁ and F ₂
In each of the above, 1 bit is stored, and data “0” is stored in the initial state. Memory cell MC
_{1 nm} is selected, a pulse is applied to the plate line PL _m ,
When the data stored in the memory cell MC _1nm of the nonvolatile memory M ₁ is read by the sense amplifier SA, at the same time,
Memory cell FC in semiconductor memory F ₁ for storing flags
_The data stored in _{1 m} is also read by the sense amplifier FSA. Then, the data read by the sense amplifier FSA is sent to the flag determination circuit FG, and the flag determination is performed. Since the data stored in the memory cell FC _1m is “0”, in the flag determination circuit FG, it is determined that the initialization of the memory cell of the flag storage semiconductor memory forming the flag circuit is unnecessary. The data read by the sense amplifier FSA is simultaneously sent to the inverting circuit INV composed of the combinational logic circuit. Since the data input to the inverting circuit INV is "0", the data output from the inverting circuit INV is "1". This data “1”
Are held in the register RS.

Then, at the time of rewriting data in the memory cell MC _1nm , the data "1" held in the register RS is written in the memory cell FC _1m in the flag storing semiconductor memory F ₁ . When the memory cell MC _1nm of the nonvolatile memory M ₁ is selected by the above operation, the data stored in the memory cell FC _1m of the flag storing semiconductor memory F ₁ changes from “0” in the initial state to “1”. And changes.

For example, next, the m'th (m '≠ m)
This row address, if a row address was selected
Flag storage semiconductor memory F₁Or F₂To
Memory cell FC_{1m '}Or FC_{2m '}From the initial state
Change. That is, any row address is randomly assigned.
Can be accessed. The word line WL₁₁, WL ₂
It does not depend on which one was selected and also on the word line
WL_{twenty one}, WL_{twenty two}Depends on which one was selected
Yes.

When the memory cell MC _1nm of the nonvolatile memory M ₁ is selected again (the column address may have any value, and the value of n may have any value).
When a pulse is applied to the plate line PL _m and the data stored in the memory cell MC _1nm of the nonvolatile memory M ₁ is read by the sense amplifier SA, at the same time, the memory cell FC _1m in the flag storing semiconductor memory F ₁ is read. The data stored in is also read by the sense amplifier FSA. And
The data read by the sense amplifier FSA is sent to the flag determination circuit FG and flag determination is performed. Since the data stored in the memory cell FC _1m is “1”, the flag determination circuit FG determines that the memory cell of the flag storage semiconductor memory forming the flag circuit needs to be initialized. At the same time, the data read out to the sense amplifier FSA is inverted by an inverting circuit I composed of a combinational logic circuit.
Sent to NV. Since the data input to the inverting circuit INV is "1", the data output from the inverting circuit INV is "0". This data “0” is stored in the register RS
Held in.

In reading and rewriting data from the _second non-volatile memory M ₂ in the pair of non-volatile memories, the flag storing semiconductor memory is accessed every time the non-volatile memory M ₂ is accessed. The data in the memory cell FC _2m in F ₂ is “0” → “1” →
It changes from "0" to "1". Then, in the flag storage semiconductor memory F ₂ , the data stored in a certain memory cell is read out, and when this data is “1”, the flag determination circuit FG stores the flag in the flag circuit. It is determined that the memory cells of the semiconductor memory need to be initialized.

Then, when the rewriting of the data to the memory cell MC _1nm of the nonvolatile memory M ₁ is completed, all the memory cells (mth memory) in all the nonvolatile memories forming the nonvolatile memory array are completed. (Excluding cells)
Refresh operation is performed. Specifically, the operations (1) to (10) of the fifth embodiment are sequentially performed on all memory cells except the m-th memory cell.

On the other hand, in the flag circuit, when data is rewritten to the memory cell MC _1nm of the nonvolatile memory M ₁ ,
The data “0” held in the register RS is transferred to the flag storage semiconductor memory F ₁ , by the sense amplifier FSA.
It is written in the memory cells FC _1m and FC _2m in F ₂ . In addition, when the refresh operation of all the memory cells (excluding the first memory cell) in all the nonvolatile memories forming the nonvolatile memory array is performed, the memory cells in the flag storing semiconductor memories F ₁ and F ₂ are F
The initial value data "0" is written in all the memory cells other than C _1m and FC _2m via the sense amplifier FSA. As a result, the memory cells of the flag storing semiconductor memory forming the flag circuit are initialized.

In the non-volatile memory array of the ninth embodiment, the refresh operation is performed at the shortest, when the row address is selected twice, at the longest, the row address is selected (2M + 1) times. That is the case. Also,
The maximum number of disturbances received by the memory cells constituting the non-volatile memory is 2M at maximum after the completion of the previous refresh operation and before the start of this refresh operation, and (4M-1) times during the refresh operation. It is (6M-1) times in total.

Also in the non-volatile memory array of the ninth embodiment, a pair of flag storage semiconductor memories can be set to L sets, substantially as in the non-volatile memory array of the second embodiment. In this case, the refresh operation is performed at the shortest, when the row address is selected 2 ^L times, and at the longest, {(2 ^L −1) 2 M + 1} times. Further, the maximum number of disturbs received by the memory cells forming the non-volatile memory is (2 ^L −1) (2M) times after the completion of the previous refresh operation and before the start of the current refresh operation, and during the refresh operation (4
M-1) times, the maximum is {(2 ^L -1) 2M + (4M
-1)} times.

(Embodiment 10) Embodiment 10 relates to a nonvolatile memory array according to the fifth aspect of the present invention and a driving method thereof. FIG. 35 is a schematic partial cross-sectional view of the nonvolatile memory forming the nonvolatile memory array of the tenth embodiment taken along an imaginary vertical plane parallel to the bit line extending direction. FIG. FIG. 36 shows a schematic partial cross-sectional view when the is cut. Furthermore,
FIG. 37 shows a conceptual circuit diagram of the nonvolatile memory in the nonvolatile memory array of the tenth embodiment, FIG. 39 shows a more specific circuit diagram of the nonvolatile memory, and a conceptual diagram of the flag storage semiconductor memory. FIG. 38 shows a circuit diagram, and FIG. 40 shows a more specific circuit diagram of the flag storage semiconductor memory.

This non-volatile memory array includes a plurality (for example, K = 2 ⁷ ) of non-volatile memories and at least one (2 in the tenth embodiment, 2 and L = 2) flag storage semiconductor memories. Flag circuit (2 ^L-1 bit = 2 bit flag circuit). In the tenth embodiment, a pair of non-volatile memories M ₁ ,
M ₂ and a pair of flag storing semiconductor memories F ₁ and F ₂ are formed, and 1 bit is complementarily stored in a pair of memory cells having a common plate line. Also, the predetermined number of times is 2
^L (= 4 times).

Hereinafter, the kth nonvolatile memory array will be described.
Although the description will be given regarding the n-th (k is any of 1, 2, 3, ..., K) non-volatile memory, the subscript “k” representing the k-th non-volatile memory is omitted in the following description. To do. 37 to 38, a pair of non-volatile memories M ₁ and M ₂ and a pair of flag storage semiconductor memories F ₁ and F _{2 are shown.}
Although the nonvolatile memories M ₁ and M ₂ and the flag storing semiconductor memories F ₁ and F ₂ have the same structure, the nonvolatile memory M ₁ and the flag storing semiconductor memory F ₁ will be described below. Will be explained.

The nonvolatile memory M ₁ of the tenth embodiment is
(A) N (where N ≧ 2, N = 2 in the tenth embodiment) bit lines BL _1N , (B) N selection transistors TR _1N , and (C) respectively. M (however, M ≧ 2, and in the tenth embodiment, M =
8) N composed of memory cells MC _11M and MC _12M
Memory units MU _1N and (D) M plate lines PL _M.

Incidentally, in FIG. 37 and FIG. 38, the bit line BL ₁₁
, Selection transistor TR ₁₁ and memory cell MC _11M
The memory unit MU _11, which is composed of, expressed in the sub-unit SU _{1 1,} the bit line BL _12, the selection transistor TR _12, the memory unit MU _12, which is composed of the memory cells MC _12M, subunit SU ₁₂ The memory unit FU ₁₁ composed of the bit line FBL ₁₁ , the selection transistor FTR ₁₁ and the memory cell FC _11M is represented by the subunit FSU ₁₁ , and the bit line FBL ₁₂ , the selection transistor FTR ₁₂ and the memory The memory unit FU ₁₂ composed of the cell FC _{12M is} replaced with the subunit FSU.
_{Expressed as 12} .

Then, N memory units MU_1NIs
They are stacked with an insulating layer (interlayer insulating layer 26) interposed therebetween. each
The memory cell has a first electrode, a ferroelectric layer, and a second electrode.
Consists of. Specifically, the first (first layer) memory
Unit MU₁₁Memory cells MC configuring_11MIs the
From the first electrode 21, the ferroelectric layer 22, and the second electrode 23
And the second (second layer) memory unit MU₁₂To
Each constituting memory cell MC_12MIs stronger than the first electrode 31.
It is composed of a dielectric layer 32 and a second electrode 33. Furthermore, each
Memory unit MU_1nIn the memory cell MC_{1 nm}of
The first electrodes 21 and 31 are common. Specifically, the first
Th (first layer) memory unit MU ₁₁At
Morisell MC_11MThe first electrode 21 of is common. this
The common first electrode 21 is connected to the first common node CN₁₁Call
There are cases. In addition, the second (second layer) memory unit
MU₁₂In the memory cell MC_12MFirst electrode of
31 is common. This common first electrode 31 is connected to the second electrode
Common node CN₁₂Sometimes called. Furthermore, the nth
(Nth layer) (however, n = 1, 2, ..., N) memory
Unit MU_1n, The m-th (however, m = 1, 2
The second electrodes 23 and 33 of the memory cell of
Memory unit MU_1nThe m-th pre-shared between
Air line PL_mIt is connected to the. In the tenth embodiment
More specifically, each plate line has a second electrode 2
It extends from 3,33.

Nth (nth layer) (where n = 1, 2)
..., N) memory unit MU _1nCommon first in
The first electrode is the nth selection transistor TR._1nThrough
And then the nth bit line BL_1nIt is connected to the. Concrete
Specifically, the nth selection transistor TR_1nOne of
The source / drain region 14A is n-th through the connection hole 15.
Th bit line BL_1nConnected to the first selection gate
Langista TR₁₁The other source / drain region 14B
Through the connection hole 18 provided in the insulating layer 16
Layer memory unit MU₁₁Common first electrode in
21 (first common node CN₁₁)It is connected to the. Well
The second selection transistor TR ₁₂The other saw
The source / drain region 14B is connected to the insulating layer 16.
Provided in the continuous hole 18, the pad portion 25, and the interlayer insulating layer 26
The second layer memory unit through the connection hole 28 formed.
MU₁₂Common first electrode 31 (second common
De CN₁₂)It is connected to the.

Bit line BL_1nIs connected to the sense amplifier SA
Has been continued. Also, the plate line PL_MIs the plate line de
It is connected to the coder / driver PD. Furthermore,
Line WL₁, WL₂Is a word line decoder / driver WD
It is connected to the. Word line WL₁, WL₂Is shown in FIG.
It extends in the direction perpendicular to the page. In addition, the nonvolatile memory M ₁
Memory cell MC constituting the_11mThe second electrode 23 of FIG.
The non-volatile memories M adjacent to each other in the direction perpendicular to the paper of FIG.₂Construct
Memory cell MC_21mCommon with the second electrode of
Plate line PL_mDoubles as Furthermore, non-volatile memo
Re M₁Memory cell MC constituting the_12mSecond electrode 33 of
Is a non-volatile memory M adjacent in the direction perpendicular to the paper surface of FIG.
₂Memory cell MC constituting the_22mCommon to the second electrode of
, Plate line PL_mDoubles as These plates
Line PL_mAre connected in a region not shown.
Also, the word line WL₁Is a non-volatile memory M₁Make up
Selection transistor TR₁₁And in the direction perpendicular to the paper surface of FIG.
Adjacent non-volatile memory M₂Selection transitions that make up
Star TR_{twenty one}And are common. Furthermore, the word line WL
₂Is a non-volatile memory M₁Selection transistor
TR₁₂And non-volatile memory adjacent in the direction perpendicular to the paper surface of FIG.
Mori M₂Selection transistor TR_{twenty two}Common with
Is.

On the other hand, the flag storing semiconductor memory F ₁ of the tenth embodiment has (A) N (where N ≧ 2, N = 2 in the tenth embodiment) bit lines FBL _1N.
And (B) N selection transistors FTR _1N ,
(C) M memory cells FC _11M and F (where M ≧ 2, and M = 8 in the tenth embodiment).
N memory units FU composed of C _12M
1N and (D) M plate lines PL _M.

Then, the N memory units FU_1NIs
They are stacked with an insulating layer (interlayer insulating layer 26) interposed therebetween. each
The memory cell has a first electrode, a ferroelectric layer, and a second electrode.
Consists of. Specifically, the first (first layer) memory
Unit FU₁₁Each memory cell FC that composes_11MIs the
From the first electrode 21, the ferroelectric layer 22, and the second electrode 23
And the second (second layer) memory unit FU₁₂To
Each memory cell FC_12MIs stronger than the first electrode 31.
It is composed of a dielectric layer 32 and a second electrode 33. Furthermore, each
Memory unit FU_1nIn memory cell FC_{1 nm}of
The first electrodes 21 and 31 are common. Specifically, the first
Th (first layer) memory unit FU ₁₁At
Morisell FC_11MThe first electrode 21 of is common. this
The common first electrode 21 is connected to the first common node FCN.₁₁Call
There are cases where In addition, the second (second layer) memory unit
Knit FU₁₂In memory cell FC_12MThe first electric
The pole 31 is common. This common first electrode 31
Common node FCN₁₂Sometimes called. Furthermore, the nth
The th (nth layer) (however, n = 1, 2, ..., N) message
Mori Unit FU_1n, The m-th (however, m =
1, 2, ..., M) second electrodes 23, 3 of the memory cells
3 is a memory unit FU_1nM-th common between
Plate line PL_mIt is connected to the. Embodiment 10
In, more specifically, each plate line is
It extends from the electrodes 23, 33.

Nth (nth layer) (however, n = 1, 2
..., N) memory unit FU _1nCommon first in
The first electrode is the nth selection transistor TR._1nThrough
And then the nth bit line FBL_1nIt is connected to the. Ingredient
Physically, it is the nth selection transistor FTR._1nOne
One of the source / drain regions 14A is connected via the connection hole 15.
Nth bit line FBL_1nConnected to the first choice
Selection transistor FTR₁₁Other source / drain region
The area 14B is formed through the connection hole 18 provided in the insulating layer 16.
The first layer memory unit FU₁₁Common first in
1 electrode 21 (first common node FCN₁₁) Is connected to
ing. In addition, the second selection transistor FTR₁₂
The other source / drain region 14B of the
Provided connection hole 18, pad portion 25, and interlayer insulation
Through the connection hole 28 provided in the layer 26, the second layer
Mori Unit FU₁₂Common first electrode 31 (first
2 common nodes FCN₁₂)It is connected to the.

The bit line FBL _1n is connected to the sense amplifier FSA.
Connected to ₁ . Further, the plate line PL _M is connected to the plate line decoder / driver PD. Furthermore,
The word lines WL ₁ and WL ₂ are connected to the word line decoder / driver WD. The word lines WL ₁ and WL ₂ are shown in FIG.
6 extends in the direction perpendicular to the paper surface. The second electrode 23 of the memory cell FC _11m forming the flag storing semiconductor memory F ₁ is the second electrode of the memory cell FC _21m forming the flag storing semiconductor memory F ₂ which is adjacent in the direction perpendicular to the paper surface of FIG.
Of the non-volatile memories M ₁ and M ₂
It is also common to the second electrodes of the memory cells MC _11m and MC _21m constituting the _above, and also serves as the plate line PL _m . Furthermore,
Memory cell F which constitutes the flag storing semiconductor memory F _1.
The second electrode 33 of C _12m is common to the second electrode of the memory cell FC _22m constituting the flag storing semiconductor memory F ₂ which is adjacent in the direction perpendicular to the paper surface of FIG. 36, and is a non-volatile memory M ₁ , M. It is common to the second electrodes of the memory cells MC _12m and MC _22m forming the _second cell 2 and also serves as the plate line PL _m . These plate lines PL _m are connected in a region (not shown). The word line WL ₁ includes a selection transistor FTR ₁₁ that constitutes the flag storage semiconductor memory F ₁ and a selection transistor FTR that constitutes the flag storage semiconductor memory F ₂ that is adjacent in the direction perpendicular to the paper surface of FIG.
It is common to TR _21, and further, non-volatile memory M ₁ ,
It is also common to the selection transistors TR ₁₁ and TR ₂₁ forming M ₂ . In addition, the word line WL ₂ has a selection transistor FTR ₁₂ that constitutes the flag storage semiconductor memory F _1.
And the selection transistor FTR ₂₂ that constitutes the flag storage semiconductor memory F ₂ adjacent to each other in the direction perpendicular to the paper surface of FIG. 36, and further that the selection transistor TR that constitutes the nonvolatile memories M ₁ and M _{2. 12} and TR ₂₂ are common.

In the non-volatile memory array whose circuit diagrams are shown in FIGS. 37 and 38, the selection transistor TR _1n forming the non-volatile memory M ₁ , the selection transistor TR _2n forming the non-volatile memory M ₂ , and the flag storage. The selection transistor FTR _1n forming the semiconductor memory F ₁ for selection and the selection transistor FTR _2n forming the semiconductor memory F ₂ for storing a flag are connected to the word line WL _n . Then, a pair of memory cells MC _11m and MC _12m (m = 1, 2, ..., M) in the non-volatile memory M ₁ ,
A pair of memory cells MC in the non-volatile memory M ₂ .
_{21 m} and MC _{22 m} store complementary 1-bit data. Further, the paired memory cells FC _11m and MC _12m (m = 1, 2 ... In the flag storing semiconductor memory F ₁₎
, M) and complementary memory cells FC _21m and MC _{22m in} the flag storing semiconductor memory F ₂ store complementary 1-bit data.

The method of reading data from the nonvolatile memory of the tenth embodiment and rewriting it can be substantially the same as that described in the fourth embodiment.
A detailed description is omitted, and only the operation of the flag circuit will be described below. The operation of the nonvolatile memory array of the tenth embodiment is substantially the same as the operation of the nonvolatile memory array described in the sixth embodiment, except that the flag circuit has a 2-bit configuration. is there. In the following description, it is assumed that the mth row address is selected.
Here, the column address may have any value, and either the non-volatile memory M ₁ or the non-volatile memory M ₂ may be selected.

In each of the flag storing semiconductor memories F ₁ and F ₂ , 1 bit is stored complementarily, and data (0, 0) is stored in the initial state. Specifically, paired memory cells (FC _11m , FC _12m ), (F in the flag storing semiconductor memories F ₁ , F ₂ respectively)
C _21m , FC _22m ) stores complementary 1-bit data “0”. Further, the memory cell (F in which a pair of semiconductor memory F _1, F ₂ for flag storage
C _12m , FC _22m ) also stores complementary 1-bit data “0”. Note that such a state is expressed as storing data (0,0).

Kth column address, mth column address
Low address, non-volatile memory M ₁, M₂For example
Non-volatile memory M₁Is selected, and the plate line PL_mTo pal
Given a non-volatile memory M₁Mth memory of
Cell MC_11m, MC_12mThe data stored in
At the same time when read out to the SA
Body memory F₁, F₂Memory cell (FC_11m, FC
_12m), (FC_21m, FC_22mData stored in ()
Bit data) is also sense amplifier FSA₁, FSA₂Read to
To be found. And the sense amplifier FSA₁, FSA₂To
The read data is sent to the flag determination circuit FG,
Flag determination is made. Memory cell (FC_11m, F
C_12m), (FC_21m, FC_22m) The data stored in
Since it is (0, 0), in the flag determination circuit FG
Is a semiconductor memory for storing flags that constitutes a flag circuit.
It is determined that the memory cells need not be initialized. Sense amplifier
FSA₁, FSA₂The data read to the
Ink sent to the increment circuit INC
It is remented and becomes (0, 1). This data (0,
1) is held in the register RS.

When the data is rewritten in the memory cells MC _11m and MC _12m , the data (0, 1) held in the register RS becomes the flag storing semiconductor memory F ₁ ,
_Paired memory cells in F ₂ (FC _11m , F
C _12m ), (FC _21m , FC _22m ). By the above operation, if the m-th row address is selected, in the low semiconductor memory for storing a flag relating to the address _{F 1, F 2 (FC 11m} , FC 12m), (F
The data stored in C _21m , FC _22m ) is in the initial state (0,
It changes from 0) to (0, 1).

For example, next, when the m'th (m '≠ m) row address is selected, the memory cells (FC _{11m' in the} flag storing semiconductor memories F ₁ and F ₂ related to this row address are selected). , FC _{12m '} ), (FC _21m' , FC
_{22m '} ) changes from the initial state. That is, any row address can be randomly accessed.

When the m-th row address is selected again (the column address may have any value, either the nonvolatile memory M ₁ or the nonvolatile memory M ₂ may be selected, The second row address selection at the m-th row address), data (1,
0) is the memory cells (FC _11m , FC _12m ), (FC _21m , FC _22m ) in the flag storing semiconductor memories F ₁ , F ₂ .
Written in. When the m-th row address is further selected again (the column address may be any value, either the nonvolatile memory M ₁ or the nonvolatile memory M ₂ may be selected, the m-th row address may be selected). Data (1, 1) in the third row address selection of the row address of the memory cells (FC _11m , FC _12m ), (FC _21m ) in the flag storing semiconductor memories F ₁ , F ₂ . F
C _22m ). When the m-th row address is further selected again (the column address may be any value, either the nonvolatile memory M ₁ or the nonvolatile memory M ₂ may be selected, the m-th row address may be selected). The low
If the fourth row address selection in the address is performed, that is, the mth row address is selected 2 ^L times (specifically, 4 times), the memory cell (FC _11m ,
Since the data stored in FC _12m ) and (FC _21m , FC _22m ) are (1, 1), in the flag determination circuit FG, the initialization of the memory cell of the flag storage semiconductor memory which constitutes the flag circuit is performed. Is judged necessary. The data read to the sense amplifiers FSA ₁ and FSA ₂ are
It is sent to the increment circuit INC, and the data is incremented by 1 to become (0, 0). This data (0,
0) is held in the register RS.

Then, when the rewriting of data to the memory cells forming the nonvolatile memory is completed, all the memory cells in all the nonvolatile memories forming the nonvolatile memory array (the m-th memory cell is (Excluding) is performed. Specifically, the fourth embodiment
The operations (1) to (10) are sequentially performed on all memory cells except the m-th memory cell.

On the other hand, in the flag circuit, the fourth row address selection at the m-th row address is performed, and the data is held in the register RS when the data is rewritten to the memory cells forming the nonvolatile memory. The existing data (0, 0) is written in the memory cells (FC _11m , FC _12m ) and (FC _21m , FC _22m ) in the flag storing semiconductor memories F ₁ and F ₂ by the sense amplifiers FSA ₁ and FSA ₂ . In addition, when the refresh operation of all the memory cells (excluding the m-th memory cell) in all the nonvolatile memories forming the nonvolatile memory array is performed, the memory cells in the flag storing semiconductor memories F ₁ and F ₂ are The data (0, 0) which is the initial value is written into all the memory cells except (FC _11m , FC _12m ) and (FC _21m , FC _22m ) via the sense amplifiers FSA ₁ and FSA ₂ .
As a result, the memory cells of the flag storing semiconductor memory forming the flag circuit are initialized.

In the nonvolatile memory array of the tenth embodiment, the refresh operation is performed at the shortest,
If the row address is selected four times, the longest
This is the case where the address is selected (3M + 1) times. In addition, the maximum number of disturbances received by the memory cells forming the non-volatile memory is 3 (M−M) from the completion of the previous refresh operation to the start of this refresh operation.
1) times, (M-1) times during the refresh operation, which is a maximum of 4 (M-1) times in total.

Also in the non-volatile memory array of the tenth embodiment, a pair of flag storing semiconductor memories can be set in L groups, substantially as in the non-volatile memory array of the second embodiment. In this case, the refresh operation is performed at the shortest, when the row address is selected 2 ^L times, and at the longest, {(2 ^L −1) M + 1} times. In addition, the maximum number of disturbs received by the memory cells constituting the non-volatile memory is (2 ^L -1) (M-1) times after the completion of the last refresh operation and before the start of the current refresh operation during the refresh operation. (M-1) times, and the maximum is 2 ^L (M-1) times.

As shown in the conceptual circuit diagrams of FIGS. 41 and 42, the bit line B which constitutes the nonvolatile memory M _1.
L ₁₁ and the bit line BL ₂₁ that constitutes the nonvolatile memory M _2.
May be connected to the sense amplifier SA ₁ , and the bit line BL ₁₂ forming the nonvolatile memory M ₁ and the bit line BL ₂₂ forming the nonvolatile memory M ₂ may be connected to the sense amplifier SA ₂ .

(Eleventh Embodiment) The eleventh embodiment is a modification of the tenth embodiment. In the eleventh embodiment,
A pair of nonvolatile memories M ₁ and M ₂ and a pair of flag storing semiconductor memories F ₁ and F ₂ are formed, and 1 bit is stored in each of a pair of memory cells having a common plate line. The number of flag storing semiconductor memories is L = 2, and the predetermined number of times is 2 ^L (= 4 times). That is, the flag circuit has a 2-bit configuration.

The conceptual circuit diagram of the non-volatile memory and the flag circuit in the non-volatile memory array in the eleventh embodiment, and the specific circuit diagram of the non-volatile memory and the flag circuit are the same as those in FIGS. 37 to 40. 35 and 36 are schematic partial sectional views when the nonvolatile memory and the flag storage semiconductor memory of the eleventh embodiment are cut along a virtual vertical plane parallel to the extending direction of the bit lines. Since the same can be applied, detailed description will be omitted.

Since the method of reading data from the non-volatile memory of the eleventh embodiment and rewriting it can be substantially the same as that described in the fifth embodiment,
A detailed description is omitted, and only the operation of the flag circuit will be described below. The operation of the nonvolatile memory array of the eleventh embodiment is substantially the same as the operation of the nonvolatile memory array described in the seventh embodiment, except that the flag circuit has a 2-bit configuration. is there. In the following description, it is assumed that the memory cell MC _1nm of the nonvolatile memory M ₁ is selected. Here, in the flag circuit, any value of the column address may be selected, and either the nonvolatile memory M ₁ or the nonvolatile memory M ₂ may be selected. Here, the m-th plate line corresponds to a “certain plate line”.

A pair of flag storing semiconductor memories F ₁ and F ₂
In each of the above, 1 bit is stored, and data “0” is stored in the initial state. Memory cell MC
_11m is selected, a pulse is given to the plate line PL _m ,
When the data stored in the memory cell MC _11m of the nonvolatile memory M ₁ is read by the sense amplifier SA, at the same time,
The data stored in the memory cells (FC _11m , FC _21m ) in the flag storing semiconductor memories F ₁ , F ₂ are also read by the sense amplifiers FSA ₁ , FSA ₂ . Then, the data read to the sense amplifiers FSA ₁ and FSA ₂ is sent to the flag determination circuit FG, and the flag determination is performed. The data stored in the memory cells (FC _11m , FC _21m ) is (0,
Therefore, in the flag determination circuit FG, it is determined that the initialization of the memory cell of the flag storage semiconductor memory forming the flag circuit is unnecessary. Sense amplifier FSA
_The data read by ₁ and FSA ₂ are simultaneously sent to the increment circuit INC, and the data is incremented by 1 to become (0, 1). This data (0, 1) is held in the register RS.

Then, the memory cell MC_11mDay in
Data retained in register RS when rewriting
(0, 1) is the flag storage semiconductor memory F₁, F₂To
Memory cell (FC_11m, FC_21m) Is written.
By the above operation, the nonvolatile memory M₁Memory cells
MC_11mIf is selected, semiconductor memory for flag storage
F ₁, F₂Memory cell (FC_11m, FC_21m)
The stored data is from (0,0) in the initial state to (0,1)
Changes to.

For example, next, when the m'th (m '≠ m) row address is selected, the memory cells (FC _{1nm' in the} flag storing semiconductor memories F ₁ and F ₂ related to this row address are selected). , FC _{2nm '} ) changes from the initial state. That is, any row address can be randomly accessed.

When the m-th row address is selected again (the column address may have any value, either the nonvolatile memory M ₁ or the nonvolatile memory M ₂ may be selected, The second row address selection at the m-th row address), data (1,
0) is written in the memory cells (FC _11m , FC _21m ) in the flag storing semiconductor memories F ₁ , F ₂ . When the m-th row address is further selected again (the column address may have any value, either the nonvolatile memory M ₁ or the nonvolatile memory M ₂ may be selected, the m-th row address may be selected). Of the third row address selection), data (1, 1) are the memory cells (FC) of the flag storing semiconductor memories F ₁ , F ₂ .
_11m , FC _21m ). When the m-th row address is further selected again (the column address may have any value, either the nonvolatile memory M ₁ or the nonvolatile memory M ₂ may be selected, the m-th row address may be selected). When the m-th row address is selected 2 ^L times (specifically, 4 times), the memory cell (FC
_Since the data stored in ( _11m , FC _21m ) is (1, 1), in the flag determination circuit FG, it is determined that the memory cells of the flag storage semiconductor memory forming the flag circuit need to be initialized. . Sense amplifiers FSA ₁ and FSA ₂
At the same time, the data read out is sent to the increment circuit INC, where the data is incremented by 1,
It becomes (0, 0). This data (0,0) is stored in the register R
Hold at S.

Then, when the rewriting of data to the memory cell MC _11m of the non-volatile memory M ₁ is completed, all the memory cells in all the non-volatile memories constituting the non-volatile memory array (the m-th memory (Excluding cells)
Refresh operation is performed. Specifically, the operations (1) to (10) of the fifth embodiment are sequentially performed on all memory cells except the m-th memory cell.

On the other hand, in the flag circuit, when data is rewritten to the memory cell MC _11m of the nonvolatile memory M ₁ ,
The data (0, 0) held in the register RS is stored in the memory cells (FC _11m , FC) in the flag storing semiconductor memories F ₁ , F ₂ by the sense amplifiers FSA ₁ , FSA ₂ .
_21m ) will be written. In addition, when the refresh operation of all the memory cells (excluding the first memory cell) in all the nonvolatile memories forming the nonvolatile memory array is performed, the memory cells in the flag storing semiconductor memories F ₁ and F ₂ are The initial value data “0” is set in the sense amplifier F in all memory cells except (FC _11m , FC _21m ).
It is written via SA ₁ and FSA ₂ . by this,
Initialization of the memory cells of the flag storage semiconductor memory that configures the flag circuit is performed.

In the nonvolatile memory array of the eleventh embodiment, the refresh operation is performed at the shortest,
If the row address is selected four times, the longest
This is the case where the address is selected (6M + 1) times. In addition, the maximum number of disturbs received by the memory cells constituting the non-volatile memory is 3 (2 M
-1) times, (2M-1) times during the refresh operation, which is a maximum of 4 (2M-1) times in total.

Also in the non-volatile memory array of the eleventh embodiment, a pair of flag storage semiconductor memories can be set in L groups, substantially as in the non-volatile memory array of the second embodiment. In this case, the refresh operation is performed at the shortest, when the row address is selected 2 ^L times, and at the longest, {(2 ^L −1) 2 M + 1} times. In addition, the maximum number of disturbs received by the memory cells constituting the non-volatile memory is (2 ^L -1) (2 M -1) times after the completion of the previous refresh operation and before the start of the current refresh operation during the refresh operation. a (2M-1) times the maximum, 2 ^L (2M-1) times.

Note that, as shown in the conceptual circuit diagrams of FIGS. 41 and 42, the bit line B which constitutes the nonvolatile memory M _1.
L ₁₁ and the bit line BL ₂₁ that constitutes the nonvolatile memory M _2.
May be connected to the sense amplifier SA ₁ , and the bit line BL ₁₂ forming the nonvolatile memory M ₁ and the bit line BL ₂₂ forming the nonvolatile memory M ₂ may be connected to the sense amplifier SA ₂ .

(Embodiment 12) Embodiment 12 relates to a nonvolatile memory array according to a sixth aspect of the present invention and a driving method thereof. The structure and configuration of the non-volatile memory according to the twelfth embodiment can be substantially the same as the structure and configuration of the non-volatile memory according to the sixth embodiment, and detailed description thereof will be omitted.

This non-volatile memory array includes a plurality (for example, K = 2 ⁷ ) of non-volatile memories and at least one (1 in the twelfth embodiment, 1 and L = 1) semiconductor memory for storing flags. Flag circuit (2 ^L-1 bit = 1 bit flag circuit).

In the twelfth embodiment, a pair of non-volatile memories M ₁ and M ₂ and a pair of flag storing semiconductor memories F ₁ and F ₂ are formed, and a pair of memory cells having a common plate line. 1 bit is complementarily stored in. The number of the semiconductor memory for storing a flag is 2L, the predetermined number of times 2 ^L
Is.

FIG. 43 shows a conceptual circuit diagram of a flag circuit forming the nonvolatile memory array in the twelfth embodiment. The more specific circuit diagram of the flag circuit in the conceptual circuit diagram of FIG. 43 is similar to that shown in FIG. Also,
A schematic partial cross-sectional view of the flag storage semiconductor memory of the eighth embodiment taken along a virtual vertical plane parallel to the extending direction of the bit lines is similar to that shown in FIG. Therefore, detailed description is omitted.

Since the method of reading data from the non-volatile memory of the twelfth embodiment and rewriting it can be substantially the same as that described in the fourth embodiment,
Detailed description is omitted. Further, the operation of the flag circuit can be the same as that described in the eighth embodiment, and detailed description thereof will be omitted.

In the nonvolatile memory array of the twelfth embodiment,
In addition, a pair of non-volatile memory M ₁, M₂And flag case
Delivered semiconductor memory F₁, F₂And the plate line
1 bit for each of a pair of common memory cells
Can also be stored. In this case, the semiconductor for flag storage
The number of body memories is 2L, and the predetermined number of times is 2.^LIs. F
The lag circuit has a 1-bit configuration.

The circuit diagram of the flag circuit in the nonvolatile memory array having such a configuration is similar to that of FIG. In addition, the operation of the nonvolatile memory array having such a configuration is
The operation of the non-volatile memory array described in the ninth embodiment can be substantially the same as that of the ninth embodiment, and detailed description thereof will be omitted.

Although the present invention has been described based on the embodiments of the present invention, the present invention is not limited to these. The structure of the nonvolatile memory described in the embodiments of the invention, the materials used, various forming conditions, circuit configurations, driving methods, etc. are merely examples, and can be changed as appropriate.

The value of M is not limited to 8. The value of M is M
It is only necessary to satisfy ≧ 2, and as a practical value of M, for example, a power of 2 (2, 4, 8, 16 ...) Can be cited. Further, the value of N only needs to satisfy N ≧ 2, and as a practical value of N, for example, a power of 2 (2,
4, 8 ...).

Generally, when the total number of signal lines for driving the unit unit is A, the number of word lines is B, and the number of plate lines is C, A = B + C. Here, when the total number A is constant, B = C may be satisfied in order to maximize the total number of addresses (= B × C) of the unit unit. Therefore, in order to arrange the peripheral circuits most efficiently, the number of word lines B and the number of plate lines C in the unit unit should be equal. Also, the number of word lines in the row address access unit unit matches, for example, the number of stacked stages of memory cells (N), and the number of plate lines matches the number of memory cells (M) forming the memory unit. The greater the number of word lines and the number of plate lines, the higher the degree of integration of the non-volatile memory. However, it is necessary to determine the values of N, M, and L based on the upper limit value of the number of times of disturb so that the data stored in the memory cell is not destroyed.

The nonvolatile memory described in the sixth or seventh embodiment can be modified to have the structure shown in FIG. The circuit diagram is shown in FIG.

This non-volatile memory has a sense amplifier SA.
N (where N ≧ 2, N = 4 in this example) selection transistors TR ₁₁ , TR ₁₂ and T each composed of a bit line BL ₁ connected to
R ₁₃ and TR ₁₄ and N memory units MU ₁₁ and M
It is composed of U ₁₂ , MU ₁₃ , and MU ₁₄ and a plate line. The first layer memory unit MU ₁₁ has M (however,
M ≧ 2, and in this example, it is composed of M = 8) memory cells MC _11m (m = 1, 2, ..., 8). The second-layer memory unit MU ₁₂ also has M (M = 8) memory cells MC _12m (m = 1, 2 ...
8). Further, the memory unit MU ₁₃ of the third layer also has M (M = 8) memory cells MC _13m.
(M = 1, 2, ..., 8), and the memory unit MU _{14 in} the fourth layer is also M (M = 8) memory cells M.
It is composed of C _14m (m = 1, 2, ..., 8).
The number of plate lines is M (8 in this example) and is represented by PL _m (m = 1, 2, ..., 8). The word line WL _1n connected to the gate electrode of the selection transistor TR _1n is connected to the word line decoder / driver WD. On the other hand, each plate line PL _m is connected to the plate line decoder / driver PD.

The memory unit MU of the first layer₁₁To
Each constituting memory cell MC_11mWith the first electrode 21A
The ferroelectric layer 22A and the second electrode 23, and the second layer
Eye memory unit MU₁₂Memory cells MC configuring
_12mIs the first electrode 21B, the ferroelectric layer 22B and the second
The memory unit MU of the third layer, which includes the electrode 23 ₁₃
Memory cells MC configuring_13mIs the first electrode 31A
And a ferroelectric layer 32A and a second electrode 33,
Layer memory unit MU₁₄Each memory cell M constituting the
C_14mIs the first electrode 31B, the ferroelectric layer 32B, and the second electrode 31B.
Electrode 33. Then, each memory unit MU
₁₁, MU₁₂, MU₁₃, MU₁₄In the memory cell
One electrode 21A, 21B, 31A, 31B is common
It This common first electrode 21A, 21B, 31A, 3
1B is a common node CN for convenience.₁₁, CN₁₂, CN₁₃，
CN₁₄Call.

Here, the first layer memory unit MU ₁₁
Common first electrode 21A (first common node C
N ₁₁ ) is connected to the bit line BL ₁ via the first selection transistor TR ₁₁ . Further, the common first electrode 21B in the memory unit MU ₁₂ of the second layer
The (second common node CN ₁₂ ) is connected to the bit line BL ₁ via the second selection transistor TR ₁₂ . Further, the common first electrode 31A (third common node CN ₁₃ ) in the memory unit MU ₁₃ of the third layer
Is connected to the bit line BL ₁ through the third selection transistor TR ₁₃ . Further, the common first electrode 31B in the fourth layer of the memory unit MU ₁₄ (4th
Common node CN ₁₄ ) is connected to the bit line BL ₁ via the fourth selection transistor TR ₁₄ .

The memory unit MU of the first layer₁₁To
Memory cell MC_11mAnd the memory unit of the second layer
MU₁₂Memory cell MC constituting the_12mIs the second power
Shares pole 23 and shares this mth second
Electrode 23 is plate line PL _mIt is connected to the. Further
Is the memory unit MU of the third layer₁₃The memory that makes up
Cell MC_13mAnd the memory unit MU of the fourth layer₁₄Construct
Memory cell MC_{1 4m}Share the second electrode 33
And the shared m-th second electrode 33 is
Rate line PL_mIt is connected to the. Specifically, this
Play from the extension of the mth second electrode 23
Line PL_mIs shared and this shared m-th second
From the extending portion of the electrode 33 of the plate line PL_mIs configured
Cage, each plate line PL_mAre connected in the area not shown
ing.

In this non-volatile memory, the memory unit
Knit MU₁₁, MU₁₂And memory unit MU₁₃, MU₁₄
Are laminated via an insulating layer (interlayer insulating layer 26).
It Memory unit MU₁₄Is covered with an insulating film 36A
There is. In addition, the memory unit MU₁₁Is the semiconductor substrate 10
Is formed above the insulating layer 16 via the insulating layer 16. Semiconductor substrate
An element isolation region 11 is formed on the plate 10. Also,
Selection transistor TR ₁₁, TR₁₂, TR₁₃, TR
₁₄Is the gate insulating film 12, the gate electrode 13, the source / drain
It is composed of rain regions 14A and 14B. That
The first selection transistor TR₁₁, The second selection
Langista TR₁₂, Third selection transistor TR₁₃,
Fourth selection transistor TR₁₄One source / drain
The in-region 14A is connected through the connection hole (contact hole) 15.
Bit line BL₁It is connected to the. Also, the first choice
Selection transistor TR₁₁Source / drain region of the other
14B is provided in the opening formed in the insulating layer 16.
Via the connection hole 18₁₁Connected to
Has been. Furthermore, the second selection transistor TR₁₂of
The other source / drain region 14B is connected via the connection hole 18.
And the second common node CN₁₂It is connected to the. Also,
Third selection transistor TR₁₃Other source / drain
The in-region 14B includes the connection hole 18, the pad portion 25, and the interlayer insulation.
Connection hole 28 provided in the opening formed in the edge layer 26
Via the third common node CN₁₃It is connected to the. Change
Includes a fourth selection transistor TR₁₄The other source of
The / drain region 14B includes the connection hole 18, the pad portion 25,
The fourth common node CN via the connection hole 28₁₄Connected to
ing.

The structure of the nonvolatile memory described above is as follows.
It can also be applied to the non-volatile memory in the other embodiments of the invention.

The non-volatile memory of the present invention may be of so-called gain cell type. FIG. 46 shows a circuit diagram of an example of such a non-volatile memory, FIG. 47 shows a schematic layout of various transistors constituting the non-volatile memory, and a schematic partial cross-sectional view of the non-volatile memory. 48 and 49. Note that in FIG. 47, regions of various transistors are surrounded by dotted lines, active regions and wirings are shown by solid lines, and gate electrodes or word lines are shown by dashed lines.
A schematic partial cross-sectional view of the nonvolatile memory shown in FIG. 48 is a schematic partial cross-sectional view taken along the line AA of FIG. 47, and a schematic partial cross-sectional view of the nonvolatile memory shown in FIG. The partial cross-sectional view is a schematic partial cross-sectional view taken along the line BB of FIG. 47.

The case where the gain cell type is applied to the nonvolatile memory of the first embodiment will be described below. This non-volatile memory includes, for example, a bit line BL, a writing transistor (which is a selection transistor in the non-volatile memory of each embodiment) TR _W , and M (however, M ≧ 2, for example, A memory unit MU composed of M = 8) memory cells MC _M and M plate lines PL _M. Then, each memory cell MC _m has a first electrode 21
It consists DOO ferroelectric layer 22 and a second electrode 23, first electrode 21 of the memory cells MC _M constituting the memory unit MU is common in the memory unit MU, the common first electrode ( The common node CN) is connected to the bit line BL via the writing transistor TR _W, and the second electrode 23 forming each memory cell MC _m is a plate line P.
It is connected to L _m . The memory cell MC _M is an insulating film 26A.
Is covered by. Note that the number (M) of memory cells forming the memory unit MU of the nonvolatile memory is not limited to eight, and in general, M ≧ 2 should be satisfied, and a power of 2 (M = 2, 4, 4). 8 and 16 ...) is preferable.

Further, a signal detection circuit for detecting a potential change of the common first electrode and transmitting the detection result to the bit line as a current or a voltage is provided. In other words, the detection transistor TR _D and the reading transistor TR _R are provided. The signal detection circuit is a detection transistor TR.
_D and a read transistor TR _R. Then, one end of the detection transistor TR _D has a predetermined potential V
_The data stored in each memory cell MC _m is connected to a wiring having _cc (for example, a power supply line formed of an impurity layer) and the other end is connected to a bit line BL via a read transistor TR _R. When read transistor TR
_R is rendered conductive, and the potential of the common first electrode (common node CN) generated based on the data stored in each memory cell MC _m controls the operation of the detection transistor TR _D.

Specifically, various transistors are MOS
One of the source / drain regions of the writing transistor (selecting transistor) TR _W is connected to the bit line BL through a connection hole (contact hole) 15 formed in the insulating layer 16. The other source / drain region is connected to a common first electrode (common node CN) via a connection hole 18 provided in an opening formed in the insulating layer 16. Further, one source / drain region of the detecting transistor TR _D is connected to a wiring having a predetermined potential V _cc , and the other source / drain region is connected to one source / drain region of the reading transistor TR _R. Has been done. More specifically, the other source / drain region of the detection transistor TR _D and one source / drain region of the read transistor TR _R occupy one source / drain region.
Further, the other source / drain region of the read transistor TR _R is connected to the bit line BL via a connection hole (contact hole) 15, and further, a common first electrode (common node CN or write). The other source / drain region of the use transistor TR _W is connected to the gate electrode of the detection transistor TR _D via the connection hole 18A provided in the opening and the word line WL _D. The word line WL _W connected to the gate electrode of the writing transistor TR _W and the word line WL _R connected to the gate electrode of the reading transistor TR _R are connected to the word line decoder / driver WD. On the other hand, each plate line PL
_m is connected to the plate line decoder / driver PD. Further, the bit line BL is connected to the sense amplifier SA.

For example, the memory cell M of this nonvolatile memory
When reading data from C ₁ , V _cc is applied to the selected plate line PL ₁ . At this time, if data “1” is stored in the selected memory cell MC ₁ , polarization inversion occurs in the ferroelectric layer, the amount of accumulated charge increases, and the potential of the common node CN rises. On the other hand, the data “0” is stored in the selected memory cell MC _1.
Is stored, the polarization inversion does not occur in the ferroelectric layer,
The potential of the common node CN hardly rises. That is, since the common node CN is coupled to the plurality of non-selected plate lines PL _j via the ferroelectric layer of the non-selected memory cell, the potential of the common node CN is kept at a level relatively close to 0 volt. Be drunk In this way, the selected memory cell MC
The potential of the common node CN changes depending on the data stored in ₁ . Therefore, a sufficient electric field for polarization reversal can be applied to the ferroelectric layer of the selected memory cell. Then, the bit line BL is brought into a floating state and the reading transistor TR _R is turned on.

On the other hand, the selected memory cell MC₁Remembered by
To the common first electrode (common node CN) based on the data
Depending on the generated potential, the detection transistor TR_DThe operation of
Controlled. Specifically, the selected memory cell MC₁Remember
The common first electrode (common node C
If a high potential occurs in N), the detection transistor TR _D
Becomes conductive, and the detection transistor TR_DOne of
The source / drain region has a predetermined potential V_ccTo the wiring that has
Since it is connected, the transition for detection is
Star TR_DAnd read transistor TR_RA bit through
A current flows through the line BL and the potential of the bit line BL rises.
That is, the common first electrode (common node)
The change in the electrical potential of the
The voltage (potential) is transmitted to the power line BL. Where the inspection
Output transistor TR_DThe threshold of V_{t h}, Detection transistor
Star TR_DPotential of the gate electrode (that is, the common node CN
Potential)_gIf so, the potential of the bit line BL is approximately
(V_g-V_th). The detection transistor TR_DTo
If a depletion type NMOSFET is used, the threshold value V
_thTakes a negative value. As a result, the load on the bit line BL
A stable sense signal amount can be secured regardless of the size.
The detection transistor TR_DFrom PMOSFET
It can also be done.

The predetermined potential of the wiring to which one end of the detection transistor is connected is not limited to V _cc , but may be grounded, for example. That is, the predetermined potential of the wiring to which one end of the detection transistor is connected may be 0 volt.
However, in this case, when the potential (V _cc ) appears on the bit line when reading the data in the selected memory cell, the potential of the bit line is set to 0 volt when rewriting, and 0 when reading the data in the selected memory cell. When the volt appears on the bit line, it is necessary to set the potential of the bit line to V _cc when rewriting. To this end, transistors TR _IV-1 , TR _IV-2 , TR as illustrated in FIG.
A kind of switch circuit (a kind of inverting circuit) composed of _IV-3 and TR _IV-4 is arranged between bit lines, and when reading data, the transistors TR _IV-2 and TR _IV-4 are turned on. ， When rewriting data, transistor TR
_IV-1 and TR _IV-3 may be turned on.

Further, for example, as shown in FIG. 51, as a modified example of the nonvolatile memory of the sixth or seventh embodiment, the first electrodes 21 'and 31' are upper electrodes,
The second electrodes 23 'and 33' can also be used as lower electrodes. Such a structure can also be applied to the nonvolatile memory according to the other embodiments of the invention.

According to the present invention, if a plurality of non-volatile memory arrays are arranged, that is, if a multi-bank is provided, refresh operation in another non-volatile memory array can be performed during access to the non-volatile memory array. Becomes Further, by using the non-volatile memory array together with the cache memory, it is possible to reduce the frequency of access to the same row address and reduce the overhead caused by the refresh operation.

[0316]

According to the present invention, since the flag circuit composed of the flag storing semiconductor memory is provided, the ferroelectric non-volatile semiconductor memory is suppressed while suppressing a decrease in access speed to the ferroelectric non-volatile semiconductor memory. It is possible to greatly improve the random access performance to, and it is possible to dramatically expand the application and application market.
Moreover, the increase in the manufacturing cost of the ferroelectric non-volatile semiconductor memory array and the decrease in the degree of integration are negligible.
Further, since data is read and written from the flag storage semiconductor memory at the same time as reading and rewriting data from the ferroelectric non-volatile semiconductor memory, the operation speed is reduced due to the presence of the flag storage semiconductor memory. Will not invite.

[Brief description of drawings]

FIG. 1 is a schematic partial cross-sectional view of a ferroelectric non-volatile semiconductor memory according to a first embodiment of the invention when cut along a virtual vertical plane parallel to a direction in which a bit line extends.

FIG. 2 is a schematic partial cross-sectional view of the flag storing semiconductor memory according to the first embodiment of the invention when cut along a virtual vertical plane parallel to the extending direction of bit lines.

FIG. 3 is a conceptual circuit diagram of a ferroelectric non-volatile semiconductor memory array according to the first embodiment of the invention.

FIG. 4 is a more specific circuit diagram of a conceptual circuit diagram of the ferroelectric non-volatile semiconductor memory shown in FIG.

5 is a more specific circuit diagram of the conceptual circuit diagram of the flag circuit shown in FIG. 3;

FIG. 6 is a diagram showing operation waveforms in an operation of reading data from the ferroelectric non-volatile semiconductor memory according to the first embodiment of the invention and rewriting the data.

FIG. 7 is a conceptual circuit diagram of a ferroelectric non-volatile semiconductor memory array according to a second embodiment of the invention.

8 is a more specific circuit diagram of the conceptual circuit diagram of the flag circuit shown in FIG. 7. FIG.

FIG. 9 is a schematic partial cross-sectional view of a ferroelectric non-volatile semiconductor memory according to a third embodiment of the invention when cut along a virtual vertical plane parallel to the extending direction of bit lines.

FIG. 10 is a conceptual circuit diagram of a ferroelectric non-volatile semiconductor memory array according to a third embodiment of the invention.

11 is a more specific circuit diagram of the conceptual circuit diagram of the ferroelectric non-volatile semiconductor memory shown in FIG.

FIG. 12 is a schematic partial cross-sectional view of a ferroelectric non-volatile semiconductor memory according to a fourth embodiment of the invention when cut along a virtual vertical plane parallel to the direction in which a bit line extends.

FIG. 13 is a schematic partial cross-sectional view of the semiconductor memory for storing flags according to the fourth embodiment of the present invention, taken along a virtual vertical plane parallel to the extending direction of bit lines.

FIG. 14 is a conceptual circuit diagram of a ferroelectric non-volatile semiconductor memory array according to a fourth embodiment of the invention.

15 is a more specific circuit diagram of the conceptual circuit diagram of the ferroelectric non-volatile semiconductor memory shown in FIG.

16 is a more specific circuit diagram of the conceptual circuit diagram of the flag circuit shown in FIG. 14;

FIG. 17 is a diagram showing operation waveforms in an operation of reading data from the ferroelectric non-volatile semiconductor memory according to the fourth embodiment of the invention and rewriting the data.

FIG. 18 is a conceptual circuit diagram of another example of the ferroelectric non-volatile semiconductor memory array according to the fifth embodiment of the invention.

19 is a more specific circuit diagram of the conceptual circuit diagram of the ferroelectric non-volatile semiconductor memory shown in FIG.

20 is a more specific circuit diagram of the conceptual circuit diagram of the flag circuit shown in FIG. 18;

FIG. 21 is a schematic partial cross-sectional view of the ferroelectric non-volatile semiconductor memory according to the sixth embodiment of the present invention, taken along a virtual vertical plane parallel to the extending direction of bit lines.

FIG. 22 is a schematic partial cross-sectional view of the semiconductor memory for storing flags according to the sixth embodiment of the present invention, taken along a virtual vertical plane parallel to the extending direction of bit lines.

FIG. 23 is a conceptual circuit diagram of a ferroelectric non-volatile semiconductor memory array according to a sixth embodiment of the invention.

FIG. 24 is a more specific circuit diagram of the conceptual circuit diagram of the ferroelectric non-volatile semiconductor memory shown in FIG. 23.

FIG. 25 is a more specific circuit diagram of the conceptual circuit diagram of the flag circuit shown in FIG. 23.

FIG. 26 is a conceptual circuit diagram of a ferroelectric non-volatile semiconductor memory in a ferroelectric non-volatile semiconductor memory array according to a seventh embodiment of the invention.

FIG. 27 is a conceptual circuit diagram of a flag storing semiconductor memory in a ferroelectric non-volatile semiconductor memory array according to a seventh embodiment of the invention.

28 is a more specific circuit diagram of the conceptual circuit diagram of the ferroelectric non-volatile semiconductor memory shown in FIG. 26.

FIG. 29 is a more specific circuit diagram of the conceptual circuit diagram of the flag circuit shown in FIG. 27.

FIG. 30 is a conceptual circuit diagram of a ferroelectric non-volatile semiconductor memory array according to an eighth embodiment of the invention.

FIG. 31 is a more specific circuit diagram of a flag circuit in the conceptual circuit diagram of the ferroelectric non-volatile semiconductor memory array shown in FIG. 30.

FIG. 32 is a schematic partial cross-sectional view of the flag storing semiconductor memory according to the eighth embodiment of the present invention when cut along a virtual vertical plane parallel to the extending direction of bit lines.

FIG. 33 is a conceptual circuit diagram of a flag storing semiconductor memory in a ferroelectric non-volatile semiconductor memory array according to a ninth embodiment of the invention.

FIG. 34 is a more specific circuit diagram of the conceptual circuit diagram of the flag circuit shown in FIG. 33.

FIG. 35 is a schematic partial cross-sectional view when the ferroelectric non-volatile semiconductor memory according to the tenth embodiment of the invention is cut along an imaginary vertical plane parallel to the extending direction of bit lines.

FIG. 36 is a schematic partial cross-sectional view of the flag storing semiconductor memory according to the tenth embodiment of the invention when cut along a virtual vertical plane parallel to the extending direction of bit lines.

FIG. 37 is a conceptual circuit diagram of a ferroelectric non-volatile semiconductor memory according to a tenth embodiment of the invention.

FIG. 38 is a conceptual circuit diagram of a flag storage semiconductor memory according to the tenth embodiment of the invention.

FIG. 39 is a more specific circuit diagram of the conceptual circuit diagram of the ferroelectric non-volatile semiconductor memory shown in FIG. 37.

FIG. 40 is a more specific circuit diagram of the conceptual circuit diagram of the flag circuit shown in FIG. 38.

FIG. 41 is a conceptual circuit diagram of a modification of the ferroelectric non-volatile semiconductor memory according to the tenth embodiment of the invention.

FIG. 42 is a conceptual circuit diagram of a modified example of the flag storage semiconductor memory in the tenth embodiment of the invention.

43 is a conceptual circuit diagram of a flag circuit in the flag storage semiconductor memory according to the twelfth embodiment of the invention. FIG.

FIG. 44 is a schematic partial cross-sectional view showing a modified example of the ferroelectric non-volatile semiconductor memory described in the sixth embodiment or the seventh embodiment of the invention.

45 is a circuit diagram of the ferroelectric non-volatile semiconductor memory shown in FIG. 44.

FIG. 46 is a circuit diagram when a gain cell type ferroelectric non-volatile semiconductor memory is applied to the ferroelectric type non-volatile semiconductor memory described in the first embodiment of the invention.

FIG. 47 is a layout diagram in the ferroelectric non-volatile semiconductor memory shown in FIG. 46.

48 is a schematic partial cross-sectional view of the ferroelectric non-volatile semiconductor memory shown in FIG. 46.

49 is a schematic partial cross-sectional view of the ferroelectric non-volatile semiconductor memory shown in FIG. 46, as viewed in a cross section different from FIG. 48.

FIG. 50 is a circuit diagram showing a kind of switch circuit arranged between bit lines when a predetermined potential of a wiring connected to one end of a detection transistor is set to 0 volt.

FIG. 51 is a schematic partial cross-sectional view of another modification of the ferroelectric non-volatile semiconductor memory according to the sixth embodiment or the seventh embodiment of the invention.

FIG. 52 is a PE hysteresis loop diagram of a ferroelectric substance.

53 is a circuit diagram of a ferroelectric non-volatile semiconductor memory disclosed in US Pat. No. 4,873,664.

FIG. 54 is a circuit diagram of a ferroelectric non-volatile semiconductor memory disclosed in Japanese Patent Laid-Open No. 9-121032.

[Explanation of symbols]

10 ... Silicon semiconductor substrate, 11 ... Element isolation region, 12 ... Gate insulating film, 13 ... Gate electrode,
14A, 14B, 14C ... Source / drain regions,
14D ... Ground wire, 15 ... Connection hole (contact hole), 16 ... Insulating layer, 17, 27 ... Opening part,
18, 28 ... Connection holes 21, 21A, 21B, 2
1 ', 31, 31A, 31B, 31' ... 1st electrode, 22, 22A, 22B, 32, 32A, 32B ...
.Ferroelectric layer, 23, 23 ', 33, 33' ... second
Electrode, 25 ... Pad portion, 26 ... Insulating layer (interlayer insulating layer), 26A, 36A ... Insulating film, M ... Non-volatile memory, F ... Flag storing semiconductor memory, M
U, FU ... Memory unit, MC, FC ... Memory cell, TR, FTR ... Selection transistor, WL
... Word lines, BL, FBL ... Bit lines, PL
..Plate line, WD ... Word line decoder / driver, SA, FSA ... Sense amplifier, PD ... Plate line decoder / driver, CN, FCN ... Common node, FG ... Flag determination circuit , INV ... Inversion circuit, INC ... Increment circuit, RS ... Register

Claims (16)

[Claims] 1. A ferroelectric non-volatile semiconductor memory array comprising a plurality of ferroelectric non-volatile semiconductor memories and a flag circuit including at least one flag storing semiconductor memory, the ferroelectric non-volatile The semiconductor memory and the flag storage semiconductor memory include (A) a bit line, (B) a selection transistor, (C) a memory unit composed of M (where M ≧ 2) memory cells, and (D) ) M plate lines, each memory cell comprises a first electrode, a ferroelectric layer and a second electrode, and in the memory unit, the first electrode of the memory cell is common and The common first electrode is connected to the bit line via the selection transistor, and in the memory unit, the m-th electrode (however, m = 1, 2,
, M), the second electrode of the memory cell is connected to the m-th plate line. In the ferroelectric non-volatile semiconductor memory and the flag storing semiconductor memory, the M plate lines are When a data read and a data rewrite are performed a certain number of times on a certain plate line for a certain plate line, a flag storage semiconductor memory forming a flag circuit 2. The ferroelectric non-volatile semiconductor memory array is characterized in that the memory cells are initialized and the memory cells constituting each ferroelectric non-volatile semiconductor memory are refreshed. 2. A ferroelectric non-volatile semiconductor memory array comprising a plurality of ferroelectric non-volatile semiconductor memories and a flag circuit including at least one flag storing semiconductor memory, wherein the ferroelectric non-volatile semiconductor memory array is provided. The semiconductor memory and the flag storage semiconductor memory include (A) bit lines, (B) selection transistors, and (C) N (where M ≧ 2) memory cells, each of which is N ( However, N ≧ 2) memory units and (D) M × N plate lines are included. N memory units are stacked with an insulating layer in between, and each memory cell has a first In each memory unit, the first electrode of the memory cell is common, and the common first electrode is connected to the bit line through the selection transistor. Connection In the n-th layer (where n = 1, 2, ..., N) memory unit, the m-th (where m = 1, 2, ..., M)
The second electrode of the M) th memory cell is the [(n-1) M +
[m] th plate line, and in the ferroelectric type nonvolatile semiconductor memory and the flag storage semiconductor memory, the M × N plate lines are commonly used. When data reading and data rewriting from any of the memory cells that are common to each other are performed a predetermined number of times, the memory cell of the flag storing semiconductor memory that constitutes the flag circuit is initialized, and each ferroelectric type A ferroelectric non-volatile semiconductor memory array, characterized in that a refresh operation of a memory cell constituting a non-volatile semiconductor memory is performed. 3. A ferroelectric non-volatile semiconductor memory array comprising a plurality of ferroelectric non-volatile semiconductor memories and a flag circuit comprising at least one flag storing semiconductor memory, the ferroelectric non-volatile semiconductor memory array comprising: The semiconductor memory and the semiconductor memory for storing flags include (A) bit lines, (B) N (where N ≧ 2) selection transistors, and (C) M (where M ≧ 2) selection transistors. Each of the memory cells includes a first electrode, a ferroelectric layer, and a second electrode, and each memory cell includes N memory units each including memory cells and (D) M plate lines. In the memory unit, the first electrode of the memory cell is common, and the common first electrode of the nth (where n = 1, 2, ..., N) memory unit is the nth selection. Transistor for In and is connected to the bit line, the n-th memory units, the m-th (where,
The second electrode of the memory cell of m = 1, 2 ..., M) is
One of the M-th plate lines is connected to the m-th plate line that is shared by the memory units, and the M number of plate lines are shared by the ferroelectric nonvolatile semiconductor memory and the flag storage semiconductor memory. In the plate line, when data reading and data rewriting from any memory cell having the common plate line are performed a predetermined number of times, the memory cell of the flag storing semiconductor memory forming the flag circuit is initialized, In addition, a ferroelectric non-volatile semiconductor memory array is characterized in that a refresh operation is performed on a memory cell forming each ferroelectric non-volatile semiconductor memory. 4. A ferroelectric non-volatile semiconductor memory array comprising a plurality of ferroelectric non-volatile semiconductor memories and a flag circuit including at least one flag storing semiconductor memory, wherein the ferroelectric non-volatile semiconductor memory array comprises: The semiconductor memory is composed of (A) bit lines, (B) N (where N ≧ 2) selection transistors, and (C) each of M (where M ≧ 2) memory cells. , N memory units, and (D) M plate lines, each memory cell includes a first electrode, a ferroelectric layer, and a second electrode. Of the nth (where n = 1, 2, ..., N) memory unit has a common first electrode, and a common first electrode of the nth (n = 1, ... Connected to the wire, the In th memory units, the m-th (where,
The second electrode of the memory cell of m = 1, 2 ..., M) is
The flag storing semiconductor memory is connected to the m-th plate line common to the memory units, and the (E) bit line, (F) N selection transistors, and (G) Each memory cell comprises a memory unit composed of M memory cells (where M ≧ 2) and (H) M plate lines. Each memory cell includes a first electrode, a ferroelectric layer and a second electrode. The memory cell has a common first electrode of the memory cell, and the common first electrode of the memory unit is connected to the bit line through each selection transistor. In the semiconductor memory and the semiconductor memory for storing flags, the M plate lines are common, and a certain plate line has data from one of the memory cells having the common plate line. When the data reading and data rewriting are performed a predetermined number of times, the memory cells of the flag storing semiconductor memory that configure the flag circuit are initialized, and the refresh operation of the memory cells that configure each ferroelectric non-volatile semiconductor memory. A ferroelectric non-volatile semiconductor memory array, characterized in that: 5. A ferroelectric non-volatile semiconductor memory array comprising a plurality of ferroelectric non-volatile semiconductor memories and a flag circuit including at least one flag storing semiconductor memory, the ferroelectric non-volatile semiconductor memory array comprising: The semiconductor memory and the flag storage semiconductor memory include (A) N (where N ≧ 2) bit lines, (B) N selection transistors, and (C) each M (where M ≧ 2). 2) It is composed of N memory units composed of memory cells and (D) M plate lines. Each memory cell comprises a first electrode, a ferroelectric layer, and a second electrode. In each memory unit, the first electrode of the memory cell is common, and the common first electrode of the n-th (where n = 1, 2, ..., N) memory unit is the n-th memory unit. Th transition for selection Is connected to the n-th bit line through the data, in the n-th memory units, the m-th (where,
The second electrode of the memory cell of m = 1, 2 ..., M) is
One of the M-th plate lines is connected to the m-th plate line that is shared by the memory units, and the M number of plate lines are shared by the ferroelectric nonvolatile semiconductor memory and the flag storage semiconductor memory. In the plate line, when data reading and data rewriting from any memory cell having the common plate line are performed a predetermined number of times, the memory cell of the flag storing semiconductor memory forming the flag circuit is initialized, In addition, a ferroelectric non-volatile semiconductor memory array is characterized in that a refresh operation is performed on a memory cell forming each ferroelectric non-volatile semiconductor memory. 6. A ferroelectric non-volatile semiconductor memory array comprising a plurality of ferroelectric non-volatile semiconductor memories and a flag circuit including at least one flag storing semiconductor memory, the ferroelectric non-volatile semiconductor memory array comprising: The semiconductor memory is composed of (A) N (where N ≧ 2) bit lines, (B) N selection transistors, and (C) M (where M ≧ 2) memory cells. Each of the memory cells includes a first electrode, a ferroelectric layer, and a second electrode. Each memory unit includes N memory units and (D) M plate lines. , The first electrode of the memory cell is common, and the common first electrode in the n-th (where n = 1, 2, ..., N) memory unit is the n-th selection transistor. Through the nth bit In connected, the n-th memory units, the m-th (where,
The second electrode of the memory cell of m = 1, 2 ..., M) is
The flag storing semiconductor memory is connected to the m-th plate line common to the memory units, and the (E) bit line, (F) N selection transistors, and (G) Each memory cell comprises a memory unit composed of M memory cells (where M ≧ 2) and (H) M plate lines. Each memory cell includes a first electrode, a ferroelectric layer and a second electrode. The memory cell has a common first electrode of the memory cell, and the common first electrode of the memory unit is connected to the bit line through each selection transistor. In the semiconductor memory and the semiconductor memory for storing flags, the M plate lines are common, and a certain plate line has data from one of the memory cells having the common plate line. When the data reading and data rewriting are performed a predetermined number of times, the memory cells of the flag storing semiconductor memory that configure the flag circuit are initialized, and the refresh operation of the memory cells that configure each ferroelectric non-volatile semiconductor memory. A ferroelectric non-volatile semiconductor memory array, characterized in that: 7. A pair of ferroelectric non-volatile semiconductor memories are configured, and one bit is stored in each of a pair of memory cells having a common plate line to form a pair of flag storing semiconductor memories. , And 1 for each of a pair of memory cells having a common plate line.
Bits are stored, and the number of flag storage semiconductor memories is 2L (where L = 1,
2, 3 ...), and the predetermined number of times is 2 ^L.
7. The ferroelectric non-volatile semiconductor memory array according to claim 6. 8. A pair of ferroelectric type non-volatile semiconductor memories are constructed, and one bit is complementarily stored in a pair of memory cells having a common plate line to form a pair of flag storing semiconductor memories. 1 bit is complementarily stored in a pair of memory cells having a common plate line, and the number of flag storage semiconductor memories is 2L (where L = 1,
2, 3 ...), and the predetermined number of times is 2 ^L.
7. The ferroelectric non-volatile semiconductor memory array according to claim 6. 9. A ferroelectric non-volatile semiconductor memory array comprising a plurality of ferroelectric non-volatile semiconductor memories and a flag circuit including at least one flag storing semiconductor memory, the ferroelectric non-volatile semiconductor memory array comprising: The semiconductor memory and the flag storage semiconductor memory include (A) a bit line, (B) a selection transistor, and (C) a memory unit composed of M (where M ≧ 2) memory cells, and (D) ) M plate lines, each memory cell comprises a first electrode, a ferroelectric layer and a second electrode, and in the memory unit, the first electrode of the memory cell is common and The common first electrode is connected to the bit line via the selection transistor, and in the memory unit, the m-th electrode (however, m = 1, 2,
, M), the second electrode of the memory cell is connected to the m-th plate line. In the ferroelectric non-volatile semiconductor memory and the flag storing semiconductor memory, the M plate lines are A method of driving a common ferroelectric non-volatile semiconductor memory array, wherein data is read and rewritten a predetermined number of times from a memory cell having a common plate line in a certain plate line. The memory cell of the flag storing semiconductor memory that constitutes the flag circuit is initialized, and
A method of driving a ferroelectric non-volatile semiconductor memory array, characterized in that a refresh operation is performed on a memory cell constituting each ferroelectric non-volatile semiconductor memory. 10. A ferroelectric non-volatile semiconductor memory array comprising a plurality of ferroelectric non-volatile semiconductor memories and a flag circuit including at least one flag storing semiconductor memory, wherein the ferroelectric non-volatile semiconductor memory array is provided. The semiconductor memory and the flag storage semiconductor memory include (A) bit lines, (B) selection transistors, and (C) N (where M ≧ 2) memory cells, each of which is N ( However, N ≧ 2) memory units and (D) M × N plate lines are included. N memory units are stacked with an insulating layer in between, and each memory cell has a first In each memory unit, the first electrode of the memory cell is common, and the common first electrode is connected to the bit line through the selection transistor. Contact Then, in the n-th layer (where n = 1, 2, ..., N) memory unit, the m-th (where m = 1, 2 ...
The second electrode of the M) th memory cell is the [(n-1) M +
of the ferroelectric non-volatile semiconductor memory array in which the M × N plate lines are common in the ferroelectric non-volatile semiconductor memory and the flag storage semiconductor memory. A method of driving, in a certain plate line, when data reading and data rewriting from any memory cell having a common plate line are performed a predetermined number of times, a semiconductor memory for storing a flag that constitutes a flag circuit Initialize the memory cell, and
A method of driving a ferroelectric non-volatile semiconductor memory array, characterized in that a refresh operation is performed on a memory cell constituting each ferroelectric non-volatile semiconductor memory. 11. A ferroelectric non-volatile semiconductor memory array comprising a plurality of ferroelectric non-volatile semiconductor memories and a flag circuit comprising at least one flag storing semiconductor memory, wherein the ferroelectric non-volatile The semiconductor memory and the semiconductor memory for storing flags include (A) bit lines, (B) N (where N ≧ 2) selection transistors, and (C) M (where M ≧ 2) selection transistors. Each of the memory cells includes a first electrode, a ferroelectric layer, and a second electrode, and each memory cell includes N memory units each including memory cells and (D) M plate lines. In the memory unit, the first electrode of the memory cell is common, and the common first electrode of the nth (where n = 1, 2, ..., N) memory unit is the nth selection. Transistor In via is connected to the bit line, the n-th memory units, the m-th (where,
The second electrode of the memory cell of m = 1, 2 ..., M) is
The ferroelectric-type nonvolatile semiconductor memory and the flag-storing semiconductor memory are connected to the m-th plate line common to the memory units. A method of driving a non-volatile semiconductor memory array, wherein a flag circuit is configured when data reading and data rewriting from a memory cell having a common plate line are performed a predetermined number of times in a certain plate line. Initialize the memory cell of the flag storage semiconductor memory, and
A method of driving a ferroelectric non-volatile semiconductor memory array, characterized in that a refresh operation is performed on a memory cell constituting each ferroelectric non-volatile semiconductor memory. 12. A ferroelectric non-volatile semiconductor memory array comprising a plurality of ferroelectric non-volatile semiconductor memories and a flag circuit comprising at least one flag storing semiconductor memory, wherein the ferroelectric non-volatile The semiconductor memory is composed of (A) bit lines, (B) N (where N ≧ 2) selection transistors, and (C) each of M (where M ≧ 2) memory cells. , N memory units, and (D) M plate lines, each memory cell includes a first electrode, a ferroelectric layer, and a second electrode. Common electrode of the n-th (where n = 1, 2, ..., N) memory unit is connected to the bit through the n-th selection transistor. Connected to the wire, In n-th memory units, the m-th (where,
The second electrode of the memory cell of m = 1, 2 ..., M) is
The flag storing semiconductor memory, which is connected to the m-th plate line common to the memory units, includes (E) bit lines, (F) N selection transistors, and (G). Each memory cell includes a memory unit composed of M (where M ≧ 2) memory cells and (H) M plate lines. Each memory cell includes a first electrode, a ferroelectric layer and a second electrode. The memory cell has a common first electrode in the memory unit, the common first electrode in the memory unit is connected to the bit line through each selection transistor, and the ferroelectric non-volatile A method of driving a ferroelectric non-volatile semiconductor memory array in which the M plate lines are commonly used in a semiconductor memory and a flag storage semiconductor memory, wherein When data reading and data rewriting from any of the memory cells having the common gate line are performed a predetermined number of times, the memory cells of the flag storing semiconductor memory forming the flag circuit are initialized, and
A method of driving a ferroelectric non-volatile semiconductor memory array, characterized in that a refresh operation is performed on a memory cell constituting each ferroelectric non-volatile semiconductor memory. 13. A ferroelectric non-volatile semiconductor memory array comprising a plurality of ferroelectric non-volatile semiconductor memories and a flag circuit including at least one flag storing semiconductor memory, the ferroelectric non-volatile semiconductor memory array comprising: The semiconductor memory and the flag storage semiconductor memory include (A) N (where N ≧ 2) bit lines, (B) N selection transistors, and (C) each M (where M ≧ 2). 2) N memory units composed of memory cells and (D) M plate lines, each memory cell comprising a first electrode, a ferroelectric layer and a second electrode. In each memory unit, the first electrode of the memory cell is common, and the common first electrode of the nth (where n = 1, 2, ..., N) memory unit is the nth electrode. Th selection tran Is connected to the n-th bit line through the static, in the n-th memory units, the m-th (where,
The second electrode of the memory cell of m = 1, 2 ..., M) is
The ferroelectric-type nonvolatile semiconductor memory and the flag-storing semiconductor memory are connected to the m-th plate line common to the memory units. A method of driving a non-volatile semiconductor memory array, wherein a flag circuit is configured when data reading and data rewriting from a memory cell having a common plate line are performed a predetermined number of times in a certain plate line. Initialize the memory cell of the flag storage semiconductor memory, and
A method of driving a ferroelectric non-volatile semiconductor memory array, characterized in that a refresh operation is performed on a memory cell constituting each ferroelectric non-volatile semiconductor memory. 14. A ferroelectric non-volatile semiconductor memory array comprising a plurality of ferroelectric non-volatile semiconductor memories and a flag circuit including at least one flag storing semiconductor memory, wherein the ferroelectric non-volatile semiconductor memory array comprises: The semiconductor memory is composed of (A) N (where N ≧ 2) bit lines, (B) N selection transistors, and (C) M (where M ≧ 2) memory cells. Each of the memory cells includes a first electrode, a ferroelectric layer, and a second electrode. Each memory unit includes N memory units and (D) M plate lines. , The first electrode of the memory cell is common, and the common first electrode in the n-th (where n = 1, 2, ..., N) memory unit is the n-th selection transistor. Through the nth bit Is connected to line, in the n-th memory units, the m-th (where,
The second electrode of the memory cell of m = 1, 2 ..., M) is
The flag storing semiconductor memory, which is connected to the m-th plate line common to the memory units, includes (E) bit lines, (F) N selection transistors, and (G). Each memory cell includes a memory unit composed of M (where M ≧ 2) memory cells and (H) M plate lines. Each memory cell includes a first electrode, a ferroelectric layer and a second electrode. The memory cell has a common first electrode in the memory unit, the common first electrode in the memory unit is connected to the bit line through each selection transistor, and the ferroelectric non-volatile A method of driving a ferroelectric non-volatile semiconductor memory array in which the M plate lines are commonly used in a semiconductor memory and a flag storage semiconductor memory, wherein When data reading and data rewriting from any of the memory cells having the common gate line are performed a predetermined number of times, the memory cells of the flag storing semiconductor memory forming the flag circuit are initialized, and
A method of driving a ferroelectric non-volatile semiconductor memory array, characterized in that a refresh operation is performed on a memory cell constituting each ferroelectric non-volatile semiconductor memory. 15. A pair of ferroelectric type non-volatile semiconductor memories are constructed, and 1 bit is stored in each of a pair of memory cells having a common plate line to form a pair of flag storing semiconductor memories. , And 1 for each of a pair of memory cells having a common plate line.
Bits are stored, and the number of flag storage semiconductor memories is 2L (where L = 1,
2, 3 ...), and the predetermined number of times is 2 ^L.
15. A method of driving a ferroelectric non-volatile semiconductor memory array according to claim 14. 16. A pair of ferroelectric non-volatile semiconductor memories are constructed, and one bit is complementarily stored in a pair of memory cells having a common plate line to form a pair of flag storing semiconductor memories. 1 bit is complementarily stored in a pair of memory cells having a common plate line, and the number of flag storage semiconductor memories is 2L (where L = 1,
2, 3 ...), and the predetermined number of times is 2 ^L.
15. A method of driving a ferroelectric non-volatile semiconductor memory array according to claim 14.