JP4706141B2 - Ferroelectric nonvolatile semiconductor memory and semiconductor device - Google Patents

Description

【００７１】
［工程−１３０］
次に、絶縁層１６上に、窒化チタン（ＴｉＮ）から成る密着層（図示せず）を形成することが望ましい。そして、密着層上にＩｒＯ₂／Ｉｒから成る第１の電極（下部電極）２１を構成する第１の導電材料層を、例えばスパッタ法にて形成し、第１の導電材料層及び密着層をフォトリソグラフィ技術及びドライエッチング技術に基づきパターニングすることによって、ストライプ状の第１の電極２１を得ることができる。併せて、絶縁層１６に形成された接続孔１７，１１７，２１７の頂面は、第１の電極２１と同時に形成された第１の導電体層２２（実施の形態１においては、更に、密着層）で被覆される（図６の（Ｂ）参照）。その後、全面に、ＣＶＤ法にてＳｉＯ₂膜あるいはＳｉＯ₂／ＴｉＯ₂膜（図示せず）を形成し、ＣＭＰ法にてこの膜を平坦化して、第１の電極２１の間がこの膜によって埋め込まれた状態（所謂ダマシン構造）を得ることができる。ＣＭＰ法においては、アルミナを含むスラリーを研磨剤として用いればよい。
【００７２】
尚、絶縁層１６上に例えばＳｉＮ膜を形成し、次いで、第１の電極や第１の導電体層を形成すべき部分のＳｉＮ膜を選択的に除去した後、ＳｉＮ膜及び露出した絶縁層１６上に密着層、第１の導電材料層を形成し、その後、ＣＭＰ法にてＳｉＮ膜上の第１の導電材料層及び密着層を除去することによって、所謂ダマシン構造を有する第１の電極、第１の導電体層を形成することもできる。
【００７３】
［工程−１４０］
その後、例えば、ＭＯＣＶＤ法によって、Ｂｉ系層状構造ペロブスカイト型の強誘電体材料（具体的には、例えば、結晶化温度７５０゜ＣのＢｉ₂ＳｒＴａ₂Ｏ₉）から成る強誘電体薄膜を全面に形成する。その後、２５０゜Ｃの空気中で乾燥処理を行った後、７５０゜Ｃの酸素ガス雰囲気で１時間の熱処理を施し、結晶化を促進させる。その後、強誘電体薄膜をパターニングして、強誘電体層２３を形成する。
【００７４】
［工程−１５０］
次に、ＩｒＯ_2-X層、Ｐｔ層を、スパッタ法にて、順次、全面に形成した後、フォトリソグラフィ技術、ドライエッチング技術に基づき、Ｐｔ層、ＩｒＯ_2-X層を順次、パターニングして、強誘電体層２３上に第２の電極２４を形成し、第２の電極２４から延びるプレート線ＰＬを形成し、更に、第１の導電体層２２，１２２上に第２の導電体層２５，１２５を形成し、加えて、配線１２９を形成する（図７の（Ａ）参照）。尚、図７の（Ａ）には、配線１２９は図示されていない。エッチングによって、強誘電体層２３にダメージが加わる場合には、ダメージ回復に必要とされる温度にて、その後、ダメージ回復アニール処理を行えばよい。
【００７５】
［工程−１６０］
その後、
・層間絶縁層２６の形成及び平坦化処理
・開口部の形成及び接続孔２７，１２７，２２７の形成（図７の（Ｂ）参照）
・例えば、ダマシン構造を有する第１の電極３１、第１の導電体層３２，１３２の形成（図８の（Ａ）参照）
・結晶化温度７００゜ＣのＢｉ₂Ｓｒ（Ｔａ_1.5Ｎｂ_0.5）Ｏ₉から成る強誘電体層３３の形成
・第２の電極３４、第２の導電体層３５，１３５、配線１３９の形成（図８の（Ｂ）参照）
・絶縁膜３６Ａの形成
・コンタクトホール１３７Ａ，２３７Ａの形成
・例えばアルミニウム合金から成る金属配線層１５０，２５０の形成
・絶縁膜４６Ａの形成
を、順次、行う。尚、各図においては、上記の参照番号で表した構成要素が図示されていない場合がある。Ｂｉ₂Ｓｒ（Ｔａ_1.5Ｎｂ_0.5）Ｏ₉から成る強誘電体層３３に対して、結晶化促進のための熱処理を、７００゜Ｃの酸素ガス雰囲気で１時間、行えばよい。
【００７６】
尚、上方に位置するメモリユニットを構成する強誘電体層の結晶化温度を、下方に位置するメモリユニットを構成する強誘電体層の結晶化温度よりも低くすれば、積層されたメモリユニットの段数だけ結晶化熱処理を行っても、下方に位置するメモリユニットを構成するメモリセルの特性劣化といった問題は生じない。また、各段におけるメモリユニットを構成するメモリセルに対して、最適な条件での結晶化熱処理を行うことができ、特性の優れた不揮発性メモリを得ることができる。以下の表２に結晶化温度を例示する。
【００７７】
［表２］
材料名 結晶化温度
Ｂｉ₂ＳｒＴａ₂Ｏ₉ ７００〜８００゜Ｃ
Ｂｉ₂Ｓｒ（Ｔａ_1.5，Ｎｂ_0.5）Ｏ₉ ６５０〜７５０゜Ｃ
Ｂｉ₄Ｔｉ₃Ｏ₁₂ ６００〜７００゜Ｃ
Ｐｂ（Ｚｒ_0.48，Ｔｉ_0.52）Ｏ₃ ５５０〜６５０゜Ｃ
ＰｂＴｉＯ₃ ５００〜６００゜Ｃ
【００７８】
例えば、Ｂｉ₂ＳｒＴａ₂Ｏ₉から成る強誘電体薄膜の形成条件を以下の表３に例示する。尚、表３中、「ｔｈｄ」は、テトラメチルヘプタンジオネートの略である。また、表３に示したソース原料はテトラヒドロフラン（ＴＨＦ）を主成分とする溶媒中に溶解されている。
【００７９】

【００８０】
あるいは又、Ｂｉ₂ＳｒＴａ₂Ｏ₉から成る強誘電体薄膜をパルスレーザアブレーション法、ゾル−ゲル法、あるいはＲＦスパッタ法にて全面に形成することもできる。これらの場合の形成条件を以下に例示する。尚、ゾル−ゲル法によって厚い強誘電体薄膜を形成する場合、所望の回数、スピンコート及び乾燥、あるいはスピンコート及び焼成（又は、アニール処理）を繰り返せばよい。
【００８１】
［表４］
パルスレーザアブレーション法による形成
ターゲット：Ｂｉ₂ＳｒＴａ₂Ｏ₉
使用レーザ：ＫｒＦエキシマレーザ（波長２４８ｎｍ、パルス幅２５ｎ秒、５Ｈｚ）
形成温度 ：４００〜８００゜Ｃ
酸素濃度 ：３Ｐａ
【００８２】

【００８３】
［表６］
ＲＦスパッタ法による形成
ターゲット：Ｂｉ₂ＳｒＴａ₂Ｏ₉セラミックターゲット
ＲＦパワー：１．２Ｗ〜２．０Ｗ／ターゲット１ｃｍ²
雰囲気圧力：０．２〜１．３Ｐａ
形成温度 ：室温〜６００゜Ｃ
プロセスガス：Ａｒ／Ｏ₂の流量比＝２／１〜９／１
【００８４】
強誘電体層を、ＰＺＴあるいはＰＬＺＴから構成するときの、マグネトロンスパッタ法によるＰＺＴあるいはＰＬＺＴの形成条件を以下の表７に例示する。あるいは又、ＰＺＴやＰＬＺＴを、反応性スパッタ法、電子ビーム蒸着法、ゾル−ゲル法、又はＭＯＣＶＤ法にて形成することもできる。
【００８５】
［表７］
ターゲット ：ＰＺＴあるいはＰＬＺＴ
プロセスガス：Ａｒ／Ｏ₂＝９０体積％／１０体積％
圧力 ：４Ｐａ
パワー ：５０Ｗ
形成温度 ：５００゜Ｃ
【００８６】
更には、ＰＺＴやＰＬＺＴをパルスレーザアブレーション法にて形成することもできる。この場合の形成条件を以下の表８に例示する。
【００８７】
［表８］
ターゲット：ＰＺＴ又はＰＬＺＴ
使用レーザ：ＫｒＦエキシマレーザ（波長２４８ｎｍ、パルス幅２５ｎ秒、３Ｈｚ）
出力エネルギー：４００ｍＪ（１．１Ｊ／ｃｍ²）
形成温度 ：５５０〜６００゜Ｃ
酸素濃度 ：４０〜１２０Ｐａ
【００８８】
尚、絶縁層１６上に形成された配線を、第１層目のメモリセルＭＣ_11mを構成する第１の電極２１と同時に形成された第１の導電体層、及び、第１層目のメモリセルＭＣ_11mを構成する第２の電極と同時に形成された第２の導電体層の積層構造から構成し、第ｋ層目（但し、ｋ＝１，２・・・，Ｎ−１であり、実施の形態１においては、ｋ＝１）の層間絶縁層２６上に形成された配線を、第（ｋ＋１）層目のメモリセルＭＣ_12mを構成する第１の電極３１と同時に形成された第１の導電体層、及び、第（ｋ＋１）層目のメモリセルＭＣ_12mを構成する第２の電極３４と同時に形成された第２の導電体層の積層構造から構成することもできる。
【００８９】
（実施の形態２）
実施の形態２は、本発明の第１の態様及び第３の態様に係る不揮発性メモリ、並びに、本発明の半導体装置に関する。ビット線の延びる方向と平行な仮想垂直面で実施の形態２の半導体装置を切断したときの模式的な一部断面図を図９に示す。尚、ワード線の延びる方向と平行な仮想垂直面で実施の形態２の半導体装置を切断したときの模式的な一部断面図は、実質的に図２に示したと同様の構成を有する。更には、本発明の第２の態様に係る不揮発性メモリの概念的な回路図を図１０の（Ａ）及び（Ｂ）に示し、図１０の（Ａ）の概念的な回路図のより具体的な回路図を図１１に示し、図１０の（Ｂ）の概念的な回路図のより具体的な回路図を図１２に示す。尚、図１１及び図１２には、２つの不揮発性メモリＭ₁，Ｍ₂を図示するが、これらの不揮発性メモリＭ₁，Ｍ₂の構造は同一であり、以下においては、不揮発性メモリＭ₁に関しての説明を行う。また、周辺回路は、実質的に実施の形態１の半導体装置における周辺回路と同じ構成とすることができるので、詳細な説明は省略する。
【００９０】
実施の形態２の不揮発性メモリＭ₁は、
（Ａ）ビット線ＢＬ₁と、
（Ｂ）Ｎ個（但し、Ｎ≧２であり、実施の形態２においては、Ｎ＝２）の選択用トランジスタＴＲ₁₁，ＴＲ₁₂と、
（Ｃ）それぞれがＭ個（但し、Ｍ≧２であり、実施の形態２においては、Ｍ＝４）のメモリセルＭＣ_11M，ＭＣ_12Mから構成された、Ｎ個のメモリユニットＭＵ₁₁，ＭＵ₁₂と、
（Ｄ）Ｍ本のプレート線ＰＬ_M、
から成る。
【００９１】
そして、第１層目のメモリユニットＭＵ₁₁は、絶縁層１６を介して選択用トランジスタＴＲ₁₁，ＴＲ₂₁の上方に形成されており、Ｎ個のメモリユニットＭＵ₁₁，ＭＵ₁₂は、（Ｎ−１）層（実施の形態２においては１層）の層間絶縁層２６を介して積層されている。
【００９２】
また、第１層目のメモリユニットＭＵ₁₁を構成する各メモリセルＭＣ_11Mは、第１の電極２１と強誘電体層２３と第２の電極２４とから成り、第２層目のメモリユニットＭＵ₁₂を構成する各メモリセルＭＣ_12Mは、第１の電極３１と強誘電体層３３と第２の電極３４とから成る。更には、各メモリユニットにおいて、メモリセルの第１の電極は共通である。即ち、第１層目のメモリユニットＭＵ₁₁において、メモリセルＭＣ_11Mの第１の電極２１は共通である。この共通の第１の電極２１を第１の共通ノードＣＮ₁₁と呼ぶ場合がある。また、第２層目のメモリユニットＭＵ₁₂において、メモリセルＭＣ_12Mの第１の電極３１は共通である。この共通の第１の電極３１を第２の共通ノードＣＮ₁₂と呼ぶ場合がある。更には、第ｎ層目（但し、ｎ＝１，２・・・，Ｎ）のメモリユニットＭＵ_1nにおいて、第ｍ番目（但し、ｍ＝１，２・・・，Ｍ）のメモリセルの第２の電極２４，３４は、メモリユニットＭＵ_1n間で共通とされた第ｍ番目のプレート線ＰＬ_mに接続されている。実施の形態２においては、より具体的には、各プレート線は、第２の電極２４，３４から延在している。
【００９３】
そして、各選択用トランジスタＴＲ₁₁，ＴＲ₁₂の一方のソース／ドレイン領域１３Ａはビット線ＢＬ₁に接続され、第１番目の選択用トランジスタＴＲ₁₁の他方のソース／ドレイン領域１３Ｂは、絶縁層１６に設けられた第１層目の接続孔１７を介して、第１層目のメモリユニットＭＵ₁₁における共通の第１の電極２１（第１の共通ノードＣＮ₁₁）に接続されている。また、第（ｋ＋１）番目（但し、ｋ＝１，２・・・，Ｎ−１であり、実施の形態２においては、ｋ＝１）の選択用トランジスタＴＲ₁₂の他方のソース／ドレイン領域１３Ｂは、絶縁層１６に設けられた第１層目の接続孔１７、及び、第１層目の層間絶縁層から第ｋ層目（但し、ｋ＝１，２・・・，Ｎ−１）までの層間絶縁層のそれぞれに設けられた第２層目の接続孔から第（ｋ＋１）層目の接続孔のそれぞれ（実施の形態２においては、より具体的には、第１層目の層間絶縁層２６に設けられた第２層目の接続孔２７）を介して、第（ｋ＋１）層目のメモリユニットＭＵ₁₂における共通の第１の電極３１（第２の共通ノードＣＮ₁₂）に接続されている。
【００９４】
実施の形態２の不揮発性メモリＭ₁にあっても、絶縁層１６に形成された第１層目の接続孔１７の頂面は、第１層目のメモリユニットＭＵ₁₁のメモリセルＭＣ_11mを構成する第１の電極２１と同時に形成された第１の導電体層２２、及び、第１層目のメモリユニットＭＵ₁₁のメモリセルＭＣ_11Mを構成する第２の電極２４と同時に形成された第２の導電体層２５の積層構造によって被覆されている。一方、第ｋ層目（実施の形態２においては、第１層目）の層間絶縁層２６に形成された第（ｋ＋１）層目（実施の形態２においては、第２層目）の接続孔２７の頂面は、第（ｋ＋１）層目（実施の形態２においては、第２層目）のメモリユニットＭＵ₁₂のメモリセルＭＣ_12Mを構成する第１の電極３１と同時に形成された第１の導電体層３２、及び、第（ｋ＋１）層目のメモリユニットＭＵ₁₂のメモリセルＭＣ_12Mを構成する第２の電極３４と同時に形成された第２の導電体層３５の積層構造によって被覆されている。
【００９５】
ビット線ＢＬ_nは、センスアンプＳＡに接続されている。また、プレート線ＰＬ_Mはプレート線デコーダ／ドライバＰＤに接続されている。更には、ワード線ＷＬ₁，ＷＬ₂（あるいはワード線ＷＬ₁₁，ＷＬ₁₂，ＷＬ₂₁，ＷＬ₂₂）は、ワード線デコーダ／ドライバＷＤに接続されている。ワード線は、図９の紙面垂直方向に延びている。また、不揮発性メモリＭ₁を構成するメモリセルＭＣ_11mの第２の電極２４は、図９の紙面垂直方向に隣接する不揮発性メモリＭ₂を構成するメモリセルＭＣ_21mの第２の電極と共通であり、プレート線ＰＬ_mを兼ねている。更には、不揮発性メモリＭ₁を構成するメモリセルＭＣ_12mの第２の電極３４は、図９の紙面垂直方向に隣接する不揮発性メモリＭ₂を構成するメモリセルＭＣ_22mの第２の電極と共通であり、プレート線ＰＬ_mを兼ねている。これらのプレート線ＰＬ_mは、図示しない領域において接続されている。また、ワード線ＷＬ₁は、不揮発性メモリＭ₁を構成する選択用トランジスタＴＲ₁₁と、図９の紙面垂直方向に隣接する不揮発性メモリＭ₂を構成する選択用トランジスタＴＲ₂₁とで共通である。更には、ワード線ＷＬ₂は、不揮発性メモリＭ₁を構成する選択用トランジスタＴＲ₁₂と、図９の紙面垂直方向に隣接する不揮発性メモリＭ₂を構成する選択用トランジスタＴＲ₂₂とで共通である。
【００９６】
尚、Ｎ＝４とした場合には、第１番目の選択用トランジスタの他方のソース／ドレイン領域は、絶縁層に設けられた第１層目の接続孔を介して、第１層目のメモリユニットにおける共通の第１の電極に接続されている。また、第２番目の選択用トランジスタの他方のソース／ドレイン領域は、絶縁層に設けられた第１層目の接続孔、第１層目の接続孔の頂面を被覆する第１の導電体層と第２の導電体層の積層構造、及び、第１層の層間絶縁層に設けられた第２層目の接続孔を介して、第２層目のメモリユニットにおける共通の第１の電極に接続されている。更には、第３番目の選択用トランジスタの他方のソース／ドレイン領域は、絶縁層に設けられた第１層目の接続孔、第１層目の接続孔の頂面を被覆する第１の導電体層と第２の導電体層の積層構造、第１層の層間絶縁層に設けられた第２層目の接続孔、第２層目の接続孔の頂面を被覆する第１の導電体層と第２の導電体層の積層構造、及び、第２層の層間絶縁層に設けられた第３層目の接続孔を介して、第３層目のメモリユニットにおける共通の第１の電極に接続されている。また、第４番目の選択用トランジスタの他方のソース／ドレイン領域は、絶縁層に設けられた第１層目の接続孔、第１層目の接続孔の頂面を被覆する第１の導電体層と第２の導電体層の積層構造、第１層の層間絶縁層に設けられた第２層目の接続孔、第２層目の接続孔の頂面を被覆する第１の導電体層と第２の導電体層の積層構造、第２層の層間絶縁層に設けられた第３層目の接続孔、第３層目の接続孔の頂面を被覆する第１の導電体層と第２の導電体層の積層構造、及び、第３層の層間絶縁層に設けられた第４層目の接続孔を介して、第４層目のメモリユニットにおける共通の第１の電極に接続されている。尚、後述する実施の形態３における不揮発性メモリにおいて、Ｎ＝４と下場合も、同様の構造を有する。
【００９７】
図１０の（Ａ）及び図１１に回路図を示す不揮発性メモリＭ₁，Ｍ₂において、不揮発性メモリＭ₁，Ｍ₂を構成する選択用トランジスタＴＲ_1n，ＴＲ_2nは同じワード線ＷＬ_nに接続されている。そして、対となったメモリセルＭＣ_1nm，ＭＣ_2nm（ｎ＝１，２、及び、ｍ＝１，２・・・Ｍ）に相補的なデータが記憶される。例えば、メモリセルＭＣ_11m，ＭＣ_21m（ここで、ｍは１，２，３，４のいずれか）に記憶されたデータを読み出す場合、ワード線ＷＬ₁を選択し、プレート線ＰＬ_j（ｍ≠ｊ）には（１／２）Ｖ_ccの電圧を印加した状態で、プレート線ＰＬ_mを駆動する。ここで、Ｖ_ccは、例えば、電源電圧である。これによって、相補的なデータが、対となったメモリセルＭＣ_11m，ＭＣ_21mから選択用トランジスタＴＲ₁₁，ＴＲ₂₁を介して対となったビット線ＢＬ₁，ＢＬ₂に電圧（ビット線電位）として現れる。そして、かかる対となったビット線ＢＬ₁，ＢＬ₂の電圧（ビット線電位）を、センスアンプＳＡで検出する。尚、不揮発性メモリＭ₁，Ｍ₂を構成する選択用トランジスタＴＲ₁₁，ＴＲ₁₂，ＴＲ₂₁，ＴＲ₂₂を、それぞれ、異なるワード線ＷＬ₁₁，ＷＬ₁₂，ＷＬ₂₁，ＷＬ₂₂に接続し、メモリセルＭＣ_1nm，ＭＣ_2nmを独立して制御し、対となったビット線ＢＬ₁，ＢＬ₂の一方に参照電圧を印加することによって、メモリセルＭＣ_1nm，ＭＣ_2nmのそれぞれからデータを読み出すこともできる。このような構成を採用する場合の回路図は、図１０の（Ｂ）及び図１２を参照のこと。尚、選択用トランジスタＴＲ₁₁，ＴＲ₂₁を同時に駆動し、選択用トランジスタＴＲ₁₂，ＴＲ₂₂を同時に駆動すれば、図１０の（Ａ）及び図１１に示した回路と等価となる。このように、各メモリセルＭＣ_1nm，ＭＣ_2nm（ｍ＝１，２，３，４）のそれぞれに１ビットがデータとして記憶され（図１０の（Ｂ）及び図１２参照）、あるいは又、対となったメモリセルＭＣ_1nm，ＭＣ_2nmに相補的なデータが１ビットとして記憶される（図１０の（Ａ）及び図１１参照）。実際の不揮発性メモリにおいては、この１６ビットあるいは８ビットを記憶するメモリユニットの集合がアクセス単位ユニットとしてアレイ状に配設されている。尚、Ｍの値は４に限定されない。Ｍの値は、Ｍ≧２を満足すればよく、実際的なＭの値として、例えば、２のべき数（２，４，８，１６・・・）を挙げることができる。また、Ｎの値は、Ｎ≧２を満足すればよく、実際的なＮの値として、例えば、２のべき数（２，４，８・・・）を挙げることができる。
【００９８】
実施の形態２の不揮発性メモリ及び半導体装置は、実質的に、実施の形態１の不揮発性メモリ及び半導体装置の製造方法と同様の方法で作製することができるので、詳細な説明は省略する。
【００９９】
（実施の形態３）
実施の形態３は、本発明の第１の態様及び第４の態様に係る不揮発性メモリ、並びに、本発明の半導体装置に関する。ビット線の延びる方向と平行な仮想垂直面で実施の形態３の半導体装置を切断したときの模式的な一部断面図を図１３に示す。尚、ワード線の延びる方向と平行な仮想垂直面で実施の形態３の半導体装置を切断したときの模式的な一部断面図は、実質的に図２に示したと同様の構成を有する。更には、本発明の第３の態様に係る不揮発性メモリの概念的な回路図を図１４の（Ａ）及び（Ｂ）に示し、具体的な回路図を図１５に示す。尚、図１４の（Ａ）及び（Ｂ）には、２つの不揮発性メモリＭ₁，Ｍ₂を図示するが、これらの不揮発性メモリＭ₁，Ｍ₂の構造は同一であり、以下においては、不揮発性メモリＭ₁に関しての説明を行う。また、周辺回路は、実質的に実施の形態１の半導体装置における周辺回路と同じ構成とすることができるので、詳細な説明は省略する。
【０１００】
実施の形態３の不揮発性メモリＭ₁は、
（Ａ）Ｎ本（但し、Ｎ≧２であり、実施の形態３においては、Ｎ＝２）ビット線ＢＬ₁₁，ＢＬ₁₂と、
（Ｂ）Ｎ個の選択用トランジスタＴＲ₁₁，ＴＲ₁₂と、
（Ｃ）それぞれがＭ個（但し、Ｍ≧２であり、実施の形態３においては、Ｍ＝４）のメモリセルＭＣ_11M，ＭＣ_12Mから構成された、Ｎ個のメモリユニットＭＵ₁₁，ＭＵ₁₂と、
（Ｄ）Ｍ本のプレート線ＰＬ_M、
から成る。
【０１０１】
尚、図１４、図１５中、ビット線ＢＬ₁₁と、選択用トランジスタＴＲ₁₁と、メモリセルＭＣ_11Mから構成されたメモリユニットＭＵ₁₁を、サブユニットＳＵ₁₁で表し、ビット線ＢＬ₁₂と、選択用トランジスタＴＲ₁₂と、メモリセルＭＣ_12Mから構成されたメモリユニットＭＵ₁₂を、サブユニットＳＵ₁₂で表す。
【０１０２】
そして、第１層目のメモリユニットＭＵ₁₁は、絶縁層１６を介して選択用トランジスタＴＲ₁₁，ＴＲ₁₂の上方に形成されており、Ｎ個のメモリユニットＭＵ₁₁，ＭＵ₁₂は、（Ｎ−１）層（実施の形態３においては１層）の層間絶縁層２６を介して積層されている。
【０１０３】
また、第１層目のメモリユニットＭＵ₁₁を構成する各メモリセルＭＣ_11Mは、第１の電極２１と強誘電体層２３と第２の電極２４とから成り、第２層目のメモリユニットＭＵ₁₂を構成する各メモリセルＭＣ_12Mは、第１の電極３１と強誘電体層３３と第２の電極３４とから成る。更には、各メモリユニットにおいて、メモリセルの第１の電極は共通である。即ち、第１層目のメモリユニットＭＵ₁₁において、メモリセルＭＣ_11Mの第１の電極２１は共通である。この共通の第１の電極２１を第１の共通ノードＣＮ₁₁と呼ぶ場合がある。また、第２層目のメモリユニットＭＵ₁₂において、メモリセルＭＣ_12Mの第１の電極３１は共通である。この共通の第１の電極３１を第２の共通ノードＣＮ₁₂と呼ぶ場合がある。更には、第ｎ層目（但し、ｎ＝１，２・・・，Ｎ）のメモリユニットＭＵ_1nにおいて、第ｍ番目（但し、ｍ＝１，２・・・，Ｍ）のメモリセルの第２の電極２４，３４は、メモリユニットＭＵ_1n間で共通とされた第ｍ番目のプレート線ＰＬ_mに接続されている。実施の形態３においては、より具体的には、各プレート線は、第２の電極２４，３４から延在している。
【０１０４】
そして、第ｎ番目の選択用トランジスタＴＲ_1nの一方のソース／ドレイン領域１３Ａは第ｎ番目のビット線ＢＬ_1nに接続され、第１番目の選択用トランジスタＴＲ₁₁の他方のソース／ドレイン領域１３Ｂは、絶縁層１６に設けられた第１層目の接続孔１７を介して、第１層目のメモリユニットＭＵ₁₁における共通の第１の電極２１（第１の共通ノードＣＮ₁₁）に接続されている。また、第（ｋ＋１）番目（但し、ｋ＝１，２・・・，Ｎ−１であり、実施の形態３においては、ｋ＝１）の選択用トランジスタＴＲ₁₂の他方のソース／ドレイン領域１３Ｂは、絶縁層１６に設けられた第１層目の接続孔１７、及び、第１層目の層間絶縁層から第ｋ層目（但し、ｋ＝１，２・・・，Ｎ−１）までの層間絶縁層のそれぞれに設けられた第２層目の接続孔から第（ｋ＋１）層目の接続孔のそれぞれ（実施の形態３においては、より具体的には、第１層目の層間絶縁層２６に設けられた第２層目の接続孔２７）を介して、第（ｋ＋１）層目のメモリユニットＭＵ₁₂における共通の第１の電極３１（第２の共通ノードＣＮ₁₂）に接続されている。
【０１０５】
実施の形態３の不揮発性メモリＭ₁にあっても、絶縁層１６に形成された第１層目の接続孔１７の頂面は、第１層目のメモリユニットＭＵ₁₁のメモリセルＭＣ_11mを構成する第１の電極２１と同時に形成された第１の導電体層２２、及び、第１層目のメモリユニットＭＵ₁₁のメモリセルＭＣ_11Mを構成する第２の電極２４と同時に形成された第２の導電体層２５の積層構造によって被覆されている。一方、第ｋ層目（実施の形態３においては、第１層目）の層間絶縁層２６に形成された第（ｋ＋１）層目（実施の形態３においては、第２層目）の接続孔２７の頂面は、第（ｋ＋１）層目（実施の形態２においては、第２層目）のメモリユニットＭＵ₁₂のメモリセルＭＣ_12Mを構成する第１の電極３１と同時に形成された第１の導電体層３２、及び、第（ｋ＋１）層目のメモリユニットＭＵ₁₂のメモリセルＭＣ_12Mを構成する第２の電極３４と同時に形成された第２の導電体層３５の積層構造によって被覆されている。
【０１０６】
ビット線ＢＬ_1nは、センスアンプＳＡに接続されている。また、プレート線ＰＬ_Mはプレート線デコーダ／ドライバＰＤに接続されている。更には、ワード線ＷＬ₁，ＷＬ₂（あるいはワード線ＷＬ₁₁，ＷＬ₁₂，ＷＬ₂₁，ＷＬ₂₂）は、ワード線デコーダ／ドライバＷＤに接続されている。ワード線は、図１３の紙面垂直方向に延びている。また、不揮発性メモリＭ₁を構成するメモリセルＭＣ_11mの第２の電極２４は、図１３の紙面垂直方向に隣接する不揮発性メモリＭ₂を構成するメモリセルＭＣ_21mの第２の電極と共通であり、プレート線ＰＬ_mを兼ねている。更には、不揮発性メモリＭ₁を構成するメモリセルＭＣ_12mの第２の電極３４は、図１３の紙面垂直方向に隣接する不揮発性メモリＭ₂を構成するメモリセルＭＣ_22mの第２の電極と共通であり、プレート線ＰＬ_mを兼ねている。これらのプレート線ＰＬ_mは、図示しない領域において接続されている。また、ワード線ＷＬ₁は、不揮発性メモリＭ₁を構成する選択用トランジスタＴＲ₁₁と、図１３の紙面垂直方向に隣接する不揮発性メモリＭ₂を構成する選択用トランジスタＴＲ₂₁とで共通である。更には、ワード線ＷＬ₂は、不揮発性メモリＭ₁を構成する選択用トランジスタＴＲ₁₂と、図１３の紙面垂直方向に隣接する不揮発性メモリＭ₂を構成する選択用トランジスタＴＲ₂₂とで共通である。
【０１０７】
図１４の（Ａ）及び図１５に回路図を示す不揮発性メモリＭ₁，Ｍ₂においては、不揮発性メモリＭ₁，Ｍ₂を構成する選択用トランジスタＴＲ₁₁，ＴＲ₂₁は同じワード線ＷＬ₁に接続され、選択用トランジスタＴＲ₁₂，ＴＲ₂₂は同じワード線ＷＬ₂に接続されている。そして、対となったメモリセルＭＣ_1nm，ＭＣ_2nm（ｎ＝１，２、及び、ｍ＝１，２・・・Ｍ）に相補的なデータが記憶される。例えば、メモリセルＭＣ_11m，ＭＣ_21m（ここで、ｍは１，２，３，４のいずれか）に記憶されたデータを読み出す場合、ワード線ＷＬ₁を選択し、プレート線ＰＬ_j（ｍ≠ｊ）には（１／２）Ｖ_ccの電圧を印加した状態で、プレート線ＰＬ_mを駆動する。ここで、Ｖ_ccは、例えば、電源電圧である。これによって、相補的なデータが、対となったメモリセルＭＣ_11m，ＭＣ_21mから選択用トランジスタＴＲ₁₁，ＴＲ₂₁を介して対となったビット線ＢＬ₁₁，ＢＬ₂₁に電圧（ビット線電位）として現れる。そして、かかる対となったビット線ＢＬ₁₁，ＢＬ₂₁の電圧（ビット線電位）を、センスアンプＳＡで検出する。尚、不揮発性メモリＭ₁，Ｍ₂を構成する選択用トランジスタＴＲ₁₁，ＴＲ₁₂，ＴＲ₂₁，ＴＲ₂₂を、それぞれ、異なるワード線ＷＬ₁₁，ＷＬ₁₂，ＷＬ₂₁，ＷＬ₂₂に接続し、メモリセルＭＣ_1nm，ＭＣ_2nmを独立して制御し、対となったビット線ＢＬ₁₁，ＢＬ₂₁、あるいは、対となったビット線ＢＬ₁₂，ＢＬ₂₂の一方に参照電圧を印加することによって、メモリセルＭＣ_1nm，ＭＣ_2nmのそれぞれからデータを読み出すこともできる。このような構成を採用する場合の回路図は、図１４の（Ｂ）及び図１５を参照のこと。尚、選択用トランジスタＴＲ₁₁，ＴＲ₂₁を同時に駆動し、選択用トランジスタＴＲ₁₂，ＴＲ₂₂を同時に駆動すれば、図１４の（Ａ）に示した回路と等価となる。このように、各メモリセルＭＣ_1nm，ＭＣ_2nm（ｍ＝１，２，３，４）のそれぞれに１ビットがデータとして記憶され（図１４の（Ｂ）参照）、あるいは又、対となったメモリセルＭＣ_1nm，ＭＣ_2nmに相補的なデータが１ビットとして記憶される（図１４の（Ａ）参照）。実際の不揮発性メモリにおいては、この１６ビットあるいは８ビットを記憶するメモリユニットの集合がアクセス単位ユニットとしてアレイ状に配設されている。尚、Ｍの値は４に限定されない。Ｍの値は、Ｍ≧２を満足すればよく、実際的なＭの値として、例えば、２のべき数（２，４，８，１６・・・）を挙げることができる。また、Ｎの値は、Ｎ≧２を満足すればよく、実際的なＮの値として、例えば、２のべき数（２，４，８・・・）を挙げることができる。
【０１０８】
あるいは又、図１４の（Ａ）及び図１５に回路図を示す不揮発性メモリＭ₁において、例えば、対となったメモリセルＭＣ_11m，ＭＣ_12m（ｍ＝１，２・・・，Ｍ）に相補的なデータを記憶してもよい。例えば、メモリセルＭＣ_11m，ＭＣ_12m（ここで、ｍは１，２，３，４のいずれか）に記憶されたデータを読み出す場合、ワード線ＷＬ₁，ＷＬ₂を選択し、プレート線ＰＬ_j（ｍ≠ｊ）には、例えば（１／２）Ｖ_ccの電圧を印加した状態で、プレート線ＰＬ_mを駆動する。これによって、相補的なデータが、対となったメモリセルＭＣ_11m，ＭＣ_12mから選択用トランジスタＴＲ₁₁，ＴＲ₁₂を介して対となったビット線ＢＬ₁₁，ＢＬ₁₂に電圧（ビット線電位）として現れる。そして、かかる対となったビット線ＢＬ₁₁，ＢＬ₁₂の電圧（ビット線電位）を、センスアンプＳＡで検出する。尚、メモリセルＭＣ_11m，ＭＣ_12mを独立して制御し、対となったビット線ＢＬ₁₁，ＢＬ₁₂の一方に参照電圧を印加することによって、メモリセルＭＣ_11m，ＭＣ_12mのそれぞれからデータを読み出すこともできる。このような構成を採用する場合の回路図は、図１４の（Ｂ）及び図１５を参照のこと。
【０１０９】
実施の形態３の不揮発性メモリ及び半導体装置は、実質的に、実施の形態１の不揮発性メモリ及び半導体装置の製造方法と同様の方法で作製することができるので、詳細な説明は省略する。
【０１１０】
以上、本発明を、発明の実施の形態に基づき説明したが、本発明はこれらに限定されるものではない。発明の実施の形態にて説明した不揮発性メモリや半導体装置の構造、使用した材料、各種の形成条件、回路構成、駆動方法等は例示であり、適宜変更することができる。
【０１１１】
一般に、単位ユニットの駆動用の信号線の合計本数をＡ本、その内のワード線本数をＢ本、プレート線の本数をＣ本とすると、Ａ＝Ｂ＋Ｃである。ここで、合計本数Ａを一定とした場合、単位ユニットの総アドレス数（＝Ｂ×Ｃ）が最大となるには、Ｂ＝Ｃを満足すればよい。従って、最も効率良く周辺回路を配置するためには、単位ユニットにおけるワード線本数Ｂとプレート線の本数Ｃとを等しくすればよい。また、ロー・アドレスのアクセス単位ユニットにおけるワード線本数は、例えばメモリセルの積層段数に一致し、プレート線本数はメモリユニットを構成するメモリセルの数に一致するが、これらのワード線本数、プレート線本数が多いほど、実質的な不揮発性メモリの集積度は向上する。そして、ワード線本数とプレート線本数の積がアクセス可能なアドレス回数である。ここで、一括して、且つ、連続したアクセスを前提とすると、その積から「１」を減じた値がディスターブ回数である。従って、ワード線本数とプレート線本数の積の値は、メモリセルのディスターブ耐性、プロセス要因等から決定される。ここで、ディスターブとは、非選択のメモリセルを構成する強誘電体層に対して、分極が反転する方向に、即ち、保存されていたデータが劣化若しくは破壊される方向に、電界が加わる現象を指す。
【０１１２】
実施の形態２において説明した不揮発性メモリを、図１６に示す構造のように変形することもできる。尚、回路図を図１７に示す。
【０１１３】
この不揮発性メモリは、センスアンプＳＡに接続されているビット線ＢＬ₁と、ＭＯＳ型ＦＥＴから構成されたＮ個（但し、Ｎ≧２であり、この例においてはＮ＝４）の選択用トランジスタＴＲ₁₁，ＴＲ₁₂，ＴＲ₁₃，ＴＲ₁₄と、Ｎ個のメモリユニットＭＵ₁₁，ＭＵ₁₂，ＭＵ₁₃，ＭＵ₁₄と、プレート線から構成されている。第１層目のメモリユニットＭＵ₁₁は、Ｍ個（但し、Ｍ≧２であり、この例においてはＭ＝８）のメモリセルＭＣ_11m（ｍ＝１，２，・・・８）から構成されている。また、第２層目のメモリユニットＭＵ₁₂も、Ｍ個（Ｍ＝８）のメモリセルＭＣ_12m（ｍ＝１，２・・・８）から構成されている。更には、第３層目のメモリユニットＭＵ₁₃も、Ｍ個（Ｍ＝８）のメモリセルＭＣ_13m（ｍ＝１，２・・・８）から構成され、第４層目のメモリユニットＭＵ₁₄も、Ｍ個（Ｍ＝８）のメモリセルＭＣ_14m（ｍ＝１，２・・・８）から構成されている。プレート線の数は、Ｍ本（この例においては８本）であり、ＰＬ_m（ｍ＝１，２・・・８）で表している。選択用トランジスタＴＲ_1nのゲート電極に接続されたワード線ＷＬ_1nは、ワード線デコーダ／ドライバＷＤに接続されている。一方、各プレート線ＰＬ_mは、プレート線デコーダ／ドライバＰＤに接続されている。
【０１１４】
また、第１層目のメモリユニットＭＵ₁₁を構成する各メモリセルＭＣ_11mは、第１の電極２１Ａと強誘電体層２３Ａと第２の電極２４とから成り、第２層目のメモリユニットＭＵ₁₂を構成する各メモリセルＭＣ_12mは、第１の電極２１Ｂと強誘電体層２３Ｂと第２の電極２４とから成り、第３のメモリユニットＭＵ₁₃を構成する各メモリセルＭＣ_13mは、第１の電極３１Ａと強誘電体層３３Ａと第２の電極３４とから成り、第４のメモリユニットＭＵ₁₄を構成する各メモリセルＭＣ_14mは、第１の電極３１Ｂと強誘電体層３３Ｂと第２の電極３４とから成る。そして、各メモリユニットＭＵ₁₁，ＭＵ₁₂，ＭＵ₁₃，ＭＵ₁₄において、メモリセルの第１の電極２１Ａ，２１Ｂ，３１Ａ，３１Ｂは共通である。この共通の第１の電極２１Ａ，２１Ｂ，３１Ａ，３１Ｂを、便宜上、共通ノードＣＮ₁₁，ＣＮ₁₂，ＣＮ₁₃，ＣＮ₁₄と呼ぶ。
【０１１５】
ここで、第１層目のメモリユニットＭＵ₁₁における共通の第１の電極２１Ａ（第１の共通ノードＣＮ₁₁）は、第１番目の選択用トランジスタＴＲ₁₁を介してビット線ＢＬ₁に接続されている。また、第２層目のメモリユニットＭＵ₁₂における共通の第１の電極２１Ｂ（第２の共通ノードＣＮ₁₂）は、第２番目の選択用トランジスタＴＲ₁₂を介してビット線ＢＬ₁に接続されている。更には、第３層目のメモリユニットＭＵ₁₃における共通の第１の電極３１Ａ（第３の共通ノードＣＮ₁₃）は、第３番目の選択用トランジスタＴＲ₁₃を介してビット線ＢＬ₁に接続されている。また、第４層目のメモリユニットＭＵ₁₄における共通の第１の電極３１Ｂ（第４の共通ノードＣＮ₁₄）は、第４番目の選択用トランジスタＴＲ₁₄を介してビット線ＢＬ₁に接続されている。
【０１１６】
また、第１層目のメモリユニットＭＵ₁₁を構成するメモリセルＭＣ_11mと、第２層目のメモリユニットＭＵ₁₂を構成するメモリセルＭＣ_12mは、第２の電極２４を共有しており、この共有された第ｍ番目の第２の電極２４はプレート線ＰＬ_mに接続されている。更には、第３層目のメモリユニットＭＵ₁₃を構成するメモリセルＭＣ_13mと、第４層目のメモリユニットＭＵ₁₄を構成するメモリセルＭＣ_14mは、第２の電極３４を共有しており、この共有された第ｍ番目の第２の電極３４はプレート線ＰＬ_mに接続されている。具体的には、この共有された第ｍ番目の第２の電極２４の延在部からプレート線ＰＬ_mが構成され、この共有された第ｍ番目の第２の電極３４の延在部からプレート線ＰＬ_mが構成されており、各プレート線ＰＬ_mは図示しない領域で接続されている。
【０１１７】
この不揮発性メモリにおいては、メモリユニットＭＵ₁₁，ＭＵ₁₂とメモリユニットＭＵ₁₃，ＭＵ₁₄は、層間絶縁層２６を介して積層されている。メモリユニットＭＵ₁₄は絶縁膜３６Ａで被覆されている。また、メモリユニットＭＵ₁₁は、半導体基板１０の上方に絶縁層１６を介して形成されている。半導体基板１０には素子分離領域１１が形成されている。また、選択用トランジスタＴＲ₁₁，ＴＲ₁₂，ＴＲ₁₃，ＴＲ₁₄は、ゲート電極１２、ゲート絶縁膜、ソース／ドレイン領域１３から構成されている。そして、第１の選択用トランジスタＴＲ₁₁、第２の選択用トランジスタＴＲ₁₂、第３の選択用トランジスタＴＲ₁₃、第４の選択用トランジスタＴＲ₁₄の一方のソース／ドレイン領域１３はコンタクトホールを介してビット線ＢＬ₁に接続されている。また、第１の選択用トランジスタＴＲ₁₁の他方のソース／ドレイン領域１３は、絶縁層１６に形成された開口部中に設けられた接続孔１７を介して第１の共通ノードＣＮ₁₁に接続されている。更には、第２の選択用トランジスタＴＲ₁₂の他方のソース／ドレイン領域１３は、接続孔１７、第１の導電体層２２Ａ、第２の導電体層２５、第１の導電体層２２Ｂを介して第２の共通ノードＣＮ₁₂に接続されている。また、第３の選択用トランジスタＴＲ₁₃の他方のソース／ドレイン領域１３は、接続孔１７、絶縁層１６上に形成された第１の導電体層２２Ａ、第２の導電体層２５、第１の導電体層２２Ｂ、層間絶縁層２６に形成された開口部中に設けられた接続孔２７を介して第３の共通ノードＣＮ₁₃に接続されている。更には、第４の選択用トランジスタＴＲ₁₄の他方のソース／ドレイン領域１３は、接続孔１７、絶縁層１６上に形成された第１の導電体層２２Ａ、第２の導電体層２５、第１の導電体層２２Ｂ、接続孔２７、層間絶縁層２６上に形成された第１の導電体層３２Ａ、第２の導電体層３５、第１の導電体層３２Ｂを介して第４の共通ノードＣＮ₁₄に接続されている。
【０１１８】
また、本発明の第２の態様〜第４の態様に係る不揮発性メモリを、所謂ゲインセル型とすることもできる。このような不揮発性メモリの回路図を図１８に示し、不揮発性メモリを構成する各種のトランジスタの模式的なレイアウトを図１９に示し、不揮発性メモリの模式的な一部断面図を図２０及び図２１に示す。尚、図１９において、各種のトランジスタの領域を点線で囲み、活性領域及び配線を実線で示し、ゲート電極あるいはワード線を一点鎖線で示した。また、図２０に示す不揮発性メモリの模式的な一部断面図は、図１９の線Ａ−Ａに沿った模式的な一部断面図であり、図２１に示す不揮発性メモリの模式的な一部断面図は、図１９の線Ｂ−Ｂに沿った模式的な一部断面図である。
【０１１９】
この不揮発性メモリは、例えば、ビット線ＢＬと、書込用トランジスタ（本発明の第２の態様〜第４の態様に係る不揮発性メモリにおける選択用トランジスタである）ＴＲ_Wと、Ｍ個（但し、Ｍ≧２であり、例えば、Ｍ＝８）のメモリセルＭＣ_Mから構成され、層間絶縁層を介して積層されたＮ個のメモリユニットＭＵと、Ｍ本のプレート線ＰＬ_Mから成るメモリユニットＭＵから構成されている。尚、図面においては、第１層目のメモリユニットのみを図示した。そして、各メモリセルＭＣ_Mは、第１の電極２１と強誘電体層２３と第２の電極２４とから成り、メモリユニットＭＵを構成するメモリセルＭＣ_Mの第１の電極２１は、メモリユニットＭＵにおいて共通であり、この共通の第１の電極（共通ノードＣＮ）は、書込用トランジスタＴＲ_Wを介してビット線ＢＬに接続され、各メモリセルＭＣ_mを構成する第２の電極２４はプレート線ＰＬ_mに接続されている。メモリセルＭＣ_Mは層間絶縁層２６によって被覆されている。尚、不揮発性メモリのメモリユニットＭＵを構成するメモリセルの数（Ｍ）は８個に限定されず、一般には、Ｍ≧２を満足すればよく、２のべき数（Ｍ＝２，４，８，１６・・・）とすることが好ましい。
【０１２０】
更には、共通の第１の電極の電位変化を検出し、該検出結果をビット線に電流又は電圧として伝達する信号検出回路を備えている。言い換えれば、検出用トランジスタＴＲ_S、及び、読出用トランジスタＴＲ_Rを備えている。信号検出回路は、検出用トランジスタＴＲ_S及び読出用トランジスタＴＲ_Rから構成されている。そして、検出用トランジスタＴＲ_Sの一端は所定の電位Ｖ_ccを有する配線（例えば、不純物層から構成された電源線）に接続され、他端は読出用トランジスタＴＲ_Rを介してビット線ＢＬに接続され、各メモリセルＭＣ_mに記憶されたデータの読み出し時、読出用トランジスタＴＲ_Rが導通状態とされ、各メモリセルＭＣ_mに記憶されたデータに基づき共通の第１の電極（共通ノードＣＮ）に生じた電位により、検出用トランジスタＴＲ_Sの動作が制御される。
【０１２１】
具体的には、各種のトランジスタはＭＯＳ型ＦＥＴから構成されており、書込用トランジスタ（選択用トランジスタ）ＴＲ_Wの一方のソース／ドレイン領域は絶縁層１６に形成されたコンタクトホール１４を介してビット線ＢＬに接続され、他方のソース／ドレイン領域は、絶縁層１６に形成された開口部中に設けられた接続孔１７を介して共通の第１の電極（共通ノードＣＮ）に接続されている。また、検出用トランジスタＴＲ_Sの一方のソース／ドレイン領域は、所定の電位Ｖ_ccを有する配線に接続され、他方のソース／ドレイン領域は、読出用トランジスタＴＲ_Rの一方のソース／ドレイン領域に接続されている。より具体的には、検出用トランジスタＴＲ_Sの他方のソース／ドレイン領域と読出用トランジスタＴＲ_Rの一方のソース／ドレイン領域とは、１つのソース／ドレイン領域を占めている。更には、読出用トランジスタＴＲ_Rの他方のソース／ドレイン領域はコンタクトホール１４を介してビット線ＢＬに接続され、更に、共通の第１の電極（共通ノードＣＮ、あるいは、書込用トランジスタＴＲ_Wの他方のソース／ドレイン領域）は、開口部中に設けられた接続孔１７Ａ、ワード線ＷＬ_Sを介して検出用トランジスタＴＲ_Sのゲート電極に接続されている。また、書込用トランジスタＴＲ_Wのゲート電極に接続されたワード線ＷＬ_W及び読出用トランジスタＴＲ_Rのゲート電極に接続されたワード線ＷＬ_Rは、ワード線デコーダ／ドライバＷＤに接続されている。一方、各プレート線ＰＬ_mは、プレート線デコーダ／ドライバＰＤに接続されている。更には、ビット線ＢＬはセンスアンプＳＡに接続されている。
【０１２２】
この不揮発性メモリのメモリセルＭＣ₁からデータを読み出す場合、選択プレート線ＰＬ₁にＶ_ccを印加する。このとき、選択メモリセルＭＣ₁にデータ「１」が記憶されていれば、強誘電体層に分極反転が生じ、蓄積電荷量が増加し、共通ノードＣＮの電位が上昇する。一方、選択メモリセルＭＣ₁にデータ「０」が記憶されていれば、強誘電体層に分極反転が生ぜず、共通ノードＣＮの電位は殆ど上昇しない。即ち、共通ノードＣＮは、非選択メモリセルの強誘電体層を介して複数の非選択プレート線ＰＬ_kにカップリングされているので、共通ノードＣＮの電位は０ボルトに比較的近いレベルに保たれる。このようにして、選択メモリセルＭＣ₁に記憶されたデータに依存して共通ノードＣＮの電位に変化が生じる。従って、選択メモリセルの強誘電体層には、分極反転に十分な電界を与えることができる。そして、ビット線ＢＬを浮遊状態とし、読出用トランジスタＴＲ_Rをオン状態とする。一方、選択メモリセルＭＣ₁に記憶されたデータに基づき共通の第１の電極（共通ノードＣＮ）に生じた電位により、検出用トランジスタＴＲ_Sの動作が制御される。具体的には、選択メモリセルＭＣ₁に記憶されたデータに基づき共通の第１の電極（共通ノードＣＮ）に高い電位が生じれば、検出用トランジスタＴＲ_Sは導通状態となり、検出用トランジスタＴＲ_Sの一方のソース／ドレイン領域は所定の電位Ｖ_ccを有する配線に接続されているので、かかる配線から、検出用トランジスタＴＲ_S及び読出用トランジスタＴＲ_Rを介してビット線ＢＬに電流が流れ、ビット線ＢＬの電位が上昇する。即ち、信号検出回路によって共通の第１の電極（共通ノードＣＮ）の電位変化が検出され、この検出結果がビット線ＢＬに電圧（電位）として伝達される。ここで、検出用トランジスタＴＲ_Sの閾値をＶ_th、検出用トランジスタＴＲ_Sのゲート電極の電位（即ち、共通ノードＣＮの電位）をＶ_gとすれば、ビット線ＢＬの電位は概ね（Ｖ_g−Ｖ_th）となる。尚、検出用トランジスタＴＲ_Sをディプレッション型のＮＭＯＳＦＥＴとすれば、閾値Ｖ_thは負の値をとる。これにより、ビット線ＢＬの負荷の大小に拘わらず、安定したセンス信号量を確保できる。尚、検出用トランジスタＴＲ_SをＰＭＯＳＦＥＴから構成することもできる。
【０１２３】
尚、検出用トランジスタの一端が接続された配線の所定の電位はＶ_ccに限定されず、例えば、接地されていてもよい。即ち、検出用トランジスタの一端が接続された配線の所定の電位を０ボルトとしてもよい。但し、この場合には、選択メモリセルにおけるデータの読み出し時に電位（Ｖ_cc）がビット線に現れた場合、再書き込み時には、ビット線の電位を０ボルトとし、選択メモリセルにおけるデータの読み出し時に０ボルトがビット線に現れた場合、再書き込み時には、ビット線の電位をＶ_ccとする必要がある。そのためには、図２２に例示するような、トランジスタＴＲ_IV-1，ＴＲ_IV-2，ＴＲ_IV-3，ＴＲ_IV-4から構成された一種のスイッチ回路（反転回路）をビット線間に配設し、データの読み出し時には、トランジスタＴＲ_IV-2，ＴＲ_IV-4をオン状態とし，データの再書き込み時には、トランジスタＴＲ_IV-1，ＴＲ_IV-3をオン状態とすればよい。
【０１２４】
また、例えば、図２３に示すように、実施の形態２の不揮発性メモリの変形例として、第１の電極２１’，３１’を上部電極とし、第２の電極２４’，３４’を下部電極とすることもできる。このような構造は、他の発明の実施の形態における不揮発性メモリにも適用することができる。尚、図２３中、参照番号２２’，３２’は、第１の導電体層を示し、参照番号２５’，３５’は第２の導電体層を示す。
【０１２５】
【発明の効果】
本発明の強誘電体型不揮発性半導体メモリあるいは半導体装置において、接続孔の頂面は、第１の電極と同時に形成された第１の導電体層、及び、第２の電極と同時に形成された第２の導電体層の積層構造によって被覆されているので、第２の電極の形成時に接続孔の頂面に損傷が生じることを確実に防止することができる。更には、層間絶縁層のそれぞれに接続孔を形成するので、接続孔のアスペクト比が左程大きくなることがなく、確実に接続孔を形成することができる。また、第１の電極等を所謂ダマシン構造とする場合、第１の導電体層が形成されているので、ＣＭＰ法における加工精度の向上を図ることができる。本発明の半導体装置にあっては、周辺回路を構成する配線は、少なくとも、第２の電極と同時に形成された第２の導電体層から構成されているので、周辺回路の配線層数を減少させることができる。また、接続孔の頂面に第１の導電体層及び２の導電体層の積層構造によって一種の接続用のパッド部を形成するので、周辺回路における接続領域の面積の縮小化を図ることができる。しかも、本発明の半導体装置においては、配線形成のプロセスを、従来の技術と比較して簡略化することができるし、チップ面積の縮小を図ることもでき、結果として、半導体装置の製造コストダウンを図ることができる。
【図面の簡単な説明】
【図１】発明の実施の形態１の強誘電体型不揮発性半導体メモリを含む半導体装置をビット線の延びる方向と平行な仮想垂直面で切断したときの模式的な一部断面図である。
【図２】発明の実施の形態１の強誘電体型不揮発性半導体メモリを含む半導体装置をワード線の延びる方向と平行な仮想垂直面で切断したときの模式的な一部断面図である。
【図３】本発明の第２の態様に係る不揮発性メモリの概念的な回路図である。
【図４】図３の（Ａ）に示す概念的な回路図のより具体的な回路図である。
【図５】図３の（Ｂ）に示す概念的な回路図のより具体的な回路図である。
【図６】発明の実施の形態１の半導体装置の製造方法を説明するための半導体基板等の模式的な一部断面図である。
【図７】図６に引き続き、発明の実施の形態１の半導体装置の製造方法を説明するための半導体基板等の模式的な一部断面図である。
【図８】図７に引き続き、発明の実施の形態１の半導体装置の製造方法を説明するための半導体基板等の模式的な一部断面図である。
【図９】発明の実施の形態２の強誘電体型不揮発性半導体メモリを含む半導体装置をビット線の延びる方向と平行な仮想垂直面で切断したときの模式的な一部断面図である。
【図１０】本発明の第３の態様に係る不揮発性メモリの概念的な回路図である。
【図１１】図１０の（Ａ）に示す概念的な回路図のより具体的な回路図である。
【図１２】図１０の（Ｂ）に示す概念的な回路図のより具体的な回路図である。
【図１３】発明の実施の形態３の強誘電体型不揮発性半導体メモリを含む半導体装置をビット線の延びる方向と平行な仮想垂直面で切断したときの模式的な一部断面図である。
【図１４】本発明の第４の態様に係る不揮発性メモリの概念的な回路図である。
【図１５】図１４に示す概念的な回路図のより具体的な回路図である。
【図１６】発明の実施の形態２にて説明した強誘電体型不揮発性半導体メモリの変形例を示す模式的な一部断面図である。
【図１７】図１６に示す強誘電体型不揮発性半導体メモリの回路図である。
【図１８】ゲインセル型の強誘電体型不揮発性半導体メモリの回路図である。
【図１９】図１８に示したの強誘電体型不揮発性半導体メモリにおけるレイアウト図である。
【図２０】図１８に示した強誘電体型不揮発性半導体メモリの模式的な一部断面図である。
【図２１】図１８に示した強誘電体型不揮発性半導体メモリの、図２０とは異なる断面で見たときの模式的な一部断面図である。
【図２２】検出用トランジスタの一端が接続された配線の所定の電位を０ボルトとした場合の、ビット線間に配設された一種のスイッチ回路を示す回路図である。
【図２３】発明の実施の形態２の強誘電体型不揮発性半導体メモリの別の変形例の模式的な一部断面図である。
【図２４】強誘電体のＰ−Ｅヒステリシスループ図である。
【図２５】米国特許第４８７３６６４号に開示された強誘電体型不揮発性半導体メモリの回路図である。
【図２６】特開平９−１２１０３２号公報に開示された強誘電体型不揮発性半導体メモリの回路図である。
【図２７】特開平９−１２１０３２号公報に開示された不揮発性メモリにおいて、複数のメモリセルから成るメモリユニットを積層した場合を想定した半導体装置の模式的な一部断面図である。
【図２８】図２７とは別の角度から眺めた、特開平９−１２１０３２号公報に開示された不揮発性メモリにおいて、複数のメモリセルから成るメモリユニットを積層した場合を想定した半導体装置の模式的な一部断面図である。
【符号の説明】
１０・・・シリコン半導体基板、１１・・・素子分離領域、１２，１１２，２１２・・・ゲート電極、１３，１３Ａ，１３Ｂ，１１３，２１３・・・ソース／ドレイン領域、１４・・・コンタクトホール、１６・・・絶縁層、１７，２７，１１７，１２７，２１７，２２７・・・接続孔、２１，２１Ａ，２１Ｂ，２１’，３１，３１Ａ，３１Ｂ，３１’・・・第１の電極、２２，２２’，２２Ａ，２２Ｂ，３２，３２’，３２Ａ，３２Ｂ，１２２，１３２・・・第１の導電体層、２３，２３Ａ，２３Ｂ，２３’，３３，３３Ａ，３３Ｂ，３３’・・・強誘電体層、２４，３４・・・第２の電極、２５，２５’，３５，３５’１２５，１３５・・・第２の導電体層、２６・・・層間絶縁層、３６Ａ，４６Ａ・・・絶縁膜、ＴＲ・・・選択用トランジスタ、ＴＲ_W・・・書込用トランジスタ、ＴＲ_R・・・読出用トランジスタ、ＴＲ_S・・・検出用トランジスタ、ＴＲ_SW・・・スイッチング用のトランジスタ、ＷＬ・・・ワード線、ＢＬ・・・ビット線、ＰＬ・・・プレート線、ＷＤ・・・ワード線デコーダ／ドライバ、ＳＡ・・・センスアンプ、ＰＤ・・・プレート線デコーダ／ドライバ、ＣＮ・・・共通ノード[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a ferroelectric nonvolatile semiconductor memory (so-called FERAM), and a semiconductor device including a ferroelectric nonvolatile semiconductor memory and its peripheral circuit.
[0002]
[Prior art]
In recent years, research on large-capacity ferroelectric nonvolatile semiconductor memories has been actively conducted. A ferroelectric type nonvolatile semiconductor memory (hereinafter sometimes abbreviated as “nonvolatile memory”) is capable of high-speed access, is nonvolatile, is small in size and has low power consumption, and is also susceptible to impact. For example, various electronic devices having file storage and resume functions, such as portable computers, mobile phones, game machines as main storage devices, or recording media for recording audio and video Use is expected.
[0003]
This non-volatile memory is a non-volatile memory capable of high-speed rewriting, which uses a high-speed polarization reversal of the ferroelectric thin film and its residual polarization to detect changes in the amount of charge stored in the capacitor portion having the ferroelectric layer. Basically, it is composed of a memory cell (capacitor portion) and a selection transistor (switching transistor). The memory cell (capacitor portion) is composed of, for example, a lower electrode, an upper electrode, and a ferroelectric layer sandwiched between these electrodes. Data is written to and read from the nonvolatile memory by applying a ferroelectric PE hysteresis loop shown in FIG. That is, when an external electric field is applied to the ferroelectric layer and then the external electric field is removed, the ferroelectric layer exhibits spontaneous polarization. Then, the remanent polarization of the ferroelectric layer is + P when an external electric field in the positive direction is applied._rWhen an external electric field in the negative direction is applied, -P_rIt becomes. Here, the remanent polarization is + P_rIn the case of the state (see “D” in FIG. 24), “0” is set and the residual polarization is −P._rIn this state (see “A” in FIG. 24), “1” is set.
[0004]
In order to determine the state of “1” or “0”, for example, an external electric field in the positive direction is applied to the ferroelectric layer. As a result, the polarization of the ferroelectric layer becomes the state “C” in FIG. At this time, if the data is “0”, the polarization state of the ferroelectric layer changes from “D” to “C”. On the other hand, if the data is “1”, the polarization state of the ferroelectric layer changes from “A” to “C” via “B”. When the data is “0”, the polarization inversion of the ferroelectric layer does not occur. On the other hand, when the data is “1”, polarization inversion occurs in the ferroelectric layer. As a result, a difference occurs in the accumulated charge amount of the memory cell (capacitor portion). By turning on the selection transistor of the selected nonvolatile memory, this accumulated charge is detected as a signal current. When the external electric field is set to 0 after the data is read, the polarization state of the ferroelectric layer becomes the state “D” in FIG. 24 regardless of whether the data is “0” or “1”. That is, at the time of reading, the data “1” is once destroyed. Therefore, when the data is “1”, an external electric field in the negative direction is applied to make the state “A” along the paths “D” and “E”, and the data “1” is written again.
[0005]
The structure and operation of nonvolatile memories which are currently mainstream are disclosed in US Pat. Shefiled et al. The nonvolatile memory is composed of two nonvolatile memory cells as shown in a circuit diagram of FIG. In FIG. 25, one nonvolatile memory is surrounded by a dotted line. Each nonvolatile memory includes, for example, a selection transistor TR₁₁, TR₁₂, Memory cell (capacitor part) FC₁₁, FC₁₂It is composed of
[0006]
Note that a two-digit or three-digit subscript, for example, the subscript “11” is originally a subscript to be displayed as the subscript “1,1”. For example, “111” is originally a subscript “1,1,1”. Although it is a subscript to be displayed, it is displayed with a 2-digit or 3-digit subscript for simplification of display. The subscript “M” is used, for example, when collectively displaying a plurality of memory cells or plate lines, and the subscript “m” is used, for example, when displaying a plurality of memory cells or plate lines individually. The subscript “N” is used, for example, when the selection transistors and memory units are displayed collectively, and the subscript “n” is used, for example, when the selection transistors and memory units are individually displayed.
[0007]
Then, 1 bit is stored by writing complementary data in each memory cell. In FIG. 25, the symbol “WL” indicates a word line, the symbol “BL” indicates a bit line, and the symbol “PL” indicates a plate line. Focusing on one nonvolatile memory, the word line WL₁Are connected to a word line decoder / driver WD. In addition, the bit line BL₁, BL₂Are connected to the sense amplifier SA. Furthermore, the plate line PL₁Are connected to a plate line decoder / driver PD.
[0008]
When reading stored data in a nonvolatile memory having such a structure, the word line WL₁And, further, plate line PL₁, The complementary data becomes a pair of memory cells (capacitor part) FC₁₁, FC₁₂To transistor for selection TR₁₁, TR₁₂Bit line BL paired via₁, BL₂Appears as a voltage (bit line potential). The paired bit lines BL₁, BL₂Is detected by the sense amplifier SA.
[0009]
One nonvolatile memory is a word line WL₁And paired bit lines BL₁, BL₂Occupies the area surrounded by. Therefore, if the word lines and the bit lines are arranged at the shortest pitch, the minimum area of one nonvolatile memory is 8F when the minimum processing dimension is F.²It is. Therefore, the minimum area of the nonvolatile memory having such a structure is 8F.²It is.
[0010]
In order to increase the capacity of the nonvolatile memory having such a structure, the realization of the nonvolatile memory depends only on the miniaturization of the processing dimensions. Further, in order to form one nonvolatile memory, two selection transistors and two memory cells (capacitor portions) are required. Furthermore, it is necessary to arrange plate lines at the same pitch as the word lines. Therefore, it is almost impossible to arrange the nonvolatile memories at the minimum pitch. In reality, the area occupied by one nonvolatile memory is 8F.²Will increase significantly.
[0011]
Moreover, it is necessary to dispose the word line decoder / driver WD and the plate line decoder / driver PD at the same pitch as that of the nonvolatile memory. In other words, two decoders / drivers are required to select one row address. Therefore, the layout of the peripheral circuit becomes difficult, and the area occupied by the peripheral circuit becomes large.
[0012]
One means for reducing the area of the nonvolatile memory is known from Japanese Patent Laid-Open No. 9-121022. As shown in an equivalent circuit in FIG. 26, the nonvolatile memory disclosed in this patent publication is composed of one selection transistor TR.₁Memory cells MC each having one end connected in parallel to one end of the memory cell_1M(For example, M = 4), and the memory cell paired with the memory cell is also a single selection transistor TR.₂Memory cells MC each having one end connected in parallel to one end of the memory cell_2MIt is composed of Selection transistor TR₁, TR₂The other end of each bit line BL₁, BL₂It is connected to the. Paired bit lines BL₁, BL₂Are connected to the sense amplifier SA. In addition, the memory cell MC_1m, MC_2mThe other end of (m = 1, 2,... M) is the plate line PL_mIs connected to the plate line PL_mAre connected to a plate line decoder / driver PD. Furthermore, the word line WL is connected to a word line decoder / driver WD.
[0013]
The paired memory cells MC_1m, MC_2mComplementary data is stored in (m = 1, 2,... M). For example, the memory cell MC_1m, MC_2mWhen data stored in (where m is any one of 1, 2, 3 and 4) is read, the word line WL is selected and the plate line PL_j(M ≠ j) has (1/2) V_ccWith the voltage of_mDrive. Where V_ccIs, for example, a power supply voltage. As a result, the complementary data is converted into a pair of memory cells MC._1m, MC_2mTo transistor for selection TR₁, TR₂Bit line BL paired via₁, BL₂Appears as a voltage (bit line potential). The paired bit lines BL₁, BL₂Is detected by the sense amplifier SA.
[0014]
A pair of selection transistors TR in a paired nonvolatile memory₁And TR₂Are the word line WL and the paired bit line BL.₁, BL₂Occupies the area surrounded by. Accordingly, if the word lines and the bit lines are arranged at the shortest pitch, a pair of selection transistors TR in the paired nonvolatile memory is assumed.₁And TR₂The minimum area is 8F²It is. However, a pair of selection transistors TR₁, TR₂M pairs of memory cells MC_1m, MC_2m(M = 1, 2,... M), so that the selection transistor TR per bit is shared.₁, TR₂Since the number of memory cells is small and the arrangement of the word lines WL is gradual, it is easy to reduce the size of the nonvolatile memory. In addition, for the peripheral circuit, M bits can be selected by one word line decoder / driver WD and M plate line decoder / driver PD. Therefore, by adopting such a configuration, the cell area is 8F.²A layout close to that of a DRAM can be realized, and a chip size comparable to that of a DRAM can be realized.
[0015]
[Problems to be solved by the invention]
The technique for reducing the area of the nonvolatile memory disclosed in Japanese Patent Application Laid-Open No. 9-121032 is a very effective technique, but there is a strong demand for further reduction of the area of the nonvolatile memory. As one of measures for addressing such a demand, a method of stacking memory units composed of a plurality of memory cells is conceivable. 27 and 28 are schematic partial cross-sectional views of a semiconductor device including a nonvolatile memory employing such a method. 27 is a schematic partial cross-sectional view of the semiconductor device cut along a virtual vertical plane parallel to the extending direction of the bit line, and FIG. It is a typical partial sectional view when an apparatus is cut | disconnected. In FIG. 27, the memory unit MU₁And memory unit MU₂Are not located on the same virtual vertical plane, and the selection transistor TR₁And selection transistor TR₂Are not located on the same virtual vertical plane, but are shown together in FIG. 27 to simplify the drawing. The equivalent circuit is as shown in FIG.
[0016]
This non-volatile memory
(1) Two bit lines BL₁, BL₂When,
(2) Two selection transistors TR formed on the semiconductor substrate 10₁, TR₂When,
(3) Two memory units MU each consisting of four memory cells₁, MU₂When,
(4) 4 plate wires,
It is composed of
[0017]
And the memory unit MU₁Is a selection transistor TR through an insulating layer 16.₁Formed above the two memory units MU₁, MU₂Are stacked via an interlayer insulating layer 26. Each memory cell includes first electrodes 21 and 31, ferroelectric layers 23 and 33, and second electrodes 24 and 34, and each memory unit MU.₁, MU₂1, the first electrodes 21 and 31 of the memory cell are common. Further, in the n-th (where n = 1, 2, 3, 4) memory unit, the second electrodes 24 of the m-th (where m = 1, 2, 3, 4) memory cell, 34 is a memory unit MU₁, MU₂It is connected to the mth plate line, which is common among the two. In FIG. 27, the state in which the plate line is connected is omitted. Then, the selection transistor TR₁One source / drain region 13A of the bit line BL₁Connected to the transistor for selection TR₂One source / drain region 13A of the bit line BL₂It is connected to the. In FIG. 27, the bit line BL₁, BL₂Is extended in the left-right direction, but in order to simplify the drawing, the bit line BL₁, BL₂Only a part of is shown.
[0018]
The selection transistor TR₁The other source / drain region 13B of the memory unit MU is connected to the memory unit MU via a connection hole 17 provided in the insulating layer 16.₁Are connected to the common first electrode 21. On the other hand, the selection transistor TR₂The other source / drain region 13 is connected to the memory unit MU via the insulating layer 16 and the connection hole 27A provided in the interlayer insulating layer 26.₂Are connected to the common first electrode 31.
[0019]
Further, in the peripheral circuit shown in FIG. 27, the transistor TR including the gate electrode 112 and the source / drain region 113 is formed._P1, TR_P2Sense amplifier SA etc. comprised from these are provided. On the other hand, in the peripheral circuit shown in FIG. 28, the transistor TR composed of the gate electrode 212 and the source / drain region 213._P3, TR_P4, TR_P5Are provided with a word line decoder / driver WD, a plate line decoder / driver PD, and the like.
[0020]
27 and 28, reference numerals 36A and 46A are insulating films, reference numerals 150, 250, 251A and 251B are metal wirings, and reference numeral 47A is a pad portion made of a metal wiring material. Reference numerals 37A, 37B, and 47B are connection holes (contact holes) in the nonvolatile memory, and reference numerals 337A and 337B are connection holes (contact holes) in the peripheral circuit.
[0021]
In the nonvolatile memory having such a structure, in order to electrically connect the plate line PL extending from the second electrodes 24 and 34 and the transistor constituting the plate line decoder / driver PD corresponding to the peripheral circuit. In the conventional concept, the metal wiring 251A, 251B and the connection holes (contact holes) 37A, 37B, 37B are generally used.
[0022]
However, such a method has a problem that the number of metal wiring layers increases. Further, when a connection hole (contact hole) is formed in a state in which a large number of interlayer insulating layers and insulating films are laminated, the connection hole may be difficult to form because the aspect ratio of the connection hole is increased. A method of forming a connection hole every time an interlayer insulating layer or an insulating film is formed is also conceivable. However, after forming the connection hole, a first electrode material layer constituting the first electrode is formed, and the first electrode is formed. When the material layer is patterned by etching, the top surface of the connection hole is exposed, and the top surface of the connection hole may be etched to cause damage. Furthermore, when the first electrode material layer constituting the first electrode is formed and patterned by etching, the top surface of the connection hole is formed using the first electrode material layer as a kind of pad portion. However, when the second electrode material layer constituting the second electrode is formed and patterned by etching, the pad portion made of the first electrode material layer is etched. The top surface of the connection hole is exposed, and the top surface of the connection hole may be etched to cause damage.
[0023]
Accordingly, a first object of the present invention is a ferroelectric nonvolatile semiconductor memory having a multi-stack structure in which a plurality of memory cells are stacked with an interlayer insulating layer interposed therebetween, and the top surface of the connection hole is damaged. It is an object of the present invention to provide a ferroelectric nonvolatile semiconductor memory having a difficult structure.
[0024]
Furthermore, a second object of the present invention is to provide a ferroelectric nonvolatile semiconductor memory that can reliably form a connection hole (contact hole) in addition to the first object.
[0025]
A third object of the present invention is to provide a ferroelectric nonvolatile semiconductor memory and a semiconductor device including the peripheral circuit, which can reduce the number of wiring layers in the peripheral circuit.
[0026]
[Means for Solving the Problems]
In order to achieve the above first object, a ferroelectric nonvolatile semiconductor memory according to a first aspect of the present invention includes: a first insulating layer provided on a semiconductor substrate on which a transistor is formed; A ferroelectric cell having a structure in which a memory cell composed of an electrode, a ferroelectric layer, and a second electrode has a structure in which N layers are stacked via an (N-1) interlayer insulating layer (N ≧ 2). A body-type nonvolatile semiconductor memory,
A connection hole is formed in the insulating layer on the source / drain region and / or the gate electrode of the transistor, and in the insulating layer and the interlayer insulating layer.
The top surface of the connection hole formed in the insulating layer constitutes the first conductor layer formed simultaneously with the first electrode constituting the first layer memory cell, and the first layer memory cell. The second electrode layer is covered with a laminated structure of a second conductor layer formed simultaneously with the second electrode.
[0027]
In the ferroelectric nonvolatile semiconductor memory according to the first aspect of the present invention, the connection formed in the kth layer (where k = 1, 2,..., N−1) interlayer insulating layer. The top surface of the hole includes a first conductor layer formed at the same time as the first electrode constituting the (k + 1) th layer memory cell and a second conductor constituting the (k + 1) th layer memory cell. It is preferable to have a structure covered with a laminated structure of a second conductor layer formed simultaneously with the electrode of the electrode, whereby the second object described above can be achieved.
[0028]
In order to achieve the above first and second objects, the ferroelectric nonvolatile semiconductor memory according to the second aspect of the present invention includes:
(A) a bit line;
(B) a selection transistor;
(C) N (where N ≧ 2) memory units each composed of M (where M ≧ 2) memory cells;
(D) M × N plate wires,
Consisting of
The memory unit of the first layer is formed above the selection transistor via the insulating layer,
N memory units are stacked via (N-1) interlayer insulating layers,
Each memory cell includes a first electrode, a ferroelectric layer, and a second electrode,
In each memory unit, the first electrode of the memory cell is common,
In the memory unit of the nth layer (where n = 1, 2,..., N), the second electrode of the mth memory cell (where m = 1, 2,..., M) is Connected to the [(n-1) M + m] th plate line,
One source / drain region of the selection transistor is connected to the bit line,
The other source / drain region of the selection transistor is connected to a common first electrode in the first-layer memory unit via a first-layer connection hole provided in the insulating layer.
The other source / drain region of the selection transistor further includes a first-layer connection hole provided in the insulating layer, and a first-layer interlayer insulating layer to k-th layer (provided that k = 1, 2..., N−1) to the (k + 1) th layer through each of the (k + 1) th connection hole from the second layer connection hole provided in each of the interlayer insulating layers. A ferroelectric nonvolatile semiconductor memory connected to a common first electrode in a memory unit,
The top surface of the first layer connection hole formed in the insulating layer has a first conductor layer formed simultaneously with the first electrode constituting the memory cell of the first layer memory unit, and Covered with a laminated structure of a second conductor layer formed simultaneously with the second electrode constituting the memory cell of the memory layer of the first layer;
The top surface of the (k + 1) th layer connection hole formed in the kth interlayer insulating layer is formed simultaneously with the first electrode constituting the memory cell of the (k + 1) th layer memory unit. It is covered with a laminated structure of a first conductor layer and a second conductor layer formed at the same time as a second electrode constituting a memory cell of the memory unit of the (k + 1) th layer memory unit. And
[0029]
In order to achieve the above first and second objects, the ferroelectric nonvolatile semiconductor memory according to the third aspect of the present invention comprises:
(A) a bit line;
(B) N (where N ≧ 2) selection transistors;
(C) N memory units each composed of M (where M ≧ 2) memory cells;
(D) M plate wires,
Consisting of
The memory unit of the first layer is formed above the selection transistor via the insulating layer,
N memory units are stacked via (N-1) interlayer insulating layers,
Each memory cell includes a first electrode, a ferroelectric layer, and a second electrode,
In each memory unit, the first electrode of the memory cell is common,
In the memory unit of the nth layer (where n = 1, 2,..., N), the second electrode of the mth memory cell (where m = 1, 2,..., M) is It is connected to the mth plate line that is shared between memory units,
One source / drain region of each selection transistor is connected to the bit line,
The other source / drain region of the first selection transistor is connected to a common first electrode in the memory unit of the first layer via a connection hole of the first layer provided in the insulating layer. ,
The other source / drain region of the (k + 1) -th (k = 1, 2,..., N−1) selection transistor has a first layer connection hole provided in the insulating layer, and The (k + 1) th through the (k + 1) th connection hole from the second layer connection hole provided in each of the interlayer insulation layers from the first interlayer insulation layer to the kth layer. A ferroelectric-type nonvolatile semiconductor memory connected to a common first electrode in the memory unit of the layer;
The top surface of the first layer connection hole formed in the insulating layer has a first conductor layer formed simultaneously with the first electrode constituting the memory cell of the first layer memory unit, and Covered with a laminated structure of a second conductor layer formed simultaneously with the second electrode constituting the memory cell of the memory layer of the first layer;
The top surface of the (k + 1) th layer connection hole formed in the kth interlayer insulating layer is formed simultaneously with the first electrode constituting the memory cell of the (k + 1) th layer memory unit. It is covered with a laminated structure of a first conductor layer and a second conductor layer formed at the same time as a second electrode constituting a memory cell of the memory unit of the (k + 1) th layer memory unit. And
[0030]
In order to achieve the above first and second objects, a ferroelectric nonvolatile semiconductor memory according to the fourth aspect of the present invention includes:
(A) N (where N ≧ 2) bit lines;
(B) N selection transistors;
(C) N memory units each composed of M (where M ≧ 2) memory cells;
(D) M plate wires,
Consisting of
The memory unit of the first layer is formed above the selection transistor via the insulating layer,
N memory units are stacked via (N-1) interlayer insulating layers,
Each memory cell includes a first electrode, a ferroelectric layer, and a second electrode,
In each memory unit, the first electrode of the memory cell is common,
In the memory unit of the nth layer (where n = 1, 2,..., N), the second electrode of the mth memory cell (where m = 1, 2,..., M) is It is connected to the mth plate line that is shared between memory units,
One source / drain region of the nth selection transistor is connected to the nth bit line,
The other source / drain region of the first selection transistor is connected to a common first electrode in the memory unit of the first layer via a connection hole of the first layer provided in the insulating layer. ,
The other source / drain region of the (k + 1) -th (k = 1, 2,..., N−1) selection transistor has a first layer connection hole provided in the insulating layer, and The (k + 1) th through the (k + 1) th connection hole from the second layer connection hole provided in each of the interlayer insulation layers from the first interlayer insulation layer to the kth layer. A ferroelectric-type nonvolatile semiconductor memory connected to a common first electrode in the memory unit of the layer;
The top surface of the first layer connection hole formed in the insulating layer has a first conductor layer formed simultaneously with the first electrode constituting the memory cell of the first layer memory unit, and Covered with a laminated structure of a second conductor layer formed simultaneously with the second electrode constituting the memory cell of the memory layer of the first layer;
The top surface of the (k + 1) th layer connection hole formed in the kth interlayer insulating layer is formed simultaneously with the first electrode constituting the memory cell of the (k + 1) th layer memory unit. It is covered with a laminated structure of a first conductor layer and a second conductor layer formed at the same time as a second electrode constituting a memory cell of the memory unit of the (k + 1) th layer memory unit. And
[0031]
The semiconductor device of the present invention for achieving the third object is
(A) A memory cell including a first electrode, a ferroelectric layer, and a second electrode is formed on an insulating layer provided on a semiconductor substrate on which a selection transistor is formed. A ferroelectric nonvolatile semiconductor memory having a structure in which N layers are stacked through an interlayer insulating layer (where N ≧ 2),
(B) a peripheral circuit for driving a ferroelectric nonvolatile semiconductor memory;
A semiconductor device comprising:
The peripheral circuit includes a transistor formed on the semiconductor substrate, wiring formed on the insulating layer and the interlayer insulating layer, and a connection hole connecting the transistor and the wiring.
The connection hole is formed in the insulating layer on the source / drain region and / or the gate electrode of the transistor, and in the insulating layer and the interlayer insulating layer,
The top surface of the connection hole formed in the insulating layer constitutes the first conductor layer formed simultaneously with the first electrode constituting the first layer memory cell, and the first layer memory cell. Covered with a stacked structure of second conductor layers formed simultaneously with the second electrode,
The wiring formed on the insulating layer includes at least a second conductor layer formed simultaneously with the second electrode constituting the first-layer memory cell,
The top surface of the connection hole formed in the interlayer insulating layer of the k-th layer (where k = 1, 2,..., N−1) is the first of the memory cells of the (k + 1) -th layer. The first conductor layer formed simultaneously with the electrode and the second conductor layer formed simultaneously with the second electrode constituting the (k + 1) th layer memory cell are covered with the laminated structure. ,
The wiring formed on the k-th interlayer insulating layer includes at least a second conductor layer formed simultaneously with the second electrode constituting the (k + 1) -th memory cell. And
[0032]
In the semiconductor device of the present invention, the wiring formed on the insulating layer includes the first conductor layer formed simultaneously with the first electrode constituting the first-layer memory cell, and the first A layered structure of a second conductor layer formed simultaneously with the second electrode constituting the memory cell of the layer,
The wiring formed on the k-th layer (where k = 1, 2,..., N−1) interlayer insulating layer is simultaneously with the first electrode constituting the (k + 1) -th layer memory cell. The first conductor layer formed and the second conductor layer formed at the same time as the second electrode constituting the (k + 1) th memory cell may be stacked. .
[0033]
The configuration of the ferroelectric nonvolatile semiconductor memory in the semiconductor device of the present invention can be the ferroelectric nonvolatile semiconductor memory according to the second to fourth aspects of the present invention.
[0034]
In the ferroelectric-type nonvolatile semiconductor memory or semiconductor device of the present invention (hereinafter, these may be collectively referred to simply as the present invention), it is only necessary to satisfy N ≧ 2, and a practical value of N For example, a power of 2 (2, 4, 8...) Can be mentioned. In the ferroelectric nonvolatile semiconductor memory according to the second to fourth aspects of the present invention, it is only necessary to satisfy M ≧ 2, and as an actual value of M, for example, a power of 2 ( 2, 4, 8 ...).
[0035]
In the ferroelectric-type nonvolatile semiconductor memory according to the second to fourth aspects of the present invention, practically, the ferroelectric-type nonvolatile semiconductor memory is paired (for convenience, the nonvolatile memory-A, the nonvolatile memory). The bit lines constituting the pair of ferroelectric nonvolatile semiconductor memories can be connected to the same sense amplifier. In this case, the selection transistor constituting the nonvolatile memory-A and the selection transistor constituting the nonvolatile memory-B may be connected to the same word line or connected to different word lines. May be. Depending on the configuration and operation method of the non-volatile memory-A and the non-volatile memory-B, one bit can be stored in each memory cell constituting the non-volatile memory-A and the non-volatile memory-B. One of the memory cells constituting the volatile memory-A and one of the memory cells constituting the nonvolatile memory-B connected to the same plate line as the memory cell are used as a pair. Complementary data can also be stored.
[0036]
Examples of the material constituting the ferroelectric layer in the ferroelectric nonvolatile semiconductor memory include a bismuth layered compound, more specifically, a Bi-based layered structure perovskite type ferroelectric material. Bi-based layered structure perovskite type ferroelectric materials belong to so-called non-stoichiometric compounds and are tolerant of compositional shifts at both sites of metal elements and anion (O, etc.) elements. It is also not uncommon for optimal electrical characteristics to be exhibited at a slight deviation from the stoichiometric composition. Bi-based layered structure perovskite type ferroelectric materials include, for example, the general formula₂O₂)²⁺(A_m-1B_mO_{3m + 1})^2-Can be expressed as Here, “A” represents one type of metal selected from the group consisting of metals such as Bi, Pb, Ba, Sr, Ca, Na, K, and Cd, and “B” represents Ti, Nb. , Ta, W, Mo, Fe, Co, Cr, and one type selected from the group consisting of a plurality of types, or a combination based on an arbitrary ratio. M is an integer of 1 or more.
[0037]
Alternatively, the material constituting the ferroelectric layer is
(Bi_X, Sr_1-X)₂(Sr_Y, Bi_1-Y) (Ta_Z, Nb_1-Z)₂O_d  Formula (1)
(However, 0.9 ≦ X ≦ 1.0, 0.7 ≦ Y ≦ 1.0, 0 ≦ Z ≦ 1.0, 8.7 ≦ d ≦ 9.3) It is preferable to include as a phase. Alternatively, the material constituting the ferroelectric layer is
Bi_XSr_YTa₂O_d  Formula (2)
However, it is preferable that a crystal phase represented by (X + Y = 3, 0.7 ≦ Y ≦ 1.3, 8.7 ≦ d ≦ 9.3) is included as a main crystal phase. In these cases, it is more preferable that 85% or more of the crystal phase represented by the formula (1) or (2) is contained as the main crystal phase. In formula (1), (Bi_X, Sr_1-X) Means that Sr occupies the site originally occupied by Bi in the crystal structure, and the ratio of Bi and Sr at this time is X: (1-X). Also, (Sr_Y, Bi_1-Y) Means that Bi occupies the site originally occupied by Sr in the crystal structure, and the ratio of Sr and Bi at this time is Y: (1-Y). The material constituting the ferroelectric layer including the crystal phase represented by the formula (1) or (2) as the main crystal phase includes Bi oxide, Ta and Nb oxide, Bi, Ta and Nb. There may be some composite oxides.
[0038]
Alternatively, the material constituting the ferroelectric layer is
Bi_X(Sr, Ca, Ba)_Y(Ta_Z, Nb_1-Z)₂O_d  Formula (3)
(However, the crystal phase represented by 1.7 ≦ X ≦ 2.5, 0.6 ≦ Y ≦ 1.2, 0 ≦ Z ≦ 1.0, 8.0 ≦ d ≦ 10.0) is included. May be. “(Sr, Ca, Ba)” means one type of element selected from the group consisting of Sr, Ca, and Ba. If the composition of the material constituting the ferroelectric layer represented by each of these formulas is represented by the stoichiometric composition, for example, Bi₂SrTa₂O₉, Bi₂SrNb₂O₉, Bi₂BaTa₂O₉, Bi₂Sr (Ta, Nb)₂O₉Etc. Alternatively, as a material constituting the ferroelectric layer, Bi_FourSrTi_FourO₁₅, Bi_ThreeTiNbO₉, Bi_ThreeTiTaO₉, Bi_FourTi_ThreeO₁₂, Bi₂PbTa₂O₉In these cases, the ratio of each metal element can be changed to such an extent that the crystal structure does not change. That is, there may be a composition shift at both sites of the metal element and oxygen element.
[0039]
Alternatively, as a material constituting the ferroelectric layer, PbTiO_ThreePbZrO having a perovskite structure_ThreeAnd PbTiO_ThreeZirconate titanate [PZT, Pb (Zr_1-y, Ti_y) O_Three(Where 0 <y <1)], PZT compounds such as PLZT, which is a metal oxide obtained by adding La to PZT, or PNZT, which is a metal oxide obtained by adding Nb to PZT.
[0040]
In order to obtain the ferroelectric layer, the ferroelectric thin film may be patterned in the process after the ferroelectric thin film is formed. In some cases, patterning of the ferroelectric thin film is not necessary. The ferroelectric thin film can be formed by a method suitable for the material constituting the ferroelectric thin film, such as MOCVD, pulse laser ablation, sputtering, or sol-gel. The patterning of the ferroelectric thin film can be performed by, for example, an anisotropic ion etching (RIE) method.
[0041]
In the ferroelectric nonvolatile semiconductor memory according to the second to fourth aspects of the present invention, the first electrode is formed below the ferroelectric layer, and the second electrode is formed on the ferroelectric layer. (That is, the first electrode corresponds to the lower electrode and the second electrode corresponds to the upper electrode), or the first electrode is formed on the ferroelectric layer. The second electrode may be formed under the ferroelectric layer (that is, the first electrode corresponds to the upper electrode and the second electrode corresponds to the lower electrode). The plate line is preferably configured to extend from the second electrode from the viewpoint of simplifying the wiring structure. In the laminated structure of the first conductor layer and the second conductor layer, in the former case, the first conductor layer is on the lower side and the second conductor layer is on the upper side. On the other hand, in the latter case, the second conductor layer is on the bottom and the first conductor layer is on the top. As a structure in which the first electrode is common, specifically, a configuration in which a stripe-shaped first electrode is formed and a ferroelectric layer is formed so as to cover the entire surface of the stripe-shaped first electrode. Can be mentioned. In such a structure, the overlapping region of the first electrode, the ferroelectric layer, and the second electrode corresponds to a memory cell. As a structure in which the first electrode is common, a structure in which each ferroelectric layer is formed in a predetermined region of the first electrode and the second electrode is formed on the ferroelectric layer, or In addition, each first electrode is formed on a predetermined surface region of the wiring layer, a ferroelectric layer is formed on each first electrode, and a second electrode is formed on the ferroelectric layer. However, the present invention is not limited to these configurations.
[0042]
Furthermore, in the ferroelectric nonvolatile semiconductor memory according to the second to fourth aspects of the present invention, the first electrode is formed under the ferroelectric layer, and the second electrode is formed on the ferroelectric layer. In the configuration in which the first electrode is formed, the first electrode and the first conductor layer constituting the memory cell have a so-called damascene structure, and the first electrode is formed on the ferroelectric layer. In the case where the second electrode is formed under the ferroelectric layer, the second electrode constituting the memory cell has a so-called damascene structure, and the ferroelectric layer is placed on a flat base. It is preferable from the viewpoint that it can be formed.
[0043]
In the present invention, as a material constituting the first electrode, the first conductor layer, the second electrode, and the second conductor layer, for example, Ir, IrO_2-X, SrIrO_Three, Ru, RuO_2-X, SrRuO_Three, Pt, Pt / IrO_2-X, Pt / RuO_2-X, Pd, Pt / Ti laminated structure, Pt / Ta laminated structure, Pt / Ti / Ta laminated structure, La_0.5Sr_0.5CoO_Three(LSCO), Pt / LSCO laminated structure, YBa₂Cu_ThreeO₇Can be mentioned. Here, the value of X is 0 ≦ X <2. In the laminated structure, the material described before “/” constitutes the upper layer, and the material described after “/” constitutes the lower layer. The first electrode and the second electrode, or the first conductor layer and the second conductor layer may be made of the same material, or may be made of the same kind of material, You may be comprised from a dissimilar material. After forming the first conductive material layer or the second conductive material layer, the first electrode, the first conductive layer, or the second electrode or the second conductive layer is formed. In the process, the first conductive material layer or the second conductive material layer may be patterned. The first conductive material layer or the second conductive material layer is formed by, for example, a first conductive material layer or a second conductive material layer such as a sputtering method, a reactive sputtering method, an electron beam evaporation method, an MOCVD method, or a pulsed laser ablation method. It can be performed by a method suitable for the material constituting the conductive material layer. The patterning of the first conductive material layer and the second conductive material layer can be performed by, for example, an ion milling method or an RIE method.
[0044]
The selection transistor (switching transistor) and various types of transistors can be constituted by, for example, a well-known MIS type FET or MOS type FET. Examples of the material constituting the bit line include polysilicon doped with impurities and a refractory metal material. The connection hole can be obtained, for example, by embedding a tungsten plug.
[0045]
In the present invention, silicon oxide (SiO₂), Silicon nitride (SiN), SiON, SOG, NSG, BPSG, PSG, BSG, or LTO.
[0046]
In the ferroelectric nonvolatile semiconductor memory or semiconductor device of the present invention, the top surface of the connection hole is formed with the first conductor layer formed simultaneously with the first electrode and the second electrode formed simultaneously with the second electrode. Since it is covered with the laminated structure of the two conductor layers, the top surface of the connection hole is hardly damaged. Furthermore, since the connection hole is formed in each of the interlayer insulating layers, the aspect ratio of the connection hole does not increase to the left. In the semiconductor device according to the present invention, since the wiring constituting the peripheral circuit is composed of at least the second conductor layer formed simultaneously with the second electrode, the number of wiring layers in the peripheral circuit is reduced. Can be made.
[0047]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described based on embodiments of the invention (hereinafter abbreviated as embodiments) with reference to the drawings.
[0048]
(Embodiment 1)
The first embodiment relates to a ferroelectric nonvolatile semiconductor memory (hereinafter abbreviated as a nonvolatile memory) according to the first and second aspects of the present invention, and the semiconductor device of the present invention. FIG. 1 is a schematic partial cross-sectional view of the semiconductor device of the first embodiment cut along a virtual vertical plane parallel to the direction in which the bit lines extend. 2 is a schematic partial cross-sectional view when the semiconductor device of the first embodiment is cut along the arrow AA in FIG. Further, a conceptual circuit diagram of the nonvolatile memory according to the second aspect of the present invention is shown in FIGS. 3A and 3B, and more concrete than the conceptual circuit diagram of FIG. FIG. 4 shows a typical circuit diagram, and FIG. 5 shows a more specific circuit diagram of the conceptual circuit diagram of FIG. 4 and 5 show two nonvolatile memories M.₁, M₂These non-volatile memories M are shown in FIG.₁, M₂The structure of the non-volatile memory M will be described below.₁Will be explained.
[0049]
The nonvolatile memory in the first embodiment includes a transistor TR₁, TR_P1~ TR_P5A memory cell MC comprising first electrodes 21, 31, ferroelectric layers 23, 33 and second electrodes 24, 34 on an insulating layer 16 provided on a semiconductor substrate 10 on which is formed.₁₁₁~ MC₁₁₄, MC₁₂₁~ MC₁₂₄However, N layers (specifically, two layers) are stacked through (N−1) interlayer insulating layers (where N ≧ 2, N = 2 in the first embodiment) 26. This is a ferroelectric nonvolatile semiconductor memory having the above structure.
[0050]
And transistor TR₁, TR_P1~ TR_P5Connection holes 17, 117, 27, 127, 217, 227 are formed in the insulating layer 16 and the interlayer insulating layer 26 on the source / drain regions 13, 113, 213 and / or the gate electrodes 12, 112, 212. The top surfaces of the connection holes 17, 117, and 217 formed in the insulating layer 16 are the first conductor layers 22 and 122 formed simultaneously with the first electrode 21 that constitutes the first-layer memory cell, And it is covered with a laminated structure of second conductor layers 25 and 125 formed simultaneously with the second electrode 24 constituting the memory cell of the first layer.
[0051]
Further, the connection holes 27 and 127 formed in the interlayer insulating layer 26 of the k-th layer (where k = 1, 2,..., N−1, k = 1 in the first embodiment). , 227 have first conductor layers 32 formed simultaneously with the first electrode 31 constituting the memory cell of the (k + 1) th layer (the second layer in the first embodiment), 132 and a stack of second conductor layers 35 and 135 formed at the same time as the second electrode 34 constituting the memory cell of the (k + 1) th layer (the second layer in the first embodiment). Covered by structure. In addition, illustration of the connection hole 27 covered with the laminated structure of the 1st conductor layer 32 and the 2nd conductor layer 35 was abbreviate | omitted. The same applies to the following embodiments.
[0052]
Alternatively, the nonvolatile memory M of the first embodiment₁Is
(A) Bit line BL₁When,
(B) Selection transistor TR₁When,
(C) Each of M memory cells MC (where M ≧ 2 and M = 4 in the first embodiment)._1NMN memory units MU (where N ≧ 2, N = 2 in the first embodiment)₁₁, MU₁₂When,
(D) M × N plate lines PL,
Consists of.
[0053]
And the first layer memory unit MU₁₁Is a selection transistor TR through an insulating layer 16.₁N memory units MU_NAre stacked via an interlayer insulating layer 26 of (N-1) layers (one layer in the first embodiment).
[0054]
Also, the memory unit MU in the first layer₁₁Each memory cell MC comprising_11MIs composed of a first electrode 21, a ferroelectric layer 23, and a second electrode 24, and the second-layer memory unit MU.₁₂Each memory cell MC comprising_12MConsists of a first electrode 31, a ferroelectric layer 33 and a second electrode 34. Furthermore, in each memory unit, the first electrode of the memory cell is common. That is, the first layer memory unit MU₁₁Memory cell MC_11MThe first electrode 21 is common. The common first electrode 21 is connected to the first common node CN.₁₁Sometimes called. In addition, the second layer memory unit MU₁₂Memory cell MC_12MThe first electrode 31 is common. The common first electrode 31 is connected to the second common node CN.₁₂Sometimes called. Furthermore, the memory unit MU of the nth layer (where n = 1, 2,..., N)_1n, The mth memory cell MC (where m = 1, 2,..., M)_1nmThe second electrodes 24 and 34 are connected to the [(n−1) M + m] -th plate line PL._{(n-1) M + m}It is connected to the. This plate line PL_{(n-1) M + m}Is a non-volatile memory M₂Are also connected to the second electrodes 24 and 34 of each memory cell. In the first embodiment, more specifically, each plate line extends from the second electrodes 24 and 34.
[0055]
Then, the selection transistor TR₁One source / drain region 13A of the bit line BL₁Connected to the transistor for selection TR₁The other source / drain region 13B of the first layer is connected to the first layer memory unit MU via the first layer connection hole 17 provided in the insulating layer 16.₁₁First electrode 21 (first common node CN)₁₁)It is connected to the. Furthermore, the transistor for selection TR₁The other source / drain region 13B includes a first-layer connection hole 17 provided in the insulating layer 16, and a k-th layer from the first interlayer insulating layer (where k = 1, 2,. .., N−1) to the (k + 1) th layer connection holes from the second layer connection holes provided in each of the interlayer insulating layers up to (N−1) (more specifically, in the first embodiment) The (k + 1) -th layer memory unit (in the first embodiment, more specifically, through the second-layer connection hole 27 provided in the first-layer interlayer insulating layer 26) Second layer memory unit MU₁₂) Common first electrode 31 (second common node CN)₁₂)It is connected to the.
[0056]
When N = 4, the other source / drain region of the selection transistor is
(1) It is connected to the first common electrode in the memory unit of the first layer through the connection hole of the first layer provided in the insulating layer,
(2) a first layer connection hole provided in the insulating layer, a stacked structure of a first conductor layer and a second conductor layer covering the top surface of the first layer connection hole, and It is connected to the common first electrode in the second layer memory unit through the second layer connection hole provided in the first interlayer insulating layer,
(3) First layer connection hole provided in the insulating layer, a laminated structure of the first conductor layer and the second conductor layer covering the top surface of the first layer connection hole, the first layer A second-layer connection hole provided in the interlayer insulating layer, a stacked structure of the first conductor layer and the second conductor layer covering the top surface of the second-layer connection hole, and a second layer Connected to the common first electrode in the memory unit of the third layer through the connection hole of the third layer provided in the interlayer insulating layer of the layer,
(4) First layer connection hole provided in the insulating layer, a laminated structure of the first conductor layer and the second conductor layer covering the top surface of the first layer connection hole, the first layer A second layer connection hole provided in the interlayer insulating layer, a laminated structure of the first conductor layer and the second conductor layer covering the top surface of the second layer connection hole, Third layer connection hole provided in interlayer insulating layer, laminated structure of first conductor layer and second conductor layer covering top surface of third layer connection hole, and third layer The fourth layer has a structure connected to a common first electrode in the memory unit of the fourth layer through a connection hole of the fourth layer provided in the interlayer insulating layer.
[0057]
Nonvolatile Memory M of Embodiment 1₁In this case, the top surface of the first layer connection hole 17 formed in the insulating layer 16 is connected to the first layer memory unit MU.₁₁Memory cell MC_11MThe first conductor layer 22 formed simultaneously with the first electrode 21 constituting the first and the first layer memory unit MU₁₁Memory cell MC_11MIs covered with a laminated structure of a second conductor layer 25 formed simultaneously with the second electrode 24 constituting the. On the other hand, a connection hole of the (k + 1) th layer (second layer in the first embodiment) formed in the interlayer insulating layer 26 of the kth layer (first layer in the first embodiment). The top surface of 27 is the memory unit MU of the (k + 1) th layer (the second layer in the first embodiment).₁₂Memory cell MC_12MThe first conductor layer 32 formed simultaneously with the first electrode 31 constituting the memory cell and the (k + 1) th layer memory unit MU₁₂Memory cell MC_12MIs covered with a laminated structure of a second conductor layer 35 formed simultaneously with the second electrode 34 constituting the.
[0058]
Bit line BL_nAre connected to the sense amplifier SA. Plate wire PL_{(n-1) M + m}Are connected to a plate line decoder / driver PD. Furthermore, the word line WL (or the word line WL₁, WL₂) Is connected to the word line decoder / driver WD. The word line WL extends in the direction perpendicular to the paper surface of FIG. Nonvolatile memory M₁Memory cell MC constituting_11mThe second electrode 24 of the non-volatile memory M adjacent in the direction perpendicular to the paper surface of FIG.₂Memory cell MC constituting_21mThe second electrode of the plate line PL_{(n-1) M + m}Doubles as Furthermore, the non-volatile memory M₁Memory cell MC constituting_12mThe second electrode 34 of the non-volatile memory M adjacent in the direction perpendicular to the paper surface of FIG.₂Memory cell MC constituting_22mThe second electrode of the plate line PL_{(n-1) M + m}Doubles as The word line WL is connected to the nonvolatile memory M.₁Transistor TR for configuring₁And a non-volatile memory M adjacent in the direction perpendicular to the plane of FIG.₂Transistor TR for configuring₂And is common.
[0059]
The semiconductor device of the first embodiment is
(A) Selection transistor TR₁A memory cell MC comprising first electrodes 21, 31, ferroelectric layers 23, 33 and second electrodes 24, 34 on an insulating layer 16 provided on a semiconductor substrate 10 on which is formed._11m, MC_12mIs a ferroelectric nonvolatile material having a structure in which N layers are stacked through (N-1) interlayer insulating layers (where N ≧ 2 and N = 2 in the first embodiment). Semiconductor memory,
(B) a peripheral circuit for driving a ferroelectric nonvolatile semiconductor memory;
It is composed of
[0060]
The peripheral circuit is a transistor TR formed on the semiconductor substrate 10._P1~ TR_P5Wirings 129 and 139 (see FIG. 2) formed on the insulating layer 16 and the interlayer insulating layer 26, and a transistor TR_P1~ TR_P5And connection holes 117, 127, 217, and 227 connecting the wirings 129 and 139. Further, the connection holes 117, 127, 217, and 227 are connected to the transistor TR._P1~ TR_P5Formed in the insulating layer 16 on the source / drain regions 113 and 213 and / or the gate electrodes 112 and 212 (including the extension of the gate electrode functioning as a word line), or in the insulating layer 16 and the interlayer insulating layer 26 Has been. In FIG. 1, illustration of wiring configuring the peripheral circuit is omitted, but wiring is also formed in this peripheral circuit. The sense amplifier SA includes a transistor TR including a gate electrode 112 and a source / drain region 113._P1, TR_P2Etc. In addition, the word line decoder / driver WD and the plate line decoder / driver PD include a transistor TR including a gate electrode 212 and a source / drain region 213._P3, TR_P4, TR_P5Etc.
[0061]
The top surfaces of the connection holes 117 and 217 formed in the insulating layer 16 are formed on the first-layer memory cell MC._11mThe first conductor layer 122 formed simultaneously with the first electrode 21 constituting the first memory cell MC and the first layer memory cell MC_11mIs covered with a laminated structure of a second conductor layer 125 formed simultaneously with the second electrode 24 constituting the. Furthermore, the wiring 129 formed on the insulating layer 16 is connected to the first-layer memory cell MC._11mThe second conductive layer 125 is formed simultaneously with the second electrode 24 constituting the.
[0062]
On the other hand, the connection holes 127 and 227 formed in the interlayer insulating layer 26 of the k-th layer (where k = 1, 2,..., N−1 and k = 1 in the first embodiment). The top surface is the memory cell MC in the (k + 1) th layer (the second layer in the first embodiment)._12mThe first conductor layer 132 formed simultaneously with the first electrode 31 constituting the memory cell MC and the (k + 1) th layer memory cell MC_12mIs covered with a laminated structure of a second conductor layer 135 formed at the same time as the second electrode 34 constituting the. Furthermore, the wiring 139 formed on the k-th interlayer insulating layer 26 is connected to the (k + 1) -th layer memory cell MC._12mThe second electrode 34 is formed at the same time as the second electrode 34. In FIG. 2, a part of the wiring 139 is indicated by a dotted line. This means that the wiring 139 is formed so as to avoid contact with the connection hole 237A provided in the insulating film 36A.
[0063]
1 and 2, reference numeral 46A is an insulating film, reference numerals 150 and 250 are metal wirings, and reference numerals 137A and 237A are connection holes (contacts) provided in the insulating film 36A in the peripheral circuit. Hall).
[0064]
The nonvolatile memory M whose circuit diagram is shown in FIG.₁, M₂In the non-volatile memory M₁, M₂Transistor TR for configuring₁, TR₂Are connected to the same word line WL. The paired memory cells MC_1nm, MC_2nmComplementary data are stored in (n = 1, 2, and m = 1, 2,... M). For example, the memory cell MC_1nm, MC_2nmWhen data stored in (where m is any one of 1, 2, 3 and 4) is read, the word line WL is selected and the plate line PL_j(M ≠ j) has (1/2) V_ccWith the voltage of_{(n-1) M + m}Drive. Where V_ccIs, for example, a power supply voltage. As a result, the complementary data is converted into a pair of memory cells MC._1nm, MC_2nmTo transistor for selection TR₁, TR₂Bit line BL paired via₁, BL₂Appears as a voltage (bit line potential). The paired bit lines BL₁, BL₂Is detected by the sense amplifier SA. Non-volatile memory M₁, M₂Transistor TR for configuring₁, TR₂, Different word lines WL₁, WL₂Connected to the memory cell MC_1nm, MC_2nmAre controlled independently to form a pair of bit lines BL₁, BL₂By applying a reference voltage to one of the memory cells MC_1nm, MC_2nmData can also be read from each of the above. Refer to FIG. 3B and FIG. 5 for a circuit diagram in the case of adopting such a configuration. The selection transistor TR₁, TR₂Are simultaneously equivalent to the circuit shown in FIG. 3A and FIG. Thus, each memory cell MC_1nm, MC_2nm1 bit is stored as data in each of (n = 1, 2 and m = 1, 2, 3, 4) (see FIG. 3B and FIG. 5) or a pair of memories Cell MC_1nm, MC_2nmIs stored as one bit (see FIG. 3A and FIG. 4). In an actual nonvolatile memory, a set of memory units storing 16 bits or 8 bits is arranged in an array as an access unit unit. The value of M is not limited to 4. The value of M only needs to satisfy M ≧ 2. As an actual value of M, for example, a power of 2 (2, 4, 8, 16...) Can be cited. Further, the value of N only needs to satisfy N ≧ 2. As an actual value of N, for example, a power of 2 (2, 4, 8,...) Can be given.
[0065]
Hereinafter, with reference to FIGS. 6 to 8 which are schematic partial cross-sectional views when a semiconductor substrate or the like is cut along a virtual vertical plane parallel to the extending direction of the bit line, the nonvolatile memory and the semiconductor according to the first embodiment An outline of a method for manufacturing the apparatus will be described. Note that the non-volatile memories in other embodiments can be manufactured by substantially the same process.
[0066]
[Step-100]
First, a MOS transistor that functions as a selection transistor in a nonvolatile memory or a transistor constituting a peripheral circuit is formed on the semiconductor substrate 10. Therefore, for example, the element isolation region 11 having a LOCOS structure is formed based on a known method. The element isolation region may have a trench structure, or a combination of a LOCOS structure and a trench structure. Thereafter, the surface of the semiconductor substrate 10 is oxidized by, for example, a pyrogenic method to form a gate insulating film. Next, after a polysilicon layer doped with impurities is formed on the entire surface by a CVD method, the polysilicon layer is patterned to form gate electrodes 12, 112, and 212. The gate electrodes 12, 112 and 212 also serve as word lines. Note that the gate electrodes 12, 112, and 212 can be made of polycide or metal silicide instead of the polysilicon layer. Next, ion implantation is performed on the semiconductor substrate 10 to form an LDD structure. Then, SiO is deposited on the entire surface by CVD.₂After forming the layer, this SiO 2₂By etching back the layer, a gate sidewall (not shown) is formed on the side surface of the gate electrode 12. Next, after ion implantation is performed on the semiconductor substrate 10, source / drain regions 13A, 13B, 113, and 213 are formed by performing activation annealing of the implanted impurities.
[0067]
[Step-110]
Then SiO₂After forming the lower insulating layer made of the above by the CVD method, an opening is formed by the RIE method in the lower insulating layer above the one source / drain region 13A. Then, a polysilicon layer doped with impurities is formed by CVD on the lower insulating layer including the inside of the opening. Thereby, a contact hole is formed. Next, the bit line BL is formed by patterning the polysilicon layer on the lower insulating layer.₁Form. Thereafter, an upper insulating layer made of BPSG is formed on the entire surface by a CVD method. Note that it is preferable that after the formation of the upper insulating layer made of BPSG, the upper insulating layer is reflowed in a nitrogen gas atmosphere, for example, at 900 ° C. for 20 minutes. Furthermore, it is desirable to planarize the upper insulating layer by chemically and mechanically polishing the top surface of the upper insulating layer, for example, by a chemical mechanical polishing method (CMP method) as necessary. The lower insulating layer and the upper insulating layer are collectively referred to as an insulating layer 16.
[0068]
[Step-120]
Next, an opening is formed in the insulating layer 16 above the other source / drain region 13B and the source / drain regions 113 and 213 by the RIE method, and then the opening is filled with polysilicon doped with impurities. Connection holes (contact holes) 17, 117, 217 are completed (see FIG. 6A). The bit line BL extends on the lower insulating layer so as not to contact the connection hole 17 in the left-right direction in the drawing. In the figure, the connection hole 217 is not shown.
[0069]
The connection holes 17, 117, and 217 are formed in the opening formed in the insulating layer 16, for example, tungsten, Ti, Pt, Pd, Cu, TiW, TiNW, and WSi.₂, MoSi₂It can also be formed by embedding a metal wiring material composed of a refractory metal such as metal or a metal silicide. It is preferable that the top surfaces of the connection holes 17, 117, and 217 exist in substantially the same plane as the surface of the insulating layer 16. The conditions for filling the openings with tungsten and forming the connection holes 17, 117 and 217 are illustrated in Table 1 below. Note that before the opening is filled with tungsten, it is preferable that the Ti layer and the TiN layer are sequentially formed on the insulating layer 16 including the inside of the opening by, for example, magnetron sputtering. Here, the reason for forming the Ti layer and the TiN layer is to obtain an ohmic low contact resistance, to prevent damage to the semiconductor substrate 10 in the blanket tungsten CVD method, and to improve the adhesion of tungsten.
[0070]

[0071]
[Step-130]
Next, it is desirable to form an adhesion layer (not shown) made of titanium nitride (TiN) on the insulating layer 16. Then, IrO on the adhesion layer₂The first conductive material layer constituting the first electrode (lower electrode) 21 made of / Ir is formed by, for example, a sputtering method, and the first conductive material layer and the adhesion layer are formed by a photolithography technique and a dry etching technique. By patterning based on this, the striped first electrode 21 can be obtained. At the same time, the top surfaces of the connection holes 17, 117, and 217 formed in the insulating layer 16 are connected to the first conductor layer 22 formed at the same time as the first electrode 21 (in the first embodiment, further close contact) Layer) (see FIG. 6B). After that, the entire surface is made of SiO by the CVD method.₂Film or SiO₂/ TiO₂A film (not shown) is formed, and the film is flattened by a CMP method to obtain a state in which the space between the first electrodes 21 is filled with this film (so-called damascene structure). In the CMP method, a slurry containing alumina may be used as an abrasive.
[0072]
For example, a SiN film is formed on the insulating layer 16, and then the SiN film in a portion where the first electrode and the first conductor layer are to be formed is selectively removed, and then the SiN film and the exposed insulating layer are formed. A first electrode having a so-called damascene structure is formed by forming an adhesion layer and a first conductive material layer on 16 and then removing the first conductive material layer and adhesion layer on the SiN film by CMP. The first conductor layer can also be formed.
[0073]
[Step-140]
Thereafter, a Bi-based layered structure perovskite ferroelectric material (specifically, for example, Bi having a crystallization temperature of 750 ° C.) is formed by, for example, MOCVD.₂SrTa₂O₉Is formed over the entire surface. Thereafter, after drying in air at 250 ° C., heat treatment is performed in an oxygen gas atmosphere at 750 ° C. for 1 hour to promote crystallization. Thereafter, the ferroelectric thin film is patterned to form the ferroelectric layer 23.
[0074]
[Step-150]
Next, IrO_2-XAfter a layer and a Pt layer are sequentially formed on the entire surface by sputtering, a Pt layer, an IrO layer are formed on the basis of a photolithography technique and a dry etching technique._2-XThe layers are sequentially patterned to form the second electrode 24 on the ferroelectric layer 23, the plate line PL extending from the second electrode 24, and the first conductor layers 22 and 122. Second conductor layers 25 and 125 are formed, and in addition, a wiring 129 is formed (see FIG. 7A). Note that the wiring 129 is not shown in FIG. When damage is applied to the ferroelectric layer 23 by etching, a damage recovery annealing process may be performed thereafter at a temperature required for damage recovery.
[0075]
[Step-160]
afterwards,
-Formation and planarization of the interlayer insulating layer 26
-Formation of opening and formation of connection holes 27, 127, 227 (see FIG. 7B)
For example, formation of the first electrode 31 having the damascene structure and the first conductor layers 32 and 132 (see FIG. 8A)
・ Bi with crystallization temperature of 700 ° C₂Sr (Ta_1.5Nb_0.5) O₉Formation of a ferroelectric layer 33 comprising
Formation of the second electrode 34, the second conductor layers 35 and 135, and the wiring 139 (see FIG. 8B)
Formation of insulating film 36A
-Formation of contact holes 137A, 237A
-Formation of metal wiring layers 150, 250 made of, for example, an aluminum alloy
-Formation of insulating film 46A
Are sequentially performed. In each drawing, the components represented by the above reference numbers may not be shown. Bi₂Sr (Ta_1.5Nb_0.5) O₉The ferroelectric layer 33 made of may be heat-treated for promoting crystallization in an oxygen gas atmosphere at 700 ° C. for 1 hour.
[0076]
If the crystallization temperature of the ferroelectric layer constituting the upper memory unit is set lower than the crystallization temperature of the ferroelectric layer constituting the lower memory unit, Even if the crystallization heat treatment is performed for the number of stages, there is no problem of deterioration of characteristics of the memory cells constituting the memory unit located below. In addition, crystallization heat treatment can be performed under optimum conditions on the memory cells constituting the memory unit in each stage, and a nonvolatile memory with excellent characteristics can be obtained. Table 2 below illustrates the crystallization temperature.
[0077]
[Table 2]
Material name Crystallization temperature
Bi₂SrTa₂O₉                   700-800 ° C
Bi₂Sr (Ta_1.5, Nb_0.5) O₉    650-750 ° C
Bi_FourTi_ThreeO₁₂                      600-700 ° C
Pb (Zr_0.48, Ti_0.52) O_Three       550-650 ° C
PbTiO_Three                         500-600 ° C
[0078]
For example, Bi₂SrTa₂O₉Table 3 below illustrates conditions for forming a ferroelectric thin film made of In Table 3, “thd” is an abbreviation for tetramethylheptanedionate. The source materials shown in Table 3 are dissolved in a solvent containing tetrahydrofuran (THF) as a main component.
[0079]

[0080]
Alternatively, Bi₂SrTa₂O₉It is also possible to form a ferroelectric thin film made of the above by the pulse laser ablation method, the sol-gel method, or the RF sputtering method. The formation conditions in these cases are exemplified below. When a thick ferroelectric thin film is formed by the sol-gel method, a desired number of times of spin coating and drying, or spin coating and baking (or annealing treatment) may be repeated.
[0081]
[Table 4]
Formation by pulsed laser ablation
Target: Bi₂SrTa₂O₉
Laser used: KrF excimer laser (wavelength 248 nm, pulse width 25 ns, 5 Hz)
Formation temperature: 400-800 ° C
Oxygen concentration: 3 Pa
[0082]

[0083]
[Table 6]
Formation by RF sputtering
Target: Bi₂SrTa₂O₉Ceramic target
RF power: 1.2W-2.0W / target 1cm²
Atmospheric pressure: 0.2 to 1.3 Pa
Formation temperature: Room temperature to 600 ° C
Process gas: Ar / O₂Flow rate ratio = 2/1 to 9/1
[0084]
Table 7 below illustrates the formation conditions of PZT or PLZT by magnetron sputtering when the ferroelectric layer is made of PZT or PLZT. Alternatively, PZT or PLZT can be formed by reactive sputtering, electron beam evaporation, sol-gel, or MOCVD.
[0085]
[Table 7]
Target: PZT or PLZT
Process gas: Ar / O₂= 90% by volume / 10% by volume
Pressure: 4Pa
Power: 50W
Formation temperature: 500 ° C
[0086]
Furthermore, PZT and PLZT can be formed by a pulse laser ablation method. The formation conditions in this case are illustrated in Table 8 below.
[0087]
[Table 8]
Target: PZT or PLZT
Laser used: KrF excimer laser (wavelength 248 nm, pulse width 25 ns, 3 Hz)
Output energy: 400 mJ (1.1 J / cm²)
Formation temperature: 550-600 ° C
Oxygen concentration: 40 to 120 Pa
[0088]
Note that the wiring formed on the insulating layer 16 is connected to the first-layer memory cell MC._11mA first conductor layer formed at the same time as the first electrode 21 and the first-layer memory cell MC_11mThe second electrode layer is formed at the same time as the second electrode layer, and the k-th layer (where k = 1, 2,..., N−1, 1, the wiring formed on the k = 1) interlayer insulating layer 26 is connected to the (k + 1) th layer memory cell MC._12mThe first conductor layer formed simultaneously with the first electrode 31 constituting the memory cell and the (k + 1) th layer memory cell MC_12mIt is also possible to form a laminated structure of second conductor layers formed simultaneously with the second electrode 34 constituting the.
[0089]
(Embodiment 2)
The second embodiment relates to the nonvolatile memory according to the first and third aspects of the present invention and the semiconductor device of the present invention. FIG. 9 shows a schematic partial cross-sectional view when the semiconductor device of the second embodiment is cut along a virtual vertical plane parallel to the extending direction of the bit line. A schematic partial cross-sectional view of the semiconductor device of the second embodiment cut along a virtual vertical plane parallel to the direction in which the word lines extend has substantially the same configuration as shown in FIG. Further, a conceptual circuit diagram of the nonvolatile memory according to the second aspect of the present invention is shown in FIGS. 10A and 10B, and more concrete than the conceptual circuit diagram of FIG. FIG. 11 shows a typical circuit diagram, and FIG. 12 shows a more specific circuit diagram of the conceptual circuit diagram of FIG. 11 and 12 show two nonvolatile memories M.₁, M₂These non-volatile memories M are shown in FIG.₁, M₂The structure of the non-volatile memory M will be described below.₁Will be explained. Further, since the peripheral circuit can have substantially the same configuration as the peripheral circuit in the semiconductor device of the first embodiment, detailed description thereof is omitted.
[0090]
Nonvolatile Memory M of Embodiment 2₁Is
(A) Bit line BL₁When,
(B) N selection transistors TR (where N ≧ 2 and N = 2 in the second embodiment)₁₁, TR₁₂When,
(C) Each of M memory cells MC (where M ≧ 2 and M = 4 in the second embodiment)_11M, MC_12MN memory units MU composed of₁₁, MU₁₂When,
(D) M plate wires PL_M,
Consists of.
[0091]
And the first layer memory unit MU₁₁Is a selection transistor TR through an insulating layer 16.₁₁, TR_{twenty one}N memory units MU₁₁, MU₁₂Are stacked via an interlayer insulating layer 26 of (N-1) layers (one layer in the second embodiment).
[0092]
Also, the memory unit MU in the first layer₁₁Each memory cell MC comprising_11MIs composed of a first electrode 21, a ferroelectric layer 23, and a second electrode 24, and the second-layer memory unit MU.₁₂Each memory cell MC comprising_12MConsists of a first electrode 31, a ferroelectric layer 33 and a second electrode 34. Furthermore, in each memory unit, the first electrode of the memory cell is common. That is, the first layer memory unit MU₁₁Memory cell MC_11MThe first electrode 21 is common. The common first electrode 21 is connected to the first common node CN.₁₁Sometimes called. In addition, the second layer memory unit MU₁₂Memory cell MC_12MThe first electrode 31 is common. The common first electrode 31 is connected to the second common node CN.₁₂Sometimes called. Furthermore, the memory unit MU of the nth layer (where n = 1, 2,..., N)_1n, The second electrodes 24 and 34 of the mth memory cell (where m = 1, 2,..., M) are connected to the memory unit MU._1nThe mth plate line PL common to all_mIt is connected to the. In the second embodiment, more specifically, each plate line extends from the second electrodes 24 and 34.
[0093]
Each selection transistor TR₁₁, TR₁₂One source / drain region 13A of the bit line BL₁Connected to the first selection transistor TR₁₁The other source / drain region 13B of the first layer is connected to the first layer memory unit MU via the first layer connection hole 17 provided in the insulating layer 16.₁₁First electrode 21 (first common node CN)₁₁)It is connected to the. Further, the (k + 1) -th selection transistor TR (where k = 1, 2,..., N−1 and k = 1 in the second embodiment).₁₂The other source / drain region 13B includes a first-layer connection hole 17 provided in the insulating layer 16, and a k-th layer from the first interlayer insulating layer (provided that k = 1, 2,. .., N−1) to the (k + 1) th layer connection holes from the second layer connection holes provided in each of the interlayer insulating layers up to (N−1) (more specifically, in the second embodiment, The memory unit MU of the (k + 1) th layer is connected via the connection hole 27 of the second layer provided in the interlayer insulating layer 26 of the first layer.₁₂First electrode 31 (second common node CN)₁₂)It is connected to the.
[0094]
Nonvolatile Memory M of Embodiment 2₁Even in this case, the top surface of the first layer connection hole 17 formed in the insulating layer 16 is connected to the first layer memory unit MU.₁₁Memory cell MC_11mThe first conductor layer 22 formed simultaneously with the first electrode 21 constituting the first and the first layer memory unit MU₁₁Memory cell MC_11MIs covered with a laminated structure of a second conductor layer 25 formed simultaneously with the second electrode 24 constituting the. On the other hand, the connection hole of the (k + 1) th layer (second layer in the second embodiment) formed in the interlayer insulating layer 26 of the kth layer (first layer in the second embodiment). The top surface of 27 is the memory unit MU of the (k + 1) th layer (second layer in the second embodiment).₁₂Memory cell MC_12MThe first conductor layer 32 formed simultaneously with the first electrode 31 constituting the memory cell and the (k + 1) th layer memory unit MU₁₂Memory cell MC_12MIs covered with a laminated structure of a second conductor layer 35 formed simultaneously with the second electrode 34 constituting the.
[0095]
Bit line BL_nAre connected to the sense amplifier SA. Plate wire PL_MAre connected to a plate line decoder / driver PD. Furthermore, the word line WL₁, WL₂(Or word line WL₁₁, WL₁₂, WL_{twenty one}, WL_{twenty two}) Is connected to the word line decoder / driver WD. The word line extends in the direction perpendicular to the paper surface of FIG. Nonvolatile memory M₁Memory cell MC constituting_11mThe second electrode 24 of the non-volatile memory M adjacent in the direction perpendicular to the paper surface of FIG.₂Memory cell MC constituting_21mThe second electrode of the plate line PL_mDoubles as Furthermore, the non-volatile memory M₁Memory cell MC constituting_12mThe second electrode 34 of the non-volatile memory M adjacent in the direction perpendicular to the paper surface of FIG.₂Memory cell MC constituting_22mThe second electrode of the plate line PL_mDoubles as These plate lines PL_mAre connected in a region not shown. Also, the word line WL₁Is a non-volatile memory M₁Transistor TR for configuring₁₁And a non-volatile memory M adjacent in the direction perpendicular to the paper surface of FIG.₂Transistor TR for configuring_{twenty one}And is common. Furthermore, the word line WL₂Is a non-volatile memory M₁Transistor TR for configuring₁₂And a non-volatile memory M adjacent in the direction perpendicular to the paper surface of FIG.₂Transistor TR for configuring_{twenty two}And is common.
[0096]
When N = 4, the other source / drain region of the first selection transistor is connected to the first layer memory via the first layer connection hole provided in the insulating layer. Connected to a common first electrode in the unit. The other source / drain region of the second selection transistor is a first conductor that covers the first layer connection hole provided in the insulating layer and the top surface of the first layer connection hole. First electrode common to the memory unit of the second layer through the stacked structure of the layer and the second conductor layer, and the connection hole of the second layer provided in the interlayer insulating layer of the first layer It is connected to the. Further, the other source / drain region of the third selection transistor has a first conductive hole covering the top surface of the first layer connection hole and the first layer connection hole provided in the insulating layer. Laminated structure of body layer and second conductor layer, second layer connection hole provided in first interlayer insulating layer, first conductor covering top surface of second layer connection hole The first electrode common to the memory unit of the third layer through the stacked structure of the layer and the second conductor layer and the connection hole of the third layer provided in the interlayer insulating layer of the second layer It is connected to the. The other source / drain region of the fourth selection transistor is the first conductor covering the first layer connection hole provided in the insulating layer and the top surface of the first layer connection hole. Layer and the second conductor layer, the second layer connection hole provided in the first interlayer insulating layer, the first conductor layer covering the top surface of the second layer connection hole And a second conductive layer, a third connection hole provided in the second interlayer insulating layer, a first conductive layer covering the top surface of the third connection hole, Connected to the common first electrode in the memory unit of the fourth layer through the laminated structure of the second conductor layer and the connection hole of the fourth layer provided in the third interlayer insulating layer Has been. Note that the non-volatile memory in Embodiment 3 described later has the same structure even when N = 4.
[0097]
The nonvolatile memory M whose circuit diagram is shown in FIG.₁, M₂In the non-volatile memory M₁, M₂Transistor TR for configuring_1n, TR_2nIs the same word line WL_nIt is connected to the. The paired memory cells MC_1nm, MC_2nmComplementary data are stored in (n = 1, 2, and m = 1, 2,... M). For example, the memory cell MC_11m, MC_21mWhen reading data stored in (where m is 1, 2, 3, or 4), the word line WL₁Select the plate line PL_j(M ≠ j) has (1/2) V_ccWith the voltage of_mDrive. Where V_ccIs, for example, a power supply voltage. As a result, the complementary data is converted into a pair of memory cells MC._11m, MC_21mTo transistor for selection TR₁₁, TR_{twenty one}Bit line BL paired via₁, BL₂Appears as a voltage (bit line potential). The paired bit lines BL₁, BL₂Is detected by the sense amplifier SA. Non-volatile memory M₁, M₂Transistor TR for configuring₁₁, TR₁₂, TR_{twenty one}, TR_{twenty two}, Different word lines WL₁₁, WL₁₂, WL_{twenty one}, WL_{twenty two}Connected to the memory cell MC_1nm, MC_2nmAre controlled independently to form a pair of bit lines BL₁, BL₂By applying a reference voltage to one of the memory cells MC_1nm, MC_2nmData can also be read from each of the above. Refer to FIG. 10B and FIG. 12 for a circuit diagram in the case of adopting such a configuration. The selection transistor TR₁₁, TR_{twenty one}Are simultaneously driven to select transistors TR₁₂, TR_{twenty two}Are driven simultaneously, it is equivalent to the circuit shown in FIG. 10A and FIG. Thus, each memory cell MC_1nm, MC_2nm(1 bit is stored as data in each of m = 1, 2, 3, 4) (see FIG. 10B and FIG. 12) or a pair of memory cells MC_1nm, MC_2nmIs stored as one bit (see FIG. 10A and FIG. 11). In an actual nonvolatile memory, a set of memory units storing 16 bits or 8 bits is arranged in an array as an access unit unit. The value of M is not limited to 4. The value of M only needs to satisfy M ≧ 2. As an actual value of M, for example, a power of 2 (2, 4, 8, 16...) Can be cited. Further, the value of N only needs to satisfy N ≧ 2. As an actual value of N, for example, a power of 2 (2, 4, 8,...) Can be given.
[0098]
Since the nonvolatile memory and the semiconductor device of Embodiment 2 can be manufactured by substantially the same method as the manufacturing method of the nonvolatile memory and the semiconductor device of Embodiment 1, detailed description is omitted.
[0099]
(Embodiment 3)
The third embodiment relates to the nonvolatile memory according to the first and fourth aspects of the present invention and the semiconductor device of the present invention. FIG. 13 shows a schematic partial cross-sectional view when the semiconductor device of the third embodiment is cut along a virtual vertical plane parallel to the extending direction of the bit line. A schematic partial sectional view of the semiconductor device of the third embodiment cut along a virtual vertical plane parallel to the direction in which the word lines extend has substantially the same configuration as shown in FIG. Further, conceptual circuit diagrams of the nonvolatile memory according to the third aspect of the present invention are shown in FIGS. 14A and 14B, and a specific circuit diagram is shown in FIG. 14A and 14B show two nonvolatile memories M.₁, M₂These non-volatile memories M are shown in FIG.₁, M₂The structure of the non-volatile memory M will be described below.₁Will be explained. Further, since the peripheral circuit can have substantially the same configuration as the peripheral circuit in the semiconductor device of the first embodiment, detailed description thereof is omitted.
[0100]
Nonvolatile Memory M of Embodiment 3₁Is
(A) N (where N ≧ 2 and in the third embodiment, N = 2) bit line BL₁₁, BL₁₂When,
(B) N selection transistors TR₁₁, TR₁₂When,
(C) M memory cells MC each (where M ≧ 2 and M = 4 in the third embodiment)_11M, MC_12MN memory units MU composed of₁₁, MU₁₂When,
(D) M plate wires PL_M,
Consists of.
[0101]
14 and 15, the bit line BL₁₁And selection transistor TR₁₁And memory cell MC_11MMemory unit MU composed of₁₁Sub unit SU₁₁And the bit line BL₁₂And selection transistor TR₁₂And memory cell MC_12MMemory unit MU composed of₁₂Sub unit SU₁₂Represented by
[0102]
And the first layer memory unit MU₁₁Is a selection transistor TR through an insulating layer 16.₁₁, TR₁₂N memory units MU₁₁, MU₁₂Are stacked via an interlayer insulating layer 26 of (N-1) layers (one layer in the third embodiment).
[0103]
Also, the memory unit MU in the first layer₁₁Each memory cell MC comprising_11MIs composed of a first electrode 21, a ferroelectric layer 23, and a second electrode 24, and the second-layer memory unit MU.₁₂Each memory cell MC comprising_12MConsists of a first electrode 31, a ferroelectric layer 33 and a second electrode 34. Furthermore, in each memory unit, the first electrode of the memory cell is common. That is, the first layer memory unit MU₁₁Memory cell MC_11MThe first electrode 21 is common. The common first electrode 21 is connected to the first common node CN.₁₁Sometimes called. In addition, the second layer memory unit MU₁₂Memory cell MC_12MThe first electrode 31 is common. The common first electrode 31 is connected to the second common node CN.₁₂Sometimes called. Furthermore, the memory unit MU of the nth layer (where n = 1, 2,..., N)_1n, The second electrodes 24 and 34 of the mth memory cell (where m = 1, 2,..., M) are connected to the memory unit MU._1nThe mth plate line PL common to all_mIt is connected to the. In the third embodiment, more specifically, each plate line extends from the second electrodes 24 and 34.
[0104]
The nth selection transistor TR_1nOne source / drain region 13A of the nth bit line BL_1nConnected to the first selection transistor TR₁₁The other source / drain region 13B of the first layer is connected to the first layer memory unit MU via the first layer connection hole 17 provided in the insulating layer 16.₁₁First electrode 21 (first common node CN)₁₁)It is connected to the. In addition, the (k + 1) th selection transistor TR (where k = 1, 2,..., N−1, and k = 1 in the third embodiment).₁₂The other source / drain region 13B includes a first-layer connection hole 17 provided in the insulating layer 16, and a k-th layer from the first interlayer insulating layer (where k = 1, 2,. .., (N−1) to the (k + 1) th layer connection holes from the second layer connection holes provided in each of the interlayer insulating layers up to (N−1) (more specifically, in the third embodiment) The memory unit MU of the (k + 1) th layer is connected through the connection hole 27 of the second layer provided in the interlayer insulating layer 26 of the first layer.₁₂First electrode 31 (second common node CN)₁₂)It is connected to the.
[0105]
Nonvolatile Memory M of Embodiment 3₁Even in this case, the top surface of the first layer connection hole 17 formed in the insulating layer 16 is connected to the first layer memory unit MU.₁₁Memory cell MC_11mThe first conductor layer 22 formed simultaneously with the first electrode 21 constituting the first and the first layer memory unit MU₁₁Memory cell MC_11MIs covered with a laminated structure of a second conductor layer 25 formed simultaneously with the second electrode 24 constituting the. On the other hand, the connection hole of the (k + 1) th layer (second layer in the third embodiment) formed in the interlayer insulating layer 26 of the kth layer (first layer in the third embodiment). The top surface of 27 is the memory unit MU of the (k + 1) th layer (second layer in the second embodiment).₁₂Memory cell MC_12MThe first conductor layer 32 formed simultaneously with the first electrode 31 constituting the memory cell and the (k + 1) th layer memory unit MU₁₂Memory cell MC_12MIs covered with a laminated structure of a second conductor layer 35 formed simultaneously with the second electrode 34 constituting the.
[0106]
Bit line BL_1nAre connected to the sense amplifier SA. Plate wire PL_MAre connected to a plate line decoder / driver PD. Furthermore, the word line WL₁, WL₂(Or word line WL₁₁, WL₁₂, WL_{twenty one}, WL_{twenty two}) Is connected to the word line decoder / driver WD. The word line extends in the direction perpendicular to the paper surface of FIG. Nonvolatile memory M₁Memory cell MC constituting_11mThe second electrode 24 of the non-volatile memory M adjacent in the direction perpendicular to the paper surface of FIG.₂Memory cell MC constituting_21mThe second electrode of the plate line PL_mDoubles as Furthermore, the non-volatile memory M₁Memory cell MC constituting_12mThe second electrode 34 of the non-volatile memory M adjacent in the direction perpendicular to the paper surface of FIG.₂Memory cell MC constituting_22mThe second electrode of the plate line PL_mDoubles as These plate lines PL_mAre connected in a region not shown. Also, the word line WL₁Is a non-volatile memory M₁Transistor TR for configuring₁₁And a non-volatile memory M adjacent in the direction perpendicular to the sheet of FIG.₂Transistor TR for configuring_{twenty one}And is common. Furthermore, the word line WL₂Is a non-volatile memory M₁Transistor TR for configuring₁₂And a non-volatile memory M adjacent in the direction perpendicular to the sheet of FIG.₂Transistor TR for configuring_{twenty two}And is common.
[0107]
The nonvolatile memory M whose circuit diagram is shown in FIG.₁, M₂In the non-volatile memory M₁, M₂Transistor TR for configuring₁₁, TR_{twenty one}Is the same word line WL₁Connected to the transistor for selection TR₁₂, TR_{twenty two}Is the same word line WL₂It is connected to the. The paired memory cells MC_1nm, MC_2nmComplementary data are stored in (n = 1, 2, and m = 1, 2,... M). For example, the memory cell MC_11m, MC_21mWhen reading data stored in (where m is 1, 2, 3, or 4), the word line WL₁Select the plate line PL_j(M ≠ j) has (1/2) V_ccWith the voltage of_mDrive. Where V_ccIs, for example, a power supply voltage. As a result, the complementary data is converted into a pair of memory cells MC._11m, MC_21mTo transistor for selection TR₁₁, TR_{twenty one}Bit line BL paired via₁₁, BL_{twenty one}Appears as a voltage (bit line potential). The paired bit lines BL₁₁, BL_{twenty one}Is detected by the sense amplifier SA. Non-volatile memory M₁, M₂Transistor TR for configuring₁₁, TR₁₂, TR_{twenty one}, TR_{twenty two}, Different word lines WL₁₁, WL₁₂, WL_{twenty one}, WL_{twenty two}Connected to the memory cell MC_1nm, MC_2nmAre controlled independently to form a pair of bit lines BL₁₁, BL_{twenty one}Or paired bit line BL₁₂, BL_{twenty two}By applying a reference voltage to one of the memory cells MC_1nm, MC_2nmData can also be read from each of the above. Refer to FIG. 14B and FIG. 15 for a circuit diagram in the case of adopting such a configuration. The selection transistor TR₁₁, TR_{twenty one}Are simultaneously driven to select transistors TR₁₂, TR_{twenty two}Are driven simultaneously, it is equivalent to the circuit shown in FIG. Thus, each memory cell MC_1nm, MC_2nm(1 bit is stored as data in each of m = 1, 2, 3, 4) (see FIG. 14B) or a pair of memory cells MC_1nm, MC_2nmIs stored as one bit (see FIG. 14A). In an actual nonvolatile memory, a set of memory units storing 16 bits or 8 bits is arranged in an array as an access unit unit. The value of M is not limited to 4. The value of M only needs to satisfy M ≧ 2. As an actual value of M, for example, a power of 2 (2, 4, 8, 16...) Can be cited. Further, the value of N only needs to satisfy N ≧ 2. As an actual value of N, for example, a power of 2 (2, 4, 8,...) Can be given.
[0108]
Alternatively, the nonvolatile memory M whose circuit diagram is shown in FIG.₁For example, a pair of memory cells MC_11m, MC_12mData complementary to (m = 1, 2,..., M) may be stored. For example, the memory cell MC_11m, MC_12mWhen reading data stored in (where m is 1, 2, 3, or 4), the word line WL₁, WL₂Select the plate line PL_j(M ≠ j) includes, for example, (1/2) V_ccWith the voltage of_mDrive. As a result, the complementary data is converted into a pair of memory cells MC._11m, MC_12mTo transistor for selection TR₁₁, TR₁₂Bit line BL paired via₁₁, BL₁₂Appears as a voltage (bit line potential). The paired bit lines BL₁₁, BL₁₂Is detected by the sense amplifier SA. The memory cell MC_11m, MC_12mAre controlled independently to form a pair of bit lines BL₁₁, BL₁₂By applying a reference voltage to one of the memory cells MC_11m, MC_12mData can also be read from each of the above. Refer to FIG. 14B and FIG. 15 for a circuit diagram in the case of adopting such a configuration.
[0109]
Since the nonvolatile memory and the semiconductor device of Embodiment 3 can be manufactured by substantially the same method as the manufacturing method of the nonvolatile memory and the semiconductor device of Embodiment 1, detailed description is omitted.
[0110]
As mentioned above, although this invention was demonstrated based on embodiment of this invention, this invention is not limited to these. The structure of the nonvolatile memory and the semiconductor device, the materials used, various formation conditions, the circuit configuration, the driving method, and the like described in the embodiment of the invention are examples, and can be changed as appropriate.
[0111]
In general, A = B + C, where A is the total number of signal lines for driving the unit units, B is the number of word lines, and C is the number of plate lines. Here, when the total number A is constant, in order to maximize the total number of addresses (= B × C) of the unit unit, it is sufficient to satisfy B = C. Therefore, in order to arrange peripheral circuits most efficiently, the number B of word lines and the number C of plate lines in the unit unit may be made equal. In addition, the number of word lines in the row address access unit unit corresponds to, for example, the number of stacked memory cells, and the number of plate lines corresponds to the number of memory cells constituting the memory unit. As the number of lines increases, the degree of substantial non-volatile memory integration increases. The product of the number of word lines and the number of plate lines is the number of accessible addresses. Here, on the premise of continuous and continuous access, the value obtained by subtracting “1” from the product is the number of disturbances. Therefore, the value of the product of the number of word lines and the number of plate lines is determined from the disturbance tolerance of the memory cells, process factors, and the like. Here, the disturbance is a phenomenon in which an electric field is applied to the ferroelectric layer constituting a non-selected memory cell in a direction in which polarization is reversed, that is, in a direction in which stored data is deteriorated or destroyed. Point to.
[0112]
The nonvolatile memory described in Embodiment 2 can be modified as in the structure shown in FIG. A circuit diagram is shown in FIG.
[0113]
This nonvolatile memory includes a bit line BL connected to the sense amplifier SA.₁N transistors (where N ≧ 2, N = 4 in this example) made up of MOS FETs are selected.₁₁, TR₁₂, TR₁₃, TR₁₄And N memory units MU₁₁, MU₁₂, MU₁₃, MU₁₄And a plate wire. First layer memory unit MU₁₁Is M memory cells (where M ≧ 2 and M = 8 in this example)._11m(M = 1, 2,... 8). In addition, the second layer memory unit MU₁₂M memory cells MC (M = 8)_12m(M = 1, 2,... 8). Furthermore, the third layer memory unit MU₁₃M memory cells MC (M = 8)_13m(M = 1, 2,... 8), and the fourth layer memory unit MU₁₄M memory cells MC (M = 8)_14m(M = 1, 2,... 8). The number of plate lines is M (8 in this example), and PL_m(M = 1, 2,... 8). Selection transistor TR_1nWord line WL connected to the gate electrode of_1nAre connected to a word line decoder / driver WD. On the other hand, each plate line PL_mAre connected to a plate line decoder / driver PD.
[0114]
Also, the memory unit MU in the first layer₁₁Each memory cell MC comprising_11mIs composed of the first electrode 21A, the ferroelectric layer 23A, and the second electrode 24, and the second layer memory unit MU.₁₂Each memory cell MC comprising_12mIncludes a first electrode 21B, a ferroelectric layer 23B, and a second electrode 24, and a third memory unit MU.₁₃Each memory cell MC comprising_13mIncludes a first electrode 31A, a ferroelectric layer 33A, and a second electrode 34, and includes a fourth memory unit MU.₁₄Each memory cell MC comprising_14mConsists of a first electrode 31B, a ferroelectric layer 33B, and a second electrode. And each memory unit MU₁₁, MU₁₂, MU₁₃, MU₁₄, The first electrodes 21A, 21B, 31A, 31B of the memory cells are common. For the sake of convenience, the common first electrodes 21A, 21B, 31A, 31B are connected to the common node CN.₁₁, CN₁₂, CN₁₃, CN₁₄Call it.
[0115]
Here, the memory unit MU of the first layer₁₁First electrode 21A (first common node CN)₁₁) Is the first selection transistor TR₁₁Via the bit line BL₁It is connected to the. In addition, the second layer memory unit MU₁₂First electrode 21B (second common node CN)₁₂) Is the second selection transistor TR₁₂Via the bit line BL₁It is connected to the. Furthermore, the third layer memory unit MU₁₃First electrode 31A (third common node CN)₁₃) Is the third selection transistor TR₁₃Via the bit line BL₁It is connected to the. Also, the fourth layer memory unit MU₁₄Common electrode 31B (fourth common node CN)₁₄) Is the fourth selection transistor TR₁₄Via the bit line BL₁It is connected to the.
[0116]
Also, the memory unit MU in the first layer₁₁Memory cell MC constituting_11mAnd the second layer memory unit MU₁₂Memory cell MC constituting_12mShare the second electrode 24, and the shared mth second electrode 24 is the plate line PL._mIt is connected to the. Furthermore, the third layer memory unit MU₁₃Memory cell MC constituting_13mAnd the fourth layer memory unit MU₁₄Memory cell MC constituting_14mShare the second electrode 34, and the shared m-th second electrode 34 is the plate line PL._mIt is connected to the. Specifically, the plate line PL extends from the shared extension of the mth second electrode 24._mAnd the plate line PL extends from the extended portion of the shared mth second electrode 34._mEach plate line PL_mAre connected in a region not shown.
[0117]
In this nonvolatile memory, the memory unit MU₁₁, MU₁₂And memory unit MU₁₃, MU₁₄Are stacked via an interlayer insulating layer 26. Memory unit MU₁₄Is covered with an insulating film 36A. In addition, the memory unit MU₁₁Is formed above the semiconductor substrate 10 via an insulating layer 16. An element isolation region 11 is formed in the semiconductor substrate 10. The selection transistor TR₁₁, TR₁₂, TR₁₃, TR₁₄Consists of a gate electrode 12, a gate insulating film, and a source / drain region 13. The first selection transistor TR₁₁, Second selection transistor TR₁₂, Third selection transistor TR₁₃, Fourth selection transistor TR₁₄One source / drain region 13 of bit line BL is connected to bit line BL via a contact hole.₁It is connected to the. The first selection transistor TR₁₁The other source / drain region 13 of the first common node CN is connected via a connection hole 17 provided in an opening formed in the insulating layer 16.₁₁It is connected to the. Further, the second selection transistor TR₁₂The other source / drain region 13 is connected to the second common node CN via the connection hole 17, the first conductor layer 22A, the second conductor layer 25, and the first conductor layer 22B.₁₂It is connected to the. The third selection transistor TR₁₃The other source / drain region 13 includes a connection hole 17, a first conductor layer 22 A, a second conductor layer 25, a first conductor layer 22 B, and an interlayer insulating layer 26 formed on the insulating layer 16. The third common node CN via a connection hole 27 provided in the opening formed in₁₃It is connected to the. Furthermore, the fourth selection transistor TR₁₄The other source / drain region 13 includes a connection hole 17, a first conductor layer 22A formed on the insulating layer 16, a second conductor layer 25, a first conductor layer 22B, a connection hole 27, The fourth common node CN via the first conductor layer 32A, the second conductor layer 35, and the first conductor layer 32B formed on the interlayer insulating layer 26.₁₄It is connected to the.
[0118]
In addition, the nonvolatile memory according to the second to fourth aspects of the present invention can be a so-called gain cell type. A circuit diagram of such a nonvolatile memory is shown in FIG. 18, a schematic layout of various transistors constituting the nonvolatile memory is shown in FIG. 19, and a schematic partial sectional view of the nonvolatile memory is shown in FIG. It shows in FIG. In FIG. 19, various transistor regions are surrounded by dotted lines, active regions and wirings are indicated by solid lines, and gate electrodes or word lines are indicated by alternate long and short dash lines. 20 is a schematic partial cross-sectional view taken along line AA in FIG. 19, and is a schematic partial cross-sectional view of the nonvolatile memory shown in FIG. The partial cross-sectional view is a schematic partial cross-sectional view taken along line BB in FIG.
[0119]
This nonvolatile memory includes, for example, a bit line BL and a write transistor (a selection transistor in the nonvolatile memory according to the second to fourth aspects of the present invention) TR._WAnd M (where M ≧ 2, for example, M = 8) memory cells MC_MAnd N memory units MU stacked via an interlayer insulating layer and M plate lines PL_MIt is comprised from the memory unit MU which consists of. In the drawing, only the first-layer memory unit is shown. And each memory cell MC_MIncludes a first electrode 21, a ferroelectric layer 23, and a second electrode 24, and constitutes a memory cell MC constituting the memory unit MU._MThe first electrode 21 is common in the memory unit MU, and the common first electrode (common node CN) is the write transistor TR._WConnected to the bit line BL through the memory cell MC_mThe second electrode 24 constituting the plate line PL_mIt is connected to the. Memory cell MC_MIs covered with an interlayer insulating layer 26. Note that the number (M) of the memory cells constituting the memory unit MU of the nonvolatile memory is not limited to eight. In general, it is sufficient that M ≧ 2 is satisfied, and a power of 2 (M = 2, 4, 4). 8, 16...
[0120]
Further, a signal detection circuit that detects a potential change of the common first electrode and transmits the detection result to the bit line as a current or a voltage is provided. In other words, the detection transistor TR_SAnd reading transistor TR_RIt has. The signal detection circuit includes a detection transistor TR_SAnd reading transistor TR_RIt is composed of Then, the detection transistor TR_SOne end of the_ccIs connected to a wiring (for example, a power supply line composed of an impurity layer), and the other end is a reading transistor TR._RConnected to the bit line BL through the memory cell MC_mWhen the data stored in is read, the reading transistor TR_RIs rendered conductive, and each memory cell MC_mTransistor TR for detection based on the potential generated at the common first electrode (common node CN) based on the data stored in_SIs controlled.
[0121]
Specifically, the various transistors are composed of MOS type FETs, and write transistors (selection transistors) TR_WOne source / drain region is connected to the bit line BL through a contact hole 14 formed in the insulating layer 16, and the other source / drain region is provided in an opening formed in the insulating layer 16. It is connected to the common first electrode (common node CN) via the connection hole 17. Also, the detection transistor TR_SOne source / drain region of the transistor has a predetermined potential V_ccThe other source / drain region is connected to a wiring having a read transistor TR_RAre connected to one of the source / drain regions. More specifically, the detection transistor TR_SThe other source / drain region and the reading transistor TR_ROne of the source / drain regions occupies one source / drain region. Further, the reading transistor TR_RThe other source / drain region is connected to the bit line BL through the contact hole 14, and is further connected to the common first electrode (the common node CN or the write transistor TR)._WThe other source / drain region) is a connection hole 17A provided in the opening and the word line WL._SDetection transistor TR via_SConnected to the gate electrode. Also, the writing transistor TR_WWord line WL connected to the gate electrode of_WAnd reading transistor TR_RWord line WL connected to the gate electrode of_RAre connected to a word line decoder / driver WD. On the other hand, each plate line PL_mAre connected to a plate line decoder / driver PD. Further, the bit line BL is connected to the sense amplifier SA.
[0122]
Memory cell MC of this nonvolatile memory₁When reading data from the selected plate line PL₁V_ccIs applied. At this time, the selected memory cell MC₁If data “1” is stored in the ferroelectric layer, polarization inversion occurs in the ferroelectric layer, the amount of stored charge increases, and the potential of the common node CN increases. On the other hand, the selected memory cell MC₁If data “0” is stored in the ferroelectric layer, polarization inversion does not occur in the ferroelectric layer, and the potential of the common node CN hardly increases. That is, the common node CN is connected to a plurality of unselected plate lines PL via the ferroelectric layers of the unselected memory cells._kTherefore, the potential of the common node CN is kept at a level relatively close to 0 volts. In this way, the selected memory cell MC₁The potential of the common node CN changes depending on the data stored in the memory. Therefore, an electric field sufficient for polarization inversion can be applied to the ferroelectric layer of the selected memory cell. Then, the bit line BL is brought into a floating state, and the reading transistor TR_RIs turned on. On the other hand, the selected memory cell MC₁Transistor TR for detection based on the potential generated at the common first electrode (common node CN) based on the data stored in_SIs controlled. Specifically, the selected memory cell MC₁If a high potential is generated at the common first electrode (common node CN) based on the data stored in the detection transistor TR,_SBecomes conductive, and the detection transistor TR_SOne source / drain region of the transistor has a predetermined potential V_ccIs connected to the wiring having the detection transistor TR._SAnd reading transistor TR_RA current flows through the bit line BL through the bit line, and the potential of the bit line BL rises. That is, the potential change of the common first electrode (common node CN) is detected by the signal detection circuit, and the detection result is transmitted to the bit line BL as a voltage (potential). Here, the detection transistor TR_SThreshold of V_th, Detection transistor TR_SThe potential of the gate electrode (that is, the potential of the common node CN) is V_gThen, the potential of the bit line BL is approximately (V_g-V_th) The detection transistor TR_SIs a depletion type NMOSFET, the threshold V_thTakes a negative value. Thereby, a stable sense signal amount can be ensured regardless of the load of the bit line BL. The detection transistor TR_SCan also be constructed from PMOSFETs.
[0123]
The predetermined potential of the wiring to which one end of the detection transistor is connected is V_ccFor example, it may be grounded. That is, the predetermined potential of the wiring to which one end of the detection transistor is connected may be 0 volts. However, in this case, the potential (V_cc) Appears on the bit line, the potential of the bit line is set to 0 volt at the time of rewriting, and when 0 volt appears on the bit line at the time of reading data in the selected memory cell, the potential of the bit line is set to V at the time of rewriting._ccIt is necessary to. For this purpose, a transistor TR as illustrated in FIG._IV-1, TR_IV-2, TR_IV-3, TR_IV-4A kind of switch circuit (inversion circuit) composed of the above is arranged between the bit lines, and when reading data, the transistor TR_IV-2, TR_IV-4Is turned on, and the transistor TR_IV-1, TR_IV-3Can be turned on.
[0124]
Further, for example, as shown in FIG. 23, as a modification of the nonvolatile memory of the second embodiment, the first electrodes 21 ′ and 31 ′ are the upper electrodes and the second electrodes 24 ′ and 34 ′ are the lower electrodes. It can also be. Such a structure can also be applied to the nonvolatile memory in other embodiments. In FIG. 23, reference numerals 22 'and 32' indicate the first conductor layer, and reference numerals 25 'and 35' indicate the second conductor layer.
[0125]
【The invention's effect】
In the ferroelectric nonvolatile semiconductor memory or semiconductor device of the present invention, the top surface of the connection hole is formed with the first conductor layer formed simultaneously with the first electrode and the second electrode formed simultaneously with the second electrode. Since it is covered with the laminated structure of the two conductor layers, it is possible to reliably prevent the top surface of the connection hole from being damaged when the second electrode is formed. Furthermore, since the connection hole is formed in each of the interlayer insulating layers, the connection hole can be reliably formed without increasing the aspect ratio of the connection hole to the left. Further, when the first electrode or the like has a so-called damascene structure, since the first conductor layer is formed, the processing accuracy in the CMP method can be improved. In the semiconductor device according to the present invention, since the wiring constituting the peripheral circuit is composed of at least the second conductor layer formed simultaneously with the second electrode, the number of wiring layers in the peripheral circuit is reduced. Can be made. In addition, since a kind of connection pad portion is formed on the top surface of the connection hole by the laminated structure of the first conductor layer and the second conductor layer, the area of the connection region in the peripheral circuit can be reduced. it can. Moreover, in the semiconductor device of the present invention, the wiring formation process can be simplified as compared with the conventional technique, and the chip area can be reduced, resulting in a reduction in the manufacturing cost of the semiconductor device. Can be achieved.
[Brief description of the drawings]
1 is a schematic partial cross-sectional view of a semiconductor device including a ferroelectric nonvolatile semiconductor memory according to a first embodiment of the present invention, cut along a virtual vertical plane parallel to the direction in which bit lines extend;
FIG. 2 is a schematic partial cross-sectional view of the semiconductor device including the ferroelectric nonvolatile semiconductor memory according to the first embodiment of the present invention cut along a virtual vertical plane parallel to the direction in which the word lines extend.
FIG. 3 is a conceptual circuit diagram of a nonvolatile memory according to a second aspect of the present invention.
4 is a more specific circuit diagram of the conceptual circuit diagram shown in FIG.
FIG. 5 is a more specific circuit diagram of the conceptual circuit diagram shown in FIG.
6 is a schematic partial cross-sectional view of a semiconductor substrate and the like for illustrating the method of manufacturing a semiconductor device according to the first embodiment of the invention. FIG.
7 is a schematic partial cross-sectional view of the semiconductor substrate and the like for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention, following FIG. 6;
FIG. 8 is a schematic partial cross-sectional view of the semiconductor substrate and the like for explaining the method for manufacturing the semiconductor device of the first embodiment of the invention, following FIG. 7;
FIG. 9 is a schematic partial cross-sectional view of a semiconductor device including a ferroelectric nonvolatile semiconductor memory according to a second embodiment of the present invention, taken along a virtual vertical plane parallel to the direction in which bit lines extend.
FIG. 10 is a conceptual circuit diagram of a nonvolatile memory according to a third aspect of the present invention.
11 is a more specific circuit diagram of the conceptual circuit diagram shown in FIG.
12 is a more specific circuit diagram of the conceptual circuit diagram shown in FIG.
13 is a schematic partial cross-sectional view of a semiconductor device including a ferroelectric nonvolatile semiconductor memory according to a third embodiment of the present invention cut along a virtual vertical plane parallel to the direction in which the bit lines extend. FIG.
FIG. 14 is a conceptual circuit diagram of a nonvolatile memory according to a fourth aspect of the present invention.
15 is a more specific circuit diagram of the conceptual circuit diagram shown in FIG.
FIG. 16 is a schematic partial cross-sectional view showing a modification of the ferroelectric nonvolatile semiconductor memory described in the second embodiment of the present invention.
17 is a circuit diagram of the ferroelectric nonvolatile semiconductor memory shown in FIG. 16. FIG.
FIG. 18 is a circuit diagram of a gain cell type ferroelectric nonvolatile semiconductor memory.
FIG. 19 is a layout diagram of the ferroelectric-type nonvolatile semiconductor memory shown in FIG. 18;
20 is a schematic partial cross-sectional view of the ferroelectric nonvolatile semiconductor memory shown in FIG.
21 is a schematic partial cross-sectional view of the ferroelectric nonvolatile semiconductor memory shown in FIG. 18 as seen in a cross section different from that of FIG. 20;
FIG. 22 is a circuit diagram showing a kind of switch circuit arranged between bit lines when a predetermined potential of a wiring to which one end of a detection transistor is connected is 0 volt.
FIG. 23 is a schematic partial cross-sectional view of another modification of the ferroelectric nonvolatile semiconductor memory according to the second embodiment of the present invention.
FIG. 24 is a PE hysteresis loop diagram of a ferroelectric.
FIG. 25 is a circuit diagram of a ferroelectric nonvolatile semiconductor memory disclosed in US Pat. No. 4,873,664.
FIG. 26 is a circuit diagram of a ferroelectric nonvolatile semiconductor memory disclosed in Japanese Patent Application Laid-Open No. 9-121032.
FIG. 27 is a schematic partial cross-sectional view of a semiconductor device assuming a case where memory units composed of a plurality of memory cells are stacked in a nonvolatile memory disclosed in Japanese Patent Application Laid-Open No. 9-121032.
FIG. 28 is a schematic view of a semiconductor device in which a nonvolatile memory disclosed in Japanese Patent Application Laid-Open No. 9-121032 is viewed from an angle different from that in FIG. 27 and a memory unit including a plurality of memory cells is stacked. FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Silicon semiconductor substrate, 11 ... Element isolation region, 12, 112, 212 ... Gate electrode, 13, 13A, 13B, 113, 213 ... Source / drain region, 14 ... Contact hole , 16 ... insulating layer, 17, 27, 117, 127, 217, 227 ... connection hole, 21, 21A, 21B, 21 ', 31, 31A, 31B, 31' ... first electrode, 22, 22 ′, 22A, 22B, 32, 32 ′, 32A, 32B, 122, 132... First conductor layer, 23, 23A, 23B, 23 ′, 33, 33A, 33B, 33 ′. Ferroelectric layer, 24, 34 ... second electrode, 25, 25 ', 35, 35' 125, 135 ... second conductor layer, 26 ... interlayer insulating layer, 36A, 46A ... Insulating film, TR ... Selectable tiger Register, TR_W... Write transistors, TR_R... Reading transistors, TR_S... Detection transistors, TR_SW... Switching transistor, WL ... Word line, BL ... Bit line, PL ... Plate line, WD ... Word line decoder / driver, SA ... Sense amplifier, PD ... Plate line decoder / driver, CN ... Common node

Claims (6)

A memory cell including a first electrode, a ferroelectric layer, and a second electrode is formed on an insulating layer provided on a semiconductor substrate on which a transistor is formed. However, it is a ferroelectric nonvolatile semiconductor memory having a structure in which N layers are stacked through N ≧ 2),
A connection hole is formed in the insulating layer on the source / drain region and / or the gate electrode of the transistor, and in the insulating layer and the interlayer insulating layer.
The first electrode constituting the first-layer memory cell is composed of the first conductive material layer of the first layer,
The second electrode constituting the memory cell of the first layer is composed of the second conductive material layer of the first layer,
The top surface of the connection hole formed in the insulating layer is covered with a laminated structure of a first conductor layer made of the first conductive material layer and a second conductor layer made of the second conductive material layer. and,
The first electrode constituting the memory cell of the (k + 1) th layer (where k = 1, 2,..., N−1) is composed of the first conductive material layer of the (k + 1) th layer. And
The second electrode constituting the memory cell of the (k + 1) th layer is composed of the second conductive material layer of the (k + 1) th layer,
The top surface of the connection hole formed in the kth interlayer insulating layer has a first conductor layer made of the (k + 1) th first conductive material layer, and a (k + 1) th layer A ferroelectric nonvolatile semiconductor memory covered with a laminated structure of second conductive layers made of a second conductive material layer . (A) a bit line;
(B) a selection transistor;
(C) N (where N ≧ 2) memory units each composed of M (where M ≧ 2) memory cells;
(D) M × N plate wires,
Consisting of
The memory unit of the first layer is formed above the selection transistor via the insulating layer,
N memory units are stacked via (N-1) interlayer insulating layers,
Each memory cell includes a first electrode, a ferroelectric layer, and a second electrode,
In each memory unit, the first electrode of the memory cell is common,
In the memory unit of the nth layer (where n = 1, 2,..., N), the second electrode of the mth memory cell (where m = 1, 2,..., M) is Connected to the [(n-1) M + m] th plate line,
One source / drain region of the selection transistor is connected to the bit line,
The other source / drain region of the selection transistor is connected to a common first electrode in the first-layer memory unit via a first-layer connection hole provided in the insulating layer.
The other source / drain region of the selection transistor further includes a first-layer connection hole provided in the insulating layer, and a first-layer interlayer insulating layer to k-th layer (provided that k = 1, 2..., N−1) to the (k + 1) th layer through each of the (k + 1) th connection hole from the second layer connection hole provided in each of the interlayer insulating layers. A ferroelectric nonvolatile semiconductor memory connected to a common first electrode in a memory unit,
The first electrode constituting the memory cell of the first layer memory unit is composed of the first conductive material layer of the first layer,
The second electrode constituting the memory cell of the first layer memory unit is composed of the second conductive material layer of the first layer,
The top surface of the first layer connection hole formed in the insulating layer has a first conductor layer made of the first conductive material layer of the first layer and a second conductive material of the first layer. Covered by a laminated structure of second conductor layers consisting of layers ,
The first electrode constituting the memory cell of the memory unit of the (k + 1) th layer is composed of the first conductive material layer of the (k + 1) th layer,
The second electrode constituting the memory cell of the (k + 1) th layer memory unit is composed of the (k + 1) th layer of the second conductive material layer,
The top surface of the (k + 1) th connection hole formed in the kth interlayer insulating layer has a first conductor layer made of the (k + 1) th first conductive material layer, and (k + 1) th layer th second strength is covered by a laminated structure of the second conductive layer made of a conductive material layer a dielectric-type nonvolatile semiconductor memory. (A) a bit line;
(B) N (where N ≧ 2) selection transistors;
(C) N memory units each composed of M (where M ≧ 2) memory cells;
(D) M plate wires,
Consisting of
The memory unit of the first layer is formed above the selection transistor via the insulating layer,
N memory units are stacked via (N-1) interlayer insulating layers,
Each memory cell includes a first electrode, a ferroelectric layer, and a second electrode,
In each memory unit, the first electrode of the memory cell is common,
In the memory unit of the nth layer (where n = 1, 2,..., N), the second electrode of the mth memory cell (where m = 1, 2,..., M) is It is connected to the mth plate line that is shared between memory units,
One source / drain region of each selection transistor is connected to the bit line,
The other source / drain region of the first selection transistor is connected to a common first electrode in the memory unit of the first layer via a connection hole of the first layer provided in the insulating layer. ,
The other source / drain region of the (k + 1) -th (k = 1, 2,..., N−1) selection transistor has a first layer connection hole provided in the insulating layer, and The (k + 1) th through the (k + 1) th connection hole from the second layer connection hole provided in each of the interlayer insulation layers from the first interlayer insulation layer to the kth layer. A ferroelectric-type nonvolatile semiconductor memory connected to a common first electrode in the memory unit of the layer;
The first electrode constituting the memory cell of the first layer memory unit is composed of the first conductive material layer of the first layer,
The second electrode constituting the memory cell of the first layer memory unit is composed of the second conductive material layer of the first layer,
The top surface of the first layer connection hole formed in the insulating layer has a first conductor layer made of the first conductive material layer of the first layer and a second conductive material of the first layer. Covered by a laminated structure of second conductor layers consisting of layers ,
The first electrode constituting the memory cell of the memory unit of the (k + 1) th layer is composed of the first conductive material layer of the (k + 1) th layer,
The second electrode constituting the memory cell of the (k + 1) th layer memory unit is composed of the (k + 1) th layer of the second conductive material layer,
The top surface of the (k + 1) th connection hole formed in the kth interlayer insulating layer has a first conductor layer made of the (k + 1) th first conductive material layer, and (k + 1) th layer th second strength is covered by a laminated structure of the second conductive layer made of a conductive material layer a dielectric-type nonvolatile semiconductor memory. (A) N (where N ≧ 2) bit lines;
(B) N selection transistors;
(C) N memory units each composed of M (where M ≧ 2) memory cells;
(D) M plate wires,
Consisting of
The memory unit of the first layer is formed above the selection transistor via the insulating layer,
N memory units are stacked via (N-1) interlayer insulating layers,
Each memory cell includes a first electrode, a ferroelectric layer, and a second electrode,
In each memory unit, the first electrode of the memory cell is common,
In the memory unit of the nth layer (where n = 1, 2,..., N), the second electrode of the mth memory cell (where m = 1, 2,..., M) is It is connected to the mth plate line that is shared between memory units,
One source / drain region of the nth selection transistor is connected to the nth bit line,
The other source / drain region of the first selection transistor is connected to a common first electrode in the memory unit of the first layer via a connection hole of the first layer provided in the insulating layer. ,
The other source / drain region of the (k + 1) -th (k = 1, 2,..., N−1) selection transistor has a first layer connection hole provided in the insulating layer, and The (k + 1) th through the (k + 1) th connection hole from the second layer connection hole provided in each of the interlayer insulation layers from the first interlayer insulation layer to the kth layer. A ferroelectric-type nonvolatile semiconductor memory connected to a common first electrode in the memory unit of the layer;
The first electrode constituting the memory cell of the first layer memory unit is composed of the first conductive material layer of the first layer,
The second electrode constituting the memory cell of the first layer memory unit is composed of the second conductive material layer of the first layer,
The top surface of the first layer connection hole formed in the insulating layer has a first conductor layer made of the first conductive material layer of the first layer and a second conductive material of the first layer. Covered by a laminated structure of second conductor layers consisting of layers ,
The first electrode constituting the memory cell of the memory unit of the (k + 1) th layer is composed of the first conductive material layer of the (k + 1) th layer,
The second electrode constituting the memory cell of the (k + 1) th layer memory unit is composed of the (k + 1) th layer of the second conductive material layer,
The top surface of the (k + 1) th connection hole formed in the kth interlayer insulating layer has a first conductor layer made of the (k + 1) th first conductive material layer, and (k + 1) th layer th second strength is covered by a laminated structure of the second conductive layer made of a conductive material layer a dielectric-type nonvolatile semiconductor memory. (A) A memory cell including a first electrode, a ferroelectric layer, and a second electrode is formed on an insulating layer provided on a semiconductor substrate on which a selection transistor is formed. A ferroelectric nonvolatile semiconductor memory having a structure in which N layers are stacked through an interlayer insulating layer (where N ≧ 2),
(B) a peripheral circuit for driving a ferroelectric nonvolatile semiconductor memory;
A semiconductor device comprising:
The peripheral circuit includes a transistor formed on the semiconductor substrate, wiring formed on the insulating layer and the interlayer insulating layer, and a connection hole connecting the transistor and the wiring.
The connection hole is formed in the insulating layer on the source / drain region and / or the gate electrode of the transistor, and in the insulating layer and the interlayer insulating layer,
The first electrode constituting the first-layer memory cell is composed of the first conductive material layer of the first layer,
The second electrode constituting the memory cell of the first layer is composed of the second conductive material layer of the first layer,
The top surface of the connection hole formed in the insulating layer is covered with a laminated structure of a first conductor layer made of the first conductive material layer and a second conductor layer made of the second conductive material layer. and,
The wiring formed on the insulating layer includes at least a second conductive material layer of the first layer ,
The first electrode constituting the memory cell of the (k + 1) th layer (where k = 1, 2,..., N−1) is composed of the first conductive material layer of the (k + 1) th layer. And
The second electrode constituting the memory cell of the (k + 1) th layer is composed of the second conductive material layer of the (k + 1) th layer,
The top surface of the connection hole formed in the kth interlayer insulating layer has a first conductor layer made of the (k + 1) th first conductive material layer, and a (k + 1) th layer Covered with a laminated structure of second conductor layers made of a second conductive material layer;
Wiring formed in the k-th layer of the interlayer insulating layer includes at least a first (k + 1) th layer semiconductor device comprising a second conductive material layer. The wiring formed on the insulating layer has a stacked structure of a first conductive material layer of the first layer and a second conductive material layer of the first layer ,
The wirings formed on the k-th layer (where k = 1, 2,..., N−1) interlayer insulating layers include the (k + 1) th first conductive material layer and the ( 6. The semiconductor device according to claim 5 , comprising a stacked structure of a second conductive material layer of ( k + 1) th layer .

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