JP2003068990A - Ferroelectric nonvolatile semiconductor memory and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a ferroelectric nonvolatile semiconductor memory having a structure without lowering reliability even by oxidation heat treatment at a high temperature in the case of forming a ferroelectric layer. SOLUTION: The method for manufacturing the ferroelectric nonvolatile semiconductor memory having a selective transistor and a memory cell comprises a step of forming the selective transistor, a step of forming an insulating layer 16 on the entire surface, a step of forming a patterned first electrode on the layer 16, a step of forming a ferroelectric layer 22 on at least the first electrode 21, a step of forming connectors 18, 18A for electrically connecting one source/drain region 14A to the first electrode 21, and a step of forming a second electrode 23 on the layer 22.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric non-volatile semiconductor memory (so-called FERAM) and its manufacturing method.

[0002]

2. Description of the Related Art In recent years, much research has been conducted on large-capacity ferroelectric non-volatile semiconductor memories. A ferroelectric non-volatile semiconductor memory (hereinafter, may be abbreviated as a non-volatile memory) can be accessed at high speed and
It is non-volatile, small in size, low in power consumption, and resistant to shocks. It is expected to be used as a storage device or a recording medium for recording audio and video.

This non-volatile memory utilizes a high-speed polarization reversal of a ferroelectric thin film and its residual polarization to detect a change in the amount of accumulated charge in a capacitor section having a ferroelectric layer.
It is a high-speed rewritable non-volatile memory, and basically includes a memory cell (capacitor portion) and a selection transistor (switching transistor). The memory cell (capacitor section) is composed of, for example, a lower electrode, an upper electrode, and a ferroelectric layer sandwiched between these electrodes. Writing and reading of data in this nonvolatile memory are performed by applying the PE hysteresis loop of the ferroelectric substance shown in FIG. That is, when the external electric field is removed after applying the external electric field to the ferroelectric layer, the ferroelectric layer exhibits spontaneous polarization. The remanent polarization of the ferroelectric layer becomes + P _r when an external electric field in the positive direction is applied, and −P _r when an external electric field in the negative direction is applied. Here, the state where the remanent polarization is + P _r (see FIG. 30)
"D"), the residual polarization is -P _r
The state (see “A” in FIG. 30) is set to “1”.

In order to determine the state of "1" or "0", an external electric field in the positive direction, for example, is applied to the ferroelectric layer. As a result, the polarization of the ferroelectric layer becomes the state of "C" in FIG. At this time, if the data is "0", the polarization state of the ferroelectric layer changes from "D" to "C". On the other hand, if the data is “1”, the polarization state of the ferroelectric layer changes from “A” to “C” via “B”. When the data is "0", polarization inversion of the ferroelectric layer does not occur. On the other hand, when the data is "1", polarization inversion occurs in the ferroelectric layer. As a result, a difference occurs in the amount of charge stored in the memory cell (capacitor section). By turning on the selection transistor of the selected nonvolatile memory, this accumulated charge is detected as a signal current.
When the external electric field is set to 0 after reading the data, the polarization state of the ferroelectric layer becomes the state of “D” in FIG. 30, regardless of whether the data is “0” or “1”. That is, at the time of reading, the data “1” is once destroyed.
Therefore, when the data is "1", an external electric field in the negative direction is applied to bring the state of "A" through the paths "D" and "E", and the data "1" is written again.

The structure and operation of a non-volatile memory, which is currently the mainstream, is described in US Pat. No. 4,873,664. It was proposed by Sheffiled et al.
This nonvolatile memory has a circuit diagram as shown in FIG.
It is composed of two non-volatile memory cells. Incidentally, in FIG. 31, one nonvolatile memory is surrounded by a dotted line.
Each nonvolatile memory has, for example, a selection transistor TR.
₁₁ , TR ₁₂ , memory cell (capacitor part) FC ₁₁ , FC
_It consists of ₁₂ .

A two-digit or three-digit subscript, for example, a subscript "11" is originally a subscript that should be displayed as a subscript "1,1". For example, "111" is originally a subscript "1,1,". 1 "
Is a subscript to be displayed, but for simplification of the display, it is displayed with a two-digit or three-digit subscript. Also, add the subscript "M" to
For example, it is used to collectively display a plurality of memory cells or plate lines, and the subscript “m” is used, for example, to display a plurality of memory cells or plate lines individually, and the subscript “N” is used, for example. It is used to collectively display the selection transistors and memory units, and the subscript “n” is used to individually display the selection transistors and memory units, for example.

Then, one bit is stored by writing complementary data in each memory cell. In FIG. 31, reference numeral “WL” indicates a word line, reference numeral “BL” indicates a bit line, and reference numeral “PL” indicates a plate line. Focusing on one nonvolatile memory, the word line WL ₁ is connected to the word line decoder / driver WD. The bit lines BL ₁ and BL ₂ are connected to the sense amplifier SA. Furthermore, the plate line PL ₁
Are connected to the plate line decoder / driver PD.

In the nonvolatile memory having such a structure, when reading the stored data, the word line W
When L ₁ is selected and the plate line PL ₁ is driven,
Complementary data is transmitted from the paired memory cells (capacitor sections) FC ₁₁ and FC ₁₂ to the selection transistors TR ₁₁ and T.
It appears as a voltage (bit line potential) on the paired bit lines BL ₁ and BL ₂ via R ₁₂ . The voltage (bit line potential) of the paired bit lines BL ₁ and BL ₂ is detected by the sense amplifier SA.

FIG. 32 is a schematic partial cross-sectional view of a stack type non-volatile memory when such a non-volatile memory is composed of a stack type non-volatile memory. This stack type non-volatile memory includes a selection transistor formed on a semiconductor substrate 10 and an insulating layer 216 formed on the entire surface.
A lower electrode 221 formed on the insulating layer 216, a ferroelectric layer 222 formed on the lower electrode 221, an upper electrode 223 formed on the ferroelectric layer 222, and one of the selection transistors. Of the source / drain regions 14A and the lower electrode 221 are electrically connected. The connection hole 218 is formed by filling the inside of the opening formed in the insulating layer 216 with a conductive material such as polysilicon or tungsten. Connection hole 21
8 is formed, the lower electrode 221, the ferroelectric layer 222,
The upper electrode 223 is sequentially formed. In the figure, reference numeral 11
Is an element isolation region, reference numeral 12 is a gate insulating film, reference numeral 13 is a gate electrode, reference numeral 14B is the other source / drain region connected to the bit line BL, reference numeral 22
Reference numeral 226A is a plate line, and reference numeral 226A is a passivation film.

As a ferroelectric material constituting the ferroelectric layer 222, an oxide having a perovskite structure [eg,
Pb (Zr, Ti) O ₃ , (Ba, Sr) TiO ₃ etc.]
Or an oxide having a bismuth-based layered perovskite structure [eg, Bi ₂ Sr (Ta, Nb) ₂ O ₉ , (Bi, L
a) ₄ Ti ₃ O ₁₂ etc.] is used. Then, in order to obtain good characteristics, it is necessary to perform the oxidation heat treatment at a high temperature to form the ferroelectric layer 222 having no oxygen deficiency.

[0011]

However, when the oxidation heat treatment is performed, the atoms of the material forming the lower electrode 221 and the atoms of the conductive material forming the connection hole 218 are interdiffused, or these materials are oxidized. As a result, the reliability of the non-volatile memory may be reduced, and conduction failure may occur. still,
Hereinafter, such interdiffusion of atoms will be simply referred to as interdiffusion.

To prevent mutual diffusion, for example, TiN or T
It is considered to form a barrier layer composed of iAlN or the like between the lower electrode 221 and the connection hole 218. Alternatively, in order to prevent oxidation, the material forming the lower electrode 221 is stable even in a high temperature oxidizing atmosphere. In addition, it is being studied to use a platinum group material such as Ir, IrO ₂ , or SrRuO ₃ having an oxygen barrier property, or an oxide thereof. However, in any case, the structure of the lower electrode 221 becomes complicated, and not only the thickness required for the lower electrode 221 increases, but when the lower electrode 221 is made of a platinum group material, the barrier layer and the lower electrode 221 A non-volatile memory having a high reliability such as a new problem of adhesion between the lower electrode 221 and the lower electrode 221 is formed, and when the lower electrode 221 is made of oxide, the problem of oxidation of the barrier layer during the formation of the lower electrode 221 remains. It is hard to say that the manufacturing technology has been established.

Due to such a current situation, the planar non-volatile memory whose schematic partial sectional view is shown in FIG. 33 is generally adopted. In this planar non-volatile memory, selection transistors are formed, an insulating layer 216 is formed,
After forming the lower electrode 221 on the insulating layer 216 and forming the ferroelectric layer 222 including oxidation heat treatment, a passivation film 226A is formed on the entire surface, and then openings are formed in the passivation film 226A and the insulating layer 216. Formed,
One source / drain region 14 of the selecting transistor
A and the lower electrode 221 are connected by the connection holes 228A and 228B and the wiring 229.

However, the planar type nonvolatile memory has a problem that it is difficult to increase the degree of integration because of its structure.

Japanese Unexamined Patent Publication No. 9-116107 discloses a non-volatile memory having a structure in which a plurality of memory cells are connected in parallel to one selection transistor.
However, in the nonvolatile memory disclosed in this patent publication, basically, a plurality of memory cells are formed on the local oxide film (on the element isolation region). Therefore, the area of the selection transistor and the element isolation region determines the limit of integration, and there is a problem that it is difficult to cope with higher integration. Further, in a nonvolatile memory having a structure in which a plurality of memory cells are connected in parallel to one selection transistor, when a plurality of memory cells are formed above the selection transistor via an insulating layer, a stack type nonvolatile Problems similar to memory may occur.

Therefore, an object of the present invention is to provide a ferroelectric non-volatile semiconductor memory having a structure in which reliability is not deteriorated even by an oxidative heat treatment at a high temperature when forming a ferroelectric layer, and a manufacturing method thereof. To provide.

[0017]

A method of manufacturing a ferroelectric non-volatile semiconductor memory according to the present invention for achieving the above object comprises (A) a semiconductor substrate, which is provided with a source / drain region and a gate electrode. A selection transistor, and (B) a first electrode formed above the selection transistor via an insulating layer, a ferroelectric layer formed on at least the first electrode, and the ferroelectric substance. A method of manufacturing a ferroelectric non-volatile semiconductor memory, comprising: a memory cell including a second electrode formed on a layer; (a) a step of forming a selection transistor; and (b) an insulating layer over the entire surface. And (c) forming a patterned first electrode on the insulating layer, (d) forming a ferroelectric layer on at least the first electrode, and (e) one Source / drain regions of Forming a connecting portion for electrically connecting the first electrode, characterized by comprising the steps of forming a second electrode on the (f) the ferroelectric layer. still,
This method of manufacturing the ferroelectric non-volatile semiconductor memory of the present invention is referred to as a method of manufacturing the ferroelectric non-volatile semiconductor memory according to the first aspect of the present invention for convenience.

The order of step (e) and step (f) can be reversed, and such an aspect is also included in the method for manufacturing a ferroelectric non-volatile semiconductor memory according to the first aspect of the present invention. .

In the method of manufacturing a ferroelectric non-volatile semiconductor memory according to the first aspect of the present invention, the connection portion is a connection hole formed in an insulating layer, and a side portion of the first electrode. Alternatively, it may be configured by the top of the connection hole extending to the top surface.

In the method of manufacturing a ferroelectric non-volatile semiconductor memory of the present invention, the insulating layer has a structure in which a lower insulating layer and an upper insulating layer are laminated, and the step (b) is performed on the entire surface. After forming the lower insulating layer on the lower insulating layer, an intermediate wiring layer electrically connected to one of the source / drain regions is formed on the lower insulating layer, and then an upper insulating layer is formed on the lower insulating layer and the intermediate wiring layer. In the step (e), the intermediate wiring layer and the first electrode are replaced with each other by forming a connecting portion for electrically connecting one of the source / drain regions and the first electrode. It is also possible to adopt a configuration in which a connection portion for electrically connecting is formed. Such a method for manufacturing a ferroelectric non-volatile semiconductor memory of the present invention is referred to as a method for manufacturing a ferroelectric non-volatile semiconductor memory according to the second aspect of the present invention for convenience.

In the method of manufacturing the ferroelectric non-volatile semiconductor memory according to the second aspect of the present invention, the electrical connection between the one source / drain region and the intermediate wiring layer is formed in the lower insulating layer. And a second connection hole formed in the upper insulating layer, and the second connection hole extending to a side portion or a top surface of the first electrode. Can be configured to include the top of the.

In the method of manufacturing a ferroelectric non-volatile semiconductor memory according to the second aspect of the present invention, in order to prevent mutual diffusion between the intermediate wiring layer and the first electrode, the intermediate wiring layer is formed. On the upper surface, for example, TiN, WN, TaN, TiAlN
You may form the diffusion barrier layer which consists of.

A first aspect of the present invention for achieving the above object
A ferroelectric non-volatile semiconductor memory according to the aspect of
(A) A selection transistor formed on a semiconductor substrate, having a source / drain region and a gate electrode, and
(B) A first electrode formed above the selection transistor via an insulating layer, a ferroelectric layer formed on at least the first electrode, and a first electrode formed on the ferroelectric layer. A ferroelectric non-volatile semiconductor memory having a memory cell including two electrodes, wherein one source / drain region of the selection transistor and the first electrode are connection holes formed in an insulating layer, and It is characterized in that the first electrode is electrically connected through a top portion of the connection hole extending to a side portion or a top surface of the first electrode.

Second aspect of the present invention for achieving the above object
A ferroelectric non-volatile semiconductor memory according to the aspect of
(A) A selection transistor formed on a semiconductor substrate, having a source / drain region and a gate electrode, and
(B) A first electrode formed above the selection transistor via an insulating layer, a ferroelectric layer formed on at least the first electrode, and a first electrode formed on the ferroelectric layer. A ferroelectric non-volatile semiconductor memory having a memory cell including two electrodes, wherein the insulating layer has a structure in which a lower insulating layer and an upper insulating layer are stacked, and an intermediate wiring layer is formed on the lower insulating layer. Is formed, and one source of the selection transistor /
The drain region and the intermediate wiring layer are electrically connected to each other through a first connecting hole formed in the lower insulating layer, and the first electrode and the intermediate wiring layer are second electrodes formed in the upper insulating layer. Is electrically connected through the connection hole and the top portion of the second connection hole extending to the side portion or the top surface of the first electrode.

In the ferroelectric non-volatile semiconductor memory according to the second aspect of the present invention, in order to prevent mutual diffusion between the intermediate wiring layer and the first electrode, the upper surface of the intermediate wiring layer is
For example, a diffusion barrier layer made of TiN, WN, TaN, TiAlN may be formed.

A method of manufacturing a ferroelectric non-volatile semiconductor memory according to the first or second aspect of the present invention, or a ferroelectric non-volatile according to the first or second aspect of the present invention. In a semiconductor memory (hereinafter collectively referred to as the present invention), a bit line, an M
The memory unit is further provided with a memory unit composed of (where M ≧ 2) memory cells and M plate lines, and the memory unit is formed on an insulating layer. Electrode is common, and the common first electrode is connected to the bit line through the selection transistor, and is the m-th (where m = 1, 2 ..., M) in the memory unit. The second electrode of the memory cell can be connected to the m-th plate line. Note that such a configuration is referred to as a first configuration nonvolatile memory for convenience.

Alternatively, according to the present invention, a bit line and N (but N ≧ 2) memory units each composed of M (where M ≧ 2) memory cells, M × N plate lines are further provided, the first-layer memory unit is formed on an insulating layer, and the N memory units are stacked via an interlayer insulating layer. , The first electrode of the memory cell is common, and the common first electrode is connected to the bit line through the selection transistor, and the nth layer (where n =
1, 2, ..., N), the second of the m-th (where m = 1, 2 ..., M) memory cells
The electrode may be connected to the [(n-1) M + m] th plate line. Note that such a configuration is referred to as a second configuration non-volatile memory for convenience.

Alternatively, according to the present invention, a bit line and N (where N ≧ 2) memory units, each of which is composed of M (where M ≧ 2) memory cells, M plate lines are further provided, N selection transistors are provided, the first-layer memory unit is formed on an insulating layer, and the N memory units are stacked with an interlayer insulating layer interposed therebetween. In each memory unit,
The first electrode of the memory cell is common, and the common first electrode in the memory unit of the n-th layer (where n = 1, 2, ..., N) is the n-th selection transistor. The second electrode of the m-th (where m = 1, ..., M) memory cell in the n-th layer memory unit is connected to the bit line via the common line between the memory units. It can be configured to be connected to the m-th plate line. It should be noted that, for the sake of convenience, such a configuration is adopted as the third
It is called a non-volatile memory having the above configuration.

Alternatively, in the present invention, N bit lines (where N ≧ 2) and M bit lines (where M ≧ 2) are provided.
≧ 2) further comprising N memory units and M plate lines, each including N selection transistors, and the first layer memory unit is formed on an insulating layer. N memory units are stacked via an interlayer insulating layer, the first electrode of the memory cell is common in each memory unit, and the nth layer (where n = 1, 2, , N) is connected to the n-th bit line via the n-th selection transistor, and the m-th memory unit in the n-th layer memory unit. (However, m = 1,2
, M), the second electrode of the memory cell may be connected to the m-th plate line common to the memory units. Note that such a configuration is referred to as a fourth configuration non-volatile memory for convenience.

In the non-volatile memories having the second to fourth configurations, the structure of the memory cell forming the memory unit of the first layer is the same as that of the first or second aspect of the present invention. A method for manufacturing such a ferroelectric non-volatile semiconductor memory,
Alternatively, the ferroelectric non-volatile semiconductor memory according to the first aspect or the second aspect of the present invention can be applied. On the other hand, the method for manufacturing the ferroelectric non-volatile semiconductor memory according to the first aspect of the present invention is used for the memory cells constituting the memory units of the second layer to the Nth layer, or
The ferroelectric non-volatile semiconductor memory according to the first aspect of the present invention can be applied. That is, the step of forming the interlayer insulating layer on the entire surface of the memory cells constituting the memory units of the second to Nth layers, the step of forming the patterned first electrode on the interlayer insulating layer, at least the first electrode Process of forming a ferroelectric layer thereon Process of forming a connecting portion for electrically connecting one source / drain region and the first electrode Manufactured by a process of forming a second electrode on the ferroelectric layer can do. The steps may be reversed in order.

In this case, the connection portion may be composed of a connection hole formed in the interlayer insulating layer and a top portion of the connection hole extending to a side portion or a top surface of the first electrode. it can. Here, it is desirable to form the connection hole formed in the interlayer insulating layer on the connection hole formed in the insulating layer from the viewpoint of simplifying the structure.

In the non-volatile memories according to the first to fourth structures, a plurality of memory cells share one selection transistor, and moreover, in the non-volatile memories according to the second to fourth structures. Since the memory unit has a laminated structure, the number of transistors occupying the surface of the semiconductor substrate is not restricted, and the storage capacity can be dramatically increased as compared with the conventional ferroelectric nonvolatile semiconductor memory. Therefore, the effective occupied area of the bit storage unit can be significantly reduced. The address selection in the row direction is performed by a two-dimensional matrix composed of selection transistors and plate lines. For example, if a row address selection unit is composed of eight selection transistors and eight plate lines, 16 decoder / driver circuits can select, for example, 64-bit memory cells. Therefore, even if the degree of integration of the ferroelectric non-volatile semiconductor memory is the same as the conventional one, the storage capacity can be increased four times. In addition, the number of peripheral circuits and drive wiring in address selection can be reduced.

In the nonvolatile memories according to the first to fourth configurations, it is sufficient that M ≧ 2 is satisfied, and the practical M is satisfied.
As a value of, for example, a power of 2 (2, 4, 8, 16
・ ・) Can be mentioned. Also, the second configuration to the fourth configuration
In the non-volatile memory according to the above configuration, N ≧ 2 may be satisfied, and as a practical value of N, for example, a power of 2 (2, 4, 8 ...) Can be cited.

As a structure in which the first electrode is common, specifically, a stripe-shaped first electrode is formed, and a ferroelectric layer is formed so as to cover the entire surface of the stripe-shaped first electrode. The configuration can be mentioned. In such a structure, the overlapping region of the first electrode, the ferroelectric layer and the second electrode corresponds to the memory cell. As a structure in which the first electrode is common, other ferroelectric layers are formed on a predetermined region of the first electrode and the insulating layer in the vicinity thereof, and the second electrode is formed on the ferroelectric layer. However, the structure is not limited to these. The ferroelectric thin film may or may not be patterned in order to obtain the ferroelectric layer. Further, the plate line may be configured to extend from the second electrode, or may be formed separately from the second electrode,
It may be configured to be connected to the second electrode. In the latter case, the wiring material forming the plate line can be exemplified by aluminum or aluminum alloy.

The first electrode has a structure in which the surroundings are filled with an insulating layer, that is, a so-called damascene structure,
Since the ferroelectric layer can be formed on a flat base, that is, on the first electrode and the insulating layer, each layer can be flattened and the memory cell or memory unit can be more easily multilayered. Is preferable from the viewpoint that the above can be achieved. Here, the top surface of the insulating layer and the top surface of the first electrode may be in the same plane, or the top surface of the insulating layer may be the first surface.
The top surface of the electrode may protrude, or the top surface of the first electrode may sink from the insulating layer.

After forming the ferroelectric layer on the first electrode,
When forming the connection part that electrically connects one of the source / drain regions and the first electrode, when the ferroelectric layer is made of polycrystalline grains, the conductive material forming the connection part is made of crystal grains. There is a possibility that a short circuit may occur inside the ferroelectric layer by entering the field. In such a case, after forming a ferroelectric layer on the first electrode, a protective layer is formed on the ferroelectric layer to electrically connect one of the source / drain regions and the first electrode. After forming the connection part to be connected from the conductive material, the protective layer and the conductive material thereon are subjected to, for example, a chemical mechanical polishing method (CMP).
Method) or the etch back method.

As a material for forming the ferroelectric layer in the ferroelectric non-volatile semiconductor memory, a bismuth layer compound, more specifically, a Bi-based layered structure perovskite type ferroelectric material can be mentioned. The Bi-based layered structure perovskite type ferroelectric material belongs to a so-called non-stoichiometric compound, and is tolerant of composition shifts at both sites of a metal element and an anion (O etc.) element. In addition, it is not uncommon to show optimum electrical characteristics when the composition deviates slightly from the stoichiometric composition. The Bi-based layered structure perovskite type ferroelectric material is, for example, a compound represented by the general formula (Bi ₂ O ₂ ) ²⁺ (A
_{m-1 B m O 3m +} 1) can be represented by ^2. Where "A"
Represents one kind of metal selected from the group consisting of metals such as Bi, Pb, Ba, Sr, Ca, Na, K and Cd, and “B” represents Ti, Nb, Ta, W and Mo. , Fe,
It represents one kind selected from the group consisting of Co and Cr, or a combination of a plurality of kinds at an arbitrary ratio. Also, m
Is an integer of 1 or more.

Alternatively, the material forming the ferroelectric layer is (Bi _X , Sr _1-X ) ₂ (Sr _Y , Bi _1-Y ) (Ta _Z , Nb _1-Z ) ₂ O _d formula (1 (However, 0.9 ≦ X ≦ 1.0, 0.7 ≦ Y ≦ 1.0, 0
≦ Z ≦ 1.0, 8.7 ≦ d ≦ 9.3) is preferably contained as the main crystal phase. Alternatively, the material forming the ferroelectric layer is Bi _X Sr _Y Ta ₂ O _d formula (2) (where X + Y = 3, 0.7 ≦ Y ≦ 1.3, 8.7 ≦ d
It is preferable that the crystal phase represented by ≦ 9.3) is contained as a main crystal phase. In these cases, the crystal phase represented by the formula (1) or (2) is used as the main crystal phase.
% Or more is more preferable. The formula (1)
In the meaning, (Bi _X , Sr _1-X ) means that Sr occupies the site originally occupied by Bi in the crystal structure, and the ratio of Bi and Sr at this time is X: (1-X). . Further, the meaning of (Sr _Y , Bi _{1 -Y} ) means that Bi occupies the site originally occupied by Sr in the crystal structure, and the ratio of Sr and Bi at this time is Y: (1-Y). . Examples of the material forming the ferroelectric layer containing the crystal phase represented by the formula (1) or (2) as a main crystal phase include Bi oxide, Ta or Nb oxide, and Bi, Ta or Nb oxide. In some cases, a small amount of complex oxide may be contained.

Alternatively, the material forming the ferroelectric layer is Bi _X (Sr, Ca, Ba) _Y (Ta _Z , Nb _{1 -Z} ) ₂ O _d Formula (3) (where 1.7 ≦ X ≤2.5, 0.6≤Y≤1.2,0
≦ Z ≦ 1.0, 8.0 ≦ d ≦ 10.0) may be included. In addition, "(Sr, Ca, Ba)"
Means one kind of element selected from the group consisting of Sr, Ca and Ba. When the composition of the material forming the ferroelectric layer represented by each of these formulas is represented by a stoichiometric composition, for example, Bi ₂ SrTa ₂ O ₉ , Bi ₂ SrNb ₂ O ₉ ,
_{Bi 2 BaTa 2 O 9, Bi} 2 Sr (Ta, Nb) can be exemplified ₂ O _9, or the like. Alternatively, as a material for forming the ferroelectric layer, Bi ₄ SrTi ₄ O ₁₅ , Bi ₃ TiNb is used.
O ₉ , Bi ₃ TiTaO ₉ , Bi ₄ Ti ₃ O ₁₂ , Bi ₂ PbT
can be exemplified a ₂ O _9, etc., even in these cases, the ratio of the respective metal elements may change to the extent that the crystal structure does not change. That is, there may be a compositional shift at both the metal element and oxygen element sites.

Alternatively, as a material forming the ferroelectric layer, PbTiO ₃ or P having a perovskite structure is used.
Lead zirconate titanate [PZT, Pb (Zr _{1 -y} , Ti _y ) O ₃ (provided that bZrO ₃ and PbTiO ₃ are solid solutions.
0 <y <1)], PLZT which is a metal oxide obtained by adding La to PZT, or PZT compound such as PNZT which is a metal oxide obtained by adding Nb to PZT.

In order to obtain the ferroelectric layer, the ferroelectric thin film is subjected to oxidation heat treatment according to the ferroelectric material to be used in the step after the ferroelectric thin film is formed, and the ferroelectric thin film is patterned. do it. In some cases, patterning of the ferroelectric thin film is unnecessary. The ferroelectric thin film can be formed by a method suitable for the material forming the ferroelectric thin film, such as MOCVD, pulse laser ablation, sputtering, and sol-gel method. The ferroelectric thin film can be patterned by, for example, anisotropic ion etching (RIE) method.

In the present invention, the first electrode and the second electrode are at least one metal selected from the platinum group,
Alternatively, it is composed of its oxide, or alternatively, ruthenium (Ru), rhodium (Rh), palladium (P
d), at least one metal selected from the group consisting of osmium (Os), iridium (Ir), platinum (Pt) and rhenium (Re), or an oxide thereof. For example,
Ir, IrO _2-X , IrO _2-X / Ir, Ir / Ir
O _2-X , SrIrO ₃ , Ru, RuO _2-X , SrRuO ₃ ,
Pt, Pt / IrO _2-X , Pt / RuO _2-X , Pd, Pt
/ Ti laminated structure, Pt / Ta laminated structure, Pt / Ti
/ Ta can be exemplified as a laminated structure, or
La _0.5 Sr _0.5 CoO ₃ (LSCO), Pt / LSCO
And the laminated structure of YBa ₂ Cu ₃ O ₇ .
Here, the value of X is 0 ≦ X <2. In the laminated structure, the material described before "/" constitutes the upper layer and the material described after "/" constitutes the lower layer.
The first electrode and the second electrode may be made of the same material or may be made of the same material,
It may be composed of different materials. In order to form the first electrode or the second electrode, in a step after forming the first conductive material layer forming the first electrode or the second conductive material layer forming the second electrode, The first conductive material layer or the second conductive material layer may be patterned. The first conductive material layer or the second conductive material layer is formed by, for example, a first conductive material layer or a second conductive material layer such as a sputtering method, a reactive sputtering method, an electron beam evaporation method, a MOCVD method, or a pulse laser ablation method. This can be performed by a method that is appropriately suitable for the material forming the conductive material layer. The patterning of the first conductive material layer and the second conductive material layer is performed by, for example, the ion milling method, the RIE method, or the like.
It can be performed by a chemical mechanical polishing method (CMP method).

In the present invention, silicon oxide (SiO ₂ ), silicon nitride (SiN), SiON, SOG, NSG and BPS are used as materials for forming the insulating layer and the interlayer insulating layer.
G, PSG, BSG or LTO can be exemplified.

The connection portion and the connection hole are subjected to an oxidation heat treatment temperature when forming the ferroelectric layer (generally 600 ° C. to 800 ° C.).
Conductive material that can withstand (for example, refractory metal materials such as TiN, polysilicon containing impurities, and tungsten)
Can be obtained by burying in the opening formed in the insulating layer or the interlayer insulating layer and extending on the insulating layer or the interlayer insulating layer. Also, if necessary, for example,
A diffusion barrier layer made of TiN, WN, TaN, or TiAlN for preventing mutual diffusion may be formed in the connection portion or the connection hole. A CVD method, a sputtering method, and a plating method can be exemplified as the method of forming the connection portion and the connection hole.

The selection transistor (switching transistor) and various transistors formed on the semiconductor substrate below the memory cell via the insulating layer can be composed of, for example, a well-known MIS type FET or MOS type FET. .. Examples of the material forming the bit line include polysilicon doped with impurities and a refractory metal material.

In the nonvolatile memories according to the first to fourth configurations, practically, such nonvolatile memories are paired (for convenience, referred to as nonvolatile memory-A and nonvolatile memory-B), and paired. The bit lines forming the non-volatile memory can be connected to the same sense amplifier. In this case, the non-volatile memory-A
Selection transistor and a non-volatile memory-B
The selection transistor constituting the above may be connected to the same word line or different word lines. Nonvolatile Memory-A and Nonvolatile Memory-
Depending on the configuration and operating method of B, 1 is set for each memory cell that constitutes the nonvolatile memory-A and the nonvolatile memory-B.
Bits can be stored, and non-volatile memory
One of the memory cells forming A and one of the memory cells forming the non-volatile memory-B connected to the same plate line as this memory cell are set as a pair, and are complementary to these paired memory cells. Data can also be stored.

In the present invention, one source / drain region and the first source / drain region are formed in the step after the ferroelectric layer is formed.
Since the connection part that electrically connects with the electrode of is formed, it is possible to reliably prevent the reliability of the ferroelectric non-volatile semiconductor memory from being deteriorated even by the oxidation heat treatment at high temperature when forming the ferroelectric layer. can do.

[0048]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below with reference to the drawings on the basis of an embodiment of the invention (hereinafter, simply referred to as an embodiment).

(Embodiment 1) Embodiment 1 relates to a ferroelectric non-volatile semiconductor memory (hereinafter abbreviated as non-volatile memory) according to the first aspect of the present invention and a method for manufacturing the same, and more specifically, , A nonvolatile memory having the first configuration and the second configuration. FIG. 1 is a schematic partial cross-sectional view of the nonvolatile memory according to the first embodiment taken along a virtual vertical plane that is parallel to the extending direction of bit lines. Furthermore, a conceptual circuit diagram of the non-volatile memory according to the second configuration of the present invention is shown in FIGS. 2A and 2B, and is more concrete than the conceptual circuit diagram of FIG. A schematic circuit diagram is shown in FIG. 3, and a more specific circuit diagram of the conceptual circuit diagram of FIG. 2B is shown in FIG. In addition, in FIGS. 3 and 4, two nonvolatile memories M are shown.
₁ and M ₂ are shown, these nonvolatile memories M ₁ and M ₂
The structure is the same, and the non-volatile memory M ₁ will be described below.

The non-volatile memory according to the first embodiment is for selection.
Transistor TR₁And a memory cell MC₁₁₁~ MC
₁₁₄It is composed of each. Transis for selection
TR ₁Are formed on the semiconductor substrate 10 and are source / drain.
The in-regions 14A and 14B and the gate electrode 13 are provided.
It Each memory cell MC₁₁₁~ MC₁₁₄Is a transition for selection
Star TR₁Formed on the upper side of the insulating layer 16 via the insulating layer 16
Electrode 21 and at least on the first electrode 21 (embodiment
In State 1, more specifically, the insulating layer 16 and the first
A ferroelectric layer 22 formed on the electrode 21) of the
Comprising a second electrode 23 formed on the layer 22
It Then, the selection transistor TR₁One source
/ Drain region 14A and first electrode 21 are insulating layers 1
6 and the contact hole 18 formed in 6 and the top of the first electrode 21.
Electrically through the top portion 18A of the connection hole 18 extending to the surface
It is connected to the.

Alternatively, the nonvolatile memory according to the first embodiment has (1) bit line BL ₁ and (2) M ′ pieces (however,
M ′ ≧ 2, and in the first embodiment, M ′ = 8)
Further includes a memory unit MU _1N composed of memory cells MC _{111 to} MC ₁₁₄ and MC _{121 to} MC ₁₂₄ , and (3) M ′ plate lines.

The memory cell has a first electrode 21,
31 and the ferroelectric layers 22 and 32 and the second electrodes 23 and 33, the memory unit is formed on the insulating layer 16, and in the memory unit, the first electrodes 21 and 31 of the memory cells are common. And the common first electrode 21,
31 is a bit line B via the selection transistor TR _1.
The second electrodes 23 and 33 of the m'th (where m '= 1, 2, ..., M') memory cell connected to L ₁ are the m'th plate line. It is connected to the.

Alternatively, in the nonvolatile memory of the first embodiment, (1) bit lines BL ₁ and (2) are M in number (where M ≧ 2, and in the first embodiment, M =
4) N memory cells MC _1NM (where N ≧ 2, in the first embodiment, N = 2)
Memory unit MU _1N , and (3) M × N plate lines.

Then, the first-layer memory unit MU ₁₁
Is formed on the insulating layer 16, and the N memory units MU _1N are stacked via the interlayer insulating layer 26.
Each memory cell includes a first electrode 21, 31 and a ferroelectric layer 2
Consists 2,32 and second electrodes 23 and 33 Prefecture, in each of the memory units MU _1N, the first electrode of the memory cell MC _1NM are common, the common first electrode, the selection transistor TR ₁ It is connected to the bit line BL ₁ via. Specifically, in the memory unit MU ₁₁ , the first electrode 21 of the memory cell MC _11M is common (this common first electrode is referred to as the first common node CN ₁₁ ) and the common first electrode 21 is common. The electrode 21 (first common node CN ₁₁ ) is connected to the bit line BL ₁ via the selection transistor TR ₁ . Also, in the memory unit MU ₁₂ , the first electrode 31 of the memory cell MC _12M is common (this common first electrode is referred to as the second common node CN ₁₂ ) and the common first electrode 31 ( The second common node CN ₁₂ ) is connected to the bit line BL ₁ via the selection transistor TR ₁ . Furthermore, the nth layer (where n = 1, 2 ...
, N) memory unit MC _{1nm of} the m-th (where m = 1, 2 ..., M) memory cell MU _1n
The second electrodes 23 and 33 of are connected to the [(n-1) M + m] th plate line PL _{(n-1) M + m} . The plate line PL _{(n-1) M + m} is also connected to the second electrodes 23 and 33 of each memory cell forming the nonvolatile memory M ₂ . In the first embodiment, more specifically,
Each plate line extends from the second electrode 23, 33.

[0055] The other of the source / drain region 14B of the selection transistor TR ₁ is connected to the bit line BL ₁ through a contact hole 15, one of the source / drain region 14A of the selection transistor TR _1, the insulating layer 16 through the connection hole 18 (referred to as the connection hole 18 of the first layer) and the top portion 18A of the connection hole 18 extending to the top surface of the first electrode 21. It is connected to the common first electrode 21 (first common node CN ₁₁ ) in the memory unit MU ₁₁ . Furthermore, one source / drain region 14B of the selection transistor TR ₁ is
The connection hole 18 of the first layer provided in the insulating layer 16, the pad portion 25, and the connection hole 28 provided in the interlayer insulating layer 26 (second
(Called the connection hole 28 of the second layer), and the common first electrode 31 in the memory unit MU ₁₂ of the second layer via the top 28A of the connection hole 28 extending to the top surface of the first electrode 31.
(Second common node CN ₁₂ ). In the figure, reference numeral 36A is a passivation layer.

The bit line BL ₁ is connected to the sense amplifier SA. The plate line PL _{(n-1) M + m} is connected to the plate line decoder / driver PD. Furthermore, the word line WL (or the word lines WL ₁ and WL ₂ )
Are connected to the word line decoder / driver WD. The word line WL extends in the direction perpendicular to the paper surface of FIG. In addition, the memory cell M that constitutes the nonvolatile memory M ₁
The second electrode 23 of C _11m is common to the second electrode of the memory cell MC _21m that constitutes the nonvolatile memory M ₂ that is adjacent in the direction perpendicular to the paper surface of FIG. 1, and is the plate line PL _{(n-1) M. Also} serves as _{+ m} . Further, the second electrode 33 of the memory cell MC _12m forming the non-volatile memory M ₁ is the same as the second electrode of the memory cell MC _22m forming the non-volatile memory M ₂ which is adjacent in the direction perpendicular to the paper surface of FIG. Common, plate line PL
_Also serves as _{(n-1) M + m} . The word line WL is common for selection transistors TR ₁ constituting the nonvolatile memory M _1, a selection transistor TR ₂ constituting the nonvolatile memory M ₂ adjacent in the direction perpendicular to the paper surface in FIG. 1.

In the nonvolatile memories M ₁ and M ₂ whose circuit diagrams are shown in FIGS. 2A and 3, the nonvolatile memories M ₁ and M _{2 are}
The selection transistors TR ₁ and TR ₂ constituting the above are connected to the same word line WL. Then, the paired memory cells MC _1nm , MC _2nm (n = 1, 2, ..., N, and
Data complementary to m = 1, 2, ..., M) is stored. For example, memory cells MC _1nm and MC _2nm (where m
Is any one of 1, 2, 3, and 4), the word line WL is selected to read the data stored in the plate line PL _j
The (m ≠ j), for example, (1/3) while applying a voltage of V _cc, driving the plate line _{PL (n-1) M +} m. Here, V _cc is, for example, a power supply voltage. by this,
Complementary data are stored in a pair of memory cells MC _1nm , M
Voltage (bit line potential) from C _2nm to the paired bit lines BL ₁ and BL ₂ through the selection transistors TR ₁ and TR _2.
Appears as. Then, the paired bit line BL
The voltage of ₁ and BL ₂ (bit line potential) is applied to the sense amplifier SA
Detect with. The selection transistors TR ₁ and TR ₂ forming the nonvolatile memories M ₁ and M ₂ are connected to different word lines WL ₁ and WL ₂ , respectively, and the memory cells MC _1nm and M ₁ are connected.
C _2nm is independently controlled to form a pair of bit lines BL ₁ and B
By applying a reference voltage to one of L _2, it can be read out memory cells MC _{1 nm,} the data from each of the MC _{2 nm.} For the circuit diagram in the case of adopting such a configuration, refer to FIG. If the selection transistors TR ₁ and TR ₂ are driven at the same time, the circuit becomes equivalent to the circuit shown in FIG. 2A and FIG. Thus, 1 bit is stored as data in each of the memory cells MC _1nm , MC _2nm (n = 1, 2, m = 1, 2, 3, 4) ((B) of FIG. 2 and FIG. 4), or alternatively, data complementary to the paired memory cells MC _1nm and MC _2nm is stored as 1 bit ((A) of FIG. 2).
And FIG. 3). In an actual non-volatile memory, a set of memory units that store 16 bits or 8 bits is arranged in an array as an access unit. The value of M is not limited to 4. The value of M may satisfy M ≧ 2, and as a practical value of M,
For example, a power of 2 (2, 4, 8, 16 ...) Can be mentioned. Further, the value of N only needs to satisfy N ≧ 2, and examples of the practical value of N include powers of 2 (2, 4, 8 ...).

A pair of non-volatile memories in a pair
Selection transistor TR₁And TR₂Is the word line WL,
And a pair of bit lines BL₁, BL₂Surrounded by
Occupied area. Therefore, if the word line and bit
If the wires are placed at the shortest pitch, the
A pair of selection transistors TR in a volatile memory ₁
And TR₂Area is 8F²Is. However,
A pair of selection transistors TR₁, TR₂With M pairs
Memory cell MC_11m, MC_12m, MC_21m, MC_22m
1 bit because it is shared by (m = 1, 2, ..., M)
Per-selection transistor TR₁, TR₂The number of
In addition, since the arrangement of the word lines WL is loose,
It is easy to reduce the size of the volatile memory. Moreover, in the peripheral circuit
Even with one word line decoder / driver WD and M
Select M bit with book plate line decoder / driver PD
You can choose. Therefore, such a configuration is adopted.
As a result, the cell area is 8F²Realize a layout close to
It is possible to realize a chip size comparable to DRAM.
it can.

The outline of the method for manufacturing the non-volatile memory according to the first embodiment will be described below with reference to FIGS.

[Step-100] First, a MOS transistor that functions as a transistor forming a selecting transistor in a nonvolatile memory is formed on the semiconductor substrate 10. Therefore, the element isolation region 11 having, for example, a LOCOS structure is formed by a known method. Incidentally, the element isolation region may have a trench structure, or L
A combination of the OCOS structure and the trench structure may be used. Then, the surface of the semiconductor substrate 10 is oxidized by, for example, a pyrogenic method to form the gate insulating film 12. Next, the impurity-doped polysilicon layer is CVD-treated.
Then, the polysilicon layer is patterned to form the gate electrode 13. This gate electrode 13
Also serves as a word line. The gate electrode 13 may be made of polycide or metal silicide instead of being made of a polysilicon layer. Next, the semiconductor substrate 1
Ion implantation is performed at 0 to form an LDD structure. After that, a SiO ₂ layer is formed on the entire surface by a CVD method, and then the SiO ₂ layer is etched back to form a gate sidewall (not shown) on the side surface of the gate electrode 13. Then, after ion-implanting the semiconductor substrate 10, activation / annealing treatment of the ion-implanted impurities is performed to thereby form the source / drain regions 14A and 14B.
To form.

[Step-110] Next, an insulating layer is formed on the entire surface. Specifically, after forming a lower insulating layer (thickness 1 μm) having a laminated structure of SiO ₂ and SiN by a CVD method, a flattening process is performed by a CMP method to reduce the thickness of the lower insulating layer to 0. 6 μm. After that, an opening is formed by the RIE method in the lower insulating layer above the other source / drain region 14B. Then, the impurity-doped polysilicon layer is CV-formed on the lower insulating layer including the inside of the opening.
It is formed by the D method. Then, activation annealing treatment is performed at 850 ° C. for 30 minutes to activate the impurities in the polysilicon layer. As a result, the contact hole 15 is formed. Next, the bit line BL ₁ is formed by patterning the polysilicon layer on the lower insulating layer. Thereafter, an upper insulating layer made of SiO ₂ (thickness 0.4
(.mu.m) is formed on the entire surface by the CVD method, and planarization processing is performed by the CMP method so that the thickness of the upper insulating layer is 0.2 .mu.m.
The lower insulating layer and the upper insulating layer are collectively referred to as an insulating layer 16. The bit line BL ₁ is formed so as not to short-circuit with the connection hole 18 formed in a later step.

[Step-120] Next, the patterned first electrode 21 is formed on the insulating layer 16. Specifically, a SiN film with a thickness of 50 nm and an S with a thickness of 100 nm are used.
An iO ₂ film is sequentially formed on the insulating layer 16 by the CVD method, and then a groove is formed in the SiO ₂ film by the lithography technique and the dry etching technique. In the drawing, these laminated films are indicated by reference numeral 16A. Then, for example, T
An adhesion layer (not shown) made of iO ₂ and having a thickness of 20 nm is formed on the entire surface by a sputtering method, and further, a first conductive material layer (thickness) made of platinum (Pt) that constitutes the first electrode 21 is formed. 1
50 nm) is formed on the entire surface by sputtering. And
CMP the first conductive material layer and the adhesion layer on the laminated film 16A.
By removing it by the method, the stripe-shaped first electrode 21 including the adhesion layer and the first conductive material layer, that is, the first damascene structure having the so-called damascene structure is formed in the groove provided in the laminated film 16A. The electrode 21 can be obtained. The material forming the adhesion layer is not limited to TiO ₂ , and for example, Ti
Or Ta can be used, and in some cases, the formation of the adhesion layer can be omitted. In addition, the first electrode 21 is
It does not have to have a damascene structure. That is, the insulating layer 1
It is also possible to form a first conductive material layer on 6 and form a patterned first electrode 21 based on the lithography technique and the dry etching technique. Furthermore, in this case,
An insulating material may be embedded between the patterned first electrodes 21.

[Step-130] Thereafter, for example, MOC
By the VD method, a Bi-based layered structure perovskite-type strong
Dielectric material (specifically, for example, crystallization temperature 750 °
Bi of C₂SrTa₂O ₉) Ferroelectric thin film consisting of
To form. After that, dry in 250 ° C air
After that, oxidize for 1 hour at 750 ° C in oxygen gas atmosphere
The ferroelectric layer 22 is formed by heat treatment to accelerate crystallization.
To achieve. Thus, the structure shown in FIG. 5 can be obtained.
It

[Step-140] Next, one source / drain
Rain region 14A and first electrode 21 (common node C
N ₁₁) To form a connection portion for electrically connecting with. concrete
Is based on lithography technology and dry etching technology.
Therefore, the forcing above the one source / drain region 14A is performed.
The opening 17 is formed in the electric body layer 22, the laminated film 16A and the insulating layer 16.
Are formed (see FIG. 6). When dry etching, first
Since the electrode 21 of is composed of platinum,
It is difficult to generate high reaction products, and the ferroelectric layer 22 and the adhesion layer
Is etched, but the first electrode 21 is etched.
It is difficult to form the openings 17 as shown in FIG.
it can. The first electrode 21 is made of a conductive oxide material.
If formed, if the first electrode 21 is slightly etched.
There is no problem, but no problem occurs. After that, the CVD method
Based on this, the inside of the opening 17 is filled with a TiN layer, and then
By the CMP method using the ferroelectric layer 22 as a stopper layer,
The TiN layer on the dielectric layer 22 is removed, and the connection hole 18 and the
And the top of the connection hole 18 extending to the top surface of the first electrode 21.
The part 18A is completed (see FIG. 7).

By forming the connection hole 18 from the TiN layer, it is possible to reliably prevent the occurrence of mutual diffusion between the first electrode 21 and the semiconductor substrate 10. Note that depending on the first conductive material layer forming the first electrode 21, Ti
Other conductive material layers may be selected instead of N. Also,
The method of forming the connection hole is not limited to the CVD method, and a sputtering method or a plating method can be adopted. Furthermore, the removal of the TiN layer on the ferroelectric layer 22 is not limited to the CMP method, but may be performed by the etch back method, for example.

[Step-150] Then, the ferroelectric layer 22
The second electrode 23 is formed thereon. Specifically, to form the SiO ₂ film 16B having a thickness of 100nm on the entire surface, by lithography and dry etching, the SiO ₂ film 16B portions to form the second electrode is removed, together, connecting holes The SiO ₂ film 16B above 18 is removed.
After that, a platinum (Pt) layer is formed on the entire surface by a sputtering method, and then the platinum layer on the SiO ₂ film 16B is removed by a CMP method to form a second electrode 23, and at the same time, the connection hole 18 is formed. The pad portion 25 is formed on the top surface. In this way, the structure shown in FIG. 8 can be obtained.

[Step-160] After that, the step of forming the interlayer insulating layer 26 and the step of planarizing the step of forming the patterned first electrode 31 on the interlayer insulating layer 26 having a damascene structure. Of forming the ferroelectric layer 32 of Bi ₂ Sr (Ta _1.5 Nb _0.5 ) O ₉ having a crystallization temperature of 700 ° C. on the electrode 31 of the first source / drain region 14 A and the first electrode 31
A step of forming a connection portion for electrically connecting with (see FIGS. 9 and 10) A step of forming the second electrode 33 on the ferroelectric layer 32, and a step of forming a passivation layer 36A are sequentially performed. . In addition, Bi ₂ Sr (Ta _1.5 N
The ferroelectric layer 32 made of b _0.5 ) O ₉ is subjected to heat treatment for promoting crystallization in an oxygen gas atmosphere at 700 ° C.
You can go on time.

In this case, the connecting portion is the interlayer insulating layer 26.
And a top portion 28A of the connection hole 28 that extends to the top surface of the first electrode 31. The step of forming the connection portion for electrically connecting the one source / drain region 14A and the first electrode 31 in the above step (see FIGS. 9 and 10)
Can be substantially the same as [Step-140]. Further, the connection hole 28 formed in the interlayer insulating layer 26 is formed on the pad portion 25 formed on the connection hole 18 formed in the insulating layer 16. Incidentally, reference numeral 26
A and 26B are the laminated film 16A and the SiO ₂ film 1 respectively.
It is the same type of film having the same function as 6B.

In the process [140], when the opening 17 is formed in the ferroelectric layer 22, the laminated film 16A and the insulating layer 16 above the one source / drain region 14A based on the lithography technique and the dry etching technique. Depending on the size and position of the opening 17 of the, the finally formed connecting portion is
Alternatively, the connection hole 18 formed in the insulating layer 16 and the top portion 18B of the connection hole extending to the side of the first electrode 21 may be formed. Alternatively, the connection hole 18 may be formed in the interlayer insulating layer 26. Alternatively, the connection hole 28 and the top portion 28B of the connection hole extending to the side of the first electrode 31 may be used.

Further, each second electrode may not also serve as a plate line. In this case, for example, after the formation of the passivation layer 36A is completed, the second electrode 23 and the second electrode 33 are connected by a via hole, and at the same time, a plate line connected to the via hole is formed on the passivation layer 36A. do it.

By properly selecting the material forming the ferroelectric layer, the crystallization temperature (oxidation heat treatment temperature) of the ferroelectric layer forming the upper memory cell is set to the lower memory cell. Can be lower than the crystallization temperature of the ferroelectric layer forming the memory cell, or the crystallization temperature of the ferroelectric layer of the memory cell forming the memory unit located above can be lower than the crystallization temperature of the memory unit located below. Can be lower than the crystallization temperature of the ferroelectric layer of the memory cell constituting the. Table 1 below shows crystallization temperatures of typical materials forming the ferroelectric layer, but the material forming the ferroelectric layer is not limited to such materials.

The crystallization temperature of the ferroelectric layer forming the memory cell can be examined by using, for example, an X-ray diffractometer or a surface scanning electron microscope. Specifically, for example, after forming a ferroelectric thin film, heat treatment for crystallization promotion is performed by changing the heat treatment temperature for crystallization of the ferroelectric thin film, and the ferroelectric thin film after the heat treatment is The crystallization temperature of the ferroelectric layer can be determined by performing X-ray diffraction analysis and evaluating the diffraction pattern intensity (diffraction peak height) peculiar to the ferroelectric material.

By the way, when manufacturing the ferroelectric non-volatile semiconductor memories of the second to fourth structures, oxidation heat treatment (crystallization is carried out) in order to crystallize the ferroelectric thin film constituting the ferroelectric layer. (Heat treatment) must be performed for the number of stacked memory cells or memory units. Therefore, the memory cells and memory units located in the lower stage are subjected to the crystallization heat treatment for a long time, and the memory cells and memory units located in the upper stage are subjected to the oxidation heat treatment for a short time. Therefore, when the optimum oxidation heat treatment is applied to the memory cells or memory units located in the upper stage, the memory cells or memory units located in the lower stage may be subjected to an excessive heat load. The characteristics of the memory unit may be deteriorated. Although it is possible to perform the oxidation heat treatment at once after fabricating the multi-stage memory cell or memory unit, a large volume change occurs in the ferroelectric layer during crystallization, or the ferroelectric layer is removed from each ferroelectric layer. Gas is likely to be generated, and problems such as cracking and peeling of the ferroelectric layer are likely to occur.

If the crystallization temperature of the ferroelectric layer forming the memory cell or the memory unit located above is set lower than the crystallization temperature of the ferroelectric layer forming the memory cell or the memory unit located below. Even if the oxidation heat treatment is performed by the number of stacked memory cells or memory units, there is no problem of characteristic deterioration of the memory cells located below and the memory cells forming the memory unit. Further, the memory cells in each stage and the memory cells forming the memory unit can be subjected to the oxidation heat treatment under optimum conditions, and a ferroelectric non-volatile semiconductor memory having excellent characteristics can be obtained.

[Table 1] Material name Crystallization temperature Bi ₂ SrTa ₂ O ₉ 700 to 800 ° C Bi ₂ Sr (Ta _1.5 , Nb _0.5 ) O ₉ 650 to 750 ° C Bi ₄ Ti ₃ O ₁₂ 600 to 700 ° _{C Pb (Zr 0.48, Ti 0.52} ) O 3 550~650 ° C PbTiO ₃ 500 to 600 ° C

For example, the conditions for forming the ferroelectric thin film made of Bi ₂ SrTa ₂ O ₉ are shown in Table 2 below. Table 2
In the above, “thd” is an abbreviation for tetramethylheptanedionate. The source materials shown in Table 2 are dissolved in a solvent containing tetrahydrofuran (THF) as a main component.

[Table 2] Formation by MOCVD Source material: Sr (thd) ₂ -tetraglyme Bi (C ₆ H ₅ ) ₃ Ta (O-iC ₃ H ₇ ) ₄ (thd) Formation temperature: 400 to 700 ° C Process gas: Ar / O ₂ = 1000/1000 cm ³ Formation rate: 5 to 20 nm / min

Alternatively, a ferroelectric thin film made of Bi ₂ SrTa ₂ O ₉ is formed by pulse laser ablation method, sol-
It can also be formed on the entire surface by a gel method or an RF sputtering method. The formation conditions in these cases are illustrated below. When forming a thick ferroelectric thin film by the sol-gel method, spin coating and drying, or spin coating and baking (or annealing treatment) may be repeated a desired number of times.

[Table 3] Target formed by pulse laser ablation method: Bi ₂ SrTa ₂ O ₉ Laser used: KrF excimer laser (wavelength 248 nm,
Pulse width 25 nsec, 5 Hz) Forming temperature: 400 to 800 ° C Oxygen concentration: 3 Pa

[0080] [Table 4] sol - gel method by forming _{ingredients: Bi (CH 3 (CH 2} ) 3 CH (C 2 H 5) COO) 3 [ bismuth _{2-ethylhexanoate, Bi (OOc) 3] Sr} ( CH ₃ (CH ₂ ) ₃ CH (C ₂ H ₅ ) COO) ₂ [strontium.2-ethylhexanoic acid, Sr (OOc) ₂ ] Ta (OEt) ₅ [tantalum ethoxide] Spin coating conditions: 3000 rpm × 20 seconds Drying : 250 ° C x 7 minutes Firing: 700 to 800 ° C x 1 hour (RTA treatment is added if necessary)

[Table 5] Target formed by RF sputtering method: Bi ₂ SrTa ₂ O ₉ ceramic target RF power: 1.2 W to 2.0 W / target 1 cm ² Atmospheric pressure: 0.2 to 1.3 Pa Formation temperature: Room temperature ˜600 ° C. Process gas: Ar / O ₂ flow rate ratio = 2/1 to 9/1

PZ by magnetron sputtering method when the ferroelectric layer is composed of PZT or PLZT
The conditions for forming T or PLZT are shown in Table 6 below. Alternatively, PZT or PLZT may be formed by reactive sputtering, electron beam evaporation, sol-gel method, or MOCVD.
It can also be formed by a method.

[Table 6] Target: PZT or PLZT process gas: Ar / O ₂ = 90% by volume / 10% by volume Pressure: 4 Pa Power: 50 W Formation temperature: 500 ° C

Furthermore, PZT or PLZT can be formed by the pulse laser ablation method. The forming conditions in this case are illustrated in Table 7 below.

[Table 7] Target: PZT or PLZT Laser used: KrF excimer laser (wavelength 248 nm,
Pulse width 25 nsec, 3 Hz) Output energy: 400 mJ (1.1 J / cm ² ) Formation temperature: 550 to 600 ° C Oxygen concentration: 40 to 120 Pa

(Embodiment 2) Embodiment 2 relates to a non-volatile memory according to a second aspect of the present invention and a method for manufacturing the same, and more specifically, a non-volatile memory having the first configuration and the second configuration. Regarding FIG. 12 shows a schematic partial cross-sectional view of the nonvolatile memory according to the second embodiment taken along a virtual vertical plane parallel to the extending direction of the bit lines.

In the nonvolatile memory according to the second embodiment, the insulating layers are the lower insulating layer 116A and the upper insulating layer 116.
Has a structure in which are stacked B, the intermediate wiring layer 42 is formed on the lower insulating layer 116A, the selection transistor TR ₁
One source / drain region 14A and the intermediate wiring layer 42
Is the first connection hole 4 formed in the lower insulating layer 116A.
The first electrode 21 and the intermediate wiring layer 42 are electrically connected to each other via the first connection electrode 1 and the second connection hole 118 formed in the upper insulating layer 116B and the top surface of the first electrode 21. It is electrically connected through the top of the existing second connection hole 118A. Since other configurations and structures can be the same as those of the nonvolatile memory described in the first embodiment,
Detailed description is omitted.

The outline of the method of manufacturing the nonvolatile memory according to the second embodiment will be described below.

[Step-200] First, in the same manner as in [Step-100] of the first embodiment, a MOS transistor which functions as a transistor forming a selection transistor in a nonvolatile memory is formed on the semiconductor substrate 10.

[Step-210] Next, the lower insulating layer 116A is formed on the entire surface. Specifically, SiO ₂ and Si
Lower insulating layer (thickness 1 μm) 116 having N laminated structure 116
After A is formed by the CVD method, a planarization process is performed by the CMP method so that the lower insulating layer 116A has a thickness of 0.6 μm. After that, an opening 40 is formed in the lower insulating layer 116A above one of the source / drain regions 14A by the RIE method, and at the same time, an opening is formed in the lower insulating layer 116A above the other source / drain region 14B by RIE. Form by the method. Then, the lower insulating layer 116 including the inside of these openings is formed.
A polysilicon layer doped with impurities is CV
It is formed by the D method. Then, activation annealing treatment is performed at 850 ° C. for 30 minutes to activate the impurities in the polysilicon layer. As a result, the first connection hole 41 and the contact hole 15 are formed. Next, the lower insulating layer 1
By patterning the polysilicon layer on 16A, the intermediate wiring layer 42 and the bit line BL ₁ are formed on the lower insulating layer 116A. Thus, the lower insulating layer 116A
An intermediate wiring layer 42 that is electrically connected to one of the source / drain regions 14A via the first connection hole 41 can be formed on the upper side. After that, an upper insulating layer 116B (having a thickness of 0.4 μm) made of SiO ₂ is formed on the entire surface by the CVD method and flattened by the CMP method.
The thickness of 6B is 0.2 μm.

After the polysilicon layer is formed by the CVD method, the polysilicon layer is sputtered, for example,
A diffusion barrier layer made of TiN and having a thickness of 30 nm may be formed. As a result, the intermediate wiring layer 42 and the first electrode 21
It is possible to more reliably prevent mutual diffusion between and.

[Step-220] Next, similarly to [Step-120] of the first embodiment, the patterned first electrode 21 is formed on the upper insulating layer 116B.

[Step-230] After that, the ferroelectric layer 22 is formed in the same manner as in [Step-130] of the first embodiment.

[Step-240] Next, in the same manner as in [Step-140] of the first embodiment, the intermediate wiring layer 42 and the first wiring layer are formed.
To form a connection portion for electrically connecting the electrode 21 (common node CN ₁₁ ) of. Specifically, the opening 17A is formed in the ferroelectric layer 22, the laminated film 16A, and the insulating layer 16 above the intermediate wiring layer 42 based on the lithography technique and the dry etching technique. Then, a TN on the ferroelectric layer 22 is formed by a CMP method in which the TiN layer is filled in the opening 17A based on the CVD method and the ferroelectric layer 22 is used as a stopper layer.
The iN layer is removed, and the second connection hole 118 and the top portion 118A of the connection hole 118 extending to the top surface of the first electrode 21.
To complete.

[Step-250] After that, the second electrode 23 is formed on the ferroelectric layer 22 in the same manner as in [Step-150] of the first embodiment.

[Step-260] After that, in the same manner as in [Step-160] of the first embodiment, the step of forming the interlayer insulating layer 26 and performing the planarization treatment is performed by using the patterned first electrode 31 as the interlayer insulating layer. 26
Step of forming above Step of forming a ferroelectric layer 32 of Bi ₂ Sr (Ta _1.5 Nb _0.5 ) O ₉ having a crystallization temperature of 700 ° C. on at least the first electrode 31 One source / drain region 14A And the first electrode 31
Step of forming connection portions 28 and 28A for electrically connecting to each other Step of forming second electrode 33 on ferroelectric layer 32 Step of forming passivation layer 36A are sequentially performed.

In the [Step-240], when the opening 17 is formed in the ferroelectric layer 22, the laminated film 16A and the insulating layer 16 above the one source / drain region 14A, based on the lithography technique and the dry etching technique. Depending on the size and position of the opening 17, the finally formed connection part has a connection hole formed in the insulating layer 16, as in the schematic partial cross-sectional view shown in FIG. It is also possible to adopt a structure which comprises a top portion of a connection hole extending to the side portion of the first electrode 21, or alternatively to the connection hole formed in the interlayer insulating layer 26 and the side portion of the first electrode 31. It is also possible to adopt a structure including the top of the extended connection hole.

(Third Embodiment) A third embodiment is a modification of the first embodiment. The ferroelectric layer 22 is formed on the first electrode 21.
When forming the connection part for electrically connecting the one source / drain region 14A and the first electrode 21 after the formation, when the ferroelectric layer 22 is composed of polycrystalline grains, the connection part is formed. The conductive material forming
There is a possibility that a short circuit may occur inside the ferroelectric layer.
In such a case, after forming the ferroelectric layer 22 on the first electrode 21, the protective layer 29 is formed on the ferroelectric layer 22,
After forming a connection part for electrically connecting the one source / drain region 14A and the first electrode 21 from a conductive material,
The protective layer 29 and the conductive material thereon may be removed by, for example, the CMP method.

The outline of the method for manufacturing the nonvolatile memory according to the third embodiment will be described below with reference to FIGS. 13 and 14 which are schematic partial cross-sectional views of the semiconductor substrate and the like.

[Step-300] First, in the same manner as in [Step-100] of the first embodiment, a MOS transistor functioning as a transistor forming a selection transistor in a nonvolatile memory is formed on the semiconductor substrate 10.

[Step-310] Next, the insulating layer 16 is formed on the entire surface in the same manner as in [Step-110] of the first embodiment.

[Step-320] Then, in the same manner as in [Step-120] of the first embodiment, the patterned first electrode 21 is formed on the insulating layer 16.

[Step-330] After that, the ferroelectric layer 22 is formed in the same manner as in [Step-130] of the first embodiment.

[Step-340] Next, one source / drain
Rain region 14A and first electrode 21 (common node C
N ₁₁) To form a connection portion for electrically connecting with. concrete
Is formed on the ferroelectric layer 22 by the CVD method.₂Consisting of
A protective layer 29 is formed (see FIG. 13). Then litho
Based on the graphic technology and dry etching technology,
Of the protective layer 29 above the source / drain region 14A of
The opening 1 is formed in the dielectric layer 22, the laminated film 16A and the insulating layer 16.
7 is formed (see FIG. 14). When dry etching
Since the first electrode 21 is composed of platinum, vapor
It is difficult to generate reaction products with high pressure, and
The deposition layer is etched, but the first electrode 21 is etched.
It is hard to be rugged and forms the opening 17 as shown in FIG.
be able to. The first electrode 21 is made of a conductive oxide material.
If the first electrode 21 is slightly etched,
However, there is no problem. Then CV
Based on the D method, the inside of the opening 17 is filled with a TiN layer,
Induced by the CMP method using the dielectric layer 22 as a stopper layer.
The TiN layer and the protective layer 29 on the electric body layer 22 are removed and connection is made.
The hole 18 is completed. Thus, the same as shown in FIG.
Structure can be obtained, one source / drain region 1
4A and the first electrode 21 are electrically connected to each other.
To achieve.

[Step-350] After that, the second electrode 23 is formed on the ferroelectric layer 22 in the same manner as in [Step-150] of the first embodiment, and further, the same as in [Step-160]. Perform the process of.

(Embodiment 4) Embodiment 4 relates to the nonvolatile memory according to the first and third configurations. Embodiment 4 in a virtual vertical plane parallel to the extending direction of the bit line
FIG. 15 is a schematic partial sectional view of the nonvolatile memory of FIG. Further, conceptual circuit diagrams of the non-volatile memory according to the third configuration are shown in (A) and (B) of FIG. 16, and more specific circuit of the conceptual circuit diagram of FIG. FIG. 17 shows the diagram, and FIG. 18 shows a more specific circuit diagram of the conceptual circuit diagram of FIG. 16 (B). 17 and 18 show two non-volatile memories M ₁ and M ₂ , but the non-volatile memories M ₁ and M ₂ have the same structure. I will explain about ₁ .

The nonvolatile memory M _{1 according to the} fourth embodiment is
(1) bit line BL ₁ and (2) N (where N ≧ 2, N = 2 in the fourth embodiment) selection transistors TR _1N and (3) M (M) ( However, M ≧
2 and in the fourth embodiment, N memory units M each composed of M = 4) memory cells MC _1NM.
U _1N and (4) M plate lines PL _M.

Then, the memory unit MU ₁₁ of the first layer
Are formed on the insulating layer 16, and the N memory units MU _1N are stacked via the interlayer insulating layer 26.
Each memory cell comprises a first electrode, a ferroelectric layer and a second electrode. Specifically, the first-layer memory unit M
Each memory cell MC _11M forming U ₁₁ has a first electrode 2
1 and the ferroelectric layer 22 and the second electrode 23, the second
Each memory cell M constituting the memory unit MU ₁₂ of the layer
C _12M comprises a first electrode 31, a ferroelectric layer 32 and a second electrode 33. Further, in each memory unit MU _1n , the first electrodes 21 and 31 of the memory cell MC _1nm are common. Specifically, the first-layer memory unit M
In U ₁₁ , the first electrode 21 of the memory cell MC _11M is common. This common first electrode 21 may be referred to as a first common node CN ₁₁ . Further, in the memory unit MU ₁₂ of the second layer, the first electrode 31 of the memory cell MC _12M is common. This common first electrode 31 may be referred to as a second common node CN ₁₂ . Furthermore, the nth
In the memory unit MU _1n of the layer (n = 1, 2, ..., N), the m-th (however, m = 1, 2 ..., N).
The second electrodes 23 and 33 of the memory cell M) are connected to the m-th plate line P common to the memory units MU _1n.
It is connected to L _m . In the fourth embodiment, more specifically, each plate line extends from the second electrodes 23 and 33.

The nth layer (however, n = 1, 2, ..., N)
Memory unit MU_1nThe common first electrode in
Nth selection transistor TR_1nThrough bit line
BL ₁It is connected to the. Specifically, each selection
Dista TR₁₁, TR₁₂Source / drain region 1 of the other
4B is a bit line BL₁Connected to the first selection gate
Langista TR₁₁One source / drain region 14A
Is the first-layer connection hole 18 provided in the insulating layer 16, and
And a connection hole extending to the side or top surface of the first electrode 21.
Through the top portion 18A of the memory unit MU of the first layer
₁₁Common first electrode 21 (first common node C
N₁₁)It is connected to the. Also, the second selection tiger
Register TR₁₂One source / drain region 14A
Is a first-layer connection hole 18 provided on the insulating layer 16,
The contact between the pad portion 25 and the second layer provided on the interlayer insulating layer 26.
The continuous hole 28 and the side surface or top surface of the first electrode 31
The memory of the second layer is passed through the top 28A of the existing connection hole.
Unit MU₁₂Common first electrode 31 (second
Common node CN₁₂)It is connected to the.

The bit line BL ₁ is connected to the sense amplifier SA. Further, the plate line PL _M is connected to the plate line decoder / driver PD. Furthermore, word lines WL ₁ and WL ₂ (or word lines WL ₁₁ and WL ₁₂ ,
WL ₂₁ and WL ₂₂ ) are word line decoders / drivers WD
It is connected to the. The word lines WL ₁ and WL ₂ extend in the direction perpendicular to the paper surface of FIG. In addition, the nonvolatile memory M ₁
The second electrode 23 of the memory cell MC _11m forming the memory cell MC _21m is common to the second electrode of the memory cell MC _21m forming the nonvolatile memory M ₂ which is adjacent in the direction perpendicular to the paper surface of FIG.
It also serves as the plate line PL _m . Furthermore, the second electrode 33 of the memory cell MC _12m forming the nonvolatile memory M ₁
Is a non-volatile memory M adjacent in the direction perpendicular to the paper surface of FIG.
It is also common to the second electrode of the memory cell MC _22m constituting ₂ and also serves as the plate line PL _m . These plate lines PL _m are connected in a region (not shown).
Further, the word line WL ₁ is common to the selection transistor TR ₁₁ which constitutes the nonvolatile memory M ₁ and the selection transistor TR ₂₁ which constitutes the nonvolatile memory M ₂ which is adjacent in the direction perpendicular to the paper surface of FIG. . Furthermore, the word line WL
₂ is common to the selection transistor TR ₁₂ which constitutes the non-volatile memory M ₁ and the selection transistor TR ₂₂ which constitutes the non-volatile memory M ₂ which is adjacent in the direction perpendicular to the paper surface of FIG.

In the nonvolatile memories M ₁ and M ₂ whose circuit diagrams are shown in FIGS. 16A and 17, the selection transistors TR _1n and TR _2n forming the nonvolatile memories M ₁ and M ₂ are selected.
Are connected to the same word line WL _n . Then, complementary data is stored in the paired memory cells MC _1nm and MC _{2n m} (n = 1, 2, and m = 1, 2, ..., M). For example, memory cells MC _11m and MC _21m (where
m is one of 1, 2, 3, and 4), the word line WL ₁ is selected to read the data stored in the plate line P.
For L _j (m ≠ j), the plate line PL _m is driven in a state where a voltage of (1/3) V _cc is applied, for example. As a result, complementary data is stored in the paired memory cells MC.
_A voltage (bit line potential) appears on the paired bit lines BL ₁ and BL ₂ from _11m and MC _21m through the selection transistors TR ₁₁ and TR ₂₁ . Then, the sense amplifier SA detects the voltage (bit line potential) of the paired bit lines BL ₁ and BL ₂ . In addition, the selection transistors TR ₁₁ , TR ₁₂ , TR ₂₁ , and T that form the nonvolatile memories M ₁ and M _2.
R ₂₂ has different word lines WL ₁₁ , WL ₁₂ , W
The memory cells MC _1nm and MC _2nm are independently controlled by being connected to L ₂₁ and WL ₂₂ , and a reference voltage is applied to one of the paired bit lines BL ₁ and BL _{2 so} that the memory cells MC _1nm and MC _2nm are controlled.
Data can also be read from each of _{1 nm} and MC _{2 nm} . A circuit diagram when such a configuration is adopted is shown in FIG.
See (B) of 6 and FIG. If the selection transistors TR ₁₁ and TR ₂₁ are driven at the same time and the selection transistors TR ₁₂ and TR ₂₂ are driven at the same time, the circuit becomes equivalent to the circuit shown in FIGS. 16A and 17. Thus, 1 bit is stored as data in each of the memory cells MC _1nm , MC _2nm (n = 1, 2, m = 1, 2, 3, 4) ((B) of FIG. 16 and FIG. 18),
Alternatively, data complementary to the paired memory cells MC _1nm and MC _2nm is stored as 1 bit (see (A) of FIG. 16 and FIG. 17). In an actual non-volatile memory, a set of memory units that store 16 bits or 8 bits is arranged in an array as an access unit. The value of M is not limited to 4.
It suffices that the value of M satisfies M ≧ 2, and as a practical value of M, for example, a power of 2 (2, 4, 8, 16 ...)
Can be mentioned. Further, the value of N only needs to satisfy N ≧ 2, and examples of the practical value of N include powers of 2 (2, 4, 8 ...).

The nonvolatile memory of the fourth embodiment is substantially the same as that of the first, second or third embodiment.
Since it can be manufactured by the method of manufacturing a non-volatile memory described in 1), detailed description will be omitted.

(Embodiment 5) Embodiment 5 relates to a nonvolatile memory according to the first and fourth configurations. Embodiment 5 in a virtual vertical plane parallel to the extending direction of bit lines
FIG. 19 is a schematic partial sectional view of the nonvolatile memory of FIG. Furthermore, a conceptual circuit diagram of the nonvolatile memory according to the fourth aspect is shown in FIGS. 20A and 20B, and a concrete circuit diagram is shown in FIG. 20A and 20B, two nonvolatile memories M ₁ and M _{2 are shown.}
Although the structure of these non-volatile memories M ₁ and M ₂ is the same, the non-volatile memory M ₁ will be described below.

The nonvolatile memory M ₁ of the fifth embodiment is
(1) N (where N ≧ 2, in the fifth embodiment, N = 2) bit lines BL _1N , (2) N selection transistors TR _1N , and (3) respectively M (however, M ≧ 2, and M = 4 in the fifth embodiment)
Memory cells MC _{1NM of} N, and N memory units MU _1N and (4) M plate lines PL _M.

20 and 21, bit line BL
₁₁ , a selection transistor TR _11, and a memory cell MC
_The memory unit MU ₁₁ composed of _11M is represented by a subunit SU ₁₁ , and the memory unit MU ₁₂ composed of a bit line BL ₁₂ , a selection transistor TR ₁₂ and a memory cell MC _{12M is} represented by a subunit SU ₁₂ . Represent

Then, the memory unit MU ₁₁ of the first layer
Are formed on the insulating layer 16, and the N memory units MU _1N are stacked via the interlayer insulating layer 26.
Each memory cell comprises a first electrode, a ferroelectric layer and a second electrode. Specifically, the first-layer memory unit M
Each memory cell MC _11M forming U ₁₁ has a first electrode 2
1 and the ferroelectric layer 22 and the second electrode 23, the second
Each memory cell M constituting the memory unit MU ₁₂ of the layer
C _12M comprises a first electrode 31, a ferroelectric layer 32 and a second electrode 33. Further, in each memory unit MU _1n , the first electrodes 21 and 31 of the memory cell MC _1nm are common. Specifically, the first-layer memory unit M
In U ₁₁ , the first electrode 21 of the memory cell MC _11M is common. This common first electrode 21 may be referred to as a first common node CN ₁₁ . Further, in the memory unit MU ₁₂ of the second layer, the first electrode 31 of the memory cell MC _12M is common. This common first electrode 31 may be referred to as a second common node CN ₁₂ . Furthermore, the nth
In the memory unit MU _1n of the layer (n = 1, 2, ..., N), the m-th (however, m = 1, 2 ..., N).
The second electrodes 23 and 33 of the memory cell M) are connected to the m-th plate line P common to the memory units MU _1n.
It is connected to L _m . In the fifth embodiment, more specifically, each plate line extends from the second electrodes 23 and 33.

Nth layer (however, n = 1, 2, ..., N)
The common first electrode in the memory unit MU _1n of
It is connected to the n-th bit line BL _1n via the n-th selection transistor TR _1n . Specifically, the nth
Th other source / drain region 14B of the selection transistor TR _1n is connected to the n-th bit line BL _1n, one of the source / drain region 14A of the first selection transistor TR _11, an insulating layer 16 Common to the memory unit MU ₁₁ of the first layer via the connection hole 18 of the first layer and the top portion 18A of the connection hole extending to the side or top surface of the first electrode 21. First electrode 2
1 (first common node CN ₁₁ ). Further, one source / drain region 14A of the second selection transistor TR ₁₂ is provided with the first-layer connection hole 18 provided in the insulating layer 16, the pad portion 25, and the first insulating layer 26 provided in the interlayer insulating layer 26. Second-layer connection hole 28 and first electrode 3
1 is connected to the common first electrode 31 (second common node CN ₁₂ ) in the memory unit MU ₁₂ of the second layer via the top 28A of the connection hole extending to the side portion or the top surface of the first layer. There is.

The bit line BL _1n is connected to the sense amplifier SA. Further, the plate line PL _M is connected to the plate line decoder / driver PD. Furthermore, word lines WL ₁ and WL ₂ (or word lines WL ₁₁ and WL ₁₂ ,
WL ₂₁ and WL ₂₂ ) are word line decoders / drivers WD
It is connected to the. The word lines WL ₁ and WL ₂ extend in the direction perpendicular to the paper surface of FIG. In addition, the nonvolatile memory M ₁
The second electrode 23 of the memory cell MC _11m forming the memory cell MC _11m is common to the second electrode of the memory cell MC _21m forming the non-volatile memory M ₂ adjacent in the direction perpendicular to the paper surface of FIG.
It also serves as the plate line PL _m . Furthermore, the second electrode 33 of the memory cell MC _12m forming the nonvolatile memory M ₁
Is a non-volatile memory M adjacent in the direction perpendicular to the paper surface of FIG.
It is also common to the second electrode of the memory cell MC _22m constituting ₂ and also serves as the plate line PL _m . These plate lines PL _m are connected in a region (not shown).
Further, the word line WL ₁ is common to the selection transistor TR ₁₁ which constitutes the non-volatile memory M ₁ and the selection transistor TR ₂₁ which constitutes the non-volatile memory M ₂ which is adjacent in the direction perpendicular to the paper surface of FIG. . Furthermore, the word line WL
₂ is common to the selection transistor TR ₁₂ which constitutes the non-volatile memory M ₁ and the selection transistor TR ₂₂ which constitutes the non-volatile memory M ₂ which is adjacent in the direction perpendicular to the paper surface of FIG.

Circuit diagrams are shown in FIGS. 20A and 21.
Non-volatile memory M₁, M₂In the non-volatile memory M
₁, M₂Selection transistor TR₁₁, TR_{twenty one}Is
Same word line WL₁Connected to the selection transistor T
R₁₂, TR_{twenty two}Is the same word line WL₂It is connected to the.
And a pair of memory cells MC_{1 nm}, MC_{2 nm}(N =
1, 2 and m = 1, 2 ..., M)
Data is memorized. For example, the memory cell MC_11m, MC_21m
(Where m is 1, 2, 3, or 4)
Read word data WL₁Select
Rate line PL_jFor (m ≠ j), for example, (1/3) V_cc
With the voltage applied to the plate line PL _mDrive
It This allows complementary data to be paired into a memo.
Resel MC_11m, MC_21mSelect transistor T
R₁₁, TR_{twenty one}Bit line BL paired via₁₁, BL
_{twenty one}Appears as a voltage (bit line potential). And a heel
Paired bit line BL₁₁, BL_{twenty one}Voltage (bit line
Potential) is detected by the sense amplifier SA. Non-volatile
Memory M₁, M₂Selection transistor TR₁₁，
TR ₁₂, TR_{twenty one}, TR_{twenty two}Different word lines
WL₁₁, WL₁₂, WL_{twenty one}, WL_{twenty two}Connected to the memory cell
MC_{1 nm}, MC_{2 nm}Independently control and paired bits
Line BL₁₁, BL_{twenty one}, Or a pair of bit lines BL
₁₂, BL_{twenty two}By applying a reference voltage to one of
Memory cell MC_{1 nm}, MC_{2 nm}Read data from each of
It can also be seen. When adopting such a configuration
For circuit diagrams, see FIGS. 20B and 21.
In addition, the selection transistor TR₁₁, TR_{twenty one}Drive simultaneously
And select transistor TR₁₂, TR_{twenty two}Drive at the same time
Then, the circuit is equivalent to the circuit shown in FIG. this
So that each memory cell MC_{1 nm}, MC_{2 nm}(When n = 1, 2,
Yes, and 1 bit for each of m = 1, 2, 3, 4)
Stored as data (see FIG. 20B), or
Also, a pair of memory cells MC _{1 nm}, MC_{2 nm}Complementary to
Data is stored as 1 bit (see (A) of FIG. 20).
See). In an actual non-volatile memory, this 16-bit
Or a set of memory units that store 8 bits
Arranged in an array as an access unit
It The value of M is not limited to 4. The value of M is M ≧ 2
Should be satisfied, and as a practical value of M, for example, 2
You can list the powers of (2, 4, 8, 16 ...)
Wear. Also, the value of N should satisfy N ≧ 2, and
As a typical N value, for example, a power of 2 (2, 4, 8 ...
・ ・) Can be mentioned.

Alternatively, in FIG. 20 (A) and FIG.
Non-volatile memory M showing a circuit diagram₁Where, for example,
Memory cell MC_11m, MC_12m(M = 1, 2 ...
,, M) may store complementary data. For example,
Memory cell MC_11m, MC_12m(Where m is 1, 2,
When reading the data stored in (3, 4)
Word line WL₁, WL₂Select the plate line PL_j
For (m ≠ j), for example, (1/3) V_ccThe voltage of
Plate line PL_mTo drive. By this
And complementary data is stored in the paired memory cells M
C_11m, MC_12mSelect transistor TR from₁₁, TR₁₂
Bit line BL paired via₁₁, BL₁₂Voltage (V
Line potential). And it became such a pair
Bit line BL₁₁, BL ₁₂Voltage (bit line potential) of
It is detected by the sense amplifier SA. The memory cell MC_11m，
MC_12mBit line B that controls the
L₁₁, BL₁₂By applying a reference voltage to one of
Memory cell MC_11m, MC_12mData from each
Can also be read. When adopting such a configuration
For the circuit diagram of the combination, see Fig. 20 (B) and Fig. 21.
When.

The nonvolatile memory of the fifth embodiment is substantially the same as that of the first, second or third embodiment.
Since it can be manufactured by the method of manufacturing a non-volatile memory described in 1), detailed description will be omitted.

Although the present invention has been described based on the embodiments of the present invention, the present invention is not limited to these. The structure of the nonvolatile memory described in the embodiments of the invention, the materials used, various forming conditions, circuit configurations, driving methods, etc. are merely examples, and can be changed as appropriate.

The order of the step of forming a connection portion for electrically connecting one of the source / drain regions and the first electrode and the step of forming the second electrode on the ferroelectric layer is reversed. You can also In this case, for example, in the third embodiment, after [Step-330], [Step-35]
0] is performed, and then an insulating film is formed on the entire surface, and then one source / drain region 14A and the first electrode 2 are formed.
It suffices to form a connecting portion for electrically connecting the same (common node CN ₁₁ ). Specifically, the entire surface is formed by CVD using Si.
An insulating film made of O ₂ is formed. After that, based on the lithography technique and the dry etching technique, the insulating film and the ferroelectric layer 2 above the one source / drain region 14A are formed.
2. An opening 17 is formed in the laminated film 16A and the insulating layer 16. Then, the TiN layer is filled in the opening 17 based on the CVD method, and the TiN layer on the insulating film may be removed by the CMP method using the insulating film as a stopper layer.

When the stress of the ferroelectric layer is so strong that the ferroelectric layer may be peeled off from the insulating layer or the interlayer insulating layer, the ferroelectric thin film may be patterned into a desired shape. As a result, the stress of the ferroelectric layer can be relaxed. When the ferroelectric layer is damaged by etching, heat treatment may be performed at a temperature required for damage recovery.

As shown in the schematic partial cross-sectional views of FIGS. 29A and 29B, the non-volatile memory according to the first aspect or the second aspect of the present invention and the method for manufacturing the same will be described.
It can also be applied to a stack-type non-volatile memory.

Generally, if the total number of signal lines for driving the unit unit is A, the number of word lines is B, and the number of plate lines is C, then A = B + C. Here, when the total number A is constant, B = C may be satisfied in order to maximize the total number of addresses (= B × C) of the unit unit. Therefore, in order to arrange the peripheral circuits most efficiently, the number of word lines B and the number of plate lines C in the unit unit should be equal. Also, the number of word lines in the row address access unit unit matches, for example, the number of stacked stages of memory cells (N), and the number of plate lines matches the number of memory cells (M) forming the memory unit. The greater the number of word lines and the number of plate lines, the higher the degree of integration of the non-volatile memory. The product of the number of word lines and the number of plate lines is the number of accessible addresses. Here, if it is assumed that the accesses are performed collectively and continuously, the value obtained by subtracting “1” from the product is the number of times of disturbance. Therefore, the value of the product of the number of word lines and the number of plate lines is determined by the disturbance resistance of the memory cell, process factors, and the like. Here, the disturb is a direction in which the polarization is inverted with respect to the ferroelectric layer forming the non-selected memory cell,
That is, it refers to a phenomenon in which an electric field is applied in a direction in which stored data is deteriorated or destroyed.

The nonvolatile memory according to the third configuration is shown in FIG.
It can also be modified like the structure shown in FIG. The circuit diagram is shown in FIG.

This nonvolatile memory has a sense amplifier SA.
N (where N ≧ 2, N = 4 in this example) selection transistors TR ₁₁ , TR ₁₂ and T each composed of a bit line BL ₁ connected to
R ₁₃ and TR ₁₄ and N memory units MU ₁₁ and M
It is composed of U ₁₂ , MU ₁₃ , and MU ₁₄ and a plate line. The first layer memory unit MU ₁₁ has M (however,
M ≧ 2, and in this example, it is composed of M = 8) memory cells MC _11m (m = 1, 2, ..., 8). The second-layer memory unit MU ₁₂ also has M (M = 8) memory cells MC _12m (m = 1, 2 ...
8). Further, the memory unit MU ₁₃ of the third layer also has M (M = 8) memory cells MC _13m.
(M = 1, 2, ..., 8), and the memory unit MU _{14 in} the fourth layer is also M (M = 8) memory cells M.
It is composed of C _14m (m = 1, 2, ..., 8).
The number of plate lines is M (8 in this example) and is represented by PL _m (m = 1, 2, ..., 8). The word line WL _1n connected to the gate electrode of the selection transistor TR _1n is connected to the word line decoder / driver WD. On the other hand, each plate line PL _m is connected to the plate line decoder / driver PD.

Also, the memory unit MU of the first layer₁₁To
Each constituting memory cell MC_11mWith the first electrode 21A
The ferroelectric layer 22A and the second electrode 23, and the second layer
Eye memory unit MU₁₂Memory cells MC configuring
_12mIs the first electrode 21B, the ferroelectric layer 22B and the second
The memory unit MU of the third layer, which includes the electrode 23 ₁₃
Memory cells MC configuring_13mIs the first electrode 31A
And a ferroelectric layer 32A and a second electrode 33,
Layer memory unit MU₁₄Each memory cell M constituting the
C_14mIs the first electrode 31B, the ferroelectric layer 32B, and the second electrode 31B.
Electrode 33. Then, each memory unit MU
₁₁, MU₁₂, MU₁₃, MU₁₄In the memory cell
One electrode 21A, 21B, 31A, 31B is common
It This common first electrode 21A, 21B, 31A, 3
1B is a common node CN for convenience.₁₁, CN₁₂, CN₁₃，
CN₁₄Call.

Here, the first-layer memory unit MU ₁₁
Common first electrode 21A (first common node C
N ₁₁ ) is connected to the bit line BL ₁ via the first selection transistor TR ₁₁ . Further, the common first electrode 21B in the memory unit MU ₁₂ of the second layer
The (second common node CN ₁₂ ) is connected to the bit line BL ₁ via the second selection transistor TR ₁₂ . Further, the common first electrode 31A (third common node CN ₁₃ ) in the memory unit MU ₁₃ of the third layer
Is connected to the bit line BL ₁ through the third selection transistor TR ₁₃ . Further, the common first electrode 31B in the fourth layer of the memory unit MU ₁₄ (4th
Common node CN ₁₄ ) is connected to the bit line BL ₁ via the fourth selection transistor TR ₁₄ .

Also, the memory unit MU of the first layer₁₁To
Memory cell MC_11mAnd the memory unit of the second layer
MU₁₂Memory cell MC constituting the_12mIs the second power
Shares pole 23 and shares this mth second
Electrode 23 is plate line PL _mIt is connected to the. Further
Is the memory unit MU of the third layer₁₃The memory that makes up
Cell MC_13mAnd the memory unit MU of the fourth layer₁₄Construct
Memory cell MC_{1 4m}Share the second electrode 33
And the shared m-th second electrode 33 is
Rate line PL_mIt is connected to the. Specifically, this
Play from the extension of the mth second electrode 23
Line PL_mIs shared and this shared m-th second
From the extending portion of the electrode 33 of the plate line PL_mIs configured
Cage, each plate line PL_mAre connected in the area not shown
ing.

In this nonvolatile memory, the memory units MU ₁₁ and MU ₁₂ and the memory units MU ₁₃ and MU _{14 are used.}
Are stacked with an interlayer insulating layer 26 interposed therebetween. The memory unit MU ₁₄ is covered with the passivation layer 36A. In addition, the memory unit MU ₁₁ includes the semiconductor substrate 10
Is formed above the insulating layer 16 via the insulating layer 16. An element isolation region 11 is formed on the semiconductor substrate 10. Also,
Selection transistors TR ₁₁ , TR ₁₂ , TR ₁₃ , TR
Reference numeral ₁₄ is composed of a gate insulating film 12, a gate electrode 13, and source / drain regions 14A and 14B. Then, the first selection transistor TR ₁₁ , the second selection transistor TR ₁₂ , the third selection transistor TR ₁₃ ,
The other source / drain region 14B of the fourth selecting transistor TR ₁₄ is connected to the bit line BL ₁ through the contact hole 15. Further, one source / drain region 14A of the first selecting transistor TR ₁₁ is
Connection hole 1 provided in the opening formed in the insulating layer 16
8 and the first common node CN ₁₁ via the top portion 18A of the connection hole extending to the side portion or the top surface of the first electrode 21A.
It is connected to the. Further, one of the source / drain regions 14A of the second selection transistor TR ₁₂ is connected via the connection hole 18 and the top portion 18C of the connection hole extending to the side or top surface of the first electrode 21B. Second common node CN
Connected to ₁₂ . Further, one source / drain region 14A of the third selection transistor TR ₁₃ has a connection hole 18, a pad portion 25, a connection hole 28 provided in an opening formed in the interlayer insulating layer 26, and It is connected to the third common node CN ₁₃ via the top portion 28A of the connection hole extending to the side portion or the top surface of the first electrode 31. Furthermore, one of the source / drain regions 14A of the fourth selection transistor TR ₁₄ has a connection hole 18, a pad portion 25, and a connection hole 2.
8 and the side portion 31 of the first electrode or the top portion 28C of the connection hole extending to the top surface is connected to the fourth common node CN ₁₄ .

Further, the non-volatile memories according to the first to fourth configurations can be of so-called gain cell type.
A circuit diagram of such a nonvolatile memory is shown in FIG. 24, a schematic layout of various transistors constituting the nonvolatile memory is shown in FIG. 25, and a schematic partial sectional view of the nonvolatile memory is shown in FIG. As shown in FIG. Note that in FIG. 25, regions of various transistors are surrounded by dotted lines, active regions and wirings are shown by solid lines, and gate electrodes or word lines are shown by dashed lines. The schematic partial cross-sectional view of the nonvolatile memory shown in FIG. 26 is a schematic partial cross-sectional view taken along the line AA of FIG. 25, and the schematic partial cross-sectional view of the nonvolatile memory shown in FIG. 27. The partial cross-sectional view is a schematic partial cross-sectional view taken along the line BB of FIG.

The case where the gain cell type is applied to the nonvolatile memory according to the third structure will be described below. This non-volatile memory includes, for example, a bit line BL, a writing transistor (a selection transistor in the non-volatile memories according to the first to fourth configurations) TR _W , and M (however, M ≧ 2 and, for example, M = 8) memory cell MC
Consists _M, for example, the N memory units MU are stacked with an interlayer insulating layer, M plate lines PL _M
Memory unit MU. still,
In the drawings, only the first layer memory unit is shown. Then, each memory cell MC _M has a first electrode 21
It consists DOO ferroelectric layer 22 and a second electrode 23, first electrode 21 of the memory cells MC _M constituting the memory unit MU is common in the memory unit MU, the common first electrode ( The common node CN) is connected to the bit line BL via the writing transistor TR _W, and the second electrode 23 forming each memory cell MC _m is a plate line P.
It is connected to L _m . The memory cell MC _M is the interlayer insulating layer 2
It is covered by 6. Note that the number (M) of memory cells forming the memory unit MU of the nonvolatile memory is not limited to eight, and generally, M ≧ 2 may be satisfied.
It is preferable to use a power of (M = 2, 4, 8, 16 ...).

Furthermore, a signal detection circuit for detecting a potential change of the common first electrode and transmitting the detection result to the bit line as a current or a voltage is provided. In other words, the detecting transistor TR _S and the reading transistor TR _R are provided. The signal detection circuit is a detection transistor TR.
It is composed of _S and a read transistor TR _R. Then, one end of the detection transistor TR _S has a predetermined potential V
_The data stored in each memory cell MC _m is connected to a wiring having _cc (for example, a power supply line formed of an impurity layer) and the other end is connected to a bit line BL via a read transistor TR _R. When read transistor TR
_R is rendered conductive, and the potential of the common first electrode (common node CN) generated based on the data stored in each memory cell MC _m controls the operation of the detection transistor TR _S.

Specifically, various transistors are MOS
Type FET, the other source / drain region of the write transistor (selection transistor) TR _W is connected to the bit line BL through a contact hole 15 formed in the insulating layer 16, and one source The / drain region is common via the connection hole 18 provided in the opening formed in the insulating layer 16 and the top portion 18A of the connection hole extending to the side portion or the top surface of the first electrode 21. It is connected to the first electrode (common node CN). Further, one source / drain region of the detection transistor TR _S is connected to a wiring having a predetermined potential V _cc, and the other source / drain region is connected to the source / drain region of the other.
The drain region is connected to one source / drain region of the read transistor TR _R. More specifically, the other source / drain region of the detecting transistor TR _S and one source / drain region of the reading transistor TR _R occupy one source / drain region. Further, the other source / drain region of the read transistor TR _R is connected to the bit line BL through the contact hole 15, and further the common first electrode (common node CN or write transistor TR _W). One of the source / drain regions) is connected to the gate electrode of the detection transistor TR _S via the contact hole 18D provided in the opening and the word line WL _S. The word line WL _W connected to the gate electrode of the writing transistor TR _W and the word line WL _R connected to the gate electrode of the reading transistor TR _R are connected to the word line decoder / driver WD. On the other hand, each plate line PL _m is connected to the plate line decoder / driver PD. Further, the bit line BL is connected to the sense amplifier SA.

When reading data from the memory cell MC ₁ of this nonvolatile memory, V _{cc is applied} to the selected plate line PL _1.
Is applied. At this time, if data “1” is stored in the selected memory cell MC ₁ , polarization inversion occurs in the ferroelectric layer, the amount of accumulated charge increases, and the potential of the common node CN rises. On the other hand, if the data “0” is stored in the selected memory cell MC ₁ , polarization inversion does not occur in the ferroelectric layer and the potential of the common node CN hardly rises. That is, since the common node CN is coupled to the plurality of non-selected plate lines PL _j via the ferroelectric layer of the non-selected memory cell, the potential of the common node CN is kept at a level relatively close to 0 volt. Be drunk In this way, the selected memory cell MC ₁
The potential of the common node CN changes depending on the data stored in. Therefore, a sufficient electric field for polarization reversal can be applied to the ferroelectric layer of the selected memory cell. Then, the bit line BL is brought into a floating state and the reading transistor TR _R is turned on. On the other hand, due to the potential generated at the common first electrode (common node CN) based on the data stored in the selected memory cell MC ₁ , the detection transistor TR is detected.
The operation of _S is controlled. Specifically, the selected memory cell M
If a high potential is generated on the common first electrode (common node CN) based on the data stored in C ₁ , the detection transistor TR _S becomes conductive and the detection transistor TR _S
Since one of the source / drain regions is connected to a wiring having a predetermined potential V _cc , current flows from the wiring to the bit line BL via the detection transistor TR _S and the reading transistor TR _R , and the bit The potential of the line BL rises. That is, the potential change of the common first electrode (common node CN) is detected by the signal detection circuit, and the detection result is transmitted to the bit line BL as a voltage (potential). Here, if the threshold of the detection transistor TR _S is V _th and the potential of the gate electrode of the detection transistor TR _S (that is, the potential of the common node CN) is V _g , the potential of the bit line BL is approximately (V _g −V _th ). If the detection transistor TR _S is a depletion type NMOSFET, the threshold value V _th has a negative value. As a result, the bit line B
It is possible to secure a stable sense signal amount regardless of the load of L. The detection transistor TR _S is connected to the PMOSF
It can also consist of an ET.

The predetermined potential of the wiring to which one end of the detection transistor is connected is not limited to V _cc and may be grounded, for example. That is, the predetermined potential of the wiring to which one end of the detection transistor is connected may be 0 volt.
However, in this case, when the potential (V _cc ) appears on the bit line when reading the data in the selected memory cell, the potential of the bit line is set to 0 volt when rewriting, and 0 when reading the data in the selected memory cell. When the volt appears on the bit line, it is necessary to set the potential of the bit line to V _cc when rewriting. To this end, transistors TR _IV-1 , TR _IV-2 , TR as illustrated in FIG. 28 are used.
A kind of switch circuit (inversion circuit) composed of _IV-3 and TR _IV-4 is arranged between bit lines, and when reading data, the transistors TR _IV-2 and TR _IV-4 are turned on,
When data is rewritten, the transistors TR _IV-1 , T
R _IV-3 may be turned on.

The capacitor structure of the non-volatile memory of the present invention has a nonvolatile memory using a ferroelectric layer (so-called FERA).
Not only M) but also DRAM can be applied. In this case, only the paraelectric field response of the ferroelectric layer (response without inversion of the ferroelectric dipole) is used.

[0140]

According to the present invention, since the connection portion for electrically connecting one of the source / drain regions and the first electrode is formed in the step after the ferroelectric layer is formed,
Mutual diffusion does not occur even by the oxidation heat treatment at a high temperature when forming the ferroelectric layer, and it is possible to reliably prevent the reliability of the nonvolatile memory from decreasing.
Further, the first conductive material forming the first electrode does not need to have an oxygen barrier property, and any material that is stable in a high temperature oxidizing atmosphere may be used. Platinum, an oxide having a perovskite structure, or the like can be used as the first material. It becomes possible to form a ferroelectric thin film which is easily affected by the underlying layer with good controllability.

Further, in the conventional stack type non-volatile memory, due to the problem of heat resistance of the material, sufficient characteristics cannot be given to the memory cell, and it is necessary to judge information when miniaturizing the memory cell. In the present invention, the problem that the required signal amount cannot be secured can be reliably avoided because the characteristics of the memory cell can be maximized. Further, in the non-volatile memory, by adopting the first to fourth configurations, it is possible to achieve higher integration.

[Brief description of drawings]

FIG. 1 is a schematic partial cross-sectional view when a ferroelectric non-volatile semiconductor memory according to a first embodiment of the invention is cut along a virtual vertical plane parallel to a direction in which a bit line extends.

FIG. 2 is a conceptual circuit diagram of a nonvolatile memory according to a second aspect of the present invention.

FIG. 3 is a more specific circuit diagram of the conceptual circuit diagram shown in FIG.

FIG. 4 is a more specific circuit diagram of the conceptual circuit diagram shown in FIG.

FIG. 5 is a schematic partial cross-sectional view of a semiconductor substrate or the like for explaining the method of manufacturing the ferroelectric non-volatile semiconductor memory according to the first embodiment of the invention.

FIG. 6 is a schematic partial cross-sectional view of the semiconductor substrate or the like for explaining the method for manufacturing the ferroelectric non-volatile semiconductor memory according to the first embodiment of the invention, following FIG. 5;

7 is a schematic partial cross-sectional view of a semiconductor substrate or the like for explaining the method of manufacturing the ferroelectric non-volatile semiconductor memory according to the first embodiment of the present invention, following FIG.

FIG. 8 is a schematic partial cross-sectional view of the semiconductor substrate or the like for explaining the manufacturing method of the ferroelectric non-volatile semiconductor memory according to the first embodiment of the invention, following FIG. 7;

9 is a schematic partial cross-sectional view of the semiconductor substrate or the like for explaining the method of manufacturing the ferroelectric non-volatile semiconductor memory according to the first embodiment of the present invention, following FIG. 8;

FIG. 10 is a schematic partial cross-sectional view of the semiconductor substrate or the like for explaining the manufacturing method of the ferroelectric non-volatile semiconductor memory according to the first embodiment of the invention, following FIG. 9;

FIG. 11 is a schematic partial cross-sectional view when a modification of the ferroelectric non-volatile semiconductor memory according to the first embodiment of the present invention is cut along a virtual vertical plane parallel to the extending direction of the bit line.

FIG. 12 is a schematic partial cross-sectional view when the ferroelectric non-volatile semiconductor memory according to the second embodiment of the invention is cut along a virtual vertical plane parallel to the extending direction of bit lines.

FIG. 13 is a schematic partial cross-sectional view of a semiconductor substrate or the like for explaining the method of manufacturing the ferroelectric non-volatile semiconductor memory according to the third embodiment of the invention.

FIG. 14 is a schematic partial cross-sectional view of the semiconductor substrate etc. for explaining the method for manufacturing the ferroelectric non-volatile semiconductor memory according to the third embodiment of the invention, following FIG. 13;

FIG. 15 is a schematic partial cross-sectional view of the semiconductor device including the ferroelectric non-volatile semiconductor memory according to the fourth embodiment of the present invention, taken along a virtual vertical plane parallel to the extending direction of a bit line.

FIG. 16 is a conceptual circuit diagram of a nonvolatile memory according to a third aspect of the present invention.

17 is a more specific circuit diagram of the conceptual circuit diagram shown in FIG.

FIG. 18 is a more specific circuit diagram of the conceptual circuit diagram shown in FIG.

FIG. 19 is a schematic partial cross-sectional view of a semiconductor device including a ferroelectric non-volatile semiconductor memory according to a fifth embodiment of the present invention, taken along a virtual vertical plane parallel to a direction in which a bit line extends.

FIG. 20 is a conceptual circuit diagram of a nonvolatile memory according to a fourth aspect of the present invention.

FIG. 21 is a more specific circuit diagram of the conceptual circuit diagram shown in FIG. 20.

FIG. 22 is a schematic partial cross-sectional view showing a modification of the ferroelectric non-volatile semiconductor memory described in the fourth embodiment of the invention.

23 is a circuit diagram of the ferroelectric non-volatile semiconductor memory shown in FIG.

FIG. 24 is a circuit diagram of a gain cell type ferroelectric non-volatile semiconductor memory.

FIG. 25 is a layout diagram of the ferroelectric non-volatile semiconductor memory shown in FIG. 24.

FIG. 26 is a schematic partial cross-sectional view of the ferroelectric non-volatile semiconductor memory shown in FIG.

27 is a schematic partial cross-sectional view of the ferroelectric non-volatile semiconductor memory shown in FIG. 24 when seen in a cross section different from FIG. 26.

FIG. 28 is a circuit diagram showing a type of switch circuit arranged between bit lines when a predetermined potential of a wiring connected to one end of a detection transistor is set to 0 volt.

FIG. 29 is a schematic partial cross-sectional view when the present invention is applied to a stack type ferroelectric non-volatile semiconductor memory.

FIG. 30 is a PE hysteresis loop diagram of a ferroelectric substance.

FIG. 31 is a circuit diagram of a ferroelectric non-volatile semiconductor memory disclosed in US Pat. No. 4,873,664.

FIG. 32 is a schematic partial cross-sectional view of a conventional stacked ferroelectric non-volatile semiconductor memory.

FIG. 33 is a schematic partial sectional view of a conventional planar ferroelectric non-volatile semiconductor memory.

[Explanation of symbols]

10 ... Silicon semiconductor substrate, 11 ... Element isolation region, 12 ... Gate insulating film, 13 ... Gate electrode,
14A, 14B ... Source / drain regions, 15 ...
・ Contact holes, 16, 116A, 116B ...
Insulating layer, 16A, 26A ... Laminated film, 16B, 26B
... SiO ₂ film, 17, 27, 40 ... opening, 1
8, 118, 28, 41 ... Connection hole, 18A, 118
A, 28A ... Connection hole tops 21, 21A, 21
B, 31, 31, 31A, 31B ... First electrode, 22,
22A, 22B, 32, 32A, 32B ... Ferroelectric layer, 23, 33 ... Second electrode, 25 ... Pad portion, 26 ... Interlayer insulating layer, 36A, 226A ... Passivation Layer, 42 ... Intermediate wiring layer, TR ...
Selection transistor, TR _W ... Writing transistor, TR _R ... Reading transistor, TR _S ... Detection transistor, TR _SW ... Switching transistor, WL ... Word line, BL ... Bit lines, P
L ... Plate line, WD ... Word line decoder / driver, SA ... Sense amplifier, PD ... Plate line decoder / driver, CN ... Common node

Claims (14)

[Claims] 1. A selection transistor which is formed on a semiconductor substrate and has a source / drain region and a gate electrode, and a first transistor which is formed above the selection transistor on an insulating layer. Method of manufacturing a ferroelectric non-volatile semiconductor memory having an electrode, a ferroelectric layer formed on at least the first electrode, and a memory cell formed of a second electrode formed on the ferroelectric layer Where (a) a step of forming a selection transistor, (b) a step of forming an insulating layer on the entire surface, (c) a step of forming a patterned first electrode on the insulating layer, (d) a step of forming a ferroelectric layer on at least the first electrode, (e) a step of forming a connecting portion that electrically connects one source / drain region and the first electrode, (f) ) Forming a second electrode on the ferroelectric layer A method of manufacturing a ferroelectric non-volatile semiconductor memory, comprising: 2. The connecting portion comprises a connecting hole formed in the insulating layer and a top portion of the connecting hole extending to a side portion or a top surface of the first electrode. 7. A method for manufacturing a ferroelectric non-volatile semiconductor memory according to. 3. The insulating layer has a structure in which a lower insulating layer and an upper insulating layer are laminated, and in the step (b), after the lower insulating layer is formed on the entire surface, one layer is formed on the lower insulating layer. Forming an intermediate wiring layer electrically connected to the source / drain regions, and then forming an upper insulating layer on the lower insulating layer and the intermediate wiring layer. In the step (e), one of A connection part for electrically connecting the intermediate wiring layer and the first electrode is formed instead of forming a connection part for electrically connecting the source / drain region and the first electrode. Item 2. A method of manufacturing a ferroelectric non-volatile semiconductor memory according to Item 1. 4. An electrical connection between one of the source / drain regions and the intermediate wiring layer is made by a first connection hole formed in the lower insulating layer, and the connecting portion is formed in the upper insulating layer. Second connection hole,
4. The method for manufacturing a ferroelectric non-volatile semiconductor memory according to claim 3, further comprising a top portion of the second connection hole extending to a side portion or a top surface of the first electrode. 5. A bit line, a memory unit composed of M (where M ≧ 2) memory cells, and M plate lines are further provided, and the memory unit is formed on an insulating layer. , In the memory unit, the first electrode of the memory cell is common, and the common first electrode is connected to the bit line through the selection transistor, and in the memory unit, the m-th electrode (where m = 1,2
The second electrode of the memory cell (..., M) is connected to the m-th plate line.
5. A method for manufacturing a ferroelectric non-volatile semiconductor memory according to claim 4. 6. A bit line, N (where N ≧ 2) memory units each consisting of M (where M ≧ 2) memory cells, and M × N plate lines, Further, the memory unit of the first layer is formed on the insulating layer, N memory units are stacked via the interlayer insulating layer, and in each memory unit, the first memory cell of the memory cell is formed. The electrodes are common, and the common first electrode is connected to the bit line via the selection transistor, and in the n-th layer (where n = 1, 2, ..., N) memory unit, M-th (however, m = 1, 2 ...
The second electrode of the M) th memory cell is the [(n-1) M +
5. The method for manufacturing a ferroelectric non-volatile semiconductor memory according to claim 1, wherein the ferroelectric non-volatile semiconductor memory is connected to the [m] th plate line. 7. A bit line, N (where N ≧ 2) memory units each consisting of M (where M ≧ 2) memory cells, and M plate lines. In addition, N selection transistors are provided, the first-layer memory unit is formed on an insulating layer, and the N memory units are stacked via an interlayer insulating layer. In each memory unit, The first electrode of the memory cell is common, and the common first electrode of the memory unit of the nth layer (where n = 1, 2, ..., N) is the nth selection transistor. Connected to the bit line via the m-th (in the n-th layer memory unit)
The second electrode of the memory cell of m = 1, 2 ..., M) is
5. The method for manufacturing a ferroelectric non-volatile semiconductor memory according to claim 1, wherein the ferroelectric memory is connected to a m-th plate line that is common to the memory units. 8. N memory units each consisting of N (where N ≧ 2) bit lines, M (where M ≧ 2) memory cells, and M plate lines. , N selection transistors are provided, the first-layer memory unit is formed on an insulating layer, and the N memory units are stacked via an interlayer insulating layer. In the unit, the first electrode of the memory cell is common, and the common first electrode in the memory unit of the nth layer (where n = 1, 2, ..., N) is the nth selection. Is connected to the n-th bit line via the transistor for data transfer, and in the memory unit of the n-th layer, the m-th (however,
The second electrode of the memory cell of m = 1, 2 ..., M) is
5. The method for manufacturing a ferroelectric non-volatile semiconductor memory according to claim 1, wherein the ferroelectric memory is connected to a m-th plate line that is common to the memory units. 9. (A) A selection transistor formed on a semiconductor substrate and provided with source / drain regions and a gate electrode; and (B) a first selection transistor formed above the selection transistor with an insulating layer interposed therebetween. A ferroelectric non-volatile semiconductor memory comprising: an electrode; a ferroelectric layer formed on at least the first electrode; and a memory cell including a second electrode formed on the ferroelectric layer. A source / drain region and a first electrode of one of the selection transistors, a connection hole formed in the insulating layer, and a first electrode
2. A ferroelectric non-volatile semiconductor memory, which is electrically connected via a top portion of the connection hole extending to a side portion or a top surface of the electrode. 10. (A) A source / source formed on a semiconductor substrate.
A selection transistor having a drain region and a gate electrode; and (B) a first electrode formed above the selection transistor with an insulating layer interposed therebetween, and a ferroelectric formed at least on the first electrode. A ferroelectric non-volatile semiconductor memory having a layer and a memory cell including a second electrode formed on the ferroelectric layer, wherein the insulating layer is formed by laminating a lower insulating layer and an upper insulating layer. The intermediate wiring layer is formed on the lower insulating layer, and one source / drain region of the selection transistor and the intermediate wiring layer are formed through the first connection hole formed in the lower insulating layer. The first electrode and the intermediate wiring layer are electrically connected to each other, and the second connection hole formed in the upper insulating layer and the second electrode extending to the side portion or the top surface of the first electrode. That it is electrically connected through the top of the connection hole Ferroelectric-type nonvolatile semiconductor memory to the butterflies. 11. A bit line, a memory unit composed of M (where M ≧ 2) memory cells, and M plate lines, the memory unit being formed on an insulating layer. , In the memory unit, the first electrode of the memory cell is common, and the common first electrode is connected to the bit line through the selection transistor, and in the memory unit, the m-th electrode (where m = 1,2
..., M), the second electrode of the memory cell is connected to the m-th plate line.
Alternatively, the ferroelectric non-volatile semiconductor memory according to claim 10. 12. A bit line, N (where N ≧ 2) memory units each consisting of M (where M ≧ 2) memory cells, and M × N plate lines, Further, the memory unit of the first layer is formed on the insulating layer, N memory units are stacked via the interlayer insulating layer, and in each memory unit, the first memory cell of the memory cell is formed. The electrodes are common, and the common first electrode is connected to the bit line via the selection transistor, and in the n-th layer (where n = 1, 2, ..., N) memory unit, M-th (however, m = 1, 2 ...
The second electrode of the M) th memory cell is the [(n-1) M +
The ferroelectric non-volatile semiconductor memory according to claim 9 or 10, wherein the ferroelectric non-volatile semiconductor memory is connected to the (m) th plate line. 13. A bit line, N (provided that N ≧ 2) memory units, each of which is composed of M (provided that M ≧ 2) memory cells, and M plate lines. In addition, N selection transistors are provided, the first-layer memory unit is formed on an insulating layer, and the N memory units are stacked via an interlayer insulating layer. In each memory unit, The first electrode of the memory cell is common, and the common first electrode of the memory unit of the nth layer (where n = 1, 2, ..., N) is the nth selection transistor. Connected to the bit line via the m-th (in the n-th layer memory unit)
The second electrode of the memory cell of m = 1, 2 ..., M) is
The ferroelectric non-volatile semiconductor memory according to claim 9 or 10, wherein the ferroelectric memory is connected to an m-th plate line shared by the memory units. 14. N (where N ≧ 2) bit lines, N (where M ≧ 2) memory cells each consisting of N memory units, and M plate lines. , N selection transistors are provided, the first-layer memory unit is formed on an insulating layer, and the N memory units are stacked via an interlayer insulating layer. In the unit, the first electrode of the memory cell is common, and the common first electrode in the memory unit of the nth layer (where n = 1, 2, ..., N) is the nth selection. Is connected to the n-th bit line via the transistor for data transfer, and in the memory unit of the n-th layer, the m-th (however,
The second electrode of the memory cell of m = 1, 2 ..., M) is
The ferroelectric non-volatile semiconductor memory according to claim 9 or 10, wherein the ferroelectric memory is connected to an m-th plate line shared by the memory units.