JP2000269470A - Nonvolatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance the reliability of cells which tends to deteriorate while making them fine in an electrically erasable and programmable read-only memory(EEPROM) for writing and erasing data. SOLUTION: This memory has first cell areas 31a, where a tunnel oxide film 31-5a of cells is set at 80 Å thick and second cell areas 31b where a tunnel oxide film 31-5b of cells is set at 120 Åthick, thus constituting a memory cell array 31. The first cell areas 31a are allotted for storing data which are requested to be written at high speed, and the second cell areas 31b are allotted for storing data needed to be held over a long period. This provides a constitution which ensures both a high-speed operability with data write characteristics and a long reliability of data holding characteristics.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device having a stacked gate structure in which a control gate is stacked on a floating gate as a charge storage layer.
E using a memory cell capable of electrically rewriting data
EPROM (Electrically Erasable and Programmable
Read Only Memory) or 2 per memory cell
The present invention relates to a multi-valued memory capable of storing more than one data.

[0002]

2. Description of the Related Art Conventionally, as a nonvolatile semiconductor memory device, for example, an EEPROM for electrically writing and erasing data has been known. This EEPROM is
In recent years, it has attracted attention as a storage device for small portable terminals such as digital cameras and mobile phones, and as a storage medium for music instead of a compact disk, and has been put into practical use.

As described above, in order to reduce the cost of the conventional EEPROM for practical use, a small area and a large capacity (high integration) are being advanced year by year by miniaturization of cells. However, on the other hand, reliability problems have become more prominent.

That is, as the miniaturization of the cell progresses and, for example, the gate length of the memory cell becomes shorter, the characteristics of the memory cell due to the deterioration of the film quality of the insulating film (tunnel oxide film) at the gate end are affected. The effect becomes more pronounced. As a result, the long-term reliability of the data retention characteristics of the memory cell due to data rewriting deteriorates.

Although such a problem can be improved to some extent by reducing contamination and reducing damage in a cell manufacturing process, it essentially hinders miniaturization.

[0006] With the demand for lowering the operating voltage due to the miniaturization of cells, it is essential to make the tunnel oxide film thinner. Therefore, problems such as deterioration of data retention characteristics and read disturb due to thinning of the tunnel oxide film also arise.

[0007] Even now, the reliability requirements for memory cells are very strict. For example, as a music specification, the number of rewrites is 30,000, and the data retention time after the rewrite is 10 years (−25 ° C.). (Under storage temperature of ~ 85 ° C)
It has become.

[0008] Such specifications can be easily realized with, for example, a 64 megabit (Mbit) NAND memory. In the case of this memory, the gate length is relatively long at 0.36 μm, the thickness of the tunnel oxide film is as large as about 100 Å, and the selective oxidation method (LOC) is used for element isolation.
The reason is that the manufacturing process can be shortened due to the use of OS).

However, in the case of a 256-Mbit NAND memory as an example, the gate length is 0.20 μm, the thickness of the tunnel oxide film is about 80 Å, and the STI (Shallow Trench Isolation) structure is used for element isolation. The manufacturing process is very long,
It is becoming difficult to satisfy the above specifications. Therefore, in a memory of 1 gigabit (Gbit) or later, it is certain that the above-mentioned specifications will be more severely realized.

In addition, a reduction in the gate length and a reduction in the thickness of the tunnel oxide film lower the neutral threshold voltage of the memory cell. This also becomes a factor of deteriorating the data retention characteristics of the memory cell.

That is, the lowering of the neutral threshold value means that when there is a memory cell having a high write threshold value, the threshold value fluctuation greatly increases while the memory cell is left or data is read. It means becoming. This becomes very important especially in a so-called multi-value memory in which four or more data are stored in one memory cell.

In a multi-valued memory, data is usually divided into a plurality of data in a range where the threshold value is higher than a neutral threshold value. Therefore, as the number of divisions of the data increases, the maximum value of the threshold value of the stored data increases, and the influence of the decrease in the neutral threshold value becomes more remarkable.

Furthermore, the problem of cell reliability degradation due to miniaturization also depends on the number of data rewrites.

FIG. 8 schematically shows a cell structure of a memory (for example, an EEPROM) in which data writing and erasing operations are performed by injecting and discharging electrons into and from a floating gate by Fowler-Nordheim (FN) tunnel current. It is shown.

In this case, a drain 102 and a source 103 are formed on the main surface of a well region (or silicon substrate) 101. The drain 102
A thin insulating film (tunnel oxide film) 105 is provided on channel 104 between source 103 and source 103. On the tunnel oxide film 105, a floating gate 106, an inter-gate insulating film 107, and
The control (control) gate 108 is laminated. Note that the periphery of the floating gate 106 and the control gate 108 is covered with an oxide film 109.

A data write operation and an erase operation (so-called data rewrite) to the cell are performed by passing a current through the tunnel oxide film 105.
For example, data is written by flowing a current through tunnel oxide film 105 and injecting electrons into floating gate 106. Further, data is erased by flowing a current through the tunnel oxide film 105 and discharging electrons in the floating gate 106.

However, as described above, in the case of a cell in which the data writing operation and the erasing operation are performed by injecting and discharging electrons into and from the floating gate 106 by the FN tunnel current, the control gate 108 or the well region 101
It is necessary to apply a high voltage (about 18V). Therefore, a high electric field is applied to the tunnel oxide film 105 and the inter-gate insulating film 107 at the time of data write operation and data erase operation. Therefore, an increase in the number of times of data rewriting is caused by the increase in the tunnel oxide film 105 and the
As a result of increasing the stress applied to the gate insulating film 7, the tunnel oxide film 105 and the inter-gate insulating film 107 are degraded, and the reliability of the cell is reduced.

FIG. 9 shows the gate length dependence of the write characteristics and erase characteristics of the above cell. Here, under the same conditions (voltage and time are constant),
The relationship between the threshold voltage (Vth) of the cell and the gate length (L) when writing and erasing are performed is shown.

In the erase operation, the threshold voltage Vth of the cell hardly depends on the gate length.

On the other hand, in a write operation, the threshold voltage Vth of the cell decreases as the gate length L decreases. The threshold voltage Vth appears to decrease because the short channel effect appears with the miniaturization of the gate length L and the decrease in the coupling ratio due to bird's beak at the gate end 201 (see FIG. 8) The shorter the length L, the better the effect, so that the effect of making writing difficult is added.

Further, as the size of the cell is reduced, the capacitance between the adjacent word line (control gate) and the capacitance between the diffusion layer (drain / source) and the selected word line is a factor that lowers the coupling ratio. It is also known that it has become.

In the erasing operation, the fact that the threshold voltage Vth of the cell does not depend on the gate length is recognized because the short channel effect and the effect that the erasing becomes difficult due to the decrease in the coupling ratio cancel each other. It is.

As described above, the worsening of the write characteristics due to the short channel effect of the memory cell as the gate length becomes shorter means that the neutral threshold value is lowered as the semiconductor device is miniaturized. As described above, a decrease in the neutral threshold value has an adverse effect on not only a memory storing binary data but also a multi-valued memory having four or more values.

In a multi-valued memory, there is a limit in narrowing the distribution width of the threshold value, so that the data having the highest threshold value is considerably larger than that of the binary value. For example,
In the case of a NAND-type memory cell, the maximum value of the threshold value is about 1.5 V in the case of binary, while it is about 3.5 V in the case of four values.

Therefore, the difference between the neutral threshold value and the distribution of the threshold value becomes very large, and there is a problem that data is changed while the apparatus is left unattended. in this case,
With miniaturization, it is necessary to increase the channel implantation in order to cancel the effect, but this is not a fundamental solution because it may cause a problem such as erroneous writing.

In addition, when the gate length is short, the influence of the gate edge, which may significantly deteriorate the reliability at the time of data rewriting, appears more remarkably than when the gate length is long, and the data retention characteristic is reduced. It is known that it deteriorates.

This means that simply shortening the gate length of a cell with miniaturization of the cell causes a significant deterioration in the reliability of the cell as the number of data rewrites increases.

However, when comparing the area of the cells, the cell having the gate length of 0.4 μm has twice the area of the cell having the gate length of 0.2 μm. Therefore, simply increasing the gate length hinders miniaturization, not only increasing the area of the array, but also reducing the capacitance per unit area.

As described above, the conventional memory cell can be miniaturized (smaller area) by shortening the gate length. However, as the miniaturization progresses, there is a concern that the reliability is deteriorated. There was a problem that it hindered commercialization.

As a conventional idea, such a problem is that the reliability specification of the memory cell is uniformly given to all the memory cells on the array, and the rewriting operation is performed. This is because the voltage and the operation circuit are uniform, and the manufacturing parameters such as the tunnel oxide film and the gate length of the memory cell are also given uniformly.

For example, in a conventional memory cell, 256
In the case of an M-bit NAND memory, the reliability of all the 256-Mbit memory cells has been simultaneously improved, and the operation and the purpose of the memory cell of any bit have been manufactured without being divided.

[0032]

As described above, conventionally, by shortening the gate length and the thickness of the tunnel oxide film, the memory cell can be miniaturized (smaller area), the voltage can be reduced, and the speed can be increased. Although it can work,
Since the reliability specifications of all memory cells on the array were uniform, as miniaturization progressed, there was a concern that the reliability of memory cells would deteriorate, which would hinder commercialization. Was.

Accordingly, it is an object of the present invention to provide a nonvolatile semiconductor memory device that can improve the reliability of memory cells due to miniaturization and is useful for commercialization.

Furthermore, it is an object of the present invention to provide a nonvolatile memory which can achieve both high-speed operation of data writing characteristics and long-term reliability of data holding characteristics, and can realize a more reliable miniaturized product. It is to provide a semiconductor memory device.

Another object of the present invention is to realize a highly reliable miniaturized product which satisfies the data holding characteristic for rewriting a small number of data and the data holding characteristic for a large number of data rewrites. It is an object of the present invention to provide a possible nonvolatile semiconductor memory device.

[0036]

In order to achieve the above object, a nonvolatile semiconductor memory device according to the present invention comprises:
In a data-writable device, a memory cell array including a plurality of memory cells has a plurality of regions in which the tunnel oxide film thicknesses of the memory cells are different from each other.

In the nonvolatile semiconductor memory device according to the present invention, the data can be rewritten.
In a memory cell array including a plurality of memory cells, a plurality of cell blocks having different gate lengths of the memory cells are present.

According to the nonvolatile semiconductor memory device of the present invention, the memory cell array can be divided into cells holding data that need to be held for a long period and cells not holding the data without increasing the area of the array. Configurable.
This makes it possible to effectively store data that needs to be held for a long time and data that needs to be written at high speed.

According to the nonvolatile semiconductor memory device of the present invention, data can be written in a cell having a large number of data rewrites at a lower voltage while minimizing an increase in the area of the array. become. As a result, it is possible to reduce the voltage stress applied to the tunnel oxide film and the inter-gate insulating film due to the increase in the number of times of data rewriting of a cell where the number of times of data rewriting is large.

[0040]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows a schematic configuration of a nonvolatile semiconductor memory device according to a first embodiment of the present invention, taking an EEPROM as an example. Here, a case will be described in which the thickness of the tunnel oxide film is changed for each block so that both high-speed operation of data writing characteristics and long-term reliability of data retention characteristics can be achieved.

In the case of this EEPROM, the row address input is supplied to a row address buffer 11 and stored in the buffer 11. The row address input stored in the buffer 11 is supplied to a row decoder 21.

The row decoder 21 includes, for example, a first row decoder 21a and a second row decoder 21b.

The first row decoder section 21a includes, for example,
High-speed storage of data in a memory cell array 31 composed of a plurality of rows and columns in which data is frequently rewritten and long-term reliability of data retention characteristics may be slightly reduced.
A row decoder (not shown) as a decoder circuit is provided for each of the word lines WLa1 to WLan corresponding to each row in the cell area (first region) 31a.

Each row decoder of the first row decoder section 21a sets a selected state to a selected row and a non-selected state to a non-selected row when active (when a chip is selected) according to the row address input. In a standby state (when a chip is not selected), a non-selected state is applied to all rows.

Also, at the time of data write operation (or
At the time of the erase operation), the first voltage V1 (for example, 16 V) from the first power supply Vcc1 is applied to the word lines WLa1 to WLan, respectively, and the write voltage (or
(Erasing voltage).

The second row decoder section 21b includes, for example,
Regarding each row of the second cell area (second area) 31b that can guarantee long-term reliability with respect to data retention characteristics, regardless of the number of data rewrites, of the memory cell array 31 including a plurality of rows and columns. Word lines WLb1 to WL
A row decoder (not shown) as a decoder circuit is provided for each bn.

Each row decoder of the second row decoder section 21b gives a selected state to a selected row and a non-selected state to a non-selected row at the time of active, and all the rows at the time of standby in response to the row address input. Rows are given a non-selected state.

Also, at the time of data write operation (or
At the time of the erasing operation), the second voltage higher than the first voltage V1 is applied to the word lines WLb1 to WLbn.
The second voltage V2 from the power supply Vcc2 (for example, 18
V) as a write voltage (or erase voltage).

On the other hand, the column address input is supplied to a column address buffer 41 and stored in the buffer 41. The column address input stored in the buffer 41 is supplied to the column decoder 51.

The column decoder 51 selects one of the bit lines BL corresponding to each column of the memory cell array 31 composed of a plurality of rows and columns via a column selection circuit 61. For example, in response to the above column address input, a selected state is given to a selected column, a non-selected state is given to a non-selected column when active, and a non-selected state is given to all columns during standby. .

An I / O buffer 81 is further connected to the column selection circuit 61 via a sense amplifier 71 to input / output data to / from the memory cell array 31, that is, an active state. Reading of data from the memory cells corresponding to the rows and columns, which are sometimes selected, is performed.

The memory cell array 31 basically has a well-known configuration in which memory cells are arranged at intersections of rows (word lines) and columns (bit lines). The configuration of the cell is basically the same as the conventional one (see FIG. 8), and the specific configuration will be described later.

FIG. 2 shows a schematic configuration of the memory cell array 31.

The memory cell array 31 includes, for example, a first cell area 31a in which a plurality of memory cells having a first oxide film thickness Da are arranged in a matrix,
A plurality of memory cells having a second oxide film thickness Db, which is greater than the oxide film thickness Da, are arranged in a matrix.
The cell area 31b is arranged in blocks.

That is, the memory cell array 31
In the first embodiment, a drain 31-2 and a source 31-3 are selectively formed on the main surface of a well region (or silicon substrate) 31-1.

A channel 31-4 between the drain 31-2 and the source 31-3 in the first cell area 31a.
A first tunnel oxide film 31-5a having a first oxide film thickness Da is provided thereon as an ordinary thin tunnel oxide film. Then, the first tunnel oxide film 31
-5a, a floating gate 31-6, an inter-gate insulating film 31-7, and a control (control) gate 31-8 are stacked.

In the second cell area 31b, on the channel 31-4 between the drain 31-2 and the source 31-3, the second tunnel oxide film 31-5a, which is thicker than the first tunnel oxide film 31-5a, is formed. A second tunnel oxide film 31-5b having an oxide film thickness Db is provided. The floating gate 31-6, the inter-gate insulating film 31-7, and the control gate 31-8 are stacked on the second tunnel oxide film 31-5b.

The surroundings of the floating gate 31-6 and the control gate 31-8 are covered with an oxide film 31-9.

As described above, conventionally, in all areas,
While the thickness of the tunnel oxide film of each memory cell is substantially constant, the memory cell array 31 has two areas 31.
This embodiment is characterized in that a plurality of memory cells having different thicknesses of the tunnel oxide film are arranged in blocks for each of the areas 31a and 31b.

In this case, the first cell area 31a has a first oxide film thickness Da (for example, suitable for frequent rewriting of data or high-speed rewriting of data, although the long-term reliability of the data holding characteristic is lowered). (About 80 angstroms). As a result, the word lines WLa1 to WLan in the first cell area 31a are each formed with the first tunnel oxide film 31-5a of about 80 Å.

On the other hand, the second cell area 31b is not suitable for high-speed rewriting or frequent rewriting of data, but is thick and second enough to obtain sufficient long-term reliability with respect to data retention characteristics. It is formed by a plurality of memory cells having an oxide film thickness Db (for example, approximately 120 Å). Thus, the word lines WLb1 to WLbn in the second cell area 31b are set.
Are formed with a second tunnel oxide film 31-5b of about 120 angstroms.

As described above, the thickness (Db) of the tunnel oxide film 31-5b of each cell in a part of the area 31b in the memory cell array 31 is changed by the tunnel oxidation of each cell in the other area 31a. By making the film 31-5a thicker than the thickness (Da) of the film 31-5a, the data retention characteristics of the cells in the area 31b and the resistance to the voltage stress applied to the gate at the time of reading are improved for each cell in the area 31a. It is possible to increase. Therefore, as compared with the cells in the area 31a, the increase in the leak current and the decrease in the neutral threshold of each cell in the area 31b due to the thinning of the tunnel oxide film can be suppressed.

As a result, one memory cell array 31
Of the upper areas 31a and 31b, for example, the area 31a is an area which is superior to the area 31b in terms of data writing characteristics and high-speed operation, and the area 31b is an area 3
It can be an area that is more excellent in long-term reliability of holding characteristics than 1a. Therefore, in each area 31a, 31b,
The data can be stored as appropriate according to the manufacturer or the user's request, depending on the type and importance of the data.

The area 31a is excellent in high-speed operability of data rewriting characteristics. For example, the area 31a is used mainly for temporary storage of data of a computer, voice,
It is used for storing data that requires a high rewriting speed and that is frequently rewritten, such as music and image data.

The area 31b has excellent data retention characteristics and resistance to voltage stress. For example, the area 31b can be used by a manufacturer as a program system section, a data management section, a ROM, or the like, or can store valuable data of a user. Used to store.

In each cell in the area 31b, the write / erase time is increased by the thickness of the second tunnel oxide film 31-5b, so that the data rewrite speed is reduced. By increasing the operation specifications, for example, the write / erase voltage, the lowering of the rewriting speed does not matter much.

Further, since the second cell area 31b does not lead to an increase in the area of the memory cell array 31, a high-density miniaturized product can be easily realized, and as the capacity increases, it becomes difficult for manufacturers and users. Very useful.

Next, a method of manufacturing the memory cell array 31 having the above-described configuration will be described with reference to FIG.

Each of the drawings (a) to (e) corresponds to the cross section of FIG. Here, it is assumed that an N-well region is formed on a P-type silicon substrate, and a cell array is formed on a P-type well region provided on the surface of the N-well region.

For example, an N-well region, a P-well region 31-1, and a P-well region 31-1 are formed on the surface of a P-type silicon substrate by a known technique.
After forming an element isolation region, channel implantation is performed on the surface of the P-well region 31-1 to obtain a 10 keV
Boron having a concentration of about 3 × 10 ¹³ / cm ² is introduced by the accelerating voltage.

In addition, a range (second region) corresponding to, for example, the second cell area 31b on the P well region 31-1
Only in the region where the tunnel oxide film 31-5b is formed)
A thermal oxide film 311a having a thickness of about 40 Å is formed (see FIG. 3A).

This is formed by, for example, forming a thermal oxide film on the entire surface and then peeling off the thermal oxide film in a region where the first tunnel oxide film 31-5a is to be formed.

Before forming the thermal oxide film 311a, a thick oxide film for a high voltage transistor of a peripheral circuit is formed on the entire surface, and only the thick oxide film in the cell region is peeled off. You may do it.

Next, a thermal oxide film 311b having a thickness of about 80 Å is formed on the entire surface of the P well region 31-1, and only the thermal oxide film 311b is formed in a range corresponding to the first cell area 31a. In the range corresponding to the second cell area 31b, the thermal oxide film 311
a and a thermal oxide film 311b to form a laminated film having a thickness of about 120 angstroms (see FIG. 3B).

Thus, in the range corresponding to the first cell area 31a, the thermal oxide film 31 serving as the first tunnel oxide film 31-5a having the ordinary thin first oxide film thickness Da is provided.
In the range corresponding to the second cell area 31b, the second tunnel oxide film 31-5b having a second oxide film thickness Db which is thicker than the first tunnel oxide film 31-5a is provided. Laminated film (thermal oxide films 311a and 311b)
Are formed respectively.

Then, 5 × 10 ¹⁹ to 4 × 10 ²⁰
Polysilicon film 3 doped with phosphorus at a concentration of about cm ^-3
12 is deposited to a thickness of about 150 nm.
A resist film (not shown) is applied on the polysilicon film 312, and a stripe-shaped opening groove for separating a floating gate in a bit line direction is formed thereon. Then, using the resist film as a mask, the polysilicon film 312 is etched by RIE (Reactive Ion Etching) or the like to form a floating gate isolation region (not shown) in the bit line direction.

After the resist film is removed, the surface of the polysilicon film 312 is coated with a thermal oxidation method or a CVD (Ch
12 to 20 nm by emical vapor deposition) method
An oxide film 313 having a thickness of about the same is formed.

Further, a polysilicon film 314 doped with phosphorus at a concentration of, for example, about 5 × 10 ¹⁹ to 4 × 10 ²⁰ cm ^{−3 is formed} on oxide film 313 so as to have a thickness of about 350 nm. They are deposited (see FIG. 3C).

Next, on the polysilicon film 314,
In the direction orthogonal to the floating gate isolation region,
A resist pattern 315 for patterning a control gate (word line) is formed (see FIG. 4D). Note that an oxide film serving as a mask material may be formed before this.

Then, using the resist pattern 315 as a mask, the polysilicon film 314 and the oxide film 31 are formed.
3. The polysilicon film 312 and the thermal oxide films 311a and 311b are respectively etched by RIE or the like.

In this way, as shown in FIG. 11E, in a single memory cell array 31,
Each gate electrode 316a, 31 of the memory cell having the first and second tunnel oxide films 31-5a, 31-5b, respectively.
6b is performed simultaneously.

That is, in the first cell area 31a, 8
A gate electrode of a cell, in which a floating gate 31-6, an inter-gate insulating film 31-7, and a control gate 31-8 are sequentially stacked on a first tunnel oxide film 31-5a having a thickness of about 0 Å. 316a are respectively formed.

Similarly, in the second cell area 31b, 12
A gate electrode of a cell, in which a floating gate 31-6, an inter-gate insulating film 31-7, and a control gate 31-8 are sequentially stacked on a second tunnel oxide film 31-5b having a thickness of about 0 Å. 316b are respectively formed.

Thereafter, heat treatment (post-oxidation) is performed in an oxidizing atmosphere to cover the periphery of the gate electrodes 316a and 316b with an oxide film 31-9, and to perform ion implantation to form a drain 31-2 and a source 31-. By forming the diffusion layer 3, the cells having the configuration shown in FIG. 2 are completed in each of the areas 31 a and 31 b.

Although not shown in the drawing, after depositing an interlayer film on the entire surface, a contact hole is opened in the interlayer film, and further, a wiring layer is patterned. The contact hole is filled with W (tungsten) or the like, and the W is
By shaving with a P (Chemical Mechanical Polishing) method or the like, contacts with wirings such as bit lines / source lines are formed. Then, after forming an interlayer insulating film, Al (aluminum) or the like is deposited to perform wiring patterning, and thereafter, an oxide film serving as a passivation film is deposited on the entire surface by a CVD method, whereby the memory cell having the above configuration is formed. The array 31 is manufactured;

Although omitted in the above description, the formation of the peripheral circuits of the memory cell array 31 is performed according to the existing manufacturing process.

According to such a structure, the memory cell array can be constituted by cells holding data that needs to be held for a long term and cells not holding the data without increasing the area of the array. Therefore, various types of data can be stored according to the type and importance of the data according to the manufacturer or user's request.

That is, a single memory cell array is divided into a plurality of areas, and cells in each area are configured by changing the thickness of the tunnel oxide film. As a result, cells that can guarantee long-term reliability with respect to data retention characteristics and cells that can satisfy high-speed operation with respect to data rewrite characteristics can be secured for each area. Therefore, it is possible to effectively store data that needs to be retained for a long period of time and data that needs to be written at a high speed, and it can be highly useful in the future.

Further, the present invention can be easily realized without largely changing the conventional manufacturing process of the EEPROM.

In the first embodiment of the present invention described above, the area where the memory cell having the thin tunnel oxide film is arranged and the area where the memory cell having the thick tunnel oxide film is arranged are divided into blocks. Although the case of forming each of the pages has been described as an example, the invention is not limited to this, and it is also possible to form at least one page or a plurality of columns as a unit.

In this case, although it can be easily implemented by changing the thickness of the tunnel oxide film in the middle of each word line, the write voltage cannot be changed for each area.

However, if each word line is divided so that it can be driven independently, it is also possible to change the write voltage and the like for each area.

It is also possible to change the gate length of the cell for each area. For example, the gate length of a cell having a thick tunnel oxide film may be longer than the gate length of another cell having a thin tunnel oxide film. In this case, the deterioration of the write characteristics due to the short channel effect of the memory cell is reduced, so that the reliability can be further improved.

(Second Embodiment) FIG. 4 shows a schematic configuration of a nonvolatile semiconductor memory device according to a second embodiment of the present invention, taking an EEPROM as an example. Here, a case will be described in which the gate length of the cell is changed for each block so that the data retention characteristic for a small number of data rewrites and the data retention characteristic for a large number of data rewrites can be satisfied. I do.

In the case of this EEPROM, a row address input is supplied to a row address buffer 11 and stored in the buffer 11. The row address input stored in the buffer 11 is supplied to a row decoder 21 '.

The row decoder section 21 'includes, for example, the first
Row decoder section 21a 'and second row decoder section 21b'
It consists of

The first row decoder section 21a 'includes, for example, a memory cell array 31' composed of a plurality of rows and columns.
Of the first cell area (first cell block) 31a 'with relatively few data rewrites, a row decoder (not shown) as a decoder circuit for each word line WLa1' to WLan 'corresponding to each row. ) Are provided.

In response to the row address input, each row decoder of the first row decoder section 21a 'sets a selected state to a selected row and a non-selected state to a non-selected row when active (when a chip is selected). During standby (when a chip is not selected), a non-selected state is applied to all rows.

Also, at the time of data write operation (or
At the time of an erase operation), a first voltage V1 '(for example, 18 V) from a first power supply Vcc1' is applied to the word lines WLa1 'to WLan' with a write voltage (or 18V).
(Erasing voltage).

The second row decoder section 21b 'includes, for example, a memory cell array 31' composed of a plurality of rows and columns.
A row decoder (not shown) as a decoder circuit is provided for each of the word lines WLb1 'to WLbn' corresponding to each row in the second cell area (second cell block) 31b 'where data rewriting is relatively common. ) Are provided.

Each row decoder of the second row decoder section 21b 'gives a selected state to a selected row when active and a non-selected state to non-selected rows in response to the above-mentioned row address input. Row is given a non-selected state.

Also, during a data write operation (or
At the time of the erasing operation), the word lines WLb1 'to WLbn' are supplied to the second voltage lower than the first voltage V1 ', respectively.
Of the second voltage V2 '(for example, 16
V) as a write voltage (or erase voltage).

On the other hand, the column address input is supplied to a column address buffer 41 and stored in the buffer 41. The column address input stored in the buffer 41 is supplied to the column decoder 51.

The column decoder 51 selects one of the bit lines BL corresponding to each column of the memory cell array 31 ′ having a plurality of rows and columns via the column selection circuit 61. For example, according to the column address input, a selected state is given to a selected column, a non-selected state is given to a non-selected column when active, and a non-selected state is given to all columns in a standby state. I have.

An I / O buffer 81 is further connected to the column selection circuit 61 via a sense amplifier 71 to input / output data to / from the memory cell array 31 ', that is, Reading of data from memory cells corresponding to rows and columns, which are selected when active, is performed.

The memory cell array 31 'basically has a well-known structure in which memory cells are arranged at intersections of rows (word lines) and columns (bit lines), respectively. The configuration of each cell is basically the same as the conventional one (FIG. 8).
Reference), and a specific configuration will be described later.

FIG. 5 shows a schematic configuration of the memory cell array 31 '.

The memory cell array 31 'is, for example,
In a part (in this case, an upper part) of a first cell area 31a 'in which a plurality of memory cells having a first gate length La are arranged in a matrix, the first cell area 31a' is longer than the first gate length La. A second cell area 31b 'in which a plurality of memory cells having a second gate length Lb are arranged in a matrix.
Are arranged.

That is, in the prior art, while the gate length of each memory cell is substantially constant in all areas, the memory cell array 31 'is divided into two areas 31a' and 31b '.
This embodiment is characterized in that a plurality of memory cells having different gate lengths are arranged in blocks for each of the areas 31a 'and 31b'.

In this case, the first cell area 31a 'has a first gate length La (for example, approximately 0.2 μm) enough to obtain sufficient reliability for a small number of data rewrites.
m). As a result, each of the word lines WLa1 'to WLan' in the first cell area 31a 'is 0.2 μm
It is formed with a width of the order.

On the other hand, the second cell area 31b 'is formed by a plurality of memory cells having a second gate length Lb, which is sufficient to obtain sufficient reliability for rewriting data many times. In this case, the second gate length Lb
Is approximately 0.4 μm longer than the first gate length La.
It has been. As a result, the word lines WLb1 'to WLbn' in the second cell area 31b '
It will be formed with a width of about 0.4 μm.

Here, the data write characteristic of the memory cell has the gate length dependency (see FIG. 9) as described above. Therefore, the data write voltage differs between the cell having a gate length of 0.4 μm and the cell having a gate length of 0.2 μm. For example, for a cell having a gate length of 0.4 μm,
If data can be written with a write voltage of 16 V, a write voltage of 18 V is required to write data in a cell having a gate length of 0.2 μm.

As described above, during the data write operation,
The voltage stress applied to the tunnel oxide film and the inter-gate insulating film is smaller in a cell having a gate length of 0.4 μm than in a cell having a gate length of 0.2 μm. Further, as the gate length becomes longer, the deterioration of the write characteristics due to the short channel effect of the memory cell is reduced. Therefore, it can be said that a cell having a gate length of 0.4 μm has higher reliability with an increase in the number of times of data rewriting than a cell having a gate length of 0.2 μm.

Therefore, in a part of the memory cell array 31 ', for example, a maker area (first cell area 31a') used by the maker and having a small number of data rewrites.
Separately, a user area (second cell area 31b '), which allows the user to freely write and erase data and enables rewriting of data many times, is secured in advance, and a memory in the user area is secured. By making the gate length of the cell longer than that of the maker area, high reliability of the cell in the user area can be guaranteed.

Further, the user area is not limited to the case where only the user uses it, and since it is an area where high reliability of the cell can be guaranteed, only a small number of rewrites are performed. If data that needs to be temporarily stored is stored, higher reliability can be ensured.

The first and second cell areas 31
a 'and 31b' are word line units (the word lines WLa1 'to WLan' and the word lines WLb1 'to
The width of WLbn 'is substantially uniform in the row direction), and is not scattered in the array 31'.
From the viewpoint of controllability during gate processing, the word line direction (the word lines WLa1 ′ to WLan ′ and the word line WLb
It is desirable to provide them adjacent to each other in a direction along 1 ′ to WLbn ′).

Further, the second cell area 31b 'leads to an increase in the area of the memory cell array 31' (the area of the second cell area 31b 'is about two times that of the first cell area 31a').
Therefore, it is preferable to provide the memory cell array 31 ′ with a size that can minimize an increase in the area of the memory cell array 31 ′.

Next, a method of manufacturing the memory cell array 31 'having the above configuration will be described with reference to FIG.

Each of FIGS. 5A to 5E corresponds to FIG.
Cross sections substantially corresponding to the VI line are referred to as word lines WLa1 'to WLa.
n ', WLb1' to WLbn 'from the direction orthogonal to them. Here, an N-well region is formed on a P-type silicon substrate, and a P-well provided on the surface of the N-well region is formed.
It is assumed that a cell array is formed on the mold well region.

For example, the N-well region, the P-well region,
After forming an element isolation region (both not shown), a thermal oxide film 311 having a thickness of about 10 nm is formed on the P well region (see FIG. 3A).

Next, on the thermal oxide film 311, 5 × 1
A polysilicon film 312 into which phosphorus has been introduced at a concentration of about 0 ¹⁹ to 4 × 10 ²⁰ cm ⁻³ is deposited to a thickness of about 150 nm (see FIG. 4B).

Next, a resist film (not shown) is applied on the polysilicon film 312, and a stripe-shaped opening groove for separating the floating gate in the bit line direction is formed thereon. Then, using the resist film as a mask, the polysilicon film 312 is etched by RIE or the like to form a floating gate isolation region (not shown) in the bit line direction.

After removing the resist film, an oxide film 313 having a thickness of about 16 to 20 nm is formed on the surface of the polysilicon film 312 by a thermal oxidation method or a CVD method. Further, on the oxide film 313, for example, 5 ×
A polysilicon film 314 doped with phosphorus at a concentration of about 10 ¹⁹ to 4 × 10 ²⁰ cm ⁻³ is deposited to a thickness of about 350 nm (see FIG. 3C).

Next, on the polysilicon film 314,
In the direction orthogonal to the floating gate isolation region,
In the first cell area 31a ′, a first resist pattern 315a having a width of 0.2 μm is formed, and in the second cell area 31b ′.
Then, a second resist pattern 315b having a width of 0.4 μm is formed (see FIG. 4D).

Next, using the first and second resist patterns 315a and 315b as a mask, the polysilicon film 3 is formed.
14, the oxide film 313, the polysilicon film 312,
Then, the thermal oxide film 311 is etched by RIE or the like.

Thus, as shown in FIG. 17E, in the single memory cell array 31 ', the gate electrodes 316a' and 316 of the memory cells having different gate lengths are provided.
The processing of b ′ is performed simultaneously.

That is, in the first cell area 31a ',
On the tunnel oxide film 311 ', a cell gate electrode 316a' having a gate length La of 0.2 [mu] m, in which a floating gate 312 ', an inter-gate insulating film 313', and a control gate 314 'are sequentially stacked, is formed. .

Similarly, in the second cell area 31b ', a floating gate 312', an inter-gate insulating film 313 ', and a control gate 314' are sequentially stacked on a tunnel oxide film 311 '. A .4 .mu.m cell gate electrode 316b 'is formed.

Thereafter, heat treatment (post-oxidation) is performed in an oxidizing atmosphere to form the gate electrodes 316a 'and 316.
By covering the periphery of b ′ with an oxide film and forming diffusion layers serving as a drain and a source by an ion implantation method, in each of the areas 31a ′ and 31b ′,
Each of the cells is substantially the same as the conventional one (see FIG. 8).

Although not shown in the drawing, after depositing an interlayer film on the entire surface, a contact hole is opened in the interlayer film, and further, a wiring layer is patterned. Further, the contact hole is filled with W or the like, and the W is cut by a CMP method or the like, thereby forming a contact with a wiring such as a bit line / source line. Then, after forming an interlayer insulating film, Al or the like is deposited to perform wiring patterning, and thereafter, an oxide film serving as a passivation film is deposited on the entire surface by a CVD method, whereby the memory cell having the above-described structure is deposited.
Array 31 'is manufactured.

Although omitted in the above description, the formation of the peripheral circuits of the memory cell array 31 'is described below.
Performed according to existing manufacturing processes.

According to such a configuration, it is possible to write data in a cell having a large number of data rewrites with a lower voltage while minimizing an increase in the area of the array.

That is, in a part of the memory cell array,
In addition to the area where the number of data rewrites is small, an area that allows a large number of data rewrites is secured, and the gate length of the memory cell in the area with a large number of rewrites is set to be larger than that in the area with a small number of rewrites. I try to make it longer. This makes it possible to keep the data write voltage low in cells where the number of data rewrites is high, reducing the voltage stress applied to the tunnel oxide film and inter-gate insulating film due to the increase in the number of data rewrites. become able to. Therefore, it is possible to prevent deterioration of a cell having a large number of data rewrites,
High reliability can be guaranteed.

In particular, since an area that allows a large number of data rewrites is arranged in a part of the memory cell array, the entire area of the array may be an area with a large number of data rewrites. It is possible to minimize an increase in the area of the array as compared with (when the gate length of the cells in all areas is 0.4 μm).

Further, the present invention can be easily realized without greatly changing the conventional manufacturing process of the EEPROM.

In the second embodiment of the present invention, the area where the memory cell having the gate length of 0.2 μm is arranged and the area where the memory cell having the gate length of 0.4 μm is arranged Thus, the case where the memory cell array is configured has been described as an example, but the size of each area, the length of the gate length, and a combination thereof are not limited thereto.

For example, in addition to an area having a cell gate length of 0.2 μm, a plurality of areas (cell blocks) having different gate lengths of memory cells can be provided.

FIG. 7 schematically shows another configuration example (memory cell array 31 ″) of the memory cell array.

In this case, for example, when gate length L is 0.2
μm and the gate length L
Is set to 0.3 μm, and the third cell area 31 whose gate length L is set to 0.4 μm.
and c '' are arranged to form the memory cell array 31 ''.

With such a configuration, each area 31
By limiting the number of rewrites for each of a ″, 31b ″, and 31c ″, it is possible to expand the range of applications, and to expect substantially the same effects as in the above-described second embodiment. it can.

It is also possible to form the cell by changing the thickness of the tunnel oxide film of each cell for each area. For example, the tunnel oxide film of a cell having a gate length of 0.4 μm may be made thicker than the tunnel oxide film of another cell having a gate length of 0.2 μm. In this case, the reliability can be further improved regardless of whether the number of times of data rewriting is large or small.

In each of the first and second embodiments described above, the control gate is not limited to the case where the control gate is formed using only the polysilicon film.
It is also possible to form a polycide gate by using a laminated film of (tungsten silicide film) and a polysilicon film.

The inter-gate insulating film is not limited to being formed using a single oxide film, but is formed using, for example, an ONO film having a three-layer structure of an oxide film / nitride film / oxide film. You can also.

Further, the present invention is not limited to a nonvolatile semiconductor memory device storing binary data, such as an EEPROM capable of electrically rewriting data and capable of high integration, for example, a quaternary or more. Can also be applied to a multi-valued memory that stores the data of

In addition, it goes without saying that various modifications can be made without departing from the spirit of the present invention.

[0147]

As described in detail above, according to the present invention, it is possible to improve the reliability of memory cells due to miniaturization, and to provide a nonvolatile semiconductor memory device useful for commercialization.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing an example of an EEPROM in a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a memory cell in an EEPROM.
FIG. 2 is a schematic cross-sectional view illustrating a configuration example of an array.

FIG. 3 is also a process cross-sectional view for explaining the outline of the method for manufacturing the memory cell array.

FIG. 4 is a schematic configuration diagram showing an EEPROM as an example of a nonvolatile semiconductor memory device according to a second embodiment of the present invention;

FIG. 5 is a diagram showing memory cells in an EEPROM.
FIG. 2 is a schematic plan view showing a configuration example of an array.

FIG. 6 is also a process cross-sectional view for explaining the outline of the method for manufacturing the memory cell array.

FIG. 7 is a schematic plan view showing another configuration example of the memory cell array.

FIG. 8 shows EE to explain the prior art and its problems.
FIG. 2 is a sectional view schematically showing a cell structure of a memory cell array in a PROM.

FIG. 9 is a schematic characteristic diagram similarly illustrating a gate length dependency of a write characteristic and an erase characteristic in a conventional cell.

[Explanation of symbols]

11 row address buffers 21, 21 'row decoder sections 21a, 21a' first row decoder sections 21b, 21b 'second row decoder sections 31, 31', 31 '' memory cell array 31-1 ... well region 31-2 ... drain 31-3 ... source 31-4 ... channel 31-5a ... first tunnel oxide film 31-5b ... second tunnel oxide film 31-6 ... floating (floating) gate 31-7 ... inter-gate insulating film 31-8 ... control (control) gate 31-9 ... oxide film 31a, 31a ', 31a "... first cell area 31b, 31b', 31b" ... second cell area 31c "... Third cell area 41 Column address buffer 51 Column decoder 61 Column selection circuit 71 Sense amplifier 81 I / O buffer 310 P-type silicon substrate 311, 311a, 311b Oxide film 311 '... Tunnel oxide film 312 ... Polysilicon film (for floating gate) 312' ... Floating gate 313 ... Oxide film 313 '... Inter-gate insulating film 314 ... Polysilicon film (for control gate) 314' ... Control gate 315 ... resist pattern 315a ... first resist pattern 315b ... second resist pattern 316a, 316a '... gate electrode (first cell area) 316b, 316b' ... gate electrode (second cell area) BL ... bit line WLa1 to WLan, WLa1 '~ WLan' ... word line (first cell area) WLb1-WLbn, WLb1 '-WLbn' ... word line (second cell area) Vcc1, Vcc1 '... first power supply V1, V1' ... first voltage Vcc2, Vcc2 'second power supply V2, V2' second voltage L gate length La first gate length Lb second gate length D ... The first of the oxide film thickness Db ... the second oxide film thickness

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Claims (16)

[Claims] In a nonvolatile semiconductor memory device to which data can be written, a plurality of regions having different tunnel oxide film thicknesses of memory cells are present in a memory cell array including a plurality of memory cells. Nonvolatile semiconductor memory device. 2. The device according to claim 1, wherein the plurality of regions include a first region having excellent data write characteristics and high-speed operability and a second region having excellent data retention characteristics and long-term reliability. 3. The nonvolatile semiconductor memory device according to 1. 3. The first region comprises a plurality of memory cells having a first tunnel oxide thickness, and the second region comprises at least a plurality of memory cells having a second tunnel oxide thickness. 3. The nonvolatile memory according to claim 2, wherein each of the memory cells in the second region has a second tunnel oxide film thickness greater than that of each of the memory cells in the first region. Semiconductor memory device. 4. The nonvolatile semiconductor memory device according to claim 2, wherein said first and second areas are provided for at least one block. 5. The nonvolatile semiconductor memory device according to claim 2, wherein said first and second regions are provided for at least one column, respectively. 6. The nonvolatile semiconductor memory device according to claim 2, wherein said first and second regions have different data write voltages. 7. The nonvolatile semiconductor memory device according to claim 6, wherein a data write voltage in said second area is higher than a data write voltage in said first area. . 8. The nonvolatile semiconductor memory according to claim 2, wherein each memory cell in said second region has a gate length longer than that of each memory cell in said first region. apparatus. 9. A data rewritable nonvolatile semiconductor memory device, wherein a plurality of cell blocks having different gate lengths of memory cells are present in a memory cell array including a plurality of memory cells. Nonvolatile semiconductor memory device. 10. The first cell block suitable for rewriting data a small number of times, wherein the plurality of cell blocks are:
10. The nonvolatile semiconductor memory device according to claim 9, comprising a second cell block suitable for rewriting data many times. 11. The first cell block comprises a plurality of memory cells having a first gate length, and the second cell block comprises at least a plurality of memory cells having a second gate length. 11. The nonvolatile semiconductor device according to claim 10, wherein each memory cell in the second cell block has a second gate length longer than that of each memory cell in the first cell block. Storage device. 12. The nonvolatile semiconductor memory device according to claim 10, wherein each of said first and second cell blocks is provided for each word line. 13. The nonvolatile semiconductor memory device according to claim 10, wherein said first and second cell blocks are provided adjacent to each other in a word line direction. 14. The data writing voltage of the first and second cell blocks is different from each other.
0. A nonvolatile semiconductor memory device according to item 0. 15. The data write voltage in the second cell block is lower than the data write voltage in the first cell block.
5. The nonvolatile semiconductor memory device according to item 4. 16. The memory cell according to claim 10, wherein each memory cell in said second cell block has a tunnel oxide film thickness greater than that of each memory cell in said first cell block. Non-volatile semiconductor storage device.