JP2004153280A - エアギャップを有する多孔構造を有する半導体素子及びその製造方法 - Google Patents
エアギャップを有する多孔構造を有する半導体素子及びその製造方法 Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
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Abstract
【解決手段】半導体素子を製造するための方法は、(i)ベンゾシクロブテンのような有機ポリマーから作られた犠牲層4をその上に回路が形成された基板1上に蒸着する工程と、(ii)エアギャップが形成されるべき部分5を除いて犠牲層をエッチングする工程と、(iii)エアギャップ用の部分が低誘電率層内に完全に埋没するまで基板上に低誘電率層6を蒸着する工程と、(iv)それを通じるビア孔8及びトレンチ7を形成するべく低誘電率層をエッチングする工程と、(v)工程(iv)の前または後にエアギャップ用の部分を除去する工程と、(vi)銅で満たされるようビア及びトレンチ内に銅10を蒸着する工程であって、その結果銅が基板の表面と接触するところの工程と、から成る。
【選択図】図1
Description
2 配線層
3 キャップ膜層
4 犠牲層
5 エアギャップ用の部分
6 低誘電率層
7 トレンチ
8 ビア
9 エアギャップ
10 銅
Claims (27)
- 半導体素子を製造するための方法であって、
(i)その上に形成された回路を有する基板上に犠牲層を蒸着する工程と、
(ii)エアギャップが形成されるべき部分を除いて犠牲層をエッチングする工程と、
(iii)エアギャップ用の部分が低誘電率層内に完全に埋没されるまで、基板上に低誘電率層を蒸着する工程と、
(iv)それを通じるビア及びトレンチを形成するべく低誘電率層をエッチングする工程と、
(v)工程(iv)の前または後に、犠牲層のエアギャップ用の部分を除去する工程と、
(vi)ビア及びトレンチ内に銅を蒸着し、基板の表面に接触するよう銅で満たす工程と、
から成る方法。 - 請求項1に記載の方法であって、工程(v)は工程(iv)の後に実行される、ところの方法。
- 請求項1に記載の方法であって、工程(iii)は、
第1の低誘電体層及びエアギャップ用の部分が等しい高さになるまで基板上に第1の低誘電率層を蒸着する工程と、
第1の低誘電体層及びエアギャップ用の部分上に第2の低誘電体層を蒸着する工程と、
から成る方法。 - 請求項3に記載の方法であって、さらに第1の低誘電率層と第2の低誘電率層との間にエッチング停止層を蒸着する工程を含む、ところの方法。
- 請求項1に記載の方法であって、さらに基板はその上に犠牲膜が蒸着するところのキャップ層を含み、工程(ii)はさらにキャップ層をエッチングする工程を含む、ところの方法。
- 請求項5に記載の方法であって、さらに基板はキャップ層の下に配線層を含み、配線層は銅に結合される、ところの方法。
- 請求項1に記載の方法であって、犠牲層は有機ポリマーから作られる、ところの方法。
- 請求項7に記載の方法であって、有機ポリマーはベンゾシクロブテン(BCB)である、ところの方法。
- 請求項1に記載の方法であって、工程(v)はエッチング温度に基づく選択エッチングである、ところの方法。
- 請求項9に記載の方法であって、エッチング温度は400℃またはそれ以下である、ところの方法。
- 請求項3に記載の方法であって、第1の低誘電率層は3.0またはそれ以下の比誘電率を有する、ところの方法。
- 請求項11に記載の方法であって、第1の低誘電率層は圧縮応力を有する、ところの方法。
- 請求項3に記載の方法であって、第1の低誘電率層はジメチルジメトキシシラン(DMDMOS)とジビニルジメチルシラン(DVDMS)または酸素含有分子との組合せによって蒸着される、ところの方法。
- 請求項3に記載の方法であって、第2の低誘電率層は2.6またはそれ以下の比誘電率を有する、ところの方法。
- 請求項14に記載の方法であって、第2の低誘電率層は圧縮応力を有する、ところの方法。
- 請求項3に記載の方法であって、第2の低誘電率層はジメチルジメトキシシラン(DMDMOS)とジビニルジメチルシラン(DVDMS)または酸素含有分子との組合せによって蒸着される、ところの方法。
- 請求項1に記載の方法であって、低誘電率層内のエアギャップ用の部分は6%から25%の気孔率を与えるよう形成される、ところの方法。
- 請求項1に記載の方法であって、エアギャップ用の部分の高さは1nmから100nmの範囲である、ところの方法。
- 請求項1に記載の方法であって、エアギャップを含む低誘電率層は2.3またはそれ以下の比誘電率を有する、ところの方法。
- 請求項1に記載の方法であって、プラズマCVDチャンバを使って実行される、ところの方法。
- 請求項1に記載の方法であって、ビア及びエアギャップは実質的に等しい高さである、ところの方法。
- 中空構造を有する半導体素子であって、
その上に配線層が形成されるところの基板と、
6%から25%の気孔率を有する低誘電率層であって、前記低誘電率層はそれを通じて形成されたビア及びトレンチを有しかつ隣接するビアの間にボイドを有する、ところの低誘電率層と、
ビア及びトレンチが満たされるところの銅のコンタクト層であって、前記コンタクト層は配線層と接触しており、コンタクト層の上面は誘電体層から露出している、ところのコンタクト層と、
から成る半導体素子。 - 請求項22に記載の半導体素子であって、ボイドを有する低誘電率層は2.3またはそれ以下の比誘電率を有する、ところの半導体素子。
- 請求項22に記載の半導体素子であって、低誘電率層及びコンタクト層は複数回ラミネートされている、ところの半導体素子。
- 請求項22に記載の半導体素子であって、ボイドはエアギャップであり、ビア及びエアギャップは実質的に等しい高さである、ところの半導体素子。
- 請求項22に記載の半導体素子であって、低誘電率層の材料は2.9またはそれ以下の比誘電率を有する、ところの半導体素子。
- 請求項22に記載の半導体素子であって、さらに第1の低誘電率層と第2の低誘電率層との間にエッチング停止層を有する、ところの半導体素子。
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US10/693,200 US6949456B2 (en) | 2002-10-31 | 2003-10-24 | Method for manufacturing semiconductor device having porous structure with air-gaps |
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JP2006269537A (ja) * | 2005-03-22 | 2006-10-05 | Toshiba Corp | 半導体装置の製造方法及び半導体装置 |
US7439185B2 (en) | 2005-03-22 | 2008-10-21 | Kabushiki Kaisha Toshiba | Method for fabricating semiconductor device and semiconductor device |
US7884474B2 (en) | 2005-03-22 | 2011-02-08 | Kabushiki Kaisha Toshiba | Method for fabricating semiconductor device and semiconductor device |
JP4679193B2 (ja) * | 2005-03-22 | 2011-04-27 | 株式会社東芝 | 半導体装置の製造方法及び半導体装置 |
JP2008235890A (ja) * | 2007-03-16 | 2008-10-02 | Commiss Energ Atom | 集積回路用のキャビティを有する配線構造の製造方法 |
US10096485B2 (en) | 2015-02-19 | 2018-10-09 | Toshiba Memory Corporation | Semiconductor device and method of manufacturing the same |
Also Published As
Publication number | Publication date |
---|---|
US20050179135A1 (en) | 2005-08-18 |
US6949456B2 (en) | 2005-09-27 |
US20040087133A1 (en) | 2004-05-06 |
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