JP2004153102A - Multilayer structure of semiconductor material and its producing process - Google Patents

Multilayer structure of semiconductor material and its producing process Download PDF

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JP2004153102A
JP2004153102A JP2002317878A JP2002317878A JP2004153102A JP 2004153102 A JP2004153102 A JP 2004153102A JP 2002317878 A JP2002317878 A JP 2002317878A JP 2002317878 A JP2002317878 A JP 2002317878A JP 2004153102 A JP2004153102 A JP 2004153102A
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thin film
semiconductor material
substrate
insulating thin
gan
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JP4593067B2 (en
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Kiyoteru Yoshida
清輝 吉田
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Furukawa Electric Co Ltd
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Furukawa Electric Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilayer structure of a semiconductor material including a thick film semiconductor layer having high crystallinity, especially a multilayer structure of a GaN based material, and its producing process. <P>SOLUTION: The multilayer structure of a semiconductor material comprises a substrate 1, an insulating thin film 2 deposited on the surface 1a of the substrate 1 with voids 3 being distributed up to the surface 1a of the substrate 1, a buffer layer 4 of a first semiconductor material partially filling the voids 3, and a thick film 5 of a second semiconductor material of different kind from the first semiconductor material deposited to bury the insulating thin film 2 entirely including the remaining part 3a of the cavity 3. <P>COPYRIGHT: (C)2004,JPO

Description

【0001】
【発明の属する技術分野】
本発明は半導体材料の積層構造とその製造方法に関し、更に詳しくは、高品質で、表面が平坦な半導体厚膜を有する半導体材料の積層構造、とりわけその半導体がGaN系材料を代表例とする窒化物系III−V族化合物半導体である半導体材料の積層構造とそれを製造する方法に関する。
【0002】
【従来の技術】
例えば、GaN系半導体材料を用いた電界効果トランジスタ(FET)は、耐熱性が優れ、高耐圧で動作するFETとして注目されている。このようなGaN系FETを作製する場合には、所定のGaN系半導体を基板上に結晶成長させることが必要になる。
【0003】
一般に、半導体材料を用いた光素子や電子デバイスの製造に際しては、デバイス加工に先立ち、半導体基板の上にエピタキシャル結晶成長法で所定の半導体材料を順次積層して所定の積層構造を有する出発素材が作製される。
しかしながら、GaN系材料はその融点が2000℃を超え、かつその融点における蒸気圧も10GPaを超えるので、結晶成長用基板となる単結晶を直接作製することは極めて困難である。そのため、GaN系材料を結晶成長させる場合には、異種材料の基板を用いざるを得ない。
【0004】
しかしながら、GaN系材料と格子定数が一致する基板材料は全く存在しない。そのため、例えばGaNを結晶成長させる場合には、通常、基板の表面に予めバッファ層を結晶成長させ、その上に目的とするGaNを結晶成長させて、GaNと基板との間の格子不整合を緩和するという方法が採用されている。
その場合、基板としては、例えば、サファイア(Al)基板、SiC基板、Si基板、GaAs基板、GaP基板などが用いられているが、これらのうち、サファイア基板が最もよく用いられている。しかしながら、このサファイア基板とGaNとの格子不整合率は20%以上である。
【0005】
GaN系半導体材料に限らず、基板とその上に成長する半導体材料との格子定数が互いに異なる場合も上記したような問題が発生する。
実用的な半導体デバイスを作製しようとする場合、基板上に成長させる半導体材料の層の厚みは少なくとも100nm以上必要である。しかしながら、臨界膜厚の関係から、基板の材料の格子定数と基板上に成長する半導体材料の格子定数との差が0.5%より大きい場合には、成長する半導体材料の層の厚みが100nmを超えると結晶に多数の欠陥が入るという問題がある。
【0006】
そのため、このサファイア基板の上に厚膜のGaN層を成膜する場合には、従来から次のような2通りの方法で結晶成長が行われている。
第1の方法は、サファイア基板の上にAlNから成るバッファ層を予め成膜したのち、その上に、GaNを厚く結晶成長させる方法である。
具体的には、有機金属気相成長(MOCVD)法で、サファイア基板の上に、トリメチルアルミニウム(TMA)とアンモニア(NH)を用い、キャリアガスとして水素を用い、成長温度800℃で厚み50nm程度のAlNを成長させ、ついで、成長温度を1100℃程度にまで昇温し、トリメチルガリウム(TMG)とアンモニア(NH)を用いてGaNを結晶成長させて表面が平坦なGaNの厚膜を成膜している。
【0007】
第2の方法は、サファイア基板の上に、予めGaNを成長させてバッファ層とし、その上にGaNを厚く結晶成長させる方法である。
具体的には、TMGとNHを用い、キャリアガスとして水素を用い、成長温度500〜600℃程度の低温でGaNを成長させて厚み10〜20nm程度のバッファ層を成膜し、ついで成長温度を1000℃程度にまで昇温してGaNを結晶成長させ、表面が平坦な厚膜を成膜している。
【0008】
また、ガスソース分子線エピタキシャル法(GSMBE法)で、GaNのバッファ層を成膜し、その上にGaNの厚膜を成膜する場合には、基板の上に、金属Gaとプラズマ化した窒素源を用い、成長温度500〜550℃の低温でGaNのバッファ層を形成し、ついで成長温度を800℃程度にまで昇温してGaNを結晶成長させてGaNの厚膜を成膜している。
【0009】
第3の方法は、サファイアなどの基板の上に開口部を有するSiOマスクを形成したのち、その上にMOCVD法などでGaNを結晶成長させる方法である(例えば特許文献1を参照)。
【0010】
【特許文献1】
特開2000−21789号公報
【0011】
【発明が解決しようとする課題】
しかしながら、例えばSi基板を用いてGaNの厚膜を成膜する場合、バッファ層がAlN、GaNのいずれかの場合であっても、成長温度が500〜600℃程度の低温であると、膜厚が10〜20nm程度のとき、当該バッファ層は層状ではなく島状に結晶成長してしまい、各島状結晶の間にはSi基板が表出した状態になる。そしてこのような状態にある基板の上には、高品質なGaNを結晶成長させることは事実上不可能である。
【0012】
このバッファ層の厚みを厚くすると、この島状結晶は消失して全体として層状のバッファ層にすることができる。しかしながら、そのときのバッファ層の表面は平坦ではないため、この上に結晶成長されるGaNの厚膜もその表面は平坦ではなくなる。
そしてまた、GaNを厚み1μm以上結晶成長させると、その厚膜にはクラックが発生するという問題が生じてくる。
【0013】
更に、形成された厚膜におけるGaN結晶は高品質とはいえないという問題がある。これは、バッファ層の成膜時に、当該バッファ層には基板との格子不整合に基づき膜厚方向に略垂直に延びる貫通転位(欠陥)が発生し、この貫通転位が、そのまま、この上に成膜されたGaN結晶に伝播するからである。
成膜されたGaNの厚膜にこのような欠陥が高い転位密度で発生すると、この積層構造を加工して例えばGaN系FETを製作した場合、そのFETの耐圧特性は劣化して、著しく低い電界強度で絶縁破壊を起こしたりすることがある。
【0014】
ところが、前記した特許文献1に記載されているように、基板に所定の開口部を有するマスクを形成し、そしてその上にGaN系半導体材料を成長させる場合は、成長層は高品質を保つため、上記したような問題は発生しにくくなる。
しかしながら、この方法の場合、マスクに開口部を形成するためのリソグラフィー作業が必要であり、またマスク上に成長した半導体材料の層には転位は少ないが、マスク開口部の直上に成長した半導体材料の層には多数の転位が発生し、更には、開口部の大きさは所定面積以下にすることができないため、デバイスとして有効利用できる面積が制約されるという問題がある。
【0015】
本発明は、GaN系材料を例にして説明したような上記した問題を解決し、基板との格子不整合が大きい半導体結晶であっても、その結晶性は単結晶で高品質であり、また厚膜化してもクラック発生は起こりずらく、更には当該厚膜表面も平坦で鏡面化している半導体材料の積層構造とその製造方法の提供を目的とする。
【0016】
とくに、本発明は、半導体材料が窒化物III−V族化合物半導体、なかでもGaN系材料であることを好適とする半導体材料の積層構造とそれを製造する方法の提供を目的とする。
【0017】
【課題を解決するための手段】
上記した目的を達成するために、本発明においては、
基板と、前記基板の表面に成膜され、かつ前記基板の表面にまで至る空孔が分布している絶縁薄膜と、前記基板と前記絶縁薄膜を覆う半導体材料から成る層とを備えていることを特徴とする半導体材料の積層構造が提供される。
【0018】
また、本発明においては、
基板の上に、前記基板の表面にまで至る空孔が分布する絶縁薄膜を形成する工程、および、
前記絶縁薄膜をマスクとして使用する選択横方向成長法で、半導体材料を前記絶縁薄膜の空孔内と表面にエピタキシャル成長させる工程を備えていることを特徴とする半導体材料の積層構造の製造方法が提供される。
【0019】
なお、上記した空孔は、その口径が5〜10nm程度の原子オーダの大きさになっている。
好ましくは、基板の上に、前記基板の表面にまで至る空孔が分布する絶縁薄膜を形成する工程(以下、第1工程という)、
前記空孔内に第1の半導体材料をエピタキシャル成長させて、前記空孔内に、前記第1の半導体材料を部分的に充填する工程(以下、第2工程という)、および、
前記絶縁薄膜をマスクとして使用する選択横方向成長法で、前記第1の半導体材料とは異種類の第2の半導体材料をエピタキシャル成長させる工程(以下、第3工程という)を備えていることを特徴とする半導体材料の積層構造の製造方法が提供される。
【0020】
【発明の実施の形態】
図1に、本発明の積層構造の1例を示す。
この積層構造では、まず、基板1の上に絶縁薄膜2が成膜されている。そして、この絶縁薄膜2には、絶縁薄膜2の表面2aから基板1の表面1aにまで至る微細な空孔3が形成されている。この空孔3の口径は5〜10nm程度の原子オーダの大きさである。
【0021】
そして、この空孔3の中には、空孔3に表出している基板の表面1aにエピタキシャル成長された半導体材料が充填されている。その場合、前記した第2工程により、この空孔3の中に後述する第1の半導体材料をエピタキシャル成長法で結晶成長させることにより、当該第1の半導体材料が部分充填されていることが好適であり、以後の説明はこの方法に関して行う。
【0022】
この第1の半導体材料4は、基板の表面1aから空孔3内を埋めているが、空孔3の全体に充填されているのではなく、部分的に充填されていて、空孔3内の上部は未充填の状態になっている。このような状態で部分充填されている第1の半導体材料4は、目的とする厚膜5を成膜するときのバッファ層として機能する。
【0023】
そして、このバッファ層4の上部に存在する空孔3の残余の未充填部分3aと絶縁薄膜2の表面2aは、第2工程の過程で、後述する選択横方向成長法で結晶成長された第2の半導体材料から成る厚膜5で埋設されている。
この積層構造において、上記した厚膜5は、後述するように、絶縁薄膜2をマスクとし、バッファ層4の上に、エピタキシャル結晶成長法の1つである選択横方向成長(ELO:Epitaxial Lateral Overgrowth)法で結晶成長されたものであり、しかも空孔3は原子オーダの微細な孔である。したがってバッファ層4から垂直方向に伝播する欠陥も極めて微細であるため、全体として結晶性が高品質な単結晶で構成される。
【0024】
この積層構造は次のような工程を経て製造される。それを、半導体材料がGaN系材料である場合について説明する。
まず、図2で示したように、基板1の上に絶縁薄膜2を形成する。
ここで、基板1としては、例えばSi基板を用いることができる。また、サファイア基板、GaAs基板、GaP基板、SiC基板、更には、ZnO、AlN、ZrB、NdGaO、LiGaO、ScAlMgOのような材料から成る基板を用いてもよい。いずれの基板を用いても、結晶性が高品質なGaN材料の厚膜5の成膜は可能である。
【0025】
絶縁薄膜2としては、絶縁性を備えていれば何であってもよいが、例えば、SiO薄膜、SiN薄膜、TiN薄膜、TaO薄膜、Al薄膜、AlN薄膜、MoOx、WOx、TiOxのような金属酸化物の薄膜などをあげることができ、Si基板を用いた場合にはSiO薄膜であることが好ましい。
絶縁薄膜2は、例えばMOCVD法で成膜される。その膜厚は2〜100nm程度に制御することが好ましい。その場合、例えば成膜時間、成膜ガス流量、成膜温度などの成膜条件を適宜に選択することにより、成膜された絶縁薄膜には、その面内で無秩序に分布し、口径が原子オーダの前記空孔3が自然に形成される。
【0026】
なお、成膜条件によっては、絶縁薄膜2に空孔3が形成されないこともある。そのようなことを考えると、成膜した絶縁薄膜2に対して次のような処理を行って空孔3を意図的に形成することが好ましい。
例えば、絶縁薄膜2がSiO薄膜である場合には、まず、図3で示したように、基板1の表面にSiO薄膜2を成膜する。
【0027】
ついで、図4で示したように、SiO薄膜2の表面に金属Gaまたは金属Inを直接付着させる。そして基板の全体を温度600〜1000℃程度にまで昇温する。その結果、SiOと金属Ga(または金属In)の間で酸化還元反応が生起して、SiOは、より高揮発性のSiOに転換するので、その高揮発性のSiOは脱離して、その痕跡が、図5で示したように、金属Ga(または金属In)の原子オーダの大きさを有する空孔3として残置する。
【0028】
なお、このときの金属Gaや金属Inの付着量は、それぞれ10原子層以下の厚みに設定することが好ましい。10原子層よりも厚くすると、金属Gaや金属Inがドロップ(液状)となって不都合であるからである。
第2工程では、上記した第1工程で得られた中間体に例えばMOCVD法を適用し、絶縁薄膜(SiO薄膜)2をマスクとして第1の半導体材料の選択成長を行い、図6で示した中間体を製造する。
【0029】
第1の半導体材料は、空孔3の中で、基板の表面1aから選択的に核形成して順次堆積していき、空孔内には第1の半導体材料から成るバッファ層4が形成される。
その場合、成長条件、とりわけ成長時間を適正に制御することにより、空孔3の中を全て第1の半導体材料で充填するのではなく、空孔3の上部には空間部分3aが残るような厚みでバッファ層4を形成する。空孔全体の深さに対し5〜50%程度の空間部分3aが残置するように、バッファ層4を形成することが好ましい。
【0030】
その理由は、次の第3工程で第2の半導体材料の選択横方向成長を実施可能とするためである。
ここで、用いる第1の半導体材料としては、第3工程で用いる第2の半導体材料と関係で適宜に選択されるが、例えば第3工程で用いる第2の半導体材料がGaNである場合には、AlGaN、AlInGaN、AlInGaNAs、AlGaNPAs、AlInGaNPAs(0≦y,y,m,n≦1)などを単独で用いることができる。この場合、バッファ層4は1層になる。
【0031】
また、複数のGaN系材料を積層してバッファ層4を多層構造にしてもよい。例えば、AlGaN/GaN、AlINGaN/InGaN、AlInGaN/AlInGaNAs、AlInGaNAs/AlInGaPAs(0≦y,y,m≦1)などを順次積層してバッファ層にしてもよい。
この第1の半導体材料の空孔3内への結晶成長(充填)に際しては、成長温度を高温にして実施することが好ましい。具体的には、成長温度は600℃以上に設定することが好ましい。
【0032】
その理由は、成長した結晶が高品質になるので、第3工程で成膜される厚膜も高品質にすることができ、また、空孔内の基板表面1aにおける第1の半導体材料のマイグレーションが促進され、そのため、基板表面1aの全面に、ムラを生ずることなく均一に半導体材料の結晶成長を実現することができるからである。
なお、AlGaNで上記したバッファ層を形成する場合、N源(NH)の導入に先立ち、空孔内の基板表面1aに金属Alを数原子層付着させ、ついで、TMG,TAM,NHを導入してAlGa1−xN(0<x≦1)にしてもよい。
【0033】
また、NHの導入に先立ち、空孔内の表面表面1aに金属Gaを付着させてからTMG,TMA、NHを導入してAlGa1−xN(0≦x<1)にしてもよい。
これらのバッファ層を用いて後述する第3工程を行っても、成膜された第2の半導体材料から成る厚膜は、その表面が平坦になり、鏡面化する。
【0034】
また、上記したAlGa1−xN(0≦x≦1)の結晶成長時における成長温度は650〜900℃に設定することが好ましい。基板表面1aには、均一にバッファ層を形成することができるからである。
その場合、AlGa1−xNにおけるAl組成が0≦x≦0.2と低いときは、成長温度を650〜750℃に設定することが最適である。そして、Al組成が高くなるにつれて成長温度を高めていくことにより(ただし、最高900℃まで)、バッファ層を均一に形成することができる。
【0035】
第3工程では、第2工程で得られた図6の中間体に対し、例えばMOCVD法を適用して第2の半導体材料を結晶成長させて、図1で示したような本発明の積層構造を製造する。
この第3工程においては、最初に、バッファ層4の上で第2の半導体材料の結晶成長が進み、空孔内における上部の空間部分3aは当該第2の半導体材料で埋設されていく。そして空孔内の埋設が完了した時点以降は、絶縁薄膜2の表面2aの上で選択横方向成長が進行し、第2の半導体材料から成る厚膜5が形成されていく。
【0036】
この厚膜5において、空孔3内のバッファ層4の略直上部に位置する箇所では貫通転位が伝播している。一方、絶縁薄膜2の表面2aの上部に位置する箇所では貫通転位の伝播が抑制されているため、そこに成長した結晶は高品質になっている。
そして、空孔3はその口径が原子オーダと超微細な孔であるため、空孔3の全体の口径面積が結晶成長面に占める割合は極めて少ないといえる。
【0037】
したがって、成膜された厚膜5において貫通転位の転位密度は極めて低くなっていて、そのため厚膜5の結晶性は全体として高品質になっている。
用いる第2の半導体材料としては、本発明の積層構造を経由して製造される目的の光素子や電子デバイスとの関係で選定され、例えばGaN系デバイスの製造が目的であればGaNをあげることができる。
【0038】
そして、この第2の半導体材料との関係で例えば前記したような第1の半導体材料が選定される。
以上の説明は、GaN系材料について行ったが、本発明で用いる半導体材料はこれに限定されるものではなく、AlGaN、AlInGaN、AlInGaNAsPのような他の窒化物系III−V族化合物半導体であってもよい。
【0039】
【実施例】
まず、フッ酸で表面を化学エッチングしたSi基板を用意した。このSi基板をMOCVD装置にセットし、基板温度400℃で、SiH,Oをそれぞれ15sccm,30sccm流してプラズマ化した条件で運転して厚み100nmのSiO薄膜を成膜した。
【0040】
別実験で同様の条件でSiO薄膜を成膜し、その表面と断面をSEM観察したところ、この薄膜には、口径5〜10nmの微細空孔がSi基板の表面にまで形成されていた。そして、これらの微細空孔の口径面積の積算値はSiO薄膜の全体面積に対し10%程度であった。
装置内をターボポンプで5×10−6Pa以下の真空度まで真空引きしたのち1Paまで真空度を高め、基板温度を800℃に昇温した。
【0041】
ついで、基板を900rpmで回転させながら、Ga源としてTMG(58n mol/min)、Al源としてTMA(58n mol/min)、N源としてNH(12l/min)の流量で4分間基板表面に供給した。この供給量は、厚み50nmのAlGaNを結晶成長させる量に相当する。
ついで、基板温度を1300℃にまで昇温し、TMAの供給を絶ち、15分間のGaN成長を行って厚み500nmの厚膜を成膜した。
【0042】
装置から基板を取出し、GaN厚膜を目視観察した。表面は極めて平坦であり、金属光沢の鏡面を呈していた。
また、GaN厚膜の光学特性をフォトルミネッセンス(PL)法で調査したところ、バンド端(365nm)における発光強度は著しく強く、深い準位(deep level)の発光はほとんど認められなかった。このようなことから、このGaN厚膜におけるGaN結晶は高品質であることを確認することができた。
【0043】
【発明の効果】
以上の説明で明らかなように、本発明によれば、高品質で、厚膜な半導体層を有する積層構造を製造することができる。とくに本発明をGaN系材料に適用することにより、厚膜で高品質のGaN層を成膜することができ、そのことから、例えば高耐圧で低オン抵抗で動作する電子デバイスを製造することができる。
【0044】
更に、絶縁薄膜の空孔の径を数10nm以下にすることができるため、形成された厚膜においては、デバイスとして有効利用できる面積が制約されにくくなり、また、特許文献1で行っているようなマスクのリソグラフィー作業が不要になるという効果が得られる。
【図面の簡単な説明】
【図1】本発明の積層構造の1例を示す断面図である。
【図2】基板に絶縁薄膜を形成した状態を示す断面図である。
【図3】基板にSiO薄膜を成膜した状態を示す断面図である。
【図4】絶縁薄膜に金属を直接付着させた状態を示す断面図である。
【図5】図4の中間体を加熱してSiO薄膜に空孔を形成した状態を示す断面図である。
【図6】SiO薄膜の空孔内に第1の半導体材料を部分充填した状態を示す断面図である。
【符号の説明】
1 基板
1a 基板1の表面
2 絶縁薄膜
2a 絶縁薄膜2の表面
3 空孔
3a 残余の空孔の部分
4 バッファ層(第1の半導体材料)
5 厚膜(第2の半導体材料)
[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a laminated structure of a semiconductor material and a method of manufacturing the same, and more particularly, to a laminated structure of a semiconductor material having a high-quality, thick semiconductor film having a flat surface, particularly a nitride having a GaN-based material as a semiconductor. The present invention relates to a laminated structure of a semiconductor material that is a compound III-V compound semiconductor and a method of manufacturing the same.
[0002]
[Prior art]
For example, a field effect transistor (FET) using a GaN-based semiconductor material has attracted attention as an FET which has excellent heat resistance and operates at a high withstand voltage. When fabricating such a GaN-based FET, it is necessary to grow a predetermined GaN-based semiconductor on a substrate.
[0003]
Generally, when manufacturing an optical element or an electronic device using a semiconductor material, prior to device processing, a starting material having a predetermined laminated structure is obtained by sequentially laminating a predetermined semiconductor material on a semiconductor substrate by an epitaxial crystal growth method. It is made.
However, since the GaN-based material has a melting point exceeding 2000 ° C. and a vapor pressure at the melting point also exceeding 10 GPa, it is extremely difficult to directly produce a single crystal as a substrate for crystal growth. Therefore, when growing a GaN-based material in a crystal, a substrate of a different material must be used.
[0004]
However, there is no substrate material whose lattice constant matches that of the GaN-based material. Therefore, for example, when GaN is crystal-grown, usually, a buffer layer is crystal-grown in advance on the surface of the substrate, and the target GaN is crystal-grown on the buffer layer. The method of relaxation is adopted.
In this case, as the substrate, for example, a sapphire (Al 2 O 3 ) substrate, a SiC substrate, a Si substrate, a GaAs substrate, a GaP substrate, or the like is used. Of these, the sapphire substrate is most often used. . However, the lattice mismatch between the sapphire substrate and GaN is 20% or more.
[0005]
Not only the GaN-based semiconductor material but also the above-described problem occurs when the lattice constants of the substrate and the semiconductor material grown thereon are different from each other.
In order to manufacture a practical semiconductor device, the thickness of a layer of a semiconductor material grown on a substrate needs to be at least 100 nm or more. However, when the difference between the lattice constant of the material of the substrate and the lattice constant of the semiconductor material grown on the substrate is larger than 0.5%, the thickness of the layer of the semiconductor material to be grown is 100 nm. If the number exceeds the range, there is a problem that the crystal has many defects.
[0006]
Therefore, when a thick GaN layer is formed on this sapphire substrate, crystal growth has conventionally been performed by the following two methods.
The first method is to form a buffer layer made of AlN on a sapphire substrate in advance and then grow GaN thick crystal thereon.
Specifically, trimethylaluminum (TMA) and ammonia (NH 3 ) are used on a sapphire substrate by a metal organic chemical vapor deposition (MOCVD) method, hydrogen is used as a carrier gas, and a thickness of 50 nm is formed at 800 ° C. About AlN is grown, and then the growth temperature is raised to about 1100 ° C., and GaN is crystal-grown using trimethylgallium (TMG) and ammonia (NH 3 ) to form a GaN thick film having a flat surface. The film is formed.
[0007]
The second method is a method in which GaN is grown on a sapphire substrate in advance to serve as a buffer layer, on which GaN is grown in a thick crystal.
Specifically, GaN is grown at a low temperature of about 500 to 600 ° C. using TMG and NH 3 and hydrogen as a carrier gas to form a buffer layer with a thickness of about 10 to 20 nm. Is heated to about 1000 ° C. to grow GaN crystals, thereby forming a thick film having a flat surface.
[0008]
When a GaN buffer layer is formed by a gas source molecular beam epitaxy method (GSMBE method) and a GaN thick film is formed thereon, metallic Ga and plasma-converted nitrogen are formed on the substrate. Using a source, a buffer layer of GaN is formed at a low temperature of 500 to 550 ° C., and the GaN crystal is grown by raising the growth temperature to about 800 ° C. to form a thick GaN film. .
[0009]
A third method is a method of forming a SiO 2 mask having an opening on a substrate such as sapphire and then growing GaN thereon by MOCVD or the like (for example, see Patent Document 1).
[0010]
[Patent Document 1]
JP 2000-21789 A
[Problems to be solved by the invention]
However, for example, when a GaN thick film is formed using a Si substrate, even if the buffer layer is made of AlN or GaN, if the growth temperature is as low as about 500 to 600 ° C., Is about 10 to 20 nm, the buffer layer grows not in layers but in islands, and the Si substrate is exposed between the islands. It is practically impossible to grow high-quality GaN on the substrate in such a state.
[0012]
When the thickness of the buffer layer is increased, the island-like crystals disappear and the entire buffer layer can be formed. However, since the surface of the buffer layer at that time is not flat, the surface of the GaN thick film to be crystal-grown thereon is no longer flat.
In addition, when GaN is grown to a thickness of 1 μm or more, there is a problem that cracks occur in the thick film.
[0013]
Further, there is a problem that the GaN crystal in the formed thick film is not of high quality. This is because, during the formation of the buffer layer, threading dislocations (defects) that extend substantially perpendicular to the film thickness direction are generated in the buffer layer due to lattice mismatch with the substrate, and the threading dislocations remain on the buffer layer as it is. This is because it propagates to the formed GaN crystal.
When such defects occur at a high dislocation density in a formed GaN thick film, when this stacked structure is processed to produce, for example, a GaN-based FET, the withstand voltage characteristics of the FET are deteriorated, and an extremely low electric field is generated. It may cause dielectric breakdown at high strength.
[0014]
However, when a mask having a predetermined opening is formed on a substrate and a GaN-based semiconductor material is grown thereon, as described in Patent Document 1 described above, the growth layer must maintain high quality. However, the above-described problem is less likely to occur.
However, this method requires a lithography operation to form an opening in the mask, and the semiconductor material layer grown on the mask has few dislocations, but the semiconductor material grown directly on the mask opening. In this layer, a large number of dislocations are generated, and the size of the opening cannot be reduced to a predetermined area or less. Therefore, the area that can be effectively used as a device is limited.
[0015]
The present invention solves the above-described problems as described using a GaN-based material as an example. Even in the case of a semiconductor crystal having a large lattice mismatch with a substrate, the crystallinity is a single crystal and high quality. It is another object of the present invention to provide a laminated structure of a semiconductor material in which cracks are unlikely to occur even when the film thickness is increased and the surface of the thick film is flat and mirror-finished, and a method of manufacturing the same.
[0016]
In particular, it is an object of the present invention to provide a laminated structure of a semiconductor material, which is preferably a nitride III-V compound semiconductor, especially a GaN-based material, and a method of manufacturing the same.
[0017]
[Means for Solving the Problems]
In order to achieve the above object, in the present invention,
A substrate, an insulating thin film formed on the surface of the substrate and having holes distributed to the surface of the substrate, and a layer made of a semiconductor material that covers the substrate and the insulating thin film. A laminated structure of a semiconductor material is provided.
[0018]
In the present invention,
Forming on the substrate an insulating thin film in which holes reaching the surface of the substrate are distributed, and
A method of manufacturing a laminated structure of a semiconductor material, comprising a step of epitaxially growing a semiconductor material in a hole and a surface of the insulating thin film by a selective lateral growth method using the insulating thin film as a mask. Is done.
[0019]
In addition, the above-mentioned pores have a size of an atomic order of about 5 to 10 nm in diameter.
Preferably, a step (hereinafter referred to as a first step) of forming, on the substrate, an insulating thin film in which holes reaching the surface of the substrate are distributed;
A step of epitaxially growing a first semiconductor material in the hole and partially filling the hole with the first semiconductor material (hereinafter, referred to as a second step);
A step of epitaxially growing a second semiconductor material different from the first semiconductor material by a selective lateral growth method using the insulating thin film as a mask (hereinafter, referred to as a third step). A method for manufacturing a laminated structure of a semiconductor material is provided.
[0020]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 shows an example of the laminated structure of the present invention.
In this laminated structure, first, an insulating thin film 2 is formed on a substrate 1. The insulating thin film 2 has fine holes 3 extending from the surface 2 a of the insulating thin film 2 to the surface 1 a of the substrate 1. The diameter of the holes 3 is on the order of 5 to 10 nm in atomic order.
[0021]
The holes 3 are filled with a semiconductor material epitaxially grown on the surface 1 a of the substrate exposed in the holes 3. In this case, it is preferable that the first semiconductor material is partially filled in the holes 3 by growing a first semiconductor material, which will be described later, in this hole 3 by an epitaxial growth method. Yes, and the rest of the description will be in terms of this method.
[0022]
The first semiconductor material 4 fills the holes 3 from the surface 1a of the substrate, but does not fill the whole holes 3 but partially fills the holes 3. Is in an unfilled state. The first semiconductor material 4 partially filled in such a state functions as a buffer layer when a target thick film 5 is formed.
[0023]
The remaining unfilled portion 3a of the hole 3 existing on the upper part of the buffer layer 4 and the surface 2a of the insulating thin film 2 are formed in the second step by crystal growth by selective lateral growth described later. 2 buried in a thick film 5 made of a semiconductor material.
In this laminated structure, as described later, the thick film 5 is formed on the buffer layer 4 by using the insulating thin film 2 as a mask and selectively laterally growing (ELO) which is one of the epitaxial crystal growth methods. ) Method, and the vacancies 3 are fine pores on the atomic order. Therefore, the defects that propagate from the buffer layer 4 in the vertical direction are also extremely fine, so that the whole is composed of a high-quality single crystal.
[0024]
This laminated structure is manufactured through the following steps. The case where the semiconductor material is a GaN-based material will be described.
First, an insulating thin film 2 is formed on a substrate 1 as shown in FIG.
Here, for example, a Si substrate can be used as the substrate 1. Further, a sapphire substrate, a GaAs substrate, a GaP substrate, a SiC substrate, or a substrate made of a material such as ZnO, AlN, ZrB 2 , NdGaO 3 , LiGaO 3 , and ScAlMgO 4 may be used. Whichever substrate is used, it is possible to form a thick film 5 of a GaN material with high crystallinity.
[0025]
The insulating thin film 2 may be anything as long as it has an insulating property. For example, an SiO 2 thin film, a SiN thin film, a TiN thin film, a TaO x thin film, an Al 2 O 3 thin film, an AlN thin film, MoOx, WOx, TiOx And a metal oxide thin film as described above. When a Si substrate is used, a SiO 2 thin film is preferable.
The insulating thin film 2 is formed by, for example, the MOCVD method. It is preferable to control the film thickness to about 2 to 100 nm. In such a case, for example, by appropriately selecting film forming conditions such as a film forming time, a film forming gas flow rate, and a film forming temperature, the formed insulating thin film is randomly distributed in the plane, and the diameter is atomic. The holes 3 of the order are naturally formed.
[0026]
Note that, depending on the film forming conditions, the holes 3 may not be formed in the insulating thin film 2. Considering such a situation, it is preferable to intentionally form the holes 3 by performing the following processing on the formed insulating thin film 2.
For example, the insulating thin film 2 when it is SiO 2 thin film, first, as shown in FIG. 3, for forming the SiO 2 thin film 2 on the surface of the substrate 1.
[0027]
Then, as shown in FIG. 4, metal Ga or metal In is directly attached to the surface of the SiO 2 thin film 2. Then, the entire substrate is heated to a temperature of about 600 to 1000 ° C. As a result, the occurrence is a redox reaction between the SiO 2 and metal Ga (or metal an In), SiO 2, since converted More SiO 2 of high volatility, SiO 2 of the high volatility desorbs As a result, as shown in FIG. 5, the trace is left as a hole 3 having the size of the atomic order of metal Ga (or metal In).
[0028]
In this case, it is preferable that the adhesion amounts of the metal Ga and the metal In are each set to a thickness of 10 atomic layers or less. If the thickness is more than 10 atomic layers, metal Ga or metal In becomes a drop (liquid), which is inconvenient.
In the second step, for example, the MOCVD method is applied to the intermediate obtained in the first step, and the first semiconductor material is selectively grown using the insulating thin film (SiO 2 thin film) 2 as a mask. To produce an intermediate.
[0029]
The first semiconductor material is selectively nucleated from the surface 1a of the substrate and sequentially deposited in the holes 3, and a buffer layer 4 made of the first semiconductor material is formed in the holes. You.
In this case, by properly controlling the growth conditions, especially the growth time, the voids 3 are not completely filled with the first semiconductor material, but the space 3a remains above the voids 3. The buffer layer 4 is formed with a thickness. It is preferable to form the buffer layer 4 so that the space portion 3a of about 5% to 50% of the depth of the whole hole is left.
[0030]
The reason is that it is possible to carry out the selective lateral growth of the second semiconductor material in the next third step.
Here, the first semiconductor material used is appropriately selected in relation to the second semiconductor material used in the third step. For example, when the second semiconductor material used in the third step is GaN, , using AlGaN, Al x in y GaN, Al x in y GaNAs m, Al x GaNP n As m, Al x in y GaNP n As m (0 ≦ y, y, m, n ≦ 1) and the like alone Can be. In this case, the buffer layer 4 becomes one layer.
[0031]
Further, the buffer layer 4 may have a multilayer structure by stacking a plurality of GaN-based materials. For example, AlGaN / GaN, AlINGaN / InGaN , Al x In y GaN / Al x In y GaNAs m, Al x In y GaNAs m / Al x In y GaPAs m (0 ≦ y, y, m ≦ 1) and sequentially They may be stacked to form a buffer layer.
The crystal growth (filling) of the first semiconductor material into the holes 3 is preferably performed at a high growth temperature. Specifically, the growth temperature is preferably set to 600 ° C. or higher.
[0032]
The reason is that the quality of the grown crystal becomes high, so that the thick film formed in the third step can also be made high quality, and the migration of the first semiconductor material on the substrate surface 1a in the hole. Is promoted, so that the crystal growth of the semiconductor material can be realized uniformly without causing unevenness on the entire surface 1a of the substrate.
When the above-mentioned buffer layer is formed of AlGaN, several atomic layers of metal Al are attached to the substrate surface 1a in the holes before introducing the N source (NH 3 ), and then TMG, TAM, and NH 3 are added. Al x Ga 1-x N (0 <x ≦ 1) may be introduced.
[0033]
Prior to the introduction of NH 3 , metal Ga is attached to the surface 1 a in the pores, and then TMG, TMA, and NH 3 are introduced to make Al x Ga 1-x N (0 ≦ x <1). Is also good.
Even when a third step described later is performed using these buffer layers, the surface of the formed thick film made of the second semiconductor material becomes flat and mirror-finished.
[0034]
Further, it is preferable that the growth temperature during the crystal growth of Al x Ga 1 -xN (0 ≦ x ≦ 1) be set to 650 to 900 ° C. This is because the buffer layer can be uniformly formed on the substrate surface 1a.
In that case, when the Al composition in Al x Ga 1-x N as low as 0 ≦ x ≦ 0.2 is optimal to set the growth temperature to 650 to 750 ° C.. By increasing the growth temperature as the Al composition becomes higher (up to a maximum of 900 ° C.), the buffer layer can be formed uniformly.
[0035]
In the third step, a crystal of a second semiconductor material is grown on the intermediate of FIG. 6 obtained in the second step, for example, by applying the MOCVD method, and the laminated structure of the present invention as shown in FIG. To manufacture.
In the third step, first, the crystal growth of the second semiconductor material proceeds on the buffer layer 4, and the upper space portion 3a in the hole is buried with the second semiconductor material. After the completion of the filling of the holes, the selective lateral growth proceeds on the surface 2a of the insulating thin film 2, and the thick film 5 made of the second semiconductor material is formed.
[0036]
In the thick film 5, threading dislocations are propagated at a position located almost directly above the buffer layer 4 in the hole 3. On the other hand, the propagation of threading dislocations is suppressed at a position above the surface 2a of the insulating thin film 2, and the crystal grown there is of high quality.
Since the pores 3 are ultrafine pores having a diameter on the order of atoms, it can be said that the ratio of the entire diameter area of the pores 3 to the crystal growth surface is extremely small.
[0037]
Therefore, the dislocation density of threading dislocations in the formed thick film 5 is extremely low, and the crystallinity of the thick film 5 is of high quality as a whole.
The second semiconductor material to be used is selected in relation to an optical element or an electronic device to be manufactured via the laminated structure of the present invention. For example, GaN is used for the purpose of manufacturing a GaN-based device. Can be.
[0038]
Then, for example, the first semiconductor material as described above is selected in relation to the second semiconductor material.
Although the above description has been made with reference to GaN-based materials, the semiconductor material used in the present invention is not limited to this, and other nitride-based III-V compound semiconductors such as AlGaN, AlInGaN, and AlInGaNAsP can be used. You may.
[0039]
【Example】
First, a Si substrate whose surface was chemically etched with hydrofluoric acid was prepared. The Si substrate was set in an MOCVD apparatus, and operated at a substrate temperature of 400 ° C. under the conditions that SiH 4 and O 2 were supplied at a flow rate of 15 sccm and 30 sccm, respectively, to form a plasma, and a 100 nm thick SiO 2 thin film was formed.
[0040]
In another experiment, a SiO 2 thin film was formed under the same conditions, and its surface and cross section were observed by SEM. As a result, fine holes having a diameter of 5 to 10 nm were formed in the thin film up to the surface of the Si substrate. And the integrated value of the diameter area of these fine pores was about 10% with respect to the whole area of the SiO 2 thin film.
The inside of the apparatus was evacuated to a degree of vacuum of 5 × 10 −6 Pa or less by a turbo pump, then the degree of vacuum was increased to 1 Pa, and the substrate temperature was raised to 800 ° C.
[0041]
Then, while rotating the substrate at 900 rpm, the substrate surface was coated with TMG (58 nmol / min) as the Ga source, TMA (58 nmol / min) as the Al source, and NH 3 (12 l / min) as the N source for 4 minutes. Supplied. This supply amount corresponds to the amount of crystal growth of AlGaN having a thickness of 50 nm.
Then, the substrate temperature was raised to 1300 ° C., supply of TMA was stopped, and GaN was grown for 15 minutes to form a thick film having a thickness of 500 nm.
[0042]
The substrate was taken out of the apparatus and the GaN thick film was visually observed. The surface was extremely flat and had a metallic glossy mirror surface.
When the optical characteristics of the GaN thick film were examined by photoluminescence (PL), the emission intensity at the band edge (365 nm) was remarkably strong, and emission at a deep level was hardly observed. Thus, it was confirmed that the GaN crystal in the GaN thick film was of high quality.
[0043]
【The invention's effect】
As apparent from the above description, according to the present invention, it is possible to manufacture a laminated structure having a high-quality and thick semiconductor layer. In particular, by applying the present invention to a GaN-based material, a high-quality GaN layer can be formed in a thick film, and thus, for example, it is possible to manufacture an electronic device that operates with high withstand voltage and low on-resistance. it can.
[0044]
Further, since the diameter of pores in the insulating thin film can be reduced to several tens of nm or less, in the formed thick film, the area that can be effectively used as a device is less likely to be restricted, and as described in Patent Document 1. The effect of eliminating the need for a lithography operation for a simple mask is obtained.
[Brief description of the drawings]
FIG. 1 is a sectional view showing an example of a laminated structure of the present invention.
FIG. 2 is a cross-sectional view showing a state where an insulating thin film is formed on a substrate.
FIG. 3 is a cross-sectional view showing a state where a SiO 2 thin film is formed on a substrate.
FIG. 4 is a sectional view showing a state in which a metal is directly attached to an insulating thin film.
FIG. 5 is a cross-sectional view showing a state where holes are formed in the SiO 2 thin film by heating the intermediate of FIG. 4;
FIG. 6 is a cross-sectional view showing a state in which holes of a SiO 2 thin film are partially filled with a first semiconductor material.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Substrate 1a Surface 1 of substrate 1 Insulating thin film 2a Surface of insulating thin film 2 Hole 3a Portion of remaining hole 4 Buffer layer (first semiconductor material)
5 Thick film (second semiconductor material)

Claims (12)

基板と、前記基板の表面に成膜され、かつ前記基板の表面にまで至る空孔が分布している絶縁薄膜と、前記基板と前記絶縁薄膜を覆う半導体材料から成る層とを備えていることを特徴とする半導体材料の積層構造。A substrate, an insulating thin film formed on the surface of the substrate and having holes distributed to the surface of the substrate, and a layer made of a semiconductor material that covers the substrate and the insulating thin film. A laminated structure of a semiconductor material characterized by the above-mentioned. 前記絶縁薄膜は酸化物から成る請求項1の半導体材料の積層構造。2. The laminated structure according to claim 1, wherein said insulating thin film is made of an oxide. 前記絶縁薄膜は、SiO,Al、またはTaOxから成る請求項2の半導体材料の積層構造。 3. The laminated structure according to claim 2 , wherein the insulating thin film is made of SiO 2 , Al 2 O 3 , or TaOx. 前記空孔は、前記絶縁薄膜の一部分が還元され、前記一部分が脱離して形成された痕跡である請求項2または3の半導体材料の積層構造。The laminated structure of a semiconductor material according to claim 2, wherein the vacancy is a trace formed by reducing a part of the insulating thin film and removing the part. 前記絶縁薄膜の一部分を還元する物質が金属原子である請求項4の半導体材料の積層構造。The laminated structure of a semiconductor material according to claim 4, wherein the substance that reduces a part of the insulating thin film is a metal atom. 前記金属原子は、InまたはGaである請求項5の半導体材料の積層構造。The laminated structure of a semiconductor material according to claim 5, wherein the metal atom is In or Ga. 基板の上に、前記基板の表面にまで至る空孔が分布する絶縁薄膜を形成する工程、および、
前記絶縁薄膜をマスクとして使用する選択横方向成長法で、半導体材料を前記絶縁薄膜の空孔内と表面にエピタキシャル成長させる工程を備えていることを特徴とする半導体材料の積層構造の製造方法。
Forming on the substrate an insulating thin film in which holes reaching the surface of the substrate are distributed, and
A method for manufacturing a laminated structure of a semiconductor material, comprising a step of epitaxially growing a semiconductor material in holes and on a surface of the insulating thin film by a selective lateral growth method using the insulating thin film as a mask.
前記基板の上に絶縁薄膜を成膜したのち、前記絶縁薄膜の表面に前記絶縁薄膜を還元する物質を部分的に堆積し、ついで全体を昇温して前記物質が堆積している箇所の絶縁薄膜を還元し、その反応生成物を脱離させて空孔を形成する工程を含む請求項7の半導体材料の積層構造の製造方法。After forming an insulating thin film on the substrate, a substance for reducing the insulating thin film is partially deposited on the surface of the insulating thin film, and then the whole is heated to insulate the portion where the substance is deposited. 8. The method according to claim 7, further comprising the step of reducing the thin film and desorbing the reaction product to form voids. 絶縁薄膜を還元する物質が金属原子である請求項8の半導体材料の積層構造の製造方法。9. The method according to claim 8, wherein the substance that reduces the insulating thin film is a metal atom. 前記金属原子がInまたはGaである請求項9の半導体材料の積層構造の製造方法。10. The method according to claim 9, wherein the metal atom is In or Ga. 前記金属原子の堆積の厚みは、10原子層以下の厚みである請求項9または10の半導体材料の積層構造の製造方法。11. The method according to claim 9, wherein the deposition thickness of the metal atoms is 10 atomic layers or less. 前記絶縁薄膜の成膜、前記空孔の形成、前記半導体材料のエピタキシャル成長は、いずれも同一の装置を用いて行われる請求項7の半導体材料の積層構造の製造方法。8. The method according to claim 7, wherein the formation of the insulating thin film, the formation of the holes, and the epitaxial growth of the semiconductor material are all performed using the same apparatus.
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