JP2004134685A - Solid state imaging device and its fabricating method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid state imaging device in which the image quality of a reproduction screen is prevented from deteriorating by reducing a leak current being generated as the interface level increases due to crystal defect, or the like, in the vicinity of the substrate surface in a region where a photodiode is fabricated. <P>SOLUTION: The solid state imaging device is characterized by being provided with a first conductivity type semiconductor region 301, a second conductivity type signal storage region 302 for storing signal charges formed in the first conductivity type semiconductor region 301, and a gate electrode 305 formed on the first conductivity type semiconductor region 301 through a gate insulating film 304 to cover a region above the second conductivity type signal storage region 302. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a solid-state imaging device, and more particularly to an electrode structure of a reading transistor for reading a signal from a signal accumulation region.
[0002]
[Prior art]
As a solid-state imaging device, a CCD solid-state imaging device and a MOS solid-state imaging device are known. In recent years, in MOS type solid-state imaging devices, various peripheral circuits such as an image sensor, a scanning circuit, a register circuit, a timing circuit, an A / D conversion circuit, and a DSP are simultaneously formed on the same substrate by a CMOS process to reduce the system size and process. We are reducing the number. Further, in the imaging device and other peripheral circuits, further miniaturization in the horizontal and vertical directions is being promoted with respect to the upper surface of the substrate.
[0003]
FIG. 14 is a plan view showing a layout of a unit cell in a conventional solid-state imaging device. FIG. 15 is a cross-sectional view of a main part taken along line AA of the solid-state imaging device in FIG. FIG. 16 shows another example, and is a cross-sectional view of a principal part taken along line AA of the solid-state imaging device in FIG. Here, the unit cell includes a photodiode for accumulating a signal, a reading transistor for reading a signal, an amplifying transistor for amplifying a signal, a vertical selection transistor for selecting a line from which a signal is read, and a reset transistor for resetting a signal charge of the photodiode. It is configured.
[0004]
As shown in FIG. 14, a drain 1406 extends from the photodiode 1401, and below the drain 1406, a read gate 1402, a reset gate 1405, an amplification gate 1403, and a horizontal address gate 1404 are arranged in this order from the photodiode 1401 side. It is formed perpendicular to the drain 1406. As shown in FIG. 15, a signal accumulation region 1408 and an element isolation region 1410 are formed in a P well 1407 formed on a semiconductor substrate (not shown), and a gate insulating film 1409 is formed on the P well 1407. A read gate 1402 is formed. Further, a reset gate 1405 is formed apart from the read gate 1402. By turning on the read gate 1402, signal charges accumulated in the signal accumulation region 1408 can be read.
[0005]
FIG. 16 shows another example of a solid-state imaging device having a shield region on a signal accumulation region. As shown in FIG. 16, a signal accumulation region 1408 is formed in a P well 1407 formed on a semiconductor substrate (not shown), and a shield region 1411 is formed in a P well surface region on the signal accumulation region 1408. I have. The shield region 1411 is connected to an element isolation region 1410 formed in the P well 1407. Further, a read gate 1402 is formed over the P well 1407 with a gate insulating film 1409 interposed therebetween. Further, a reset gate 1405 is formed apart from the read gate 1402.
[0006]
Since the shield region 1411 is in contact with the element isolation region 1410 and is grounded, the provision of the shield region 1411 makes it difficult to accumulate noise charges generated on the substrate surface in the photodiode. In addition, the signal charge can be read by a read gate from a portion of the signal accumulation region 1408 where the shield region 1411 is not formed above.
[0007]
Next, a method for manufacturing the solid-state imaging device shown in FIG. 15 will be described with reference to FIGS. As shown in FIG. 17A, an element isolation region 1410 such as STI (Shallow Trench Isolation) is formed in a P well 1407 formed on a semiconductor substrate (not shown). A gate insulating film 1409 is formed over the P well 1407. Next, as shown in FIG. 17B, a polysilicon layer 1412 is formed on the gate insulating film 1409. Next, as shown in FIG. 18C, a resist is applied on the polysilicon layer 1412, and a resist pattern 1413a is formed on a region where a read gate is to be formed. A read gate 1402 is formed by isotropic dry etching (RIE). Next, as shown in FIG. 18D, the resist pattern 1413a is removed, a resist pattern 1413b having an opening in a region where a signal accumulation region is to be formed is formed, and N-type impurities are ion-implanted. , A signal accumulation region 1408 is formed in the surface region of the P well 1407.
[0008]
A method of manufacturing the solid-state imaging device shown in FIG. 16 which is another example will be described with reference to FIGS. As shown in FIG. 19A, an element isolation region 1410 such as STI (Shallow Trench Isolation) is formed in a P well 1407 formed on a substrate (not shown). Next, a resist pattern 1413c having an opening in a region where a signal accumulation region is to be formed is formed, and an N-type impurity is ion-implanted to form a signal accumulation region 1408 in the P well 1407. Next, as shown in FIG. 19B, the resist pattern 1413c is removed, a resist pattern 1413d having an opening in a region where a shield region is to be formed is formed, and then a P-type impurity is ion-implanted. Thus, a shield region 1411 is formed in the surface region of the P well 1407.
[0009]
Next, as shown in FIG. 20C, the resist pattern 1413d is removed, a gate insulating film 1409 is formed on the P well 1407, and a polysilicon layer 1412 is formed on the gate insulating film 1409. Next, as shown in FIG. 20D, a resist is applied on the polysilicon layer 1412, and a resist pattern 1413e is formed on a region where a read gate is to be formed. The read gate 1402 is formed by isotropic dry etching. This type of solid-state imaging device is described in, for example, Patent Document 1.
[0010]
[Patent Document 1]
JP 2000-150847 A (FIG. 2)
[0011]
[Problems to be solved by the invention]
The above-described solid-state imaging device is an analog circuit, and there is a problem in that sensitivity is reduced due to noise. One of the main causes of noise is leakage current generated by photodiodes that store signals. This leakage current is caused by crystal defects, disordered crystal arrangement, and heavy metal contamination near the surface of the semiconductor substrate. This is caused by an increase in levels and generation of false signal charges. Noise on the reproduction screen caused by the generation of the leak current significantly degrades the image quality.
[0012]
In the solid-state imaging device described above, a circuit such as a DSP is simultaneously formed in another region on the substrate by a CMOS process, and further miniaturization in the vertical and horizontal directions is being promoted. As further miniaturization progresses, films such as gate insulating films are also formed to be thinner.
[0013]
18C and FIG. 20D, when the polysilicon layer 1412 is etched by anisotropic dry etching in FIG. 18C and FIG. As indicated by the broken line, there is a problem that the vicinity of the surface of the P well 1407 is easily damaged. Until now, this was dealt with by selecting the etching conditions (such as the etching ratio) so as not to cause large damage near the surface of the P well 1407. However, as the gate insulating film is further reduced in thickness, However, there is a possibility that the problem cannot be solved by selecting the etching conditions. Large damage that occurs near the surface of the P-well 1407 causes crystal defects and disordered crystal arrangement, and generates a leak current due to an increase in interface states.
[0014]
The present invention has been made to solve the above-described problems, and it is possible to reduce the occurrence of leakage current due to damage near the substrate surface caused by an impact such as dry etching and to suppress the deterioration of the image quality of a reproduced screen. It is an object of the present invention to provide a solid-state imaging device.
[0015]
[Means for Solving the Problems]
One embodiment of the solid-state imaging device of the present invention for achieving the above object includes a first conductivity type semiconductor region,
A second conductivity type signal storage region formed in the first conductivity type semiconductor region for storing signal charges;
A gate electrode formed on the first conductivity type semiconductor region via a gate insulating film, and formed to cover a region on the second conductivity type signal accumulation region.
[0016]
According to another embodiment of the present invention, there is provided a solid-state imaging device which includes a photoelectric conversion unit having a signal accumulation region, a reading transistor which reads a signal charge from the photoelectric conversion unit by a gate electrode, and a device which discharges the signal charge. An imaging region configured by arranging a plurality of unit cells having at least a reset transistor,
In a solid-state imaging device having a peripheral circuit portion disposed around the imaging region,
A gate electrode of the read transistor is formed so as to cover the photoelectric conversion unit.
[0017]
One embodiment of a method for manufacturing a solid-state imaging device according to the present invention for achieving the above object includes a step of forming a second conductivity type signal accumulation region for accumulating signal charges in a first conductivity type semiconductor region;
Forming a conductor on the first conductivity type semiconductor region via a gate insulating film, and forming a gate electrode covering the region on the second conductivity type signal accumulation region by dry etching the conductor; And characterized in that:
[0018]
According to one embodiment of the present invention, since the gate electrode is formed so as to cover at least a region on the signal accumulation region, a crystal defect or a crystal array is formed near the substrate surface in the region where the photodiode is formed. It is possible to provide a solid-state imaging device and a method of manufacturing the solid-state imaging device, which hardly cause disturbance of the image, reduce a leak current generated due to an increase in interface state, and can suppress deterioration of image quality of a reproduction screen.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
(First Embodiment)
1 to 7 show a solid-state imaging device according to a first embodiment of the present invention.
FIG. 2 is a diagram illustrating a circuit configuration of a unit cell of the solid-state imaging device, and FIG. 3 is a plan view illustrating a layout of the unit cell of the solid-state imaging device. Here, the unit cell includes a photodiode that is a photoelectric conversion unit that stores a signal, a readout transistor that is a signal scanning circuit unit that reads out a signal, an amplification transistor that amplifies a signal, a vertical selection transistor that selects a line that reads out a signal, It is composed of a reset transistor that resets the signal charge of the photodiode.
[0020]
As shown in FIG. 2, by turning on the gate (reading gate) of the reading transistor 2, the signal of the photodiode 1 in which the signal charge is accumulated is read. The horizontal address line 6 wired in the horizontal direction is connected to the gate (horizontal address gate) of the vertical selection transistor 4 and selects a line from which a signal is read. The reset address line 7 is connected to the gate of the reset transistor 5 (reset gate). The gate of the amplification transistor 3 (amplification gate) is connected to the drain of the read transistor 2, and the source of the amplification transistor 3 is connected to the source of the vertical selection transistor 4. The drain of the amplification transistor 3 is connected to the V _DD It is connected to the.
[0021]
As shown in FIG. 3, a drain 9-1 extends from the photodiode 1-1, and a read gate 2-1 and a reset gate 7-1 are arranged below the drain 9-1 in order from the photodiode 1-1. , An amplification gate 3-1 and a horizontal address gate 6-1 are formed perpendicular to the drain 9-1.
[0022]
FIG. 1 is a cross-sectional view of a principal part taken along line AA of the solid-state imaging device in FIG. As shown in FIG. 1, a signal accumulation region 302 is formed in a P well 301 formed on a semiconductor substrate (not shown), and a shield region 303 is formed in a surface region of the P well 301 on a part of the signal accumulation region 302. Is formed. Further, an element isolation region 307 is formed so as to be in contact with the shield region 303. On the P well 301, a read gate 305 is formed via a gate insulating film 304, and a reset gate 306 is formed separately from the read gate 305. A photodiode serving as a photoelectric conversion unit includes a P-well 301 and a signal accumulation region 302. Here, the P well 301 is not limited to a well formed on a semiconductor substrate, and may be a P-type semiconductor substrate. Since the shield region 303 is in contact with the element isolation region 307 and is grounded, the provision of the shield region 303 makes it difficult to accumulate noise charges generated on the substrate surface in the photodiode. In addition, signal charges can be read from a portion of the signal accumulation region 302 where the shield region 303 is not formed on the upper portion by turning on a read gate.
[0023]
The read gate 305 is formed so as to extend at least to cover a region on the signal accumulation region 302 and the shield region 303. The end of the read gate 305 is formed on the element isolation region 307, and is arranged on the element isolation region 307 with a matching margin of about 0.1 μm to 0.2 μm. The read gate 305 may be formed so as to extend at least to cover a region on the signal accumulation region 302 and the shield region 303. However, when the read gate 305 is dry-etched, Since there is a possibility that etching damage occurring in the formed region may enter the internal element formation region, the edge of the read gate 305 is slightly overlaid on the element isolation region 307 by about 0.1 μm to 0.2 μm. It is preferable to be arranged to have.
[0024]
FIG. 4 shows an outline of a basic configuration of the solid-state imaging device. An imaging region in which a plurality of unit cells are arranged is formed on the same substrate, and various circuits such as a scanning circuit, an AD conversion circuit, and a DSP are formed around the imaging region. These circuits are formed simultaneously by a CMOS process.
[0025]
Next, a method for manufacturing the solid-state imaging device shown in FIG. 1 according to the present embodiment will be described with reference to FIGS. As shown in FIG. 5A, an element isolation region 307 such as STI (Shallow Trench Isolation) is formed in a P well 301 formed on a substrate (not shown) by using an insulating film such as an oxide film. Next, a resist pattern 308a having an opening in a region where a signal accumulation region is to be formed is formed, and an N-type impurity is ion-implanted to form a signal accumulation region 302 in the P well 301. Next, as shown in FIG. 5B, the resist pattern 308a is removed, a resist pattern 308b having an opening in a region where a shield region is to be formed is formed, and P-type impurities are ion-implanted. A shield region 303 is formed in a surface region of the P well 301.
[0026]
Next, as shown in FIG. 6C, the resist pattern 308b is removed, a gate insulating film 304 is formed on the P well 301, and a polysilicon layer 309 is formed on the gate insulating film 304. The gate insulating film 304 can be formed with a thickness of 8 nm or less. Here, the thickness of the gate insulating film 304 is about 7 nm. Alternatively, a thin film having a thickness smaller than that may be used. The gate insulating film may be formed to have a thickness (for example, about 2.5 μm) which is the same as the thickness of a gate insulating film formed in a peripheral circuit portion such as a DSP. Next, as shown in FIG. 6D, a resist is applied on the polysilicon layer 309, and a resist pattern 308c is formed in at least a region where a read gate and a shield region are to be formed and a region on the signal accumulation region 302. I do. Subsequently, the polysilicon layer 309 is subjected to anisotropic dry etching to form a read gate 305. At this time, another gate, such as a reset gate 306, is formed at the same time.
[0027]
In the present embodiment, the read gate 305 is formed so as to extend at least to cover a region on the signal accumulation region 302 and the shield region 303. Therefore, when the read gate 305 is dry-etched, almost no damage occurs in the region covered with the read gate 305, and therefore, in the vicinity of the substrate surface in the region where the photodiode is formed, crystal defects and crystal arrangements are reduced. The structure is not easily disturbed. Therefore, it is not necessary to add a step, and it is possible to easily reduce a leak current generated due to an increase in interface states, and to suppress a deterioration in image quality of a reproduced screen. Further, since the end of the read gate 305 is formed on the element isolation region 307 with an alignment margin of about 0.1 μm to 0.2 μm, the etching generated in the region where the end of the read gate 305 is formed Damage can be suppressed from entering the internal element formation region, and the leakage current can be more reliably reduced, and deterioration in the image quality of the reproduced screen can be suppressed. In the vicinity of the surface of the P well 301 where the signal accumulation region 302 is not formed, since the charge accumulation time is short, almost no leak current occurs due to an increase in the interface state.
[0028]
In this embodiment, an example in which the shield region is formed so as to be in contact with the element isolation region has been described. However, the present embodiment can be applied to a case where the shield region is not formed as shown in FIG. In the solid-state imaging device having such a configuration, since damage near the substrate surface due to dry etching is directly applied to the signal accumulation region, crystal defects and crystal arrangement disorder are large, and a large amount of leak current is generated. Since the read gate 305 is formed so as to cover at least a region on the signal accumulation region 302, when the read gate 305 is dry-etched, almost no damage occurs in the region covered by the read gate 305. Therefore, a structure in which a crystal defect and a disorder of a crystal arrangement do not easily occur near the substrate surface in a region where the photodiode is formed. Therefore, it is possible to easily reduce the leak current generated due to the increase of the interface state without adding a process, and to suppress the deterioration of the image quality of the reproduction screen.
[0029]
Further, it is preferable that an end of the read gate 305 is formed on the element isolation region 307 with an alignment margin of about 0.1 μm to 0.2 μm. As described above, by disposing the end of the read gate 305 on the element isolation region 307 so as to have an alignment margin of about 0.1 μm to 0.2 μm, the end of the read gate 305 is formed in a region where the end of the read gate 305 is formed. The generated etching damage can be prevented from entering the internal element formation region, so that the leak current can be reduced more surely and the deterioration of the image quality of the reproduction screen can be suppressed.
(Second embodiment)
8 to 13 show a solid-state imaging device according to a second embodiment of the present invention. The circuit configuration of the unit cell of the solid-state imaging device is the same as that of the first embodiment shown in FIG. FIG. 8 is a plan view showing a layout of a unit cell of the solid-state imaging device.
[0030]
As shown in FIG. 8, a drain 9-1 extends from the photodiode 1-1, and a read gate 2-1 and a reset gate 7-1 are arranged below the drain 9-1 in order from the photodiode 1-1. , An amplification gate 3-1 and a horizontal address gate 6-1 are formed perpendicular to the drain 9-1.
[0031]
FIG. 9 is a cross-sectional view of a principal part taken along line AA of the solid-state imaging device in FIG. As shown in FIG. 9, a signal accumulation region 302 is formed in a P well 301 formed on a semiconductor substrate (not shown), and a shield region 303 is formed in a surface region of the P well 301 on a part of the signal accumulation region 302. Is formed. Further, an element isolation region 307 is formed so as to be in contact with the shield region 303. On the P well 301, a read gate 305 is formed via a gate insulating film 304, and a reset gate 306 is formed separately from the read gate 305. A recess 901 is formed in the read gate 305. A photodiode serving as a photoelectric conversion unit includes a P-well 301 and a signal accumulation region 302.
[0032]
Here, the P well 301 is not limited to a well formed on a semiconductor substrate, and may be a P-type semiconductor substrate. Since the shield region 303 is in contact with the element isolation region 307 and is grounded, the provision of the shield region 303 makes it difficult to accumulate noise charges generated on the substrate surface in the photodiode. In addition, signal charges can be read from a portion of the signal accumulation region 302 where the shield region 303 is not formed on the upper portion by turning on a read gate. The read gate 305 is formed so as to extend at least to cover a region on the signal accumulation region 302 and the shield region 303. The end of the read gate 305 is formed on the element isolation region 307, and is arranged on the element isolation region 307 with a matching margin of about 0.1 μm to 0.2 μm. The read gate 305 may be formed so as to extend at least to cover a region on the signal accumulation region 302 and the shield region 303. However, when the read gate 305 is dry-etched, Since there is a possibility that etching damage occurring in the formed region may enter the internal element formation region, the edge of the read gate 305 is slightly overlaid on the element isolation region 307 by about 0.1 μm to 0.2 μm. It is preferable to be arranged to have.
[0033]
In addition, a concave portion 901 is formed on the surface of the read gate 305. The thickness of the read gate 305 is, for example, 200 nm, and the thickness of the recess 901 is, for example, 50 nm. With the readout gate 305 having a thickness of about 200 nm or less, even if the light has short absorption wavelength (blue light), deterioration of sensitivity due to absorption is small. In order to prevent etching damage from entering the inside, the thickness of the concave portion 901 is preferably 10 nm or more. Therefore, by forming the concave portion 901 having a thickness of 50 nm, in the vicinity of the substrate surface in the region where the photodiode is formed, it is difficult to cause crystal defects and disorder of the crystal arrangement, and short wavelength light having a large absorption coefficient is used. The sensitivity of light (blue light) can be further improved.
[0034]
In addition, the concave portion 901 may be formed in another region except for a part of the readout gate 305 having a function as a control electrode, or may be formed only in a region corresponding to a condensing region of a lens. Good. Further, as shown in FIG. 10, the recess 901 may have a region where the thickness of the gate electrode is thinner than other regions, and is not limited to the concave shape, and may be a step having an L-shaped cross section. .
[0035]
The diagram showing the outline of the basic configuration of the solid-state imaging device is the same as the diagram shown in the first embodiment. An imaging region in which a plurality of unit cells are arranged is formed on the same substrate, and various circuits such as a scanning circuit, an AD conversion circuit, and a DSP are formed around the imaging region. These circuits are formed simultaneously by a CMOS process.
[0036]
A method for manufacturing the solid-state imaging device shown in FIG. 9 according to the present embodiment will be described with reference to FIGS. As shown in FIG. 11A, an element isolation region 307 such as an STI (Shallow Trench Isolation) is formed in a P well 301 formed on a substrate (not shown) using an insulating film such as an oxide film. Next, a resist pattern 308a having an opening in a region where a signal accumulation region is to be formed is formed, and an N-type impurity is ion-implanted to form a signal accumulation region 302 in the P well 301. Next, as shown in FIG. 11B, the resist pattern 308a is removed, a resist pattern 308b having an opening in a region where a shield region is to be formed is formed, and a P-type impurity is ion-implanted. A shield region 303 is formed in a surface region of the P well 301.
[0037]
Next, as shown in FIG. 12C, the resist pattern 308b is removed, a gate insulating film 304 is formed on the P well 301, and a polysilicon layer 309 is formed on the gate insulating film 304. The gate insulating film 304 can be formed with a thickness of 8 nm or less. Here, the thickness of the gate insulating film 304 is about 7 nm. Alternatively, a thin film having a thickness smaller than that may be used. The gate insulating film may be formed to have a thickness (for example, about 2.5 μm) which is the same as the thickness of a gate insulating film formed in a peripheral circuit portion such as a DSP. Next, as shown in FIG. 12D, a resist is applied on the polysilicon layer 309, and a resist pattern 308c is formed in at least a region where a read gate and a shield region are to be formed and a region on the signal accumulation region 302. I do. Subsequently, the polysilicon layer 309 is subjected to anisotropic dry etching to form a read gate 305. At this time, another gate, such as a reset gate 306, is formed at the same time. Next, as shown in FIG. 12E, a resist pattern 308d is formed so that a part of the readout gate 305 is exposed, and half etching is performed to form a concave portion 901 having a thickness of about 50 nm in the readout gate 305. I do. Subsequently, the resist pattern is removed. Half-etching is an etching method for etching the readout gate 305 so that the gate insulating film 304 formed thereunder is not exposed, and can be usually formed by performing time control.
[0038]
In the present embodiment, the read gate 305 is formed so as to extend at least to cover a region on the signal accumulation region 302 and the shield region 303. Further, a concave portion 901 is formed in the read gate 305. Therefore, when the read gate 305 is dry-etched, almost no damage occurs in the region covered with the read gate 305, and therefore, in the vicinity of the substrate surface in the region where the photodiode is formed, crystal defects and crystal arrangements are reduced. It has a structure that does not easily cause disturbance. Therefore, it is possible to reduce the leak current generated due to the increase in the interface state, and to suppress the deterioration of the image quality of the reproduction screen.
[0039]
Further, since a thin region is formed in a part of the readout gate 305, sensitivity of short-wavelength light (blue light) having a large absorption coefficient can be further improved. Further, since the end of the read gate 305 is formed on the element isolation region 307 with an alignment margin of about 0.1 μm to 0.2 μm, the etching generated in the region where the end of the read gate 305 is formed Damage can be suppressed from entering the internal element formation region, and the leakage current can be more reliably reduced, and deterioration in the image quality of the reproduced screen can be suppressed. In the vicinity of the surface of the P well 301 where the signal accumulation region 302 is not formed, since the charge accumulation time is short, almost no leak current occurs due to an increase in the interface state.
[0040]
In this embodiment, an example in which the shield region is formed so as to be in contact with the element isolation region is described. However, the present embodiment can be applied to a case where the shield region is not formed as shown in FIG. In the solid-state imaging device having such a configuration, since damage near the substrate surface due to dry etching is directly applied to the signal accumulation region, crystal defects and crystal arrangement disorder are large, and a large amount of leak current is generated. The read gate 305 is formed so as to cover at least a region on the signal accumulation region 302. When the read gate 305 is dry-etched, almost no damage occurs in the region covered by the read gate 305, and crystal defects and disorder of the crystal arrangement occur near the substrate surface in the region where the photodiode is formed. It has a difficult structure. Therefore, it is possible to greatly reduce the leak current generated due to the increase in the interface state, and to suppress the deterioration of the image quality of the reproduction screen. Further, since a thin region is formed in a part of the readout gate 305, sensitivity of short-wavelength light (blue light) having a large absorption coefficient can be further improved.
[0041]
Further, it is preferable that an end of the read gate 305 is formed on the element isolation region 307 with an alignment margin of about 0.1 μm to 0.2 μm. As described above, by disposing the end of the read gate 305 on the element isolation region 307 so as to have an alignment margin of about 0.1 μm to 0.2 μm, the end of the read gate 305 is formed in a region where the end of the read gate 305 is formed. The generated etching damage can be prevented from entering the internal element formation region, so that the leak current can be reduced more surely and the deterioration of the image quality of the reproduction screen can be suppressed.
[0042]
【The invention's effect】
As described above in detail, according to the present invention, in the vicinity of the substrate surface in the region where the photodiode is formed, crystal defects and disorder of the crystal arrangement are less likely to occur, and the leakage current generated by the increase in the interface state is reduced. However, it is possible to suppress the deterioration of the image quality of the reproduction screen.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a principal part along AA of the solid-state imaging device shown in FIG. 3 according to a first embodiment of the present invention;
FIG. 2 is a diagram showing a circuit configuration of a unit cell in the solid-state imaging device according to the first and second embodiments of the present invention.
FIG. 3 is a diagram illustrating a layout of unit cells in the solid-state imaging device according to the first embodiment of the present invention;
FIG. 4 is a diagram illustrating an outline of a basic configuration of solid-state imaging devices according to first and second embodiments of the present invention.
5 is a fragmentary cross-sectional view showing a part of steps of a method for manufacturing the solid-state imaging device shown in FIG. 3 according to the first embodiment of the present invention.
6 is a fragmentary cross-sectional view showing part of a step in a method for manufacturing the solid-state imaging device shown in FIG. 3 according to the first embodiment of the present invention.
FIG. 7 is a cross-sectional view of a principal part along AA of another solid-state imaging device shown in FIG. 2 according to the first embodiment of the present invention;
FIG. 8 is a diagram showing a layout of unit cells in a solid-state imaging device according to a second embodiment of the present invention.
FIG. 9 is a cross-sectional view of a principal part along AA of the solid-state imaging device shown in FIG. 8 according to the second embodiment of the present invention;
FIG. 10 is a cross-sectional view of a principal part along AA of another solid-state imaging device shown in FIG. 8 according to the second embodiment of the present invention;
FIG. 11 is a cross-sectional view of a principal part showing a part of steps of a method of manufacturing the solid-state imaging device shown in FIG. 8 according to the second embodiment of the present invention.
FIG. 12 is a cross-sectional view of a principal part showing a part of steps of a method of manufacturing the solid-state imaging device shown in FIG. 8 according to the second embodiment of the present invention.
FIG. 13 is a cross-sectional view of a principal part along AA of another solid-state imaging device shown in FIG. 8 according to the second embodiment of the present invention;
FIG. 14 is a diagram showing a layout of a unit cell in a conventional solid-state imaging device.
FIG. 15 is a cross-sectional view of a main part of the conventional solid-state imaging device shown in FIG.
FIG. 16 is a cross-sectional view of a main part along AA of another solid-state imaging device shown in FIG. 14 of the related art.
17 is a fragmentary cross-sectional view showing a part of the process of the method of manufacturing the solid-state imaging device shown in FIG. 15 in the related art.
18 is a fragmentary cross-sectional view showing a part of the process of the method of manufacturing the solid-state imaging device shown in FIG. 15 of the related art.
19 is a fragmentary cross-sectional view showing part of a step in a method for manufacturing the solid-state imaging device shown in FIG. 16 of the conventional technique.
20 is a fragmentary cross-sectional view showing a part of the process of the method of manufacturing the solid-state imaging device shown in FIG. 16 in the related art.
[Explanation of symbols]
1,1-1 ... photodiode
2 ... Readout transistor
2-1 305 read gate
3 ... amplifying transistor
3-1 ... Amplification gate
4 ... vertical select transistor
5 ... Reset transistor
6 ... horizontal address line
6-1 Horizontal address gate
7 ... Reset address line
7-1, 306: Reset gate
8 ... vertical signal line
9 Power supply
9-1 ・ ・ ・ Drain
301 ... P well
302: signal storage area
303: shield area
304 ・ ・ ・ Gate insulating film
307 ・ ・ ・ Element isolation region
308 ・ ・ ・ Resist pattern
309: polysilicon layer
901... Recess of readout gate

Claims (13)

A first conductivity type semiconductor region;
A second conductivity type signal storage region formed in the first conductivity type semiconductor region for storing signal charges;
A solid-state imaging device comprising: a gate electrode formed on the first conductivity type semiconductor region via a gate insulating film; and a gate electrode formed to cover a region on the second conductivity type signal accumulation region. A first conductivity type semiconductor region;
A second conductivity type signal storage region formed in the first conductivity type semiconductor region for storing signal charges;
A first conductivity type shield region having a higher impurity concentration than the first conductivity type semiconductor region, formed on a surface region of the first conductivity type semiconductor region on the second conductivity type signal accumulation region;
A gate electrode formed on the first conductive type semiconductor region with a gate insulating film interposed therebetween, and a gate electrode formed to cover the second conductive type signal accumulation region and a region on the first conductive type shield region; A solid-state imaging device characterized by the above-mentioned. 3. The solid-state imaging device according to claim 1, wherein the thickness of the gate insulating film is 8 nm or less. An imaging region configured by arranging a plurality of unit cells each including at least a photoelectric conversion unit having a signal accumulation region for accumulating signal charges and a readout transistor reading signal charges from the photoelectric conversion unit with a gate electrode,
In a solid-state imaging device having a peripheral circuit portion disposed around the imaging region,
A solid-state imaging device, wherein a gate electrode of the read transistor is formed so as to cover the signal accumulation region of the photoelectric conversion unit. The photoelectric conversion unit,
A first conductivity type semiconductor region;
5. The solid-state imaging device according to claim 4, wherein the solid-state imaging device includes a second conductivity type signal storage region formed in the first conductivity type semiconductor region and storing signal charges. The photoelectric conversion unit,
A first conductivity type semiconductor region;
A second conductivity type signal storage region formed in the first conductivity type semiconductor region for storing signal charges;
The first conductivity type shield region having a higher impurity concentration than the first conductivity type semiconductor region is formed on the surface region of the first conductivity type semiconductor region on the second conductivity type signal accumulation region. The solid-state imaging device according to claim 4, wherein: 7. The gate electrode according to claim 1, wherein the gate electrode on at least a part of the signal storage region is formed thinner than other parts, and a step is formed on a surface of the gate electrode. A solid-state imaging device according to any one of the above. The solid-state imaging device according to claim 7, wherein a thickness of the gate electrode portion formed to be thin is 10 nm or more and 200 nm or less. The solid-state imaging device according to claim 1, wherein an end of the gate electrode is formed on an element isolation region formed outside the signal accumulation region. Forming a second conductivity type signal storage region for storing signal charges in the first conductivity type semiconductor region;
Forming a conductor on the first conductivity type semiconductor region via a gate insulating film; and dry-etching the conductor to form a gate electrode covering a region on the second conductivity type signal accumulation region. And a method for manufacturing a solid-state imaging device. Forming a second conductivity type signal storage region for storing signal charges in the first conductivity type semiconductor region;
Forming a first conductivity type shield region having a higher impurity concentration than the first conductivity type semiconductor region in a surface region of the first conductivity type semiconductor region on the second conductivity type signal accumulation region;
Forming a conductor on the first conductivity type semiconductor region via a gate insulating film; and dry-etching the conductor to form a region on the second conductivity type signal accumulation region and the first conductivity type shield region. Forming a gate electrode covering the semiconductor device. Etching the gate electrode on at least a part of the signal storage region so that the gate insulating film is not exposed, and forming a step having a depression on a part of the surface of the gate electrode. The method for manufacturing a solid-state imaging device according to claim 10, wherein: 13. The solid-state imaging device according to claim 12, wherein in the step of forming a step in the gate electrode, etching is performed so that a thickness of a recessed and thinly formed portion of the gate electrode is 10 nm or more and 200 nm or less. Device manufacturing method.

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