JP2004119962A - ナノメートル・スケールの半導体デバイスと製造法 - Google Patents
ナノメートル・スケールの半導体デバイスと製造法 Download PDFInfo
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- JP2004119962A JP2004119962A JP2003293392A JP2003293392A JP2004119962A JP 2004119962 A JP2004119962 A JP 2004119962A JP 2003293392 A JP2003293392 A JP 2003293392A JP 2003293392 A JP2003293392 A JP 2003293392A JP 2004119962 A JP2004119962 A JP 2004119962A
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Abstract
【解決手段】 基板と、基板の上に配置された第1の極性のドーパントを含むベース・エピタキシャル半導体層と、前記基板の上に配置された第2の極性のドーパントを含む第1の半導体層と、前記ベース・エピタキシャル半導体層と前記第1の半導体層との間に形成された第1の接合であって、少なくとも1つの横寸法が約75ナノメートルよりも小さいエリアを持つ第1の接合と、を備える半導体デバイスを提供する。この半導体デバイスは、ベース・エピタキシャル半導体層の上に形成された第2の極性のドーパントを含む第2の半導体層と、ベース・エピタキシャル半導体層および第2の半導体層との間に形成された第2の接合であって、少なくとも1つの横寸法が約75ナノメートルよりも小さいエリアを持つ第2の接合を備える。
【選択図】図3
Description
214 ショットキー障壁
216 導電層
220 基板
226 誘電体層
232 第1の半導体層
242 ベース・エピタキシャル半導体層242
234 第1の接合
244 第2の接合
246 第2の半導体層
248 幅
249 長さ
Claims (18)
- 基板と、
前記基板の上に配置された第1の極性のドーパントを含むベース・エピタキシャル半導体層と、
前記基板の上に配置された第2の極性のドーパントを含む第1の半導体層と、
前記ベース・エピタキシャル半導体層と前記第1の半導体層との間に形成された第1の接合であって、少なくとも1つの横寸法が約75ナノメートルよりも小さいエリアを持つ第1の接合と、
を備える半導体デバイス。 - 前記ベース・エピタキシャル半導体層の上に形成された前記第2の極性のドーパントを含む第2の半導体層と、
前記ベース・エピタキシャル半導体層と前記第2の半導体層との間に形成された、長さおよび幅を持つ第2の接合であって、少なくとも1つの横寸法が約75ナノメートルよりも小さいエリアを持つ第2の接合と、
をさらに備える請求項1記載の半導体デバイス。 - 前記ベース・エピタキシャル半導体層の一部に対してオーミック・コンタクトを形成し、また前記第1の半導体層か、前記第2の半導体層のいずれかの一部に対してショットキー障壁を形成して、それにより、ショットキー・ダイオード・クランプ・バイポーラ接合トランジスタが形成される導電層をさらに備える請求項2記載の半導体デバイス。
- 前記基板が、前記第2の極性のドーパントを持って前記第1の半導体層を形成する半導体基板をさらに備える請求項1記載の半導体デバイス。
- 前記ベース・エピタキシャル半導体層が、互いにほぼ平行な複数のエピタキシャル半導体ベース・ラインをさらに備え、前記第1の半導体層は、互いにほぼ平行で、かつ、前記複数のエピタキシャル半導体ベース・ラインに対して所定の角度をなす複数の第1の半導体ラインをさらに備える請求項1記載の半導体デバイス。
- 互いにほぼ平行で、かつ、前記複数のエピタキシャル半導体ベース・ラインに対して所定の角度をなす複数の第2の半導体ラインをさらに備える請求項5記載の半導体デバイス。
- 前記基板が、前記基板と、前記エピタキシャル半導体ベース・ラインとの間に設けられた誘電体層をさらに備える請求項5記載の半導体デバイス。
- 前記基板が、前記基板と、前記ベース・エピタキシャル半導体層との間に設けられた誘電体層をさらに備える請求項1記載の半導体デバイス。
- ナノ・スケールの半導体接合を形成する方法であって、
エピタキシャル半導体層上に刷込み層を作り出すステップと、
ナノ・インプリンタを、前記刷込み層に対して押し付けるステップと、
前記エピタキシャル半導体層の選択部分を除去するステップと、
少なくとも1つの横寸法が約75ナノメートルよりも小さいエリアを持つエピタキシャル半導体構造物を形成するステップと、
少なくとも1つの横寸法が約75ナノメートルよりも小さいエリアを持つ第1の半導体接合を形成するステップと、
を有する方法。 - 第1の極性のドーパントを含むエピタキシャル半導体層を、相補形ドープ半導体基板上に作り出すステップをさらに有する請求項9記載の方法。
- 前記基板と、前記エピタキシャル半導体層との間に、誘電体層を作り出すステップをさらに有する請求項10記載の方法。
- 請求項9の方法によって作り出されるバイポーラ接合トランジスタ。
- 前記エピタキシャル半導体構造物の上に、第1の平坦化用誘電体層を作り出すステップと、
前記エピタキシャル半導体構造物とほぼ同じ厚さに、前記第1の平坦化用誘電体層を平坦化するステップと、
第2の極性のドーパントを含む第2の半導体層を、前記エピタキシャル半導体層および前記第1の平坦化用誘電体層の上に作り出すステップと、
前記第2の半導体層上で、第2の刷込み層を作り出すステップと、
ナノ・インプリンタを、前記第2の刷込み層に対して押し付けるステップと、
前記第2の半導体層の選択部分を除去するステップと、
少なくとも1つの横寸法が約75ナノメートルよりも小さいエリアを持つ第2の半導体構造物を形成するステップと、
をさらに有する請求項9記載の方法。 - 前記エピタキシャル半導体構造物を形成するステップは、互いにほぼ平行な複数のエピタキシャル半導体ラインを形成するステップをさらに含み、また、前記第2の半導体構造物を形成するステップは、互いにほぼ平行で、かつ、前記複数のエピタキシャル半導体ラインに対して所定の角度をなす複数の第2の半導体ラインを形成するステップをさらに有する請求項13記載の方法。
- 前記刷込み層の一部と、前記エピタキシャル半導体層の一部の上に、エッチング・マスクを生成するステップをさらに有する請求項9記載の方法。
- 前記エッチング・マスクを生成するステップが、
前記刷込み層の一部と、前記エピタキシャル半導体層の一部の上に、拡散バリヤを作り出すステップと、
前記拡散バリヤの上に、導電層を作り出すステップと、
をさらに有する請求項15記載の方法。 - 前記ナノ・インプリンタを押し付けるステップは、前記刷込み層を加熱するステップをさらに有する請求項9記載の方法。
- 前記エピタキシャル半導体層をエッチングするステップをさらに有する請求項9記載の方法。
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