JP2004095750A5 - - Google Patents

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Publication number
JP2004095750A5
JP2004095750A5 JP2002253151A JP2002253151A JP2004095750A5 JP 2004095750 A5 JP2004095750 A5 JP 2004095750A5 JP 2002253151 A JP2002253151 A JP 2002253151A JP 2002253151 A JP2002253151 A JP 2002253151A JP 2004095750 A5 JP2004095750 A5 JP 2004095750A5
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JP
Japan
Prior art keywords
electronic component
manufacturing
insulator layer
layer
multilayer electronic
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Pending
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JP2002253151A
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Japanese (ja)
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JP2004095750A (en
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Priority to JP2002253151A priority Critical patent/JP2004095750A/en
Priority claimed from JP2002253151A external-priority patent/JP2004095750A/en
Publication of JP2004095750A publication Critical patent/JP2004095750A/en
Publication of JP2004095750A5 publication Critical patent/JP2004095750A5/ja
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Claims (7)

絶縁体層と導体パターンを積層し、積層体内に該導体パターンによって回路素子が形成された積層型電子部品の製造方法において、
支持体上に感光剤入りの絶縁材料を用い、硬化処理を施して第1の絶縁体層を形成する工程、該第1の絶縁体層上に、感光性導電ペーストを用いフォトリソ技術によって形成された導体パターンと感光剤入りの絶縁材料で形成された第2の絶縁体層とが積み重ねられる工程及び、これらの積層体上に、感光剤入りの絶縁材料を用いて第3の絶縁体層を形成する工程を備えたことを特徴とする積層型電子部品の製造方法。
In a method for manufacturing a laminated electronic component in which an insulator layer and a conductor pattern are laminated, and a circuit element is formed by the conductor pattern in the laminate,
A step of forming a first insulator layer by applying a curing treatment using an insulating material containing a photosensitive agent on the support, and a photoconductive technique using a photosensitive conductive paste on the first insulator layer. A conductive layer and a second insulator layer formed of an insulating material containing a photosensitive agent, and a third insulating layer formed on the laminate using an insulating material containing a photosensitive agent. A method of manufacturing a multilayer electronic component, comprising the step of forming.
絶縁体層と導体パターンを積層し、積層体内に該導体パターンによって回路素子が形成された積層型電子部品の製造方法において、
支持体上に絶縁性セラミック材料で第1の絶縁体層を形成する工程、該第1の絶縁体層上に感光剤入りの絶縁材料を用いて緩衝層を形成する工程、該緩衝層上に、感光性導電ペーストを用いフォトリソ技術によって形成された導体パターンと感光剤入りの絶縁材料で形成された第2の絶縁体層とが積み重ねられる工程及び、これらの積層体上に第3の絶縁体層を形成する工程を備えたことを特徴とする積層型電子部品の製造方法。
In a method for manufacturing a laminated electronic component in which an insulator layer and a conductor pattern are laminated, and a circuit element is formed by the conductor pattern in the laminate,
Forming a first insulator layer of an insulating ceramic material on a support, forming a buffer layer on the first insulator layer using an insulating material containing a photosensitive agent, and forming a buffer layer on the buffer layer; A step of stacking a conductive pattern formed by a photolithography technique using a photosensitive conductive paste and a second insulator layer formed of an insulating material containing a photosensitive agent, and a third insulator on the laminate A method of manufacturing a multilayer electronic component, comprising a step of forming a layer.
前記回路素子は、前記絶縁体層間の所定の導体パターンが該絶縁体層のスルーホール内の導体を介して接続されて、該導体パターンによって積層体内に形成された請求項1又は請求項2に記載の積層型電子部品の製造方法。  The circuit element according to claim 1 or 2, wherein a predetermined conductor pattern between the insulator layers is connected through a conductor in a through hole of the insulator layer, and the conductor element is formed in the laminate. The manufacturing method of the multilayer electronic component of description. 前記導体パターンが、感光性導電ペーストを塗布し、これを露光、現像した後、加熱処理を施すことにより形成される請求項1乃至請求項3のいずれかに記載の積層型電子部品の製造方法。  The method for manufacturing a multilayer electronic component according to any one of claims 1 to 3, wherein the conductive pattern is formed by applying a photosensitive conductive paste, exposing and developing the conductive paste, and then performing a heat treatment. . 前記導体パターンが、感光性導電ペーストを塗布し、これを露光、現像した後、加熱の最高温度(℃)×100℃以上の温度領域にさらされる時間(秒)が40000℃・秒以上、60000℃・秒以下の条件で加熱処理を施すことにより形成される請求項1乃至請求項3のいずれかに記載の積層型電子部品の製造方法。  The conductive pattern is coated with a photosensitive conductive paste, exposed to light, developed, and then exposed to a temperature range of a maximum heating temperature (° C.) × 100 ° C. or more (seconds) 40000 ° C. · second or more, 60000 The method for manufacturing a multilayer electronic component according to any one of claims 1 to 3, wherein the multilayer electronic component is formed by performing a heat treatment under the condition of ° C or less. 前記緩衝層の厚みが30μm以上に形成される請求項2に記載の積層型電子部品の製造方法。  The method for manufacturing a multilayer electronic component according to claim 2, wherein the buffer layer has a thickness of 30 μm or more. 前記第1の絶縁体層及び第3の絶縁体層が誘電体、磁性体のいずれかによって形成される請求項1乃至請求項6のいずれかに記載の積層型電子部品の製造方法。  The method for manufacturing a multilayer electronic component according to any one of claims 1 to 6, wherein the first insulator layer and the third insulator layer are formed of either a dielectric or a magnetic material.
JP2002253151A 2002-08-30 2002-08-30 Method for manufacturing laminated electronic component Pending JP2004095750A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002253151A JP2004095750A (en) 2002-08-30 2002-08-30 Method for manufacturing laminated electronic component

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002253151A JP2004095750A (en) 2002-08-30 2002-08-30 Method for manufacturing laminated electronic component

Publications (2)

Publication Number Publication Date
JP2004095750A JP2004095750A (en) 2004-03-25
JP2004095750A5 true JP2004095750A5 (en) 2005-10-20

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JP2002253151A Pending JP2004095750A (en) 2002-08-30 2002-08-30 Method for manufacturing laminated electronic component

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JP (1) JP2004095750A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4579774B2 (en) * 2005-06-10 2010-11-10 東光株式会社 Manufacturing method of multilayer electronic component

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