JP2004095750A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2004095750A5 JP2004095750A5 JP2002253151A JP2002253151A JP2004095750A5 JP 2004095750 A5 JP2004095750 A5 JP 2004095750A5 JP 2002253151 A JP2002253151 A JP 2002253151A JP 2002253151 A JP2002253151 A JP 2002253151A JP 2004095750 A5 JP2004095750 A5 JP 2004095750A5
- Authority
- JP
- Japan
- Prior art keywords
- electronic component
- manufacturing
- insulator layer
- layer
- multilayer electronic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Claims (7)
支持体上に感光剤入りの絶縁材料を用い、硬化処理を施して第1の絶縁体層を形成する工程、該第1の絶縁体層上に、感光性導電ペーストを用いフォトリソ技術によって形成された導体パターンと感光剤入りの絶縁材料で形成された第2の絶縁体層とが積み重ねられる工程及び、これらの積層体上に、感光剤入りの絶縁材料を用いて第3の絶縁体層を形成する工程を備えたことを特徴とする積層型電子部品の製造方法。In a method for manufacturing a laminated electronic component in which an insulator layer and a conductor pattern are laminated, and a circuit element is formed by the conductor pattern in the laminate,
A step of forming a first insulator layer by applying a curing treatment using an insulating material containing a photosensitive agent on the support, and a photoconductive technique using a photosensitive conductive paste on the first insulator layer. A conductive layer and a second insulator layer formed of an insulating material containing a photosensitive agent, and a third insulating layer formed on the laminate using an insulating material containing a photosensitive agent. A method of manufacturing a multilayer electronic component, comprising the step of forming.
支持体上に絶縁性セラミック材料で第1の絶縁体層を形成する工程、該第1の絶縁体層上に感光剤入りの絶縁材料を用いて緩衝層を形成する工程、該緩衝層上に、感光性導電ペーストを用いフォトリソ技術によって形成された導体パターンと感光剤入りの絶縁材料で形成された第2の絶縁体層とが積み重ねられる工程及び、これらの積層体上に第3の絶縁体層を形成する工程を備えたことを特徴とする積層型電子部品の製造方法。In a method for manufacturing a laminated electronic component in which an insulator layer and a conductor pattern are laminated, and a circuit element is formed by the conductor pattern in the laminate,
Forming a first insulator layer of an insulating ceramic material on a support, forming a buffer layer on the first insulator layer using an insulating material containing a photosensitive agent, and forming a buffer layer on the buffer layer; A step of stacking a conductive pattern formed by a photolithography technique using a photosensitive conductive paste and a second insulator layer formed of an insulating material containing a photosensitive agent, and a third insulator on the laminate A method of manufacturing a multilayer electronic component, comprising a step of forming a layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002253151A JP2004095750A (en) | 2002-08-30 | 2002-08-30 | Method for manufacturing laminated electronic component |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002253151A JP2004095750A (en) | 2002-08-30 | 2002-08-30 | Method for manufacturing laminated electronic component |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2004095750A JP2004095750A (en) | 2004-03-25 |
JP2004095750A5 true JP2004095750A5 (en) | 2005-10-20 |
Family
ID=32059236
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2002253151A Pending JP2004095750A (en) | 2002-08-30 | 2002-08-30 | Method for manufacturing laminated electronic component |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2004095750A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4579774B2 (en) * | 2005-06-10 | 2010-11-10 | 東光株式会社 | Manufacturing method of multilayer electronic component |
-
2002
- 2002-08-30 JP JP2002253151A patent/JP2004095750A/en active Pending
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS63258055A (en) | Manufacture of electronic circuit device | |
JP3765627B2 (en) | Multilayer circuit board and manufacturing method thereof | |
KR960019477A (en) | Electrostatic chuck device and its manufacturing method | |
TW465265B (en) | Circuit board features with reduced parasitic capacitance and method therefor | |
JP2004095750A5 (en) | ||
JP2003264361A (en) | Circuit board manufacturing method | |
JP2003324026A (en) | Method of manufacturing laminated electronic component | |
JP2586745B2 (en) | Manufacturing method of printed wiring board | |
JP2003234231A (en) | Method of manufacturing laminated electronic component | |
JP2000232019A (en) | Inductor and its manufacture | |
JP2003234231A5 (en) | ||
JP2850518B2 (en) | Organic resin multilayer wiring board and method of manufacturing organic resin multilayer wiring board | |
TWI696241B (en) | Manufacturing method of high-power inductance element and its element | |
JPS5929160B2 (en) | Manufacturing method of wiring board | |
JP2004095750A (en) | Method for manufacturing laminated electronic component | |
JPH1051112A (en) | Formation method for circuit board using heat-resistant resin composition | |
JPH0945570A (en) | Electronic component and manufacture thereof | |
JPH0453297A (en) | Forming method for insulating layer | |
TW202344159A (en) | Method for producing wiring circuit board | |
JP2002237426A5 (en) | ||
JP2644847B2 (en) | Multilayer wiring board and method of manufacturing the same | |
JP2755019B2 (en) | Method for manufacturing multilayer wiring board | |
JP2004179485A (en) | Printed wiring board and method of manufacturing the same | |
JPH03280492A (en) | Formation of multilayered insulating film | |
TW201228510A (en) | Muti-layer printed circuit board and method for manufacturing the same |