JP2004055810A - Method of evaluating semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of evaluating a semiconductor device which can identify islands by defective trenches among many trench islands. <P>SOLUTION: On an SOI substrate (thin film silicon layer), a silicon oxide film is formed. On the silicon oxide film, an aluminum interconnection 27 is formed which connects thin film silicon layers of each island 14 in series through contact holes 26, and an aluminum interconnection 29 is formed which is connected to the thin film silicon layers outside each island 14 through contact holes 28. By measuring the voltage using the aluminum interconnection 29 when causing a current to flow across the aluminum interconnection 27, islands where a separation fault happens by defective trenches can be identified. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for evaluating a semiconductor device.
[0002]
[Prior art]
There is a semiconductor device using an SOI substrate and using a trench isolation technique. For example, as shown in FIG. 5, a square island-shaped trench 11 is formed in the thin film silicon layer of the SOI substrate 10 to form a large island 12, and a small island 14 is formed in the island 12 by a number of square frame-shaped trenches 13. Many are arranged in all directions. In a semiconductor device of this type, reduction of defects in trench isolation is an important item for improving yield.
[0003]
Then, in order to evaluate the poor trench isolation, as shown in FIG. 6, an aluminum wiring 51 is connected to a thin silicon layer of each small island 14 through a contact hole 50 in a partial region of the wafer-like SOI substrate 10. The aluminum wiring 53 is connected to the thin silicon layer of the large island 12 through the contact hole 52. A voltage was applied between the aluminum wiring 51 and the aluminum wiring 53 to determine the presence or absence of a leak current, thereby evaluating the trench defect rate in the large islands 12 arranged in a large number in the wafer.
[0004]
Although the wiring patterns 51 and 53 can be used to evaluate the trench defect rate, it is necessary to clarify the cause of the trench defect in order to improve the trench defect. It is necessary to specify the location. However, in the wiring patterns 51 and 53 of FIG. 6, the defect rate could be evaluated, but the defective portion could not be specified.
[0005]
More specifically, when a CMOS transistor, a bipolar transistor, and a device having characteristics different from those of a power transistor are formed on each island isolated by a trench, and these devices are arranged in one chip, a trench insulation defect is caused. It is an important item that must be crushed in order to achieve the yield target in order to directly relate to the yield. In order to take appropriate measures against the failure, it is necessary to determine the true cause of the trench failure. In other words, the trench is defective if at least one of the trenches surrounding the island does not reach the buried oxide film. Conventionally, when there is one defect, in order to identify the defect, the defect or the TEG pattern is specified by checking the chip or the TEG pattern little by little while checking the surface with a microscope. With this method, it takes half a day to one day to specify one place. Actually, since a plurality of causes are often overlapped, it is necessary to examine a plurality of (for example, 20 to 30) TEG elements. It would take between 15 and 30 days to research as many as 30. Therefore, a method that can electrically specify the location is required.
[0006]
[Problems to be solved by the invention]
The present invention has been made under such a background, and an object of the present invention is to provide a semiconductor device evaluation method capable of specifying an island due to a defective trench among many trench islands. is there.
[0007]
[Means for Solving the Problems]
According to the first aspect of the present invention, a wire connecting the thin film silicon layers of each island in series is formed, and a wire connected to the thin film silicon layer outside each island is formed. Then, when a current flows between both ends of the wiring connecting the thin-film silicon layers of each island in series, the voltage is measured using the wiring connected to the thin-film silicon layer outside each island. This makes it possible to identify the island where the separation failure has occurred due to the defective trench. That is, an island due to a defective trench out of the many trench islands can be specified.
[0008]
As described in the second aspect, when the wiring resistances between a number of islands are made equal, the identification can be easily performed.
It may be used in the process development stage as described in claim 3, or may be used in the wafer flow stage after the process development stage as described in claim 4. As described, islands separated by trenches may be formed in the scribe line on the wafer.
[0009]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment of the present invention will be described below with reference to the drawings.
FIG. 1 shows a plan view of a semiconductor substrate (wafer) according to the present embodiment. FIG. 2 shows a vertical section taken along line XX in FIG.
[0010]
In FIG. 2, a thin-film silicon layer 22 is formed on a silicon substrate 20 via a silicon oxide film (buried oxide film) 21 to constitute the SOI substrate 10. Specifically, for example, an SOI substrate is obtained by bonding a first silicon substrate and a second silicon substrate via a silicon oxide film 21 and thinning one of the silicon substrates.
[0011]
In the SOI substrate 10, as shown in FIG. 5, large trench islands 12 are formed, and a large number of small trench islands 14 are formed in the trench islands 12. Specifically, as shown in FIG. 2, a trench 11 reaching the buried oxide film 21 is formed in a rectangular frame shape in the thin film silicon layer 22 of the SOI substrate 10 (see FIG. 5), and a trench island 12 It has become. The trench 11 is filled with a silicon oxide film 23. Further, in the trench island 12, a trench 13 reaching the buried oxide film 21 is formed in the thin-film silicon layer 22 in a rectangular frame shape (see FIG. 5), and a trench island 14 is formed inside. The trench 13 is filled with a silicon oxide film 24. As shown in FIG. 5, a large number of trench islands 14 are formed vertically and horizontally. In FIG. 5, four are provided in the vertical direction and five in the horizontal direction.
[0012]
As a structure inside the trench 13, besides filling the silicon oxide film 24 inside the trench 13, a silicon oxide film is formed on the inner wall surface of the trench 13 and a polysilicon film is filled inside the trench 13. Is also good.
[0013]
As described above, as a semiconductor device to be evaluated, a trench reaching the buried insulating film 21 in the thin silicon layer 22 in the SOI substrate 10 in which the thin silicon layer 22 is disposed on the silicon substrate 20 via the buried insulating film 21 13 are formed, and a large number of islands 14 separated by the trenches 13 are assumed. Devices such as CMOS transistors and bipolar transistors are formed in each island 14.
[0014]
As shown in FIG. 1, an island (island separated by a trench) 14 having this structure is formed in a partial region of a wafer-like SOI substrate, and a trench 11 is formed therearound. In this embodiment, the trench islands 14 are arranged at equal intervals in the vertical and horizontal directions.
[0015]
Then, a silicon oxide film 25 is formed on the SOI substrate 10 (thin film silicon layer 22), as shown in FIG. In this silicon oxide film 25, contact holes 26 for applying a voltage to the thin film silicon layer 22 in each of the small trench islands 14 are formed. In the large trench island 12, a contact hole 28 for detecting a voltage (potential) of the thin film silicon layer 22 in the large island is formed.
[0016]
As shown in FIGS. 1 and 2, an aluminum wiring 27 for trench evaluation is patterned on the silicon oxide film 25, and the small trench island (thin silicon layer) 14 is electrically connected to the aluminum wiring 27 through the contact hole 26. It is connected. At this time, the pattern of the aluminum wiring 27 extends in a belt shape as shown in FIG. 1 and connects the thin film silicon layers 22 of each trench island 14 in series.
[0017]
On the silicon oxide film 25 of FIG. 2, an aluminum wiring 29 for trench evaluation is patterned as shown in FIG. 1, and the thin silicon layer 22 of the large trench island 12 is connected to the aluminum wiring 29 through the contact hole 28. It is electrically connected. The aluminum wiring 29 allows the voltage (potential) of the thin film silicon layer of the large trench island 12 to be measured.
[0018]
In this manner, the wiring patterns 27 and 29 for performing a failure analysis for improving the yield of the trench at the process development stage are provided.
Here, the trench islands 12 and 14 are square in shape, but any shape such as a triangle or a polygon having five or more pentagons may be used as long as they are islands. The size of the small trench island 14 is not particularly defined. However, in order to increase the trench area with a small area, the size is preferably as small as possible (for example, the vertical and horizontal dimensions are several μm).
[0019]
Next, an evaluation method will be described with reference to FIG.
Now, it is assumed that a trench failure occurs at a location indicated by D in the predetermined trench island 14 in FIG. That is, it is assumed that the trench 13 does not reach the buried oxide film 21 in the portion D.
[0020]
One end of the strip-shaped aluminum wiring 27 is connected to the A terminal, and the other end is connected to the B terminal. Further, another aluminum wiring 29 is connected to the C terminal. Then, a predetermined voltage VD is applied between both terminals of AB, and a predetermined current flows between both terminals of AB. Specifically, the B terminal is grounded, and a predetermined voltage VD is applied to the A terminal. FIG. 4 shows an equivalent circuit in this state. In FIG. 4, a large number of wiring resistors are connected in series so as to connect the trench islands 14 between the A terminal and the B terminal. That is, since the aluminum wiring 27 is connected to the small trench island 14 through the contact hole 26, a voltage obtained by subtracting a voltage drop due to wiring resistance is applied to each trench island 14. At this time, since the trench islands 14 are arranged at equal intervals, the wiring resistance between the islands becomes equal.
[0021]
Then, in this state, the voltage at the C terminal by the aluminum wiring 29 in the large trench island 12 is measured (measured). At this time, if a trench failure does not occur, a small voltage such as noise is detected as a voltage measurement value at the C terminal. That is, if there is no defective trench portion, only a voltage lower than the measurement limit such as noise can be detected from the voltage monitoring electrode (C terminal).
[0022]
On the other hand, if there is a trench defect at the location indicated by D in FIG. 3 and the inside and outside of the small trench island 14 are electrically connected at this location, as shown in FIG. , C, the voltage VC corresponding to the voltage drop with respect to the A terminal is detected. Here, since the small trench islands 14 are arranged at equal intervals, the trench islands 14 causing the trench failure by the proportional calculation using the measured voltage VC at the C terminal and the voltage VAB between the two terminals of AB are used. Can be specified. Specifically, the voltage VC at the C terminal is the voltage VCB between the C and B terminals, and the voltage VAC between the A and C terminals is calculated from the voltage VAB between the A and B terminals from the voltage between the C and B terminals. It is a value obtained by subtracting VCB (= VAB-VCB). Therefore, from the ratio between the VAB value and the VAC value, it is possible to identify the island (trench island) 14 having a trench failure when the terminal A is used as a reference among the both ends of the aluminum wiring 27.
[0023]
Although the voltage applied between the two terminals of the AB is not particularly defined, a defective trench (defective island) can be more easily identified when a large amount of current is allowed to flow between the two terminals of the AB.
[0024]
By using such an evaluation structure (evaluation method) as a large-scale TEG in the process development stage, it is necessary to evaluate variations in the wafer surface, variations in lots and lots, etc., and to study process conditions with a good trench yield. Can be. Further, in the flow stage, the empty space in the wafer can be used for confirming the workmanship in the process and for managing the process. In this case, a scribe line is preferable as an arrangement place, but may be arranged in a product chip.
[0025]
As described above, the present evaluation method may be used in the process development stage or in the wafer flow stage after the process development stage. When the evaluation method is used in the wafer flow stage, the trench 13 It is preferable to form islands 14 separated from each other.
[0026]
As described above, a large number of islands 14 separated by trenches 13 are formed in a partial region of a wafer-like SOI substrate (SOI wafer) for evaluation, and an insulating film 25 is disposed on the thin silicon layer 22. Then, in the insulating film 25, an intra-island contact hole 26 is formed for each of the islands 14, and an extra-island contact hole 28 is formed outside of each of the islands 14. An aluminum wiring 27 connecting the thin film silicon layers 22 of the islands 14 in series is formed, and an aluminum wiring 29 connected to the thin film silicon layer 22 outside each of the islands 14 through the contact holes 28 outside the islands is formed. When a current flows between both ends of an aluminum wiring 27 connecting the layers 22 in series, a thin film outside each island 14 is formed. By measuring the voltage using the aluminum wiring 29 connected to the silicon layer 22, separation failure was made to identify the island generated due to defective trench. In this manner, the island due to the defective trench among the many trench islands 14 can be specified.
[0027]
That is, paying attention to the fact that the defective trench portion is connected to the thin film silicon layer 22 outside the plurality of trench islands 14, the plurality of trench islands 14 are connected in series by the aluminum wiring 27, and a current flows between both ends. By monitoring the potential of the thin film silicon layer 22 outside the trench island 14, the potential of the voltage drop from the defective trench can be monitored as the potential of the thin film silicon layer 22 outside the trench island 14, and the defective pattern (trench) can be monitored. Island) can be identified.
[0028]
That is, by using the trench yield evaluation test pattern (wiring pattern) 27 shown in FIG. 1 and connecting the trench islands 14 in series, it is possible to electrically specify a place where the trench 13 is not formed. Specifically, a current is applied by applying a voltage to the wiring pattern 27 connecting the islands 14 in series. If the trench 13 is completely separated, a voltage of almost 0 volt is detected because the outside of the island 14 is floating, but if the trench 13 is not completely formed, a voltage corresponding to the voltage drop is output. Therefore, if the voltage is monitored, a defective trench portion can be specified.
[0029]
Further, when the wiring resistances between the multiple islands 14 are equalized, it becomes easy to specify a defective trench portion (defective island).
[Brief description of the drawings]
FIG. 1 is a plan view of a semiconductor substrate according to an embodiment.
FIG. 2 is a longitudinal sectional view taken along line XX in FIG.
FIG. 3 is a plan view for explaining an evaluation method.
FIG. 4 is a diagram showing an equivalent circuit for explaining an evaluation method.
FIG. 5 is a plan view of a semiconductor substrate.
FIG. 6 is a plan view for explaining a conventional evaluation method.
[Explanation of symbols]
10 SOI substrate, 13 trench, 14 island, 20 silicon substrate, 21 silicon oxide film (embedded insulating film), 22 thin silicon layer, 25 silicon oxide film (insulating film), 26 contact hole , 28 contact hole, 27 aluminum wiring, 29 aluminum wiring.

Claims (5)

The buried insulating film (21) reaches the thin-film silicon layer (22) in the SOI substrate (10) in which the thin-film silicon layer (22) is disposed on the silicon substrate (20) via the buried insulating film (21). A method for evaluating a semiconductor device in which a trench (13) is formed and a number of islands (14) separated by the trench (13) are formed,
Forming a plurality of islands (14) separated by the trench (13) for evaluation in a partial region of the wafer-like SOI substrate, and disposing an insulating film (25) on the thin silicon layer (22); In the insulating film (25), an intra-island contact hole (26) is formed for each island (14), and an extra-island contact hole (28) is formed outside each island (14). A wiring (27) for connecting the thin-film silicon layers (22) of each island (14) in series through the contact holes (26) in each island is formed on each of the islands (14) through the contact holes (28) outside the island. ), A wiring (29) connected to the thin film silicon layer (22) outside is formed, and a current flows between both ends of the wiring (27) connecting the thin film silicon layers (22) of each island (14) in series. Wherein the island where separation failure due to a defective trench has occurred is specified by measuring a voltage using a wiring (29) connected to the thin film silicon layer (22) outside each island (14). Semiconductor device evaluation method. 2. The method according to claim 1, wherein wiring resistances between the plurality of islands are made equal. 3. The method for evaluating a semiconductor device according to claim 1, wherein the method is used in a process development stage. 3. The method for evaluating a semiconductor device according to claim 1, wherein the method is used in a wafer flow stage after the process development stage. The method according to claim 4, wherein islands (14) separated by the trenches (13) are formed in scribe lines on the wafer.

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