TWI817572B - Monitoring method of semiconductor device - Google Patents

Abstract

A monitoring method of a semiconductor device includes: providing a semiconductor device including a first metal layer, a second metal layer disposed over the first metal layer, and conductive vias connected between the first metal layer and the second metal layer; placing the semiconductor device in a first state, in which the first metal layer electrically connected to a first conductive element and the second metal layer electrically connected to a second conductive element; placing the semiconductor device in a second state, in which the first metal layer electrically connected to the second conductive element and the second metal layer electrically connected to the third conductive element; and electrically connecting a powering assembly and a grounding assembly of a testing device to the conductive elements to acquire a first voltage value and a first current value of the semiconductor device placed in the first state and a second voltage value and a second current value of the semiconductor device placed in the second state.

Description

Monitoring Methods for Semiconductor Components

The present disclosure relates to a method for monitoring semiconductor components.

Before the manufactured wafer-level semiconductor components are shipped, they will first undergo a series of wafer acceptance tests (WAT). The wafer acceptance test includes NMOS components, PMOS components, Electrical testing of resistors, capacitors, bipolar junction transistors (BJT), etc. In particular, in resistance test projects, the industry usually uses a four-wire measurement (kelvin measurement) method to measure the voltage and current values of semiconductor components (such as test element groups (TEG) located on the wafer dicing lane), and then The resistance value of the semiconductor element is calculated from the measured voltage value and current value. By analyzing the resistance value, we can further monitor whether there is an overlay shift between the metal layer and the conductive connecting pillar in the semiconductor device due to defects in the manufacturing process, and then determine the die of the entire wafer. manufacturing status.

However, because there are so many factors that affect the measured resistance value of a semiconductor device, it is difficult to infer the existence of coverage offset in a semiconductor device based solely on the measured resistance value, even using current resistance testing methods. Moreover, the current resistance testing method can only detect the coverage shift in a single direction in the semiconductor device on the production line (in-line). In other words, if the semiconductor component actually produces coverage deviation in another direction different from the above-mentioned single direction, such coverage deviation may not be detected using the current resistance testing method, resulting in the subsequent integrated circuit chip packaging process. Problems are discovered only in the process, which leads to waste. In view of this, another solution in the industry is to use the image of a scanning electron microscope (SEM) after the above-mentioned resistance test to determine the exact direction in which the coverage shift of the semiconductor element occurs. However, waiting for SEM image output is actually time-consuming, thus affecting the production efficiency of integrated circuit chips.

Therefore, how to propose a monitoring method for semiconductor components, especially a monitoring method that can more completely monitor the coverage offset problem on the production line, is one of the issues that the industry is currently eager to invest in R&D resources to solve.

In view of this, one purpose of the present disclosure is to provide a monitoring method for semiconductor devices that can solve the above problems.

In order to achieve the above object, according to an embodiment of the present disclosure, a method for monitoring a semiconductor element includes: providing a semiconductor element, the semiconductor element includes a first metal layer, a second metal layer and one or more conductive connecting pillars, the second metal layer Disposed above the first metal layer, one or more conductive communication pillars are connected between the first metal layer and the second metal layer; the semiconductor element is placed in the first manner, wherein the first metal layer is electrically connected to the first conductive element And the second metal layer is electrically connected to the second conductive element; the semiconductor element is placed in a second manner, wherein the first metal layer is electrically connected to the second conductive element and the second metal layer is electrically connected to the third conductive element; the test element is The power component and the ground component are electrically connected to the first conductive component and the second conductive component respectively to obtain the first voltage value and the first current value of the semiconductor component placed in the first manner; and the power component of the test component and The ground component is electrically connected to the second conductive element and the third conductive element respectively to obtain the second voltage value and the second current value of the semiconductor element placed in the second manner.

In one or more embodiments of the present disclosure, the phase difference between the semiconductor device of the first aspect and the semiconductor device of the second aspect is 90 degrees.

In one or more embodiments of the present disclosure, the first conductive element, the second conductive element, and the third conductive element are electrical measurement pads.

In one or more embodiments of the present disclosure, the semiconductor devices of the first aspect are arranged in a first direction, and the semiconductor devices of the second aspect are arranged in the second direction.

In one or more embodiments of the present disclosure, the test element is a probe station.

According to an embodiment of the present disclosure, the step of electrically connecting the power component and the ground component of the test component to the first conductive component and the second conductive component respectively is performed after the step of placing the semiconductor component in the first manner and is performed in Before the step of placing the semiconductor device in the second aspect.

In one or more embodiments of the present disclosure, the step of electrically connecting the power component and the ground component of the test component to the second conductive component and the third conductive component respectively is performed after the step of placing the semiconductor component in the second manner. .

In one or more embodiments of the present disclosure, the method for monitoring a semiconductor element further includes: placing the semiconductor element in a second manner, wherein the first metal layer is electrically connected to the third conductive element and the second metal layer is electrically connected to the fourth conductive element. component; and electrically connecting the power component and the ground component of the test component to the third conductive component and the fourth conductive component respectively to obtain the second voltage value and the second current value of the semiconductor component placed in the second manner.

In one or more embodiments of the present disclosure, the step of electrically connecting the power component and the ground component of the test component to the third conductive component and the fourth conductive component respectively is performed by electrically connecting the power component and the ground component of the test component to each other respectively. After the step of sexually connecting the first conductive element and the second conductive element.

In one or more embodiments of the present disclosure, the step of electrically connecting the power component and the ground component of the test component to the third conductive component and the fourth conductive component respectively is performed after the step of placing the semiconductor component in the second manner. .

To sum up, in the monitoring method of the semiconductor element of the present disclosure, since the first voltage value and the first current value of the semiconductor element placed in the first aspect are obtained, the semiconductor element is placed in the second aspect. And based on this, the second voltage value and the second current value are obtained, and then the resistance values of the semiconductor element in several directions are calculated respectively, so that the semiconductor element can be reliably monitored on the production line to detect the coverage offset problem, and determine In which direction the above coverage offset occurs. In addition, in the monitoring method of the semiconductor element of the present disclosure, since the semiconductor element has completed the measurement of the voltage value and current value when placed in the first aspect and the second aspect on the production line, the monitor can Monitored problems can be reported to front-end process technicians in a timely manner, which can not only avoid material waste during the manufacturing process of semiconductor components, but also achieve the purpose of saving process time of semiconductor components.

The above is only used to describe the problems to be solved by the present disclosure, the technical means to solve the problems, the effects thereof, etc. The specific details of the present disclosure will be introduced in detail in the following implementation modes and related drawings.

A plurality of implementation manners of the present disclosure will be disclosed below with drawings. For clarity of explanation, many practical details will be explained together in the following description. However, it should be understood that these practical details should not be used to limit the disclosure. That is to say, in some implementations of the present disclosure, these practical details are not necessary. In addition, for the sake of simplifying the drawings, some commonly used structures and components will be illustrated in a simple schematic manner in the drawings. The same reference numbers will be used throughout the drawings to refer to the same or similar elements.

Spatially relative terms (e.g., "below," "below," "below," "above," "above," and other related terms) are used here to simply describe the relationship between an element or feature as shown in the figure and another. Relationship between components or features. These spatially relative terms cover different directions of use or operation of the device in addition to the direction illustrated in the figures. Furthermore, these devices may be rotated (90 degrees or other angles) and the spatially relative descriptors used herein interpreted accordingly. Additionally, the term "made of" can mean "comprising" or "consisting of."

Please refer to FIG. 1 , which is a flow chart of a method 100 for monitoring a semiconductor device according to an embodiment of the present disclosure. As shown in FIG. 1 , the semiconductor element monitoring method 100 includes steps S101 , S102 , S103 , S104 and S105 . When this article describes steps S101 to S105 in Figure 1 in detail, please refer to Figures 2A, 2B, and Figures 3 to 10.

The operations of step S101, step S102, step S103, step S104 and step S105 are described in detail below.

First, step S101 is performed: providing a semiconductor component.

Please refer to Figures 2A and 2B, which provide a semiconductor device 200. In this embodiment, the semiconductor element 200 is located on the scribe line SL of the wafer W. In more detail, as shown in FIG. 2A , the above-mentioned wafer W includes several wafers D and dicing lines SL surrounding the wafers D, where the dicing lines SL define the range of the wafers D. In some embodiments, the wafer W includes a plurality of laterally extending scribe lines SL and a plurality of longitudinally extending scribe lines SL. In some embodiments, each transversely extending cutting lane SL is perpendicular to each longitudinally extending cutting lane SL. In some embodiments, the scribe lane SL serves as a cutting path for the manufacturer to cut the wafer W into a plurality of separate wafers D.

Next, please refer to Figure 2B, which illustrates a partial enlarged view of wafer W. As shown in FIG. 2B , the cutting line SL further includes several semiconductor elements 200 and several conductive elements P. For example, a plurality of semiconductor elements 200 and a number of conductive elements P are alternately arranged on each transversely extending scribe line SL and each longitudinally extending scribe line SL. In other words, as shown in FIG. 2B , the semiconductor element 200 is located between the two conductive elements P, and the conductive element P is located between the two semiconductor elements 200 .

In some embodiments, the semiconductor element 200 may be a Test Element Group (TEG) located on the scribe line SL. The operator/monitor can determine the manufacturing status of the remaining semiconductor devices in the die by testing the semiconductor device 200 used as the test device set.

In some embodiments, the conductive element P can be used as an electrical test pad for electrical testing of the semiconductor device 200 . Specifically, by contacting a test element such as a probe with two adjacent conductive elements P, the electrical parameters (eg, voltage, current, etc.) of the semiconductor element 200 located between the two conductive elements P can be obtained.

It should be noted that the size, shape, arrangement and quantity of the wafer D, the dicing line SL, the semiconductor element 200 and the conductive element P shown in Figures 2A and 2B are only examples for simple explanation, and this disclosure is not intended to There are restrictions on the size, shape, arrangement and quantity of the wafer D, the scribe lines SL, the semiconductor elements 200 and the conductive elements P.

Please refer to picture 3. As shown in Figure 3, a semiconductor element 300 is provided. It should be noted that the semiconductor element 300 in FIG. 3 is substantially the same as the semiconductor element 200 in FIG. 2B. In this embodiment, the semiconductor element 300 includes a first metal layer 310 , a dielectric material layer 320 , a second metal layer 330 and a conductive via pillar 340 . The dielectric material layer 320 is disposed on the first metal layer 310 . The second metal layer 330 is disposed above the first metal layer 310 and on the dielectric material layer 320 such that the dielectric material layer 320 is disposed between the first metal layer 310 and the second metal layer 330 . The conductive communication pillar 340 penetrates the dielectric material layer 320 and is connected between the first metal layer 310 and the second metal layer 330 .

In some embodiments, the first metal layer 310 may be made of a metal material such as copper or tungsten, but the disclosure is not limited thereto. In some embodiments, the first metal layer 310 may be made of any conductive metal material. Alternatively, in some implementations, the first metal layer 310 may also be made of a conductive material such as polysilicon, but the present disclosure is not limited thereto. In some embodiments, the first metal layer 310 may be made of any conductive material capable of conducting electricity.

In some embodiments, the dielectric material layer 320 may be an oxide layer formed of a material such as SiO ₂ , but the present disclosure is not limited thereto. In some embodiments, the dielectric material layer 320 may be a nitride layer formed of a material such as silicon nitride, but the present disclosure is not limited thereto. In some embodiments, the dielectric material layer 320 may be made of any dielectric material that can serve as a dielectric layer (eg, a low-k material).

In some embodiments, the second metal layer 330 may be made of a metal material such as copper or tungsten, but the disclosure is not limited thereto. In some embodiments, the second metal layer 330 may be made of any conductive metal material. Alternatively, in some embodiments, the second metal layer 330 may also be made of a conductive material such as polysilicon, but the present disclosure is not limited thereto. In some embodiments, the second metal layer 330 may be made of any conductive material that can conduct electricity.

In some embodiments, the conductive communication pillar 340 may be made of a metal material such as copper or tungsten, but the present disclosure is not limited thereto. In some embodiments, the conductive communication pillar 340 may be made of any conductive metal material. Alternatively, in some embodiments, the conductive communication pillar 340 may also be made of conductive material such as polysilicon, but the present disclosure is not limited thereto. In some embodiments, the conductive communication pillars 340 may be made of any conductive material capable of conducting electricity.

In some embodiments, the first metal layer 310 , the dielectric material layer 320 , the second metal layer 330 and the conductive via pillars 340 can be formed by, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition. Deposition (ALD) or other possible processes. This disclosure is not intended to limit the formation methods of the first metal layer 310, the dielectric material layer 320, the second metal layer 330 and the conductive via pillars 340.

Please refer to Figure 4. As shown in FIG. 4 , a top view of an exemplary semiconductor device 300 is shown. In this embodiment, at least one of the first metal layer 310 and the second metal layer 330 may have a special routing pattern. For example, as shown in FIG. 4 , the first metal layer 310 may be a flat conductive material layer (in other words, without a winding pattern), and the second metal layer 330 may be a finger-shaped layer. ) layer of conductive material in the winding pattern. By way of example, but not limitation, the above-mentioned finger-like winding patterns of the second metal layer 330 may be elongated in at least one direction (eg, direction X) and arranged in parallel in another direction (eg, direction Y). However, the present disclosure Not limited to this.

As shown in FIG. 4 , for example, the finger-shaped winding pattern of the second metal layer 330 has seven rows of finger-shaped winding patterns arranged in the other direction (eg, direction Y). This is just an example for simple explanation, but the present disclosure is not limited to this.

In some embodiments, the finger-shaped winding pattern of the second metal layer 330 may be arranged with about ten to about fifty rows of finger-shaped winding patterns in the other direction (for example, direction Y). However, this The disclosure is not limited to this.

In some embodiments, the semiconductor device 300 may have one or more conductive via pillars 340 connected between the first metal layer 310 and the second metal layer 330 . For example, as shown in FIG. 4 , the exemplary semiconductor device 300 may have a plurality of conductive vias 340 . The present disclosure is not intended to limit the number of conductive via pillars 340 .

Next, step S102 is performed: placing the semiconductor device in the first aspect.

Please refer to Figure 5. As shown in FIG. 5 , it shows several semiconductor devices 300 and conductive elements P1 , P2 , P3 and conductive elements located on the dicing lane SL (not shown) of the wafer W (not shown). Schematic arrangement of elements P4.

As shown in FIG. 5 , each semiconductor device 300 located on the scribe line SL of the wafer W includes a flat first metal layer 310 and a second metal layer 330 with a finger-like winding pattern, wherein the finger-like The winding patterns extend elongated in at least one direction (for example, direction X) and are arranged in parallel in another direction (for example, direction Y). In other words, each semiconductor device 300 is placed on the wafer W in the same manner. In FIG. 5 , the semiconductor device 300 is placed along with the wafer W, so that the finger-like winding pattern of the second metal layer 330 elongates along the horizontal direction (ie, equivalent to the direction X in FIG. 5 ) and extends Arranged in parallel in the vertical direction (ie, equivalent to the direction Y in Figure 5), such an aspect is defined as the first aspect F1.

Please refer to Figure 6 and Figure 7 again. In this embodiment, one of the first metal layer 310 and the second metal layer 330 is electrically connected to the conductive element P1, and the other of the first metal layer 310 and the second metal layer 330 is electrically connected to the conductive element P1. P2. For example, as shown in Figures 6 and 7, the first metal layer 310 is electrically connected to the conductive element P1, and the second metal layer 330 is electrically connected to the conductive element P2. Alternatively, in some embodiments, the first metal layer 310 may be electrically connected to the conductive element P2, and the second metal layer 330 may be electrically connected to the conductive element P1.

For simplicity of explanation, only four semiconductor devices 300 are shown in FIG. 5 , but in fact, the scribe line SL of the wafer W may include more than four semiconductor devices 300 . Similarly, only four conductive elements (eg, conductive element P1, conductive element P2, conductive element P3, and conductive element P4) are shown in FIG. 5 , but in fact, the scribe line SL of the wafer W may include more than Four conductive elements.

As shown in FIG. 5 , the conductive element P1 , the conductive element P2 and the semiconductor element 300 located between the conductive element P1 and the conductive element P2 are arranged in one direction (for example, direction X). This is just an example for simple description. In fact, the cutting track SL may have several conductive elements P1 and P2 alternately arranged in this direction (for example, direction X). Specifically, the conductive element P1, the conductive element P2 and the semiconductor element 300 on the dicing line SL extending along the direction (for example, the direction 300. Arrangement of conductive elements P1,...".

As shown in FIG. 5 , the conductive element P3 , the conductive element P4 , and the semiconductor element 300 located between the conductive element P3 and the conductive element P4 are arranged in one direction (for example, direction X). This is just an example for simple description. In fact, the cutting track SL may have several conductive elements P3 and P4 alternately arranged in this direction (for example, direction X). Specifically, the conductive element P3, the conductive element P4, and the semiconductor element 300 on the dicing line SL extending along the direction (for example, the direction 300. Arrangement of conductive elements P3,...".

As shown in FIG. 5 , the conductive element P1 , the conductive element P4 and the semiconductor element 300 located between the conductive element P1 and the conductive element P4 are arranged in another direction (eg, direction Y). This is just an example for simple description. In fact, the cutting track SL may have several alternately arranged conductive elements P1 and P4 in the other direction (for example, direction Y). Specifically, the conductive element P1, the conductive element P4 and the semiconductor element 300 on the dicing line SL extending along the other direction (eg, direction Y) may be, for example, "the conductive element P1, the semiconductor element 300, the conductive element P4, Arrangement of semiconductor element 300, conductive elements P1, ...".

As shown in FIG. 5 , the conductive element P2 , the conductive element P3 , and the semiconductor element 300 located between the conductive element P2 and the conductive element P3 are arranged in another direction (eg, direction Y). This is just an example for simple description. In fact, the cutting track SL may have several alternately arranged conductive elements P2 and P3 in the other direction (eg, direction Y). Specifically, the conductive element P2, the conductive element P3 and the semiconductor element 300 on the dicing line SL extending along the other direction (eg, direction Y) may be, for example, "the conductive element P2, the semiconductor element 300, the conductive element P3, Arrangement of semiconductor element 300, conductive elements P2, ...".

In some embodiments, as shown in Figures 5, 6 and 7, one of the first metal layer 310 and the second metal layer 330 can be electrically connected to the conductive element P1 through the wire L1. The other one of the first metal layer 310 and the second metal layer 330 can be electrically connected to the conductive element P2 through the wire L2. For example, the first metal layer 310 can be electrically connected to the conductive element P1 through the wire L1, and the second metal layer 330 can be electrically connected to the conductive element P2 through the wire L2.

In some embodiments, the conductor L1 and the conductor L2 may be any suitable conductive material, but the present disclosure is not limited thereto. In some embodiments, the material of the wire L1 is the same as the material of the first metal layer 310 , and the material of the wire L2 is the same as the material of the second metal layer 330 , but the disclosure is not limited thereto. In some embodiments, the material of the conductor L1 may be different from the material of the first metal layer 310 , and the material of the conductor L2 may also be different from the material of the second metal layer 330 .

Next, step S103 is performed: electrically connecting the power component and the ground component of the test component to the first conductive component and the second conductive component respectively to obtain the first voltage value and the first current value of the semiconductor component placed in the first manner. .

Please refer to FIG. 5 , which illustrates a schematic diagram of a monitoring stage of the semiconductor device monitoring method 100 . In this embodiment, the voltage value and current value of the semiconductor element 300 placed in the first aspect F1 can be obtained by electrically connecting the test element (not shown) to the conductive element P1 and the conductive element P2. In more detail, the test component includes a power component TP and a ground component TG. The power component TP serves as the power terminal of the test component, and the ground component TG serves as the ground terminal of the test component. In this embodiment, one of the power component TP and the ground component TG is electrically connected to the conductive element P1, and the other one of the power component TP and the ground component TG is electrically connected to the conductive element P2. In a usage scenario, as shown in Figures 5, 6 and 7, the operator/monitor can contact the power component TP to the conductive element P1, and the ground component TG to the conductive element P2, and then connect the test component The power supply is applied, so that the power component TP is electrically connected to the conductive element P1 and the ground component TG is electrically connected to the conductive element P2 to generate a potential difference and current between the conductive element P1 and the conductive element P2, and then obtain the first state F1 accordingly. The voltage value and current value of the placed semiconductor device 300. The operator/monitor can calculate the resistance value by using the voltage value and the current value obtained by the monitoring method as described above.

In some embodiments, the test element may be a detection instrument such as a probe station, but this disclosure is not intended to be limiting.

Please refer to Figure 6. In another embodiment of the present disclosure, the semiconductor device 300 includes a first metal layer 310, an offset second metal layer 330S, and a conductive via pillar 340. The difference in this embodiment is that the offset second metal layer 330S has a coverage offset during the manufacturing process of the semiconductor device 300 (for example, the second metal layer 330 does not completely cover all the conductive via pillars 340 in the top view). Such coverage offset may be caused by the fact that the second metal layer 330 is not aligned with the first metal layer 310 and the conductive via pillars 340 located below it during the process of forming the second metal layer 330 . Specifically, the finger-shaped winding pattern of the offset second metal layer 330S is at least entirely offset relative to the conductive via 340, so the resulting finger-shaped winding pattern of the offset second metal layer 330S is relative to the normally fabricated finger-shaped winding pattern. The finger winding pattern of the second metal layer 330 has an offset in the vertical direction (ie, equivalent to the direction Y in FIG. 6).

In a usage scenario, the operator/monitor can contact the power component TP to the conductive element P1 electrically connected to the first metal layer 310, and the ground component TG to contact the conductive element electrically connected to the offset second metal layer 330S. Component P2, and then apply power to the test component, so that the power component TP is electrically connected to the conductive component P1 and the ground component TG is electrically connected to the conductive component P2 to generate a potential difference and current between the conductive component P1 and the conductive component P2, and then based on Another voltage value and another current value of the semiconductor device 300 placed in the first aspect F1 are obtained. In this case, another resistance value (ie, the resistance value of the semiconductor element 300 having the offset second metal layer 330S) calculated from the above-mentioned other voltage value and the other current value measured by the test element is relatively different. Compared with the resistance value calculated from the above-mentioned voltage value and current value measured by the test device (ie, the resistance value of the semiconductor device 300 with the second metal layer 330 that is not offset, or the "ideal resistance value") is more big.

In other words, when the operator/monitor has not yet learned whether the semiconductor device 300 has coverage offset during the manufacturing process, he or she can perform step S103 to electrically connect the power component TP and the ground component TG of the test component respectively. If the calculated resistance value of conductive element P1 or conductive element P2 is greater than the ideal resistance value, the operator/monitor can determine that the semiconductor element 300 has coverage bias in at least one direction (for example, direction Y). shift.

Next, step S104 is performed: placing the semiconductor element in the second aspect.

Please refer to Figure 8. As shown in FIG. 8 , it shows several semiconductor elements 300 and conductive elements P1 and P2 located on the dicing lane SL (not shown) of the wafer W (not shown) similar to that shown in FIG. 5 , a schematic arrangement of conductive elements P3 and P4. The arrangement of the semiconductor element 300, the conductive element P1, the conductive element P2, the conductive element P3 and the conductive element P4 in Figure 8 is rotated 90 degrees relative to the arrangement in Figure 5 (for example, Figure 8 is clockwise relative to Figure 5 rotated 90 degrees).

As shown in FIG. 8 , each semiconductor device 300 located on the scribe line SL of the wafer W includes a flat first metal layer 310 and a second metal layer 330 with a finger-like winding pattern, wherein the finger-like The winding patterns extend elongated in at least one direction (for example, direction X) and are arranged in parallel in another direction (for example, direction Y). In other words, each semiconductor device 300 is placed on the wafer W in the same manner. In FIG. 8 , the semiconductor device 300 is placed along the wafer W, so that the finger-like winding pattern of the second metal layer 330 is elongated along the vertical direction (ie, equivalent to the direction X in FIG. 8 ) and Arranged in parallel in the horizontal direction (ie, equivalent to the direction Y in Figure 8), such an aspect is defined as the second aspect F2.

In one usage scenario, the operator/monitor may rotate wafer W 90 degrees (eg, 90 degrees clockwise or counterclockwise). For example, the semiconductor device 300 shown in FIG. 5 is rotated 90 degrees clockwise). This causes the semiconductor device 300 to change from the first aspect F1 as shown in FIG. 5 to the second aspect F2 as shown in FIG. 8 .

Please refer to Figure 9 and Figure 10 again. In this embodiment, one of the first metal layer 310 and the second metal layer 330 is electrically connected to the conductive element P2, and the other of the first metal layer 310 and the second metal layer 330 is electrically connected to the conductive element P2. P3. For example, as shown in Figures 9 and 10, the first metal layer 310 is electrically connected to the conductive element P2, and the second metal layer 330 is electrically connected to the conductive element P3. Alternatively, in some embodiments, the first metal layer 310 may be electrically connected to the conductive element P3, and the second metal layer 330 may be electrically connected to the conductive element P2.

In some embodiments, as shown in Figures 8, 9 and 10, one of the first metal layer 310 and the second metal layer 330 can be electrically connected to the conductive element P2 through the wire L1. The other one of the first metal layer 310 and the second metal layer 330 can be electrically connected to the conductive element P3 through the wire L2. For example, the first metal layer 310 can be electrically connected to the conductive element P2 through the wire L1, and the second metal layer 330 can be electrically connected to the conductive element P3 through the wire L2.

Next, step S105 is performed: connect the power component and the ground component of the test component to the second conductive component and the third conductive component respectively to obtain the second voltage value and the second current value of the semiconductor component placed in the second manner.

Please refer to FIG. 8 , which illustrates a schematic diagram of one of the monitoring stages of the semiconductor device monitoring method 100 . In this embodiment, the voltage value and current value of the semiconductor element 300 placed in the second aspect F2 can be obtained by electrically connecting the test element (not shown) to the conductive element P2 and the conductive element P3. In this embodiment, one of the power component TP and the ground component TG is electrically connected to the conductive element P1, and the other one of the power component TP and the ground component TG is electrically connected to the conductive element P2. In a usage scenario, as shown in Figures 8, 9 and 10, the operator/monitor can contact the power component TP to the conductive component P2, and the ground component TG to the conductive component P3, and then connect the test component The power is supplied, so that the power component TP is electrically connected to the conductive element P2 and the ground component TG is electrically connected to the conductive element P3 to generate a potential difference and current between the conductive element P2 and the conductive element P3, and then obtain the second state F2 accordingly. The voltage value and current value of the placed semiconductor device 300. The operator/monitor can calculate the resistance value by using the voltage value and the current value obtained by the monitoring method as described above.

Please refer to Figure 9. In another embodiment of the present disclosure, the semiconductor device 300 includes a first metal layer 310, an offset second metal layer 330S and a conductive via pillar 340 as shown in FIG. 6 . Specifically, the finger winding pattern of the offset second metal layer 330S is at least entirely offset relative to the conductive via pillar 340, and because the semiconductor device 300 of FIG. 9 is rotated clockwise relative to the semiconductor device 300 of FIG. 6 90 degrees, so the resulting finger winding pattern of the offset second metal layer 330S is in the horizontal direction relative to the finger winding pattern of the normally fabricated second metal layer 330 (i.e., equivalent to that in FIG. 9 has an offset in direction Y).

In a usage scenario, the operator/monitor can contact the power component TP to the conductive element P2 electrically connected to the first metal layer 310, and the ground component TG to contact the conductive element electrically connected to the offset second metal layer 330S. Component P3, and then apply power to the test component, so that the power component TP is electrically connected to the conductive component P2 and the ground component TG is electrically connected to the conductive component P3 to generate a potential difference and current between the conductive component P2 and the conductive component P3, and then based on Another voltage value and another current value of the semiconductor device 300 placed in the second aspect F2 are obtained. In this case, since the semiconductor element 300 of the second aspect F2 is rotated 90 degrees relative to the semiconductor element 300 of the first aspect F1, the other voltage value and the other current value measured by the test element are The other calculated resistance value (i.e., the resistance value of the semiconductor device 300 with the offset second metal layer 330S) is the calculated resistance value (i.e., the resistance value with The resistance value of the semiconductor device 300 of the non-offset second metal layer 330 (also known as the “ideal resistance value”) is theoretically the same.

In summary, when the operator/monitor has not yet learned whether the semiconductor device 300 has coverage offset during the manufacturing process, he or she can perform steps S103 and S105 to connect the power component TP and ground of the test device. The component TG is electrically connected to the conductive element P1 or the conductive element P2 respectively, and then is electrically connected to the conductive element P2 or the conductive element P3 respectively. If the calculated resistance of the semiconductor element 300 in the first aspect F1 and/or the second aspect F2 If the value is greater than the ideal resistance value, the operator/monitor can determine that the semiconductor device 300 has coverage offset in at least one direction (eg, direction X and/or direction Y).

By executing the above steps S101 , S102 , S103 , S104 and S105 , the operator/monitor can reliably detect the possible coverage offset of the semiconductor device 300 through the semiconductor device monitoring method 100 .

The semiconductor device monitoring method 100 has advantages. The advantage is that the operator/monitor can monitor whether several semiconductor elements on the entire wafer W have coverage offset in at least one direction by monitoring adjacent semiconductor elements. Moreover, by executing the semiconductor element monitoring method 100, the operator/monitor can promptly reflect the monitored coverage deviation to the front-end process technicians to avoid material waste in the manufacturing process of the semiconductor element and save the cost of the semiconductor element. Process time.

Please refer to FIG. 11 , which is a flowchart of another method 1100 for monitoring a semiconductor device according to an embodiment of the present disclosure. As shown in FIG. 11 , the semiconductor element monitoring method 1100 includes step S1101, step S1102, step S1103, step S1104, and step S1105. When this article describes steps S1101 to S1105 in Figure 11 in detail, please refer to Figures 2A and 2B at the same time.

The operations of step S1101, step S1102, step S1103, step S1104 and step S1105 are described in detail below.

In this embodiment, step S1101, step S1102 and step S1103 are similar to step S101, step S102 and step S103.

In step S1101, the semiconductor device described is actually the same as the aforementioned semiconductor device 200 shown in FIG. 2B or the semiconductor device 300 shown in FIGS. 3 to 10.

In step S1102, the operator/monitor may first place the wafer W as shown in Figure 2A, so that the conductive elements Pa and the conductive elements Pb are alternately arranged in the horizontal direction of Figure 2B (ie, as in the first aspect F1).

In step S1103, the operator/monitor can electrically connect the power component TP and the ground component TG of the test component (not shown), such as the conductive component Pa or the conductive component Pb, respectively, to obtain, for example, placement in the first aspect F1 The first voltage value and the first current value of the semiconductor device 200 (or the semiconductor device 300).

In this embodiment, similarly to step S104, step S1104 changes the semiconductor element 200 (or the semiconductor element 300) from being placed in the first aspect F1 to being placed in the second aspect F2. However, step S1104 is different from step S104. In step S1104, the semiconductor element 200 (or the semiconductor element 300) refers to the semiconductor element 200 located between the conductive element Pc and the conductive element Pd. It can be seen that the difference between step S1104 and step S104 is that the conductive element (for example, conductive element P2) is reused when performing step S104, but step S1104 uses a conductive element that is not repeated in step S1102 and step S1103.

In this embodiment, step S1105 is different from step S105. In step S1105, the operator/monitor electrically connects the power component TP and the ground component TG of the test component to the conductive component Pc and the conductive component Pd, respectively, to obtain the semiconductor component 200 (or semiconductor component) placed in the second aspect F2 300) the second voltage value and the second current value. It can be seen that the difference between step S1105 and step S105 is that the conductive element (for example, conductive element P2) is reused when performing step S103, but step S1105 uses a conductive element that is not repeated in step S1102 and step S1103. Specifically, the operator/monitor electrically connects the power component TP and the ground component TG to the conductive element Pa and the conductive element Pb, and then electrically connects the conductive element Pc and the conductive element Pd respectively to obtain the semiconductor element 200 (or The above-mentioned first voltage value, first current value, second voltage value and second current value of the semiconductor device 300).

By executing the above steps S1101, S1102, S1103, S1104 and S1105, the operator/monitor can reliably monitor possible coverage of the semiconductor element 200 (or semiconductor element 300) through the semiconductor element monitoring method 1100. offset.

The semiconductor device monitoring method 1100 has advantages. The advantage is that when any conductive element on the dicing line SL of the wafer W is damaged, the operator/monitor can monitor the non-adjacent semiconductor elements or the presence of several semiconductor elements on the entire wafer W. Coverage offset in at least one direction. Moreover, by executing the semiconductor element monitoring method 1100, the operator/monitor can promptly reflect the monitored coverage deviation to the front-end process technicians to avoid material waste in the manufacturing process of the semiconductor element and save the cost of the semiconductor element. Process time.

From the above detailed description of the specific embodiments of the present disclosure, it can be clearly seen that in the monitoring method of the semiconductor element of the present disclosure, since the first voltage value of the semiconductor element placed in the first aspect and the first After the current value, the semiconductor element is placed in a second aspect, and its second voltage value and second current value are obtained accordingly, and then the resistance values of the semiconductor element in several directions are calculated respectively so that the semiconductor element can be placed on the production line The problem of coverage offset is reliably detected, and it is determined in which direction the above-mentioned coverage offset occurs. In addition, in the monitoring method of the semiconductor element of the present disclosure, since the semiconductor element has completed the measurement of the voltage value and current value when placed in the first aspect and the second aspect on the production line, the monitor can Monitored problems can be reported to front-end process technicians in a timely manner, which can not only avoid material waste during the manufacturing process of semiconductor components, but also achieve the purpose of saving process time of semiconductor components.

The above content summarizes the features of several embodiments so that those familiar with this technology can better understand the aspects of this case. Those skilled in the art should understand that the above may be readily used as a basis for designing or modifying other variations without departing from the spirit and scope of the present application in order to carry out the same purposes and/or implementations of the embodiments described herein. Same advantages. The above contents should be understood as examples of the present disclosure, and the scope of protection shall be subject to the scope of the patent application.

100,1100: Monitoring methods for semiconductor components

200,300: Semiconductor components

310: First metal layer

320: Dielectric material layer

330: Second metal layer

330S: Offset second metal layer

340: Conductive connecting pillar

D:wafer

F1: first form

F2: Second form

L1, L2: Wires

P,P1,P2,P3,P4,Pa,Pb,Pc,Pd: conductive components

S101, S102, S103, S104, S105, S1101, S1102, S1103, S1104, S1105: Steps

SL: cutting lane

TP: power component

TG: ground component

W:wafer

X,Y: direction

In order to make the above and other objects, features, advantages and embodiments of the present disclosure more obvious and understandable, the accompanying drawings are described as follows: FIG. 1 is a flowchart illustrating a method for monitoring a semiconductor device according to an embodiment of the present disclosure. Figure 2A is a schematic diagram illustrating a wafer according to an embodiment of the present disclosure. Figure 2B is a partial enlarged view of a wafer according to an embodiment of the present disclosure. FIG. 3 is a schematic diagram illustrating a semiconductor device according to an embodiment of the present disclosure. FIG. 4 is a schematic diagram illustrating a semiconductor device according to an embodiment of the present disclosure. FIG. 5 is a schematic diagram illustrating a monitoring stage of a monitoring method for a semiconductor device according to an embodiment of the present disclosure. FIG. 6 is a schematic diagram illustrating a monitoring stage of a method for monitoring a semiconductor device according to an embodiment of the present disclosure. FIG. 7 is a schematic diagram illustrating a monitoring stage of a method for monitoring a semiconductor device according to an embodiment of the present disclosure. FIG. 8 is a schematic diagram illustrating a monitoring stage of a method for monitoring a semiconductor device according to an embodiment of the present disclosure. FIG. 9 is a schematic diagram illustrating a monitoring stage of a method for monitoring a semiconductor device according to an embodiment of the present disclosure. FIG. 10 is a schematic diagram illustrating a monitoring stage of a method for monitoring a semiconductor device according to an embodiment of the present disclosure. FIG. 11 is a flow chart illustrating a method for monitoring a semiconductor device according to an embodiment of the present disclosure.

Domestic storage information (please note in order of storage institution, date and number) without Overseas storage information (please note in order of storage country, institution, date, and number) without

100: Monitoring methods for semiconductor components

S101, S102, S103, S104, S105: Steps

Claims (9)

A method for monitoring a semiconductor element, including: providing a semiconductor element, the semiconductor element includes a first metal layer, a second metal layer and one or more conductive connecting pillars, the second metal layer is disposed on the first metal layer Above, the one or more conductive connecting pillars are connected between the first metal layer and the second metal layer; the semiconductor element is placed in a first manner, wherein the first metal layer is electrically connected to a first conductive component and the second metal layer is electrically connected to a second conductive component; the semiconductor component is placed in a second manner, wherein the first metal layer is electrically connected to the second conductive component and the second metal layer is electrically connected A third conductive element, wherein a phase difference between the semiconductor element in the first aspect and the semiconductor element in the second aspect is 90 degrees; a power component and a ground component of a test component are electrically connected respectively Sexually connecting the first conductive element and the second conductive element to obtain a first voltage value and a first current value of the semiconductor element placed in the first manner; and connecting the power component of the test element and The ground component is electrically connected to the second conductive element and the third conductive element respectively to obtain a second voltage value and a second current value of the semiconductor element placed in the second manner. The method of claim 1, wherein the first conductive element, the second conductive element and the third conductive element are electrical measurement pads. The method of claim 1, wherein the semiconductor elements of the first aspect are arranged in a first direction, and the semiconductor elements of the second aspect are arranged in a second direction perpendicular to the first direction. arranged in the direction. The method of claim 1, wherein the test component is a probe station. The method of claim 1, wherein the step of electrically connecting the power component and the ground component of the test component to the first conductive component and the second conductive component respectively is performed in the first mode The step of placing the semiconductor element is performed after and before the step of placing the semiconductor element in the second aspect. The method of claim 1, wherein the step of electrically connecting the power component and the ground component of the test component to the second conductive component and the third conductive component respectively is performed in the second mode After the step of placing the semiconductor component. The method of claim 1, further comprising: placing the semiconductor device in the second aspect, wherein the first metal layer is electrically connected to the third conductive element and the second metal layer is connected to a fourth conductive element; and electrically connect the power component and the ground component of the test component respectively The third conductive element and the fourth conductive element are connected to obtain the second voltage value and the second current value of the semiconductor element placed in the second manner. The method of claim 7, wherein the step of electrically connecting the power component and the ground component of the test component to the third conductive component and the fourth conductive component respectively is performed when the power component and the ground component of the test component are electrically connected to each other. After the step of electrically connecting the power component and the ground component to the first conductive component and the second conductive component respectively. The method of claim 7, wherein the step of electrically connecting the power component and the ground component of the test component to the third conductive component and the fourth conductive component respectively is performed in the second mode After the step of placing the semiconductor component.

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