CN112103203B - Semiconductor test structure, forming method thereof and test method of semiconductor device - Google Patents

Abstract

The invention provides a semiconductor test structure, a forming method thereof and a test method of a semiconductor device, wherein the semiconductor test structure comprises the following components: the device comprises at least one semiconductor device, at least two test ends and at least four unidirectional conduction structures; wherein the semiconductor device is formed on a substrate; one semiconductor device is connected with two test terminals; two one-way conduction structures are connected in parallel between one test end and one semiconductor device, and the conduction directions of the two one-way conduction structures are opposite. When the semiconductor testing structure provided by the invention is used for testing a semiconductor device, the abnormal position can be positioned, so that failure analysis can be carried out only on the abnormal position, the condition that machine resources and human resources of the failure analysis are wasted due to blind and comprehensive failure analysis is avoided, the efficiency is improved, and the cost is reduced.

Description

Semiconductor test structure, forming method thereof and test method of semiconductor device

Technical Field

The invention relates to the technical field of semiconductors, in particular to a semiconductor test structure, a forming method thereof and a test method of a semiconductor device.

Background

In the field of semiconductor technology, test structures are usually formed on a wafer for reliability testing of the wafer.

In the related art, the test structure includes a semiconductor device, a connection structure and a pad, the connection structure includes a plurality of metal lines, and two adjacent metal lines are connected by plugs. One end of the connecting structure is connected with the bonding pad, and the other end of the connecting structure is connected with the semiconductor device. And each semiconductor device may connect, for example, two pads. Fig. 1 is a schematic structural view of a semiconductor test structure in the related art, and fig. 2 is an equivalent circuit diagram of a semiconductor test structure in the related art, in which, as shown in fig. 1 and 2, a semiconductor device is connected to a first pad and a second pad through a connection structure C and a connection structure D, respectively. When testing the semiconductor device, a high potential may be applied to the first pad, and a low potential may be applied to the second pad so that the first pad, the connection structure C, the semiconductor device, the connection structure D, and the second pad form a path, thereby reading an electrical parameter of the semiconductor device, determining whether the read electrical parameter is normal, and when abnormal, performing failure analysis on the test structure to determine the cause of the abnormality.

The reasons for the abnormality of the read electrical parameters are generally: a semiconductor device abnormality or a connection structure abnormality. However, since the test method in the related art can only test the abnormal condition and cannot locate the abnormal position, that is, it is impossible to determine that the semiconductor device is abnormal or the connection structure is abnormal, when the electrical parameter is detected to be abnormal, the semiconductor test structure needs to be subjected to a comprehensive failure analysis, which wastes the resources of the factory failure analysis, reduces the efficiency, and increases the cost.

Disclosure of Invention

The invention aims to provide a semiconductor test structure, a forming method thereof and a test method of a semiconductor device, and aims to solve the technical problems that the test method of the semiconductor device in the related art wastes resources for failure analysis and reduces efficiency.

To solve the above technical problem, in a first aspect, the present invention provides a semiconductor test structure, including:

a substrate on which a semiconductor device is formed; and the number of the first and second groups,

the test terminals are electrically connected with the semiconductor devices, and one semiconductor device is connected with two test terminals;

the testing end is connected with the semiconductor device through a one-way conduction structure, two one-way conduction structures are connected in parallel between one testing end and one semiconductor device, and the conduction directions of the two one-way conduction structures are opposite.

Optionally, the unidirectional via structure includes a first plug, a layer of metal line, and a second plug; the layer of metal wire is electrically connected with the semiconductor device through the first plug and is electrically connected with the test end through the second plug, and a one-way conduction device is formed in the layer of metal wire.

Optionally, the unidirectional via structure includes a first plug, at least two layers of metal lines, a third plug for electrically connecting metal lines of adjacent layers, and a second plug; the bottom layer metal wire of the at least two layers of metal wires is electrically connected with the semiconductor device through a first plug, the top layer metal wire of the at least two layers of metal wires is electrically connected with the test end through a second plug, and a one-way conduction device is formed in any one layer of metal wire of the at least two layers of metal wires.

Optionally, the unidirectional conducting device includes a PN junction.

In a second aspect, the present invention provides a method for forming a semiconductor test structure, the method comprising:

providing a substrate, wherein a semiconductor device is formed on the substrate;

forming a unidirectional conduction structure and a test end on the substrate;

the testing ends are connected with the semiconductor devices through unidirectional conduction structures, one semiconductor device is connected with two testing ends, two unidirectional conduction structures are connected in parallel between one testing end and one semiconductor device, and the conduction directions of the two unidirectional conduction structures are opposite.

Optionally, the method for forming the unidirectional conducting structure and the test end on the substrate includes:

forming a first dielectric layer on the substrate, and forming four first plugs in the first dielectric layer, each first plug being electrically connected to the semiconductor device;

forming N layers of metal interconnection structures on the first dielectric layer, wherein N is a positive integer, and each layer of metal interconnection structure comprises four metal wires which are separately arranged; when N is 1, the N layers of metal interconnection structures comprise a layer of metal interconnection structure, each metal wire in the layer of metal interconnection structure is connected to a first plug respectively, and a one-way conduction device is formed in each metal wire in the layer of metal interconnection structure; when N is larger than 1, each metal wire of a bottom layer metal interconnection structure in the N layers of metal interconnection structures is respectively connected to a first plug, each metal wire of each layer of metal interconnection structure in the N layers of metal interconnection structures is connected to one metal wire of an adjacent layer of metal interconnection structure through a third plug, so that a plurality of groups of N layers of metal wires connected in a stacked mode are formed, and a one-way conduction device is formed in any one layer of metal wire in each group of N layers of metal wires connected in the stacked mode; the conducting direction of the one-way conducting devices in at least part of the metal wires in the metal wires with the one-way conducting devices is opposite to the conducting direction of the one-way conducting devices in other metal wires;

forming a second dielectric layer on the N-layer metal interconnection structure, wherein four second plugs are formed in the second dielectric layer; when N is 1, and the N-layer metal interconnection structure comprises a layer of metal interconnection structure, each second plug is connected to one metal wire in the layer of metal interconnection structure, and the first plug, the metal wire and the second plug which are connected with each other form a one-way conduction structure; when N is larger than 1, each second plug is connected to one metal wire in a top-layer metal interconnection structure of the N-layer metal interconnection structure, and the first plugs, the N-layer metal wires and the second plugs which are connected with one another form a one-way conduction structure;

and forming two testing ends on the second medium layer, wherein each testing end is correspondingly connected with two one-way conduction structures, and the conduction directions of the two one-way conduction structures are opposite.

Optionally, the unidirectional conducting device includes a PN junction;

and the method for forming the one-way conduction device in the metal wire comprises the following steps:

defining a first area and a second area which are adjacent in the metal wire;

and respectively injecting N-type ions and P-type ions into the first region and the second region to form a PN junction.

In a third aspect, the present invention also provides a method for testing a semiconductor device, the method comprising:

providing the semiconductor test structure according to the first aspect, wherein in the semiconductor test structure, a first unidirectional conducting structure and a second unidirectional conducting structure are connected in parallel between one test end and one semiconductor device, and conducting directions of the first unidirectional conducting structure and the second unidirectional conducting structure are opposite;

applying a test voltage to the test end of the semiconductor test structure to enable the first one-way conduction structure between the test end and the semiconductor device to be conducted, and obtaining a first electrical parameter of the semiconductor device;

judging whether the first electrical parameter is within a standard range to test whether the semiconductor test structure is normal or not and obtain a first test result; when the first test result is: stopping executing the test method when the semiconductor test structure is normal; when the first test result is: when the semiconductor test structure is abnormal, applying reverse voltage of the test voltage to the test end to enable a second one-way conduction structure between the test end and the semiconductor device to be conducted, obtaining a second electrical parameter of the semiconductor device, and judging whether the second electrical parameter is in a standard range to test whether the semiconductor test structure is normal again to obtain a second test result;

judging whether the first test result is the same as the second test result, and if so, determining that an abnormal position in the semiconductor test structure is the semiconductor device; and when the abnormal positions are different, determining that the abnormal position in the semiconductor test structure is a first unidirectional conduction structure.

Optionally, one of the semiconductor devices is connected with two test terminals, which are a first test terminal and a second test terminal respectively.

Optionally, the test method includes:

applying a first potential to the first test end, applying a second potential to the second test end, wherein the first potential is higher than the second potential, so that a first path is formed among the first test end, a first unidirectional conduction structure connected with the first test end, the semiconductor device, a first unidirectional conduction structure connected with the second test end, and a first electrical parameter of the semiconductor device is obtained;

judging whether the first electrical parameter is within a standard range to test whether the semiconductor test structure is normal or not and obtain a first test result; when the first test result is: stopping executing the test method when the semiconductor test structure is normal; when the first test result is: when the semiconductor test structure is abnormal, the second electric potential is applied to the first test end, the first electric potential is applied to the second test end, a second channel is formed among the first test end, a second unidirectional conduction structure connected with the first test end, the semiconductor device, the second unidirectional conduction structure connected with the second test end and the second test end, a second electrical parameter of the semiconductor device is obtained, and whether the second electrical parameter is in the standard range or not is judged to retest whether the semiconductor test structure is normal or not and a second test result is obtained;

judging whether the first test result is the same as the second test result, and if so, determining that an abnormal position in the semiconductor test structure is the semiconductor device; and when the abnormal positions are different, determining that the abnormal position in the semiconductor test structure is a first unidirectional conduction structure.

In summary, the two unidirectional conducting structures with opposite conducting directions are connected in parallel between the testing end and the semiconductor device, so that when a testing voltage is applied to the testing end to test the semiconductor device, only a part of the unidirectional conducting structures in the testing end and the semiconductor device are conducted, and the other unidirectional conducting structures are cut off, so that a testing result is obtained. When the test result is abnormal, the reverse voltage of the test voltage can be applied to the test end for testing again, and at the moment, the test end is conducted with only the other one-way conduction structures in the semiconductor device, and another test result can be obtained. In view of the fact that the conducted unidirectional conduction structures are different in the two tests, whether the abnormal position is a semiconductor device or the unidirectional conduction structure can be determined by comparing whether the test results obtained by the two tests are the same or not, failure analysis is only needed to be carried out on the abnormal position, failure analysis is not needed to be carried out on other positions, the situation that machine resources and human resources of the failure analysis are wasted due to blind and comprehensive failure analysis can be avoided, efficiency is improved, and cost is reduced.

In addition, when the abnormal position is determined to be in the one-way conduction structure, failure analysis is not needed, resources can be further saved, cost is reduced, and efficiency is improved.

Drawings

FIG. 1 is a schematic diagram of a semiconductor test structure according to the related art;

FIG. 2 is an equivalent circuit diagram of a semiconductor test structure in the related art;

FIG. 3 is a flowchart illustrating a method for forming a semiconductor test structure according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a semiconductor test structure obtained after the step 200a is executed according to an embodiment of the present invention;

FIG. 5 is a top view of the semiconductor test structure shown in FIG. 4;

FIG. 6 is a schematic structural diagram of a semiconductor test structure after a first step or a second step is performed according to a first embodiment of the present invention;

FIG. 7 is a top view of the semiconductor test structure shown in FIG. 6;

FIG. 8 is a schematic structural diagram illustrating a semiconductor test structure after performing a second step according to an embodiment of the present invention;

FIG. 9 is a schematic structural diagram of a semiconductor test structure after performing step two according to a first embodiment of the present invention;

FIG. 10 is a schematic structural diagram of a semiconductor test structure after step three is performed according to an embodiment of the present invention;

FIG. 11 is a schematic structural diagram illustrating a semiconductor test structure after step three according to an embodiment of the present invention;

FIG. 12 is a schematic diagram illustrating a semiconductor test structure after performing step 400a according to one embodiment of the present invention;

FIG. 13 is a schematic structural diagram illustrating a semiconductor test structure after performing step 500a according to one embodiment of the present invention;

FIG. 14 is a schematic structural diagram of a semiconductor test structure according to a second embodiment of the present invention;

FIG. 15 is an equivalent circuit diagram of the semiconductor test structure shown in FIG. 14;

FIG. 16 is a schematic structural diagram of another semiconductor test structure according to a second embodiment of the present invention;

fig. 17 is a flowchart illustrating a testing method of a semiconductor device according to a third embodiment of the present invention.

Reference numerals:

reference numerals of figures 1-2 referred to in the background: C. d-connecting structure.

Reference numerals of figures 3-17 in embodiments of the invention: 00-a substrate; 10-a first dielectric layer; 11-a first plug; 20-an underlying metal interconnect structure; 21-bottom layer metal lines; 30-an interlayer dielectric layer; 31-a third plug; 40-a second level metal interconnect structure; 41-top layer metal lines; 50-a second dielectric layer; 51-a second plug; 01-a first set of N layer metal lines connected in a stacked manner; 02-a second set of N layers of metal lines connected in a stacked manner; 03-a third group of N layers of metal wires connected in a stacked manner; 04-a fourth group of N layers of metal wires connected in a stacked manner; aa-a first unidirectional conducting device; bb-a second unidirectional conducting device; a-a first unidirectional conducting structure; b-a second unidirectional conducting structure.

Detailed Description

The semiconductor test structure, the forming method thereof and the testing method of the semiconductor device according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

Example one

The embodiment of the invention provides a method for forming a semiconductor test structure. Fig. 3 is a schematic flowchart of a method for forming a semiconductor test structure according to an embodiment of the present invention, and as shown in fig. 3, the method for forming the semiconductor test structure may include:

step 100a, providing a substrate, wherein a semiconductor device is formed on the substrate.

The substrate may be a substrate after performing front end of line processing, and the semiconductor device may include, for example, a MOS transistor or the like as is well known in the art. And the semiconductor device can be formed in the dicing street region of the substrate, and the semiconductor device formed in the dicing street region and the semiconductor device formed in the chip region of the substrate are formed simultaneously by the same process, so that the reliability of the semiconductor device in the chip region can be reflected equivalently by the detection result of the reliability of the semiconductor device in the dicing street region.

Step 200a, forming a first dielectric layer on the substrate, and forming at least four first plugs in the first dielectric layer, wherein each first plug is electrically connected to the semiconductor device.

Fig. 4 is a schematic structural diagram of a semiconductor test structure obtained after the step 200a is performed according to an embodiment of the present invention, and fig. 5 is a top view of the semiconductor test structure shown in fig. 4. As shown in fig. 4, a first dielectric layer 10 is formed on the substrate 00, and four first plugs 11 are formed in the first dielectric layer 10. The first dielectric layer 10 may be made of silicon oxide or silicon oxynitride, for example, and may be formed by a Chemical Vapor Deposition (CVD) process. The material of the first plug 11 may be, for example, metal copper, and the method for forming the first plug may include: forming a through hole in the first dielectric layer 10 by using a photolithography and etching process, depositing a barrier layer and a copper seed layer by using a Physical Vapor Deposition (PVD) method, forming a first conductive layer (for example, a copper layer) on the first dielectric layer 10 by using an electroplating process, filling the through hole in the first dielectric layer 10 with the first conductive layer, and removing the first conductive layer on the first dielectric layer 10 by using a chemical mechanical polishing process.

Step 300a, forming N layers of metal interconnection structures on the first dielectric layer 10, where N is a positive integer, and each layer of metal interconnection structure includes at least four metal lines which are separately arranged.

In a specific embodiment, N is 1, that is, a metal interconnection structure is formed on the first dielectric layer 10, and specifically, the formation method may include the following steps:

the method comprises the steps of firstly, depositing a third dielectric layer on the first dielectric layer 10, forming at least four openings in the third dielectric layer by utilizing photoetching and etching processes, wherein each opening formed in the third dielectric layer exposes one first plug 11, then, electroplating a first metal layer (such as a copper layer) on the third dielectric layer, filling each opening in the third dielectric layer with the first metal layer, and removing the first metal layer positioned above the third dielectric layer by utilizing chemical mechanical polishing to form at least four metal wires in the third dielectric layer in a standing manner.

Fig. 6 is a schematic structural diagram of a semiconductor test structure after the first step is performed according to an embodiment of the present invention, and fig. 7 is a top view of the semiconductor test structure shown in fig. 6, as shown in fig. 6, a layer of metal interconnection structure 20 is formed on the first dielectric layer 10, and the layer of metal interconnection structure 20 includes four metal lines 21 separated from each other and a third dielectric layer located between the metal lines 21 separated from each other. And, referring to fig. 7, the sectional shape of the metal wire 21 may be a rectangle.

And secondly, forming a one-way conduction device in each metal wire.

The conducting direction of the one-way conduction device in at least part of the metal lines in all the metal lines in which the one-way conduction device is formed is opposite to the conducting direction of the one-way conduction device in other metal lines, for example, the conducting direction of the one-way conduction device in one half of the metal lines in all the metal lines in which the one-way conduction device is formed can be opposite to the conducting direction of the one-way conduction device in the other half of the metal lines.

In this embodiment, the unidirectional conducting device may be a PN junction, and the method for forming the PN junction in the metal line may be: defining a first area and a second area which are adjacent in the metal wire, wherein the first area and the second area are positioned in the metal wire, and the first area and the second area are adjacent; and respectively injecting N-type ions and P-type ions into the first area and the second area to form an N-type area in the first area and a P-type area in the second area, so that the adjacent N-type area and the P-type area are formed in the metal wire, a PN junction is formed in the metal wire, and the conduction direction of the PN junction is the direction of the P-type area pointing to the N-type area.

Fig. 8 is a schematic structural diagram of a semiconductor test structure after performing the second step according to an embodiment of the present invention, and as shown in fig. 8, two metal lines of four metal lines 21 of the one-layer metal interconnect structure 20 are formed with a first one-way conduction device aa, and the other two metal lines 21 are formed with a second one-way conduction device bb, where conduction directions of the first one-way conduction device aa and the second one-way conduction device bb are opposite.

Further, in another embodiment, if N is greater than 1, the method for forming the N-layer metal interconnection structure may be (for example, a two-layer metal interconnection structure is formed):

firstly, a third dielectric layer is formed on the first dielectric layer 10, wherein the third dielectric layer may be made of silicon oxide or silicon oxynitride, and the third dielectric layer may be formed by a CVD process. And after forming a third dielectric layer, forming at least four openings in the third dielectric layer by using photolithography and etching processes, wherein each opening formed in the third dielectric layer exposes a first plug, then forming a first metal layer (for example, a copper layer) by electroplating on the third dielectric layer, so that the openings in the third dielectric layer are filled with the first metal layer, and removing the first metal layer on the third dielectric layer by using chemical mechanical polishing, so as to form at least four metal lines in the third dielectric layer in a discrete manner, thereby obtaining a bottom metal interconnection structure.

Fig. 6 and 7 show a schematic structural diagram of the semiconductor test structure after the first step is performed, at this time, the metal interconnection structure 20 shown in fig. 6 is substantially a bottom metal interconnection structure 20, the bottom metal interconnection structure 20 is formed on the first dielectric layer 10, the bottom metal interconnection structure 20 includes four metal lines 21 separated from each other and a third dielectric layer located between the metal lines 21 separated from each other, where the metal line 21 formed in the bottom metal interconnection structure 20 may be defined as the bottom metal line 21. And, referring to fig. 7, the cross-sectional shape of the underlying metal line 21 may be rectangular.

And secondly, forming an interlayer dielectric layer on the bottom metal interconnection structure 20, wherein the interlayer dielectric layer can be made of silicon oxide or silicon oxynitride and can be formed by adopting a CVD (chemical vapor deposition) process. After forming an interlayer dielectric layer, forming at least four through holes in the interlayer dielectric layer by utilizing photoetching and etching processes, exposing one metal wire 21 in a bottom-layer metal interconnection structure through each through hole formed in the interlayer dielectric layer, depositing a barrier layer and a copper seed crystal layer on the interlayer dielectric layer by utilizing a PVD (physical vapor deposition) process, forming a third conductive layer (such as a copper layer) on the interlayer dielectric layer by utilizing an electroplating process, filling each through hole in the interlayer dielectric layer with the third conductive layer, and finally removing the third conductive layer on the interlayer dielectric layer by utilizing chemical mechanical polishing to form at least four third plugs in the interlayer dielectric layer, wherein the cross section of each third plug can be rectangular.

Fig. 9 is a schematic structural diagram of the semiconductor test structure after the second step is performed according to the first embodiment of the present invention, as shown in fig. 9, an interlayer dielectric layer 30 is formed on the bottom metal interconnection structure 20, four third plugs 31 are formed in the interlayer dielectric layer 30, and each third plug 31 is electrically connected to one bottom metal line 21 in the bottom metal interconnection structure 20.

And thirdly, forming a fourth dielectric layer on the interlayer dielectric layer 30, wherein the fourth dielectric layer can be made of silicon oxide or silicon oxynitride and can be formed by adopting a CVD (chemical vapor deposition) process. After a fourth dielectric layer is formed, at least four openings are formed in the fourth dielectric layer by utilizing photoetching and etching processes, wherein each opening formed in the fourth dielectric layer exposes a third plug, a second metal layer (such as a copper layer) is formed on the fourth dielectric layer in an electroplating mode, the second metal layer fills each opening in the fourth dielectric layer, and finally the second metal layer above the fourth dielectric layer is removed by utilizing chemical mechanical polishing to obtain a second-layer metal interconnection structure.

Fig. 10 is a schematic structural diagram of the semiconductor test structure after the third step is performed according to the first embodiment of the present invention, as shown in fig. 10, a second-layer metal interconnection structure 40 (i.e., a top-layer metal interconnection structure 40) is formed on the interlayer dielectric layer 30, and the second-layer metal interconnection structure 40 includes four metal lines 41 separated from each other and a fourth dielectric layer located between the metal lines 41 separated from each other. And, each metal line 41 in the second-level metal interconnect structure 40 is connected to one metal line 11 in the bottom-level metal interconnect structure 10 through one third plug 31, wherein the metal line 41 formed in the top-level metal interconnect structure 40 may be defined as the top-level metal line 41.

Then, as can be seen from the above, each metal line in each metal interconnection layer is connected to one metal line in an adjacent metal interconnection layer through a third plug 31, so that multiple sets of stacked and connected N metal lines are formed in the N metal interconnection layers. As shown in fig. 10, four sets of stacked and connected metal lines are formed in the semiconductor test structure, namely, a first set of stacked and connected metal lines 01, a second set of stacked and connected metal lines 02, a third set of stacked and connected metal lines 03 and a fourth set of stacked and connected metal lines 04.

And a unidirectional conducting device is formed in any layer of metal wire in each group of metal wires which are connected in a stacked mode, and the conducting direction of the unidirectional conducting device in at least part of metal wires in all the metal wires in which the unidirectional conducting device is formed in the semiconductor test structure is opposite to the conducting direction of the unidirectional conducting device in other metal wires. For details of the method for forming the unidirectional conducting device, the above description may be referred to, and this embodiment is not described herein again.

For example, referring to fig. 10, a unidirectional-conduction device may be formed in the top metal line 41 of each set of stacked-connection metal lines, wherein a first unidirectional-conduction device aa may be formed in the top metal line 41 of the first set of stacked-connection metal lines 01 and the third set of stacked-connection metal lines 03, and a second unidirectional-conduction device bb may be formed in the top metal line 41 of the second set of stacked-connection metal lines 02 and the fourth set of stacked-connection metal lines 04.

It should be noted that, when N is greater than 1, the one-way-conduction device may be formed in any one of the N layers of metal lines connected in a stacked manner, that is, the one-way-conduction devices in different groups of metal lines connected in a stacked manner may be formed in metal lines in different layers. For example, each set of stacked and connected bottom metal lines may have a unidirectional-conduction device formed therein, or fig. 11 is a schematic structural diagram of another semiconductor test structure after performing step three according to an embodiment of the present invention, which is different from the test structure shown in fig. 10 in that unidirectional-conduction devices are not all formed in the top metal line 41, as shown in fig. 11, a first unidirectional-conduction device aa is formed in the bottom metal line 21 in the first set of stacked and connected metal lines 01, a second unidirectional-conduction device bb is formed in the top metal line 41 in the second set of stacked and connected metal lines 02, a first unidirectional-conduction device aa is formed in the top metal line 41 in the third set of stacked and connected metal lines 03, and a second unidirectional-conduction device bb is formed in the bottom metal line 21 in the fourth set of stacked and connected metal lines 04.

In addition, when the semiconductor device is a MOS transistor, an ion implantation process is usually performed to form a well region in the MOS transistor to obtain a source and a drain. On the basis, an ion implantation process is also required to form the unidirectional conducting device (i.e. PN junction) so as to form a well region in the metal line to form an N-type region and a P-type region. Therefore, when the well region in the semiconductor device is formed through one-step ion implantation technology, the well region is synchronously formed in the metal wire to form a PN junction, so that the technology can be saved, and the cost can be reduced.

Step 400a, forming a second dielectric layer on the N-layer metal interconnection structure, wherein at least four second plugs are formed in the second dielectric layer.

The second dielectric layer may be made of silicon oxide or silicon oxynitride, for example, and may be formed by a CVD process. The second plug can be made of metal copper; the method for forming the second plug may include: forming a through hole in a second dielectric layer by using photoetching and etching processes, depositing a barrier layer and a copper seed crystal layer on the second dielectric layer by using a PVD (physical vapor deposition) process, forming a second conductive layer (such as a copper layer) on the second dielectric layer by using an electroplating process, filling the through hole in the second dielectric layer with the second conductive layer, and finally removing the conductive layer on the second dielectric layer by using chemical mechanical polishing. The second plug may have a rectangular cross-sectional shape.

Further, in the first embodiment, when N is 1, the N-level metal interconnection structure includes a level of metal interconnection structure, each of the second plugs is connected to one metal line in the level of metal interconnection structure, and the first plug, the metal line, and the second plug that are connected to each other form a unidirectional conducting structure.

When N is larger than 1, each second plug is connected to one metal wire of the top-layer metal interconnection structure of the N-layer metal interconnection structure, and the first plugs, the N-layer metal wires and the second plugs which are connected with one another in a stacked mode form a one-way conduction structure.

Fig. 12 is a schematic structural diagram of a semiconductor test structure after step 400a is performed according to an embodiment of the present invention, as shown in fig. 12, the semiconductor test structure includes two layers of metal interconnection structures, namely, a bottom layer metal interconnection structure 20 and a second layer metal interconnection structure 40 (that is, a top layer metal interconnection structure 40), the semiconductor test structure includes four sets of metal lines connected in a stacked manner, where the four sets of metal lines include: a first group of stacked and connected metal wires 01, a second group of stacked and connected metal wires 02, a third group of stacked and connected metal wires 03 and a fourth group of stacked and connected metal wires 04. And a second dielectric layer 50 is formed on the top-level metal interconnection structure 40, four second plugs 51 are formed in the second dielectric layer 50, and each second plug 51 is connected to one top-level metal line 41 in the top-level metal interconnection structure 40.

As further shown in fig. 12, the first plug 11, the first group of stacked and connected metal lines 01, and the second plug 21, which are connected to each other, form a first unidirectional conductive structure; the first plug 11, the second group of metal wires 02 and the second plug 21 which are connected with each other form a second one-way conduction structure; a first plug 11, a third set of stacked and connected metal lines 03 connected to each other; the second plug 21 forms a third one-way conduction structure; the first plug 11, the fourth group of metal wires 04 and the second plug 21 which are connected with each other in a stacked manner form a fourth unidirectional conducting structure, so that four unidirectional conducting structures are formed. The second unidirectional conduction structure and the third unidirectional conduction structure in the unidirectional conduction structure, which are formed with the first unidirectional conduction device aa, are named as a first unidirectional conduction structure A, the second unidirectional conduction structure and the fourth unidirectional conduction structure in the unidirectional conduction structure, which are formed with the second unidirectional conduction device bb, are named as a first unidirectional conduction structure B, and the conduction direction of the first unidirectional conduction structure A is opposite to the conduction direction of the first unidirectional conduction structure B.

Step 500a, at least two testing terminals are formed on the second dielectric layer 50, each testing terminal is correspondingly connected with at least two unidirectional conduction structures, and the conduction direction of at least one unidirectional conduction structure of the at least two unidirectional conduction structures is opposite to the conduction direction of the other unidirectional conduction structures.

The testing terminal may be, for example, a pad, and the material of the pad may include a metal material, such as metal aluminum. And, the forming method of the pad may include: depositing an insulating layer on the second dielectric layer 50 by using a CVD process, forming at least two openings in the insulating layer by using photolithography and etching processes, exposing a second plug in two unidirectional conductive structures with opposite conductive directions in each opening formed in the insulating layer, and plating a fourth conductive layer (for example, an aluminum layer) on the insulating layer, wherein each opening in the insulating layer is filled with the fourth conductive layer; and then, removing the fourth conducting layer above the insulating layer by chemical grinding to form a bonding pad.

Fig. 13 is a schematic structural diagram of the semiconductor test structure after the step 500a is executed according to the first embodiment of the present invention, and as shown in fig. 13, the semiconductor test structure includes two test terminals, which are a first test terminal and a second test terminal, respectively, and two unidirectional conducting structures with opposite conducting directions, which are a first unidirectional conducting structure a and a second unidirectional conducting structure B, are connected in parallel between each test terminal and the semiconductor device.

Example two

The present embodiment provides a semiconductor test structure, which is mainly formed in the scribe line region of the substrate, and the semiconductor test structure is formed by using the method for forming the semiconductor test structure according to the first embodiment. Fig. 14 is a schematic structural diagram of a semiconductor test structure according to a second embodiment of the present invention, and fig. 15 is an equivalent circuit diagram of the semiconductor test structure shown in fig. 14. As shown in fig. 14, the semiconductor test structure may specifically include:

a substrate (not shown in the drawings) on which a semiconductor device is formed; and the number of the first and second groups,

a test terminal connected to the semiconductor device. The testing end may be, for example, a pad, and the forming method of the pad is described in detail in step 500a of the above embodiment, which is not described herein again.

The semiconductor device comprises a semiconductor device body, a testing end and at least two unidirectional conduction structures, wherein the semiconductor device body is at least connected with two testing ends, the testing ends are connected with the semiconductor device body through the unidirectional conduction structures, the at least two unidirectional conduction structures are connected between one testing end and one semiconductor device body in parallel, and the conduction direction of at least one unidirectional conduction structure in the at least two unidirectional conduction structures is opposite to the conduction direction of other unidirectional conduction structures.

The embodiment of the present invention is described by taking an example that one semiconductor device is connected to two test terminals, and two unidirectional conducting structures are connected between one semiconductor device and one test terminal, as shown in fig. 14 and 15, one semiconductor device is respectively connected to a first test terminal and a second test terminal, two unidirectional conducting structures, namely a first unidirectional conducting structure a and a second unidirectional conducting structure B, may be connected in parallel between one test terminal and one semiconductor device, and the conducting direction of the first unidirectional conducting structure a is opposite to the conducting direction of the second unidirectional conducting structure B.

Further, the unidirectional conducting structure may specifically include: the first plug, N layer metal wire, second plug, N is the positive integer.

When N is 1, the unidirectional conducting structure includes a layer of metal line, the layer of metal line is connected to the semiconductor device through the first plug and is connected to the test end through the second plug, a unidirectional conducting device is formed in the layer of metal line, the unidirectional conducting device may be, for example, a PN junction, and a method for forming the PN junction may be specifically described in step 300a of the above embodiment, which is not described in detail in this embodiment ii.

And when N is larger than 1, the unidirectional conduction structure further comprises a third plug used for electrically connecting metal wires of adjacent layers, a bottom metal wire of the N layers of metal wires is connected with the semiconductor device through the first plug, a top metal wire of the N layers of metal wires is connected with the test end through the second plug, and a unidirectional conduction device is formed in any one layer of metal wire of the N layers of metal wires.

The conducting direction of the one-way conduction devices in at least part of the metal lines in all the metal lines formed with the one-way conduction devices is opposite to the conducting direction of the one-way conduction devices in other metal lines, for example, the conducting direction of the one-way conduction devices in one half of the metal lines in all the metal lines formed with the one-way conduction devices is opposite to the conducting direction of the one-way conduction devices in the other half of the metal lines.

For example, referring to fig. 14, N may be equal to 2, then two metal lines connected in a stacked manner may be included in each of the first unidirectional conductive structure a and the second unidirectional conductive structure B, respectively, the bottom metal line 21 and the top metal line 41, wherein, the bottom layer metal wire 21 is connected to the semiconductor device through the first plug 11, the bottom layer metal wire 21 and the top layer metal wire 41 are connected through the third plug 31, the top layer metal wire 41 is connected to the test terminal through the second plug 51, and a unidirectional conducting device is formed in the bottom layer metal wire 21 in each unidirectional conducting structure, wherein, the conducting direction of the first one-way conducting device aa formed in the first one-way conducting structure A is opposite to the conducting direction of the second one-way conducting device bb formed in the second one-way conducting structure B, so that the conduction directions of the first unidirectional conduction structure A and the second unidirectional conduction structure B are opposite.

In addition, when N is greater than 1, the one-way conduction device may be formed in any one of the N layers of metal lines connected in a stacked manner, that is, the one-way conduction devices in different one-way conduction structures may be formed in metal lines in different layers. For example, fig. 16 is a schematic structural diagram of another semiconductor test structure according to the second embodiment of the present invention, which is different from the test structure shown in fig. 14 in that the unidirectional conducting devices are not all formed in the bottom metal line 21, as shown in fig. 16, a first one-way conduction device aa connected between the first test terminal and the first one-way conduction structure a of the semiconductor device is formed in the bottom layer metal line 21, a second one-way conduction device bb connected between the first test terminal and the second one-way conduction structure B of the semiconductor device is formed in the top layer metal line 41, a first one-way conduction device aa connected between the second test terminal and the first one-way conduction structure a of the semiconductor device is formed in the top layer metal line 41, and a second one-way conduction device bb connected between the second test terminal and the second one-way conduction structure B of the semiconductor device is formed in the bottom layer metal line 21.

It should be further noted that the unidirectional conducting structure is mainly connected to the electrical input end or the electrical output end of the semiconductor device when being connected to the semiconductor device. Specifically, for a unidirectional conducting structure with a conducting direction from a testing terminal to a semiconductor device, it should be connected with an electrical input terminal of the semiconductor device, and for a unidirectional conducting structure with a conducting direction from a semiconductor device to a testing terminal, it should be connected with an electrical output terminal of the semiconductor device. For example, referring to fig. 15, the first unidirectional conducting structure a connected between the first test terminal and the semiconductor device, and the second unidirectional conducting structure B connected between the second test terminal and the semiconductor device are both connected to the electrical input terminal of the semiconductor device; and the second unidirectional conduction structure B connected between the first test end and the semiconductor device and the first unidirectional conduction device A connected between the second test end and the semiconductor device are both connected with the electrical output end of the semiconductor device.

EXAMPLE III

A third embodiment of the present invention provides a method for testing a semiconductor device, and fig. 17 is a schematic flow chart of the method for testing a semiconductor device provided by the third embodiment of the present invention, as shown in fig. 17, the method for testing may include:

step 100b, providing the semiconductor test structure according to the first embodiment, wherein at least one first unidirectional conduction structure and at least one second unidirectional conduction structure with opposite conduction directions are connected in parallel between one test end and one semiconductor device in the semiconductor test structure.

Step 200b, applying a test voltage to the test end of the semiconductor test structure to enable the first unidirectional conduction structure between the test end and the semiconductor device to be conducted, and obtaining a first electrical parameter of the semiconductor device.

For example, the semiconductor test structure includes two test terminals (i.e., a first test terminal and a second test terminal). In this step 200b, referring to fig. 14 and 15 in combination, a first potential (e.g., a high potential) may be applied to the first testing terminal, and a second potential (e.g., a low potential) may be applied to the second testing terminal, so that a first path is formed between the first testing terminal, the first unidirectional conducting structure a connected to the first testing terminal, the semiconductor device, the first unidirectional conducting structure a connected to the second testing terminal, and the second testing terminal, so as to obtain a first electrical parameter of the semiconductor device.

Step 300b, judging whether the first electrical parameter is within a standard range so as to test whether the semiconductor test structure is normal and obtain a first test result; when the first test result is: stopping executing the test method when the semiconductor test structure is normal; when the first test result is: and when the semiconductor test structure is abnormal, applying reverse voltage of the test voltage to the test end to enable the second unidirectional conduction structure between the test end and the semiconductor device to be conducted, acquiring a second electrical parameter of the semiconductor device, and judging whether the second electrical parameter is in a standard range to test whether the semiconductor test structure is normal again and obtain a second test result.

When the first electrical parameter is within the standard range, the semiconductor test structure is determined to be normal, the test method is stopped, otherwise, the semiconductor test structure is determined to be abnormal.

And, when the first test result is: when the semiconductor test structure is abnormal, it may be considered that a semiconductor device in the semiconductor test structure is abnormal or the first unidirectional conduction structure is abnormal. At this time, a second potential (that is, a low potential) may be applied to the first test end, and a first potential (that is, a high potential) may be applied to the second test end, so that a second path is formed between the first test end, the second unidirectional conducting structure B connected to the first test end, the semiconductor device, the second unidirectional conducting structure B connected to the second test end, and the second test end, so as to obtain a second electrical parameter of the semiconductor device, and determine whether the second electrical parameter is within a standard range, so as to determine whether the semiconductor test structure normally obtains a second test result. Then, by comparing the first test result and the second test result, it can be determined whether the abnormal position in the semiconductor test structure is specifically the semiconductor device or the first unidirectional conducting structure (for a specific principle, see the subsequent step 400 b).

Step 400b, judging whether the first test result is the same as the second test result, and if so, executing step 500 b; when different, step 600b is performed.

It should be appreciated, among other things, that when a test voltage is applied to the test terminal, a first path is formed in the semiconductor test structure in which the first unidirectional conducting structure a is conducting. When the reverse voltage of the test voltage is applied to the test end, a second path formed in the test structure is conducted, and a second one-way conduction structure B is conducted in the second path. Wherein, the only difference between the first path and the second path is only that: the conducted one-way conduction structures are different. Based on this, the first test result is: when the semiconductor test structure is abnormal, if the first test result is the same as the second test result, the method comprises the following steps: the results of the two tests are as follows: if the semiconductor test structure is abnormal, it can be determined that the first unidirectional conduction structure a and the second unidirectional conduction structure B are both normal, and the semiconductor device is abnormal, so that step 500B can be executed; if the first test result is different from the second test result, the second test result is: if the semiconductor test structure is normal, it can be determined that the semiconductor device and the second unidirectional conducting structure are normal, and the first unidirectional conducting structure is abnormal, so that step 600b can be executed.

And 500b, determining that the semiconductor device is abnormal, and performing failure analysis on the semiconductor device only.

And step 600b, determining that the first unidirectional conduction structure is abnormal.

In view of the fact that the influence of the abnormal one-way conduction structure on the integrated chip is small, the failure analysis of the first one-way conduction device may be selected in step 600b, or the subsequent steps may be directly performed without performing the failure analysis on the first one-way conduction device.

It should be noted that the semiconductor test structure, the forming method thereof, and the testing method of the semiconductor device provided in the embodiments of the present invention may be applied to a substrate formed with circuit elements (for example, resistors, MOS transistors, and other semiconductor devices) in order to test the reliability of the circuit elements formed in the chip region of the substrate.

In summary, in the semiconductor test structure, the forming method thereof and the test method of the semiconductor device provided by the present invention, two unidirectional conducting structures with opposite conducting directions are connected in parallel between the test terminal and the semiconductor device, so that when a test voltage is applied to the test terminal to test the semiconductor device, only a part of the unidirectional conducting structures in the test terminal and the semiconductor device are conducted, and the other unidirectional conducting structures are cut off, and a test result is obtained. When the test result is abnormal, the reverse voltage of the test voltage can be applied to the test end for testing again, and at the moment, the test end is conducted with only the other one-way conduction structures in the semiconductor device, and another test result can be obtained. In view of the fact that the conducted unidirectional conduction structures are different in the two tests, whether the abnormal position is a semiconductor device or the unidirectional conduction structure can be determined by comparing whether the test results obtained by the two tests are the same or not, failure analysis is only needed to be carried out on the abnormal position, failure analysis is not needed to be carried out on other positions, the situation that machine resources and human resources of the failure analysis are wasted due to blind and comprehensive failure analysis can be avoided, efficiency is improved, and cost is reduced.

In addition, when the abnormal position is determined to be in the one-way conduction structure, failure analysis is not needed, resources can be further saved, cost is reduced, and efficiency is improved.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the system disclosed by the embodiment, the description is relatively simple because the system corresponds to the method disclosed by the embodiment, and the relevant points can be referred to the method part for description.

The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims (10)

1. A semiconductor test structure, comprising:

a substrate on which a semiconductor device is formed; and the number of the first and second groups,

the test terminals are electrically connected with the semiconductor devices, and one semiconductor device is connected with two test terminals;

the two test ends are connected with the semiconductor device through a one-way conduction structure, two one-way conduction structures are connected in parallel between any one of the two test ends and the semiconductor device, and the conduction directions of the two one-way conduction structures are opposite.

2. The semiconductor test structure of claim 1,

the unidirectional conduction structure comprises a first plug, a layer of metal wire and a second plug; the layer of metal wire is electrically connected with the semiconductor device through the first plug and is electrically connected with the test end through the second plug, and a one-way conduction device is formed in the layer of metal wire.

3. The semiconductor test structure of claim 1, wherein the unidirectional via structure comprises a first plug, at least two layers of metal lines, a third plug for electrically connecting metal lines of adjacent layers, and a second plug; the bottom layer metal wire of the at least two layers of metal wires is electrically connected with the semiconductor device through a first plug, the top layer metal wire of the at least two layers of metal wires is electrically connected with the test end through a second plug, and a one-way conduction device is formed in any one layer of metal wire of the at least two layers of metal wires.

4. The semiconductor test structure of claim 2 or 3, wherein the unidirectional conducting device comprises a PN junction.

5. A method for forming a semiconductor test structure, the method comprising:

providing a substrate, wherein a semiconductor device is formed on the substrate;

forming a unidirectional conduction structure and a test end on the substrate;

the testing ends are connected with the semiconductor devices through unidirectional conduction structures, one semiconductor device is connected with two testing ends, two unidirectional conduction structures are connected between any one of the two testing ends and the semiconductor device in parallel, and the conduction directions of the two unidirectional conduction structures are opposite.

6. The method of forming a semiconductor test structure of claim 5, wherein the method of forming a unidirectional conducting structure and a test terminal on the substrate comprises:

forming a first dielectric layer on the substrate, and forming four first plugs in the first dielectric layer, each first plug being electrically connected to the semiconductor device;

forming N layers of metal interconnection structures on the first dielectric layer, wherein N is a positive integer, and each layer of metal interconnection structure comprises four metal wires which are separately arranged; when N is 1, the N layers of metal interconnection structures comprise a layer of metal interconnection structure, each metal wire in the layer of metal interconnection structure is connected to a first plug respectively, and a one-way conduction device is formed in each metal wire in the layer of metal interconnection structure; when N is larger than 1, each metal wire of a bottom layer metal interconnection structure in the N layers of metal interconnection structures is respectively connected to a first plug, each metal wire of each layer of metal interconnection structure in the N layers of metal interconnection structures is connected to one metal wire of an adjacent layer of metal interconnection structure through a third plug, so that a plurality of groups of N layers of metal wires connected in a stacked mode are formed, and a one-way conduction device is formed in any one layer of metal wire in each group of N layers of metal wires connected in the stacked mode; the conducting direction of the one-way conducting devices in at least part of the metal wires in the metal wires with the one-way conducting devices is opposite to the conducting direction of the one-way conducting devices in other metal wires;

forming a second dielectric layer on the N-layer metal interconnection structure, wherein four second plugs are formed in the second dielectric layer; when N is 1, and the N-layer metal interconnection structure comprises a layer of metal interconnection structure, each second plug is connected to one metal wire in the layer of metal interconnection structure, and the first plug, the metal wire and the second plug which are connected with each other form a one-way conduction structure; when N is larger than 1, each second plug is connected to one metal wire in a top-layer metal interconnection structure of the N-layer metal interconnection structure, and the first plugs, the N-layer metal wires and the second plugs which are connected with one another form a one-way conduction structure;

and forming two testing ends on the second medium layer, wherein each testing end is correspondingly connected with two one-way conduction structures, and the conduction directions of the two one-way conduction structures are opposite.

7. The method of forming a semiconductor test structure of claim 6, wherein said unidirectional conducting device comprises a PN junction;

and the method for forming the one-way conduction device in the metal wire comprises the following steps:

defining a first area and a second area which are adjacent in the metal wire;

and respectively injecting N-type ions and P-type ions into the first region and the second region to form a PN junction.

8. A method of testing a semiconductor device, the method comprising:

providing the semiconductor test structure according to any of claims 1-4, wherein a first unidirectional conducting structure and a second unidirectional conducting structure are connected in parallel between one of the test terminals and one of the semiconductor devices in the semiconductor test structure, and the conducting directions of the first unidirectional conducting structure and the second unidirectional conducting structure are opposite;

applying a test voltage to the test end of the semiconductor test structure to enable the first one-way conduction structure between the test end and the semiconductor device to be conducted, and obtaining a first electrical parameter of the semiconductor device;

judging whether the first electrical parameter is within a standard range to test whether the semiconductor test structure is normal or not and obtain a first test result; when the first test result is: stopping executing the test method when the semiconductor test structure is normal; when the first test result is: when the semiconductor test structure is abnormal, applying reverse voltage of the test voltage to the test end to enable a second one-way conduction structure between the test end and the semiconductor device to be conducted, obtaining a second electrical parameter of the semiconductor device, and judging whether the second electrical parameter is in a standard range to test whether the semiconductor test structure is normal again to obtain a second test result;

judging whether the first test result is the same as the second test result, and if so, determining that an abnormal position in the semiconductor test structure is the semiconductor device; and when the abnormal positions are different, determining that the abnormal position in the semiconductor test structure is a first unidirectional conduction structure.

9. The method for testing a semiconductor device according to claim 8, wherein two test terminals, a first test terminal and a second test terminal, are connected to one of the semiconductor devices.

10. The method for testing a semiconductor device according to claim 9, wherein the method for testing comprises:

applying a first potential to the first test end, applying a second potential to the second test end, wherein the first potential is higher than the second potential, so that a first path is formed among the first test end, a first unidirectional conduction structure connected with the first test end, the semiconductor device, a first unidirectional conduction structure connected with the second test end, and a first electrical parameter of the semiconductor device is obtained;

judging whether the first electrical parameter is within a standard range to test whether the semiconductor test structure is normal or not and obtain a first test result; when the first test result is: stopping executing the test method when the semiconductor test structure is normal; when the first test result is: when the semiconductor test structure is abnormal, the second electric potential is applied to the first test end, the first electric potential is applied to the second test end, a second channel is formed among the first test end, a second unidirectional conduction structure connected with the first test end, the semiconductor device, the second unidirectional conduction structure connected with the second test end and the second test end, a second electrical parameter of the semiconductor device is obtained, and whether the second electrical parameter is in the standard range or not is judged to retest whether the semiconductor test structure is normal or not and a second test result is obtained;

judging whether the first test result is the same as the second test result, and if so, determining that an abnormal position in the semiconductor test structure is the semiconductor device; and when the abnormal positions are different, determining that the abnormal position in the semiconductor test structure is a first unidirectional conduction structure.

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