JP2004045967A - Driving circuit of electrooptical device, electrooptical device, electronic equipment, and driving method of electrooptical device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress generation of display unevenness of an in-block dot sequential driving system. <P>SOLUTION: A selector part 14 sequentially selects image data in one horizontal period block by block, and supplies them to a signal switching part 3 through a driver part 15. The signal switching part 3 supplies the inputted image data to corresponding source lines. In an in-block dot sequential driving system like this, each source line receives an image signal for a period obtained by dividing one horizontal period by the number of blocks, and hence the driving system excels in driving capability of pixels. A timing control circuit switches the selection order of image signals and source lines within the blocks at intervals of, for example, one horizontal period by using selection signals S1 to S3. Consequently, write periods by the respective source lines are made uniform in a plurality of horizontal periods to suppress display unevenness. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a driving circuit for an electro-optical device, an electro-optical device, an electronic apparatus, and a method for driving an electro-optical device.
[0002]
[Prior art]
Conventionally, a display device having a matrix configuration such as a liquid crystal display device has been widely used. The quality of display devices, which are electro-optical devices, has also been improved. In particular, as the definition of the display device has been improved, various improvements have been made along with the increase in the definition. A so-called drive circuit for driving each pixel circuit has also been improved.
[0003]
As one of the improvements, there is a technique disclosed in JP-A-61-145597. According to the technique disclosed in the publication, a plurality of source lines are combined into one set, a source line group is divided into a plurality of sets, and a selection signal for sequentially selecting source lines in each set is supplied. , A circuit is configured. The number of connection lines between circuits is reduced by supplying an image signal for each set and selecting a source line corresponding to each set by the selection signal. As a result, the number of connection wires between circuits does not increase even if the number of pixels increases with the increase in definition of the display device.
[0004]
In such a liquid crystal display device, by supplying an image signal from a source line to a pixel electrode turned on by a scanning line, an image signal is written to a pixel electrode forming each pixel. The arrangement of liquid crystal molecules between the pixel electrode and the common electrode is controlled by an image signal written to the pixel electrode, and an image is displayed.
[0005]
[Problems to be solved by the invention]
By the way, in the proposal of Japanese Patent Application Laid-Open No. 61-145597, as described above, an image signal is supplied to each source line by sequentially selecting the source lines in each group. The image signal once supplied to the source line is held by the wiring capacitance of the source line having a sufficiently large value as compared with the liquid crystal capacitance formed by liquid crystal, and during a horizontal period in which the scanning line is turned on, It is written to the pixel electrode.
[0006]
However, since the source lines are sequentially selected within one horizontal period, the period during which the image signal is held within one horizontal period differs for each source line. Such a difference in writing time to the pixel electrode causes display unevenness. In particular, in the proposal of Japanese Patent Application Laid-Open No. 61-145597, there is a problem that display time of vertical stripes appears on a screen because a writing time to a pixel electrode differs for each source line.
[0007]
An object of the present invention is to provide a driving circuit of an electro-optical device, an electro-optical device, an electronic apparatus, and a driving method of an electro-optical device which can reduce display unevenness of a display device.
[0008]
[Means for Solving the Problems]
A driving circuit of an electro-optical device according to the present invention divides a data line for supplying an image signal to pixels arranged in a matrix into a plurality of blocks, and sequentially selects a plurality of data lines in each block in one horizontal period. A plurality of signal switching circuits for sequentially supplying image signals corresponding to respective pixels of one line in a block unit in one horizontal period. A plurality of select circuits, respectively, and the plurality of signal switching circuits and the plurality of select circuits are controlled in conjunction with each other to supply an image signal corresponding to each pixel of the one line to a corresponding data line, Control means for changing the selection order of the data lines in one horizontal period on a time axis.
[0009]
According to such a configuration, the select circuit sequentially selects an image signal corresponding to each pixel of one line in one horizontal period for each block. The image signals from the select circuits for the number of blocks are supplied to the signal switching circuit, and the data lines in each block are sequentially switched within one horizontal period by the signal switching circuit, and the image signals are supplied to the data lines. . In such sequential driving in a block, the control means changes the order of selecting data lines in one horizontal period on the time axis. Thereby, the writing time of each data line to the pixel changes on the time axis, the writing time is made uniform, and display unevenness is suppressed.
[0010]
Further, the control means changes a selection order of the data lines in the one horizontal period on a time axis such that a writing time of an image signal to each pixel is made uniform.
[0011]
According to such a configuration, for example, by changing the selection order of each data line in a block so as to be uniform for all data lines, the writing time of the image signal to each pixel is made uniform. be able to.
[0012]
Further, the control means switches the selection order of the data lines in the one horizontal period every one horizontal period.
[0013]
According to such a configuration, the writing time of the image signal by each data line is changed for each line, so that the brightness is uniformed in the screen and the display unevenness is suppressed.
[0014]
Further, the control means switches the selection order of the data lines in the one horizontal period every frame period.
[0015]
According to such a configuration, the writing time of the image signal by each data line is changed for each frame, so that the brightness is made uniform among a plurality of screens and display unevenness is suppressed.
[0016]
Further, the control means switches the selection order of the data lines in the one horizontal period every one horizontal period and every one frame period.
[0017]
According to such a configuration, the writing time of the image signal by each data line is changed for each line and each frame, so that the brightness is uniformed in the screen and between a plurality of screens, and the display unevenness is suppressed.
[0018]
The control means may change a generation pattern of a select signal for controlling operations of the signal switching circuit and the select circuit on a time axis.
[0019]
According to such a configuration, by changing the generation pattern of the select signal on the time axis, the selection order of the image signal selected by the select circuit and the data line selected by the signal switching circuit in one horizontal period is changed. can do.
[0020]
The image processing apparatus may further include a plurality of drive circuits that supply image signals from the plurality of select circuits to the plurality of signal switching circuits via a plurality of data supply lines corresponding to the respective blocks.
[0021]
According to such a configuration, the number of data supply lines for supplying image signals to the plurality of drive circuits and the signal switching circuits may be prepared by the number of blocks, and the device can be downsized.
[0022]
Further, a latch circuit for simultaneously supplying an image signal corresponding to each pixel for one line to the select circuit is further provided.
[0023]
According to such a configuration, an image signal corresponding to each pixel of one line to be supplied to the select circuit can be obtained at the same time, so that writing can be performed in block units, and the writing time by each source line can be lengthened. As a result, a high-definition image can be obtained.
[0024]
The electro-optical device according to the present invention is configured such that a driving circuit of the electro-optical device, a pixel portion having pixels arranged in a matrix and a data line divided into the plurality of blocks are dot-sequentially arranged in a block. And a display unit including the plurality of signal switching circuits for supplying an image signal.
[0025]
According to such a configuration, the driving circuit of the electro-optical device can make the writing time to each pixel by the data line uniform, so that it is possible to prevent the occurrence of display unevenness in the image display on the display unit. it can.
[0026]
An electronic apparatus according to the present invention includes the above-described electro-optical device.
[0027]
According to such a configuration, display unevenness does not occur in the electro-optical device, so that a device capable of displaying a high-definition image can be obtained.
[0028]
In the driving method of the electro-optical device according to the present invention, a data line for supplying an image signal to pixels arranged in a matrix is divided into a plurality of blocks, and a plurality of data lines in each block are sequentially selected in one horizontal period. In the driving method for supplying an image signal, the selection order of the data lines in the one horizontal period is changed on a time axis.
[0029]
According to such a configuration, one line is divided into a plurality of blocks, and an image signal is sequentially selected for each of the divided blocks. The selected image signal is supplied to a corresponding data line. The image signal and the corresponding data line are sequentially selected in one horizontal period for each block. Then, the selection order of the data lines in one horizontal period is changed on the time axis. Thereby, the writing time to the pixel by each data line is changed on the time axis to be uniform, and display unevenness is suppressed.
[0030]
Further, the selection order of the data lines in the one horizontal period is switched every one horizontal period.
[0031]
According to such a configuration, the writing time of the image signal by each data line is changed for each line, so that the brightness is uniformed in the screen and the display unevenness is suppressed.
[0032]
Further, the selection order of the data lines in the one horizontal period is switched every frame period.
[0033]
According to such a configuration, the writing time of the image signal by each data line is changed for each frame, so that the brightness is made uniform among a plurality of screens and display unevenness is suppressed.
[0034]
Further, the selection order of the data lines in the one horizontal period is switched every one horizontal period and every one frame period.
[0035]
According to such a configuration, the writing time of the image signal by each data line is changed for each line, and the writing time of the image signal by each data line is changed for each frame. The brightness is made uniform between the screens, and the display unevenness is effectively suppressed.
[0036]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0037]
First, the configuration of the electro-optical device according to the present embodiment will be described with reference to FIG. In this embodiment mode, the present invention is applied to a liquid crystal display device using a thin film transistor (hereinafter, referred to as TFT). FIG. 2 is a block diagram showing a specific circuit configuration of the TFT element substrate 1 and the driver IC 5 in FIG.
[0038]
In the present embodiment, all the source lines (data lines) are divided into k (three in FIG. 2) k blocks, and one data supply line is used for each of u blocks from the drive circuit. The present invention is applied to a liquid crystal display device that supplies an image signal of (i), a process of switching an image signal of m pixels in one line to k drive circuits, and an output of each drive circuit to a source line of m pixels. The image signal can be supplied to all the source lines by the signal switching process. That is, in the present embodiment, all source lines are divided into blocks, and point-sequential driving (hereinafter referred to as point-in-block sequential driving) is performed in each block. Further, in the present embodiment, in the signal switching circuit processing, the selection order of the source line to which the image signal is distributed in one horizontal period is switched on the time axis, for example, line by line, thereby preventing display unevenness. I am trying to do it.
[0039]
Reference numeral 1 denotes a TFT element substrate, which includes a pixel section 2 serving as a video display area, a signal switching section (DMPX) 3, and a Y driver 4. The pixel unit 2 is a matrix display unit including pixels of n rows and m columns (n and m are integers), and forms m m ■ n pixel matrices in the X direction and n directions in the matrix wiring. . The pixel unit 2, the signal switching unit 3, and the Y driver 4 are provided on the TFT element substrate 1. Reference numeral 5 denotes a driver IC as an external drive circuit. Reference numeral 6 denotes a timing control circuit for controlling the TFT element substrate 1 and the driver IC 2. Reference numeral 7 denotes a data supply line group which is a data line provided in the X direction of the pixel unit 2. The pixel section 2 is driven by a signal switching section 3, a Y driver 4, a driver IC 5, and a timing control circuit 6, which are driving circuits provided in the periphery. Note that the Y driver 4 may be constituted by a driver IC as an external drive circuit.
[0040]
The image data DATA, the latch timing signal LP, the shift register start signal ST, the data clock signal CLX, and the select signals S1, S2, and S3, which are selection signals, are supplied from the timing control circuit 6 to the driver IC5. The start signal DY of the Y driver and the shift signal CLY of the line are supplied from the timing control circuit 6 to the TFT element substrate 1.
[0041]
In FIG. 1, the shift register unit 11, the first and second latch circuits 12, 13, the selector unit 14, and the driver 15 shown in FIG. 2, which will be described later, are included in the driver IC 5. A part may be included in the TFT element substrate 1.
[0042]
FIG. 2 is a diagram illustrating a circuit configuration of the TFT element substrate 1 and the driver IC 5. Reference numeral 11 denotes a shift register unit, 12 denotes a first latch circuit, 13 denotes a second latch circuit, 14 denotes a selector unit, and 15 denotes a driver unit. Are included in the driver IC 5.
[0043]
The clock signal CLX and the start signal ST are input to the shift register unit 11. The start signal ST sequentially shifts in the shift register unit 11 according to the clock signal CLX. An output signal from each unit register of the shift register unit 11 is input to each unit latch circuit of the first latch circuit 12. On the other hand, image data DATA, which is an image signal, is simultaneously supplied to all unit latch circuits. When the output signal from the unit register is input, the image data DATA is sequentially stored in each unit latch circuit of the first latch circuit 12. Thus, the first latch circuit 12 stores m pieces of image data for one line, that is, one horizontal scanning line. The image data DATA is, for example, a 6-bit digital signal.
[0044]
The second latch circuit 13 is a circuit that directly latches the image data DATA of the first latch circuit 12 according to the latch timing signal LP. Therefore, the second latch circuit 13 simultaneously latches m data, which is data for one line. Note that each of the latch circuits 13 (1), 13 (2),... 13 (m) of the second latch circuit 13 latches image signals corresponding to source lines X1, X2,. Has become.
[0045]
The selector section 14 includes a plurality of select circuits 14 (1), 14 (2),..., 14 (k). A plurality of sets (blocks) are formed by dividing the image data DATA for one line from the head or the end of the data for one line into data corresponding to three consecutive pixels. The three sets of data are input to the corresponding select circuits. Specifically, 1, 2, and 3 of the image data DATA are input to the select circuit 14 (1), and 4, 5, and 6 of the image data DATA are input to the select circuit 14 (2). The circuit 14 (k) receives m-2, m-1, and m of the image data DATA. The selector unit 14 is supplied with select signals S1, S2, and S3, and each select circuit converts predetermined one image data from three input image data in accordance with the select signals S1, S2, and S3. The selected signal is supplied to the corresponding drive circuit of the driver unit 15 as an output signal.
[0046]
The driver unit 15 includes a plurality of drive circuits 15 (1), 15 (2),..., 15 (k). For example, when the select signal S1 is supplied, the image data DATA1 is output from the select circuit 14 (1) to the drive circuit 15 (1), and the image data DATA4 is output from the select circuit 14 (2). 15 (2), and the select circuit 14 (k) outputs the image data DATAm-2 to the drive circuit 15 (k). Each drive circuit includes a digital-to-analog converter, an amplifier circuit, and the like.
[0047]
The image signal from each drive circuit, which has been converted into an analog signal, is supplied to a corresponding signal switching circuit of the signal switching unit 3 via the data supply line group 7. The signal switching unit 3 includes a plurality of signal switching circuits 3 (1), 3 (2),..., 3 (k). Each signal switching circuit has three switch circuits SW1, SW2, and SW3. The image signal supplied from each drive circuit is supplied to one end of three switch circuits SW1, SW2, and SW3 of the corresponding signal switching circuit. The other end of each switch circuit, which is an output, is connected to a corresponding source line (data line) X1, X2,..., Xm of the data line group in the X direction of the pixel unit 2. The signal switching unit 3 is supplied with select signals S1, S2, S3 for turning on / off each switch circuit. Each of the switch circuits SW1, SW2, and SW3 of the signal switching unit 3 is selectively turned on sequentially according to the select signals S1, S2, and S3, and supplies an image signal from a corresponding drive circuit to a corresponding source line.
[0048]
For example, when the select signal S1 for turning on the switch circuit SW1 is supplied, the switch circuit SW1 of the signal switching circuit 3 (1) is turned on, and the image signal corresponding to the image data DATA1 is sent to the source line X1. Is output. Similarly, the switch circuit SW1 of the signal switching circuit 3 (2) is also turned on, and an image signal corresponding to the image data DATA4 is output to the source line X4. Similarly, the switch circuit SW1 of the signal switching circuit 3 (k) is also turned on, and an image signal corresponding to the image data DATAm-2 is output to the source line Xm-2.
[0049]
Further, for example, when the select signal S2 for turning on the switch circuit SW2 is supplied, the switch circuit SW2 of the signal switching circuit 3 (1) is turned on, and the image signal corresponding to the image data DATA2 is transmitted to the source line. Output to X2. Similarly, the switch circuit SW2 of the signal switching circuit 3 (2) is also turned on, and an image signal corresponding to the image data DATA5 is output to the source line X5. Similarly, the switch circuit SW2 of the signal switching circuit 3 (k) is also turned on, and an image signal corresponding to the image data DATAm-1 is output to the source line Xm-1.
[0050]
Further, when the select signal S3 for turning on the switch circuit SW3 is supplied, the switch circuit SW3 of the signal switching circuit 3 (1) is turned on, and the image signal corresponding to the image data DATA3 is sent to the source line X3. Is output. Similarly, the switch circuit SW3 of the signal switching circuit 3 (2) is also turned on, and the image signal corresponding to the image data DATA6 is output to the source line X6. Similarly, the switch circuit SW3 of the signal switching circuit 3 (k) is also turned on, and an image signal corresponding to the image data DATAm is output to the source line Xm.
[0051]
As described above, each signal switching circuit switches the predetermined switch circuit in accordance with the select signal so as to be turned on, thereby sequentially selecting the image signal from each drive circuit and outputting the image signal to the corresponding source line. . Each of the switch circuits SW1, SW2, and SW3 is sequentially turned on within one horizontal period, and image signals are supplied to all source lines within one horizontal period in all blocks. Thus, in FIG. 2, dot-sequential driving is performed for each block of three source lines.
[0052]
In the present embodiment, the timing control circuit 6 switches the order in which the switch circuits SW1, SW2, and SW3 are turned on by the select signals S1 to S3 on the time axis, for example, line by line.
[0053]
For example, in a predetermined horizontal period, the switch circuits SW1, SW2, and SW3 are sequentially turned on in this order by the select signals S1 to S3, and in one horizontal period, an image signal is first supplied to the source lines X1, X4, X7,. , And then an image signal is supplied to the source lines X2, X5, X8,..., And finally, an image signal is supplied to the source lines X3, X6, X9,. In this case, in the next horizontal period, the timing control circuit 6 sequentially turns on the switch circuits SW1, SW2, and SW3 in the order of, for example, the switch circuits SW2, SW1, and SW3 in response to the select signals S1 to S3, and sets one horizontal period , An image signal is supplied to the source lines X2, X5, X8,..., An image signal is supplied to the source lines X1, X4, X7,. It supplies the signal.
[0054]
In FIG. 2, reference numeral 16 denotes a TFT corresponding to each pixel. Reference numeral 17 denotes a transparent electrode (pixel electrode) electrically connected to a drain of the TFT 16 and a transparent electrode (a counter electrode) on a light-transmitting substrate. ) Shows the liquid crystal injected between them. The Y driver 4 is connected to the pixel unit 2 by n gate lines (scan lines) Y1, Y2,..., Yn. Each gate line is connected to the gates of all the TFTs 16 in each row. When a gate signal is supplied to the gate line, it is possible to write one line of image data DATA of the corresponding row to the pixel portion 2.
[0055]
Each select circuit of the selector section 14 operates in conjunction with each demultiplex circuit based on the select signals S1 to S3 to supply the output of the latch circuit corresponding to each pixel to the corresponding source line. It has become.
[0056]
Next, the state of signals in the above-described circuit configuration will be described with reference to FIG. FIG. 3 is a timing chart of the circuit configuration of FIG.
[0057]
In FIG. 3, ST is a pulse of a start signal indicating the start of operation of the shift register 11. CLX is a pulse of the data clock signal. DATA is a signal of image data. LP is a pulse of a latch timing signal for transferring data stored in the first latch circuit 12 to the second latch circuit 13. S1, S2, and S3 are pulses of the select signal. YL-1 and YL are gate signals of the L-1 and L-th rows generated by the Y driver 4 based on the start signal DY and the shift signal CLY, respectively. Here, L is an integer.
[0058]
Image data DATA1, 2,..., M corresponding to each pixel of the pixel unit 2 is supplied to the latch circuit 12 at a transfer rate corresponding to the data clock CLX. The start pulse ST sequentially shifts the shift register unit 11 according to the data clock CLX, and supplies a latch pulse to each unit latch of the latch circuit 12. Thus, each unit latch sequentially latches the image data DATA1, 2,..., M corresponding to each pixel in the horizontal direction of the pixel unit 2.
[0059]
The one line of image data DATA1, 2,..., M held in the latch circuit 12 is latched and output by the latch circuit 13 at the timing of the latch timing signal LP. One line of image data output from the latch circuit 13 is written to each pixel electrode of a gate line (scanning line) turned on by a gate signal within one horizontal period.
[0060]
Now, it is assumed that a period during which the (L−1) th gate line is selected from the n rows, that is, the (L−1) th horizontal period in FIG. In this case, a gate signal YL-1 having a signal waveform as shown in FIG. 3 is output to the corresponding gate line YL-1. Since the gate signal YL-1 becomes high level (hereinafter referred to as HIGH), the TFT 16 in the YL-1 row is turned on. In this case, the latch circuit 13 outputs one line of image data to be supplied to each pixel electrode in the (L−1) th row.
[0061]
The image data for one line from the latch circuit 13 is divided into k blocks of three adjacent pixels, and the image data of one pixel in each block is converted into the select circuits 14 (1), 14 (2), .. selected by 14 (k). This selection is made based on the select signals S1, S2, S3. As shown in FIG. 3, each of the select signals S1, S2, and S3 is a signal that becomes HIGH only for about 1/3 of one horizontal period. The select circuits 14 (1), 14 (2),..., 14 (k) select the image data of one pixel of each set in accordance with the HIGH of the select signals S1, S2, S3.
[0062]
That is, the select circuits 14 (1), 14 (2),..., 14 (k) output image data DATA1, 4, 7 of the pixels (1), (4), (7) according to the HIGH of the select signal S1. ,... Are selected and output, and the image data DATA2, 5, 8,... Of the pixels (2), (5), (8) are selected and output according to the HIGH of the select signal S2, and the HIGH of the select signal S3. , Select and output the image data DATA3, 6, 9,... Of the pixels (3), (6), (9).
[0063]
The image data from the select circuits 14 (1), 14 (2),..., 14 (k) are converted into analog signals by the drive circuits 15 (1), 15 (2),. The signal is amplified and supplied to the signal switching circuits 3 (1), 3 (2),..., 3 (k). The signal switching circuits 3 (1), 3 (2),..., 3 (k) branch the input image data to source lines X1, X2,.
[0064]
The signal switching circuits 3 (1), 3 (2),..., 3 (k) are also controlled by the select signals S1, S2, S3, and output one input to one of three outputs. That is, the signal switching circuits 3 (1), 3 (2),..., 3 (k) output the image data to the first of the three outputs according to the HIGH of the select signal S1, and the select signal S2. , The image data is output to the second output of the three outputs, and the HIGH of the select signal S3 outputs the image data to the third output of the three outputs.
[0065]
That is, while the select signal S1 is HIGH, the image data selected by the select circuits 14 (1), 14 (2),..., 14 (k) is supplied to the source lines X1, X4, X7,. When the select signal S2 is HIGH, the image data selected by the select circuits 14 (1), 14 (2),..., 14 (k) is supplied to the source lines X2, X5, X8,. When the select signal S3 is HIGH, the image data selected by the select circuits 14 (1), 14 (2),..., 14 (k) is supplied to the source lines X3, X6, X9,. Is done.
[0066]
Thus, in the first approximately one-third of the (L-1) -th horizontal period of FIG. 3, the image data DATA1, 4, 7,... , .... In the (L-1) -th horizontal period, the gate signal YL-1 is HIGH, and the first, fourth, seventh,... Th TFTs 16 of the gate line L-1 have source lines X1, X4, X7. ,... Are supplied through the pixel electrodes,..., And writing to the pixel electrodes is performed until the end of the (L-1) th horizontal period.
[0067]
In the next approximately 1/3 of the (L-1) -th horizontal period, the second, fifth, eighth,... TFTs 16 of the gate line L-1 are connected to the source line X2 by the HIGH of the select signal S2. , X5, X8,... Are supplied with image data DATA2, 5, 8,..., And thereafter, writing to the pixel electrodes is performed until the end of the (L-1) th horizontal period. Further, in the last approximately 1/3 of the (L-1) -th horizontal period, the third, sixth, ninth,... TFTs 16 of the gate line L-1 are connected to the source by the HIGH of the select signal S3. Are supplied via lines X3, X6, X9,..., And thereafter, writing to the pixel electrodes is performed until the end of the (L-1) -th horizontal period.
[0068]
As described above, the image data is supplied to each TFT 16 of the gate line L-1 until the gate signal YL-1 becomes low level (hereinafter, referred to as LOW) after the timing when the image data is input via the source line. Is supplied, and writing to the pixel electrode is performed. Therefore, the writing time to the pixel electrode via the source lines X1, X4, X7,... Is about 1H (horizontal) period, and the writing time to the pixel electrode via the source lines X2, X5, X8,. (2/3) H period, and the writing time to the pixel electrode via the source lines X3, X6, X9,... Is approximately (1/3) H period.
[0069]
Thereafter, by the same operation, the image data selected based on the select signals S1, S2, S3 is supplied to the corresponding source line, and is written to the pixel electrode via the TFT 16 which is turned on.
[0070]
In the present embodiment, in the next L-th horizontal period, the order of the source lines for writing image data is set to a different order from the (L-1) -th horizontal period. That is, as shown in FIG. 3, in the L-th horizontal period in which the gate signal YL becomes HIGH, the select signal S3 becomes HIGH during the first approximately 1/3 of one horizontal period, and the next approximately 1/3 of the period. The select signal S1 becomes HIGH during the period, and the select signal S2 becomes HIGH during the last approximately 1/3.
[0071]
Therefore, writing to the pixel electrodes via the source lines X3, X6, X9,... Is performed for about 1H from the beginning of the L-th horizontal period, and writing to the pixel electrodes via the source lines X1, X4, X7,. Is performed for about (2/3) H period from the middle of the L-th horizontal period, and writing to the pixel electrode via the source lines X2, X5, X8,. 3) H period is performed.
[0072]
Hereinafter, the generation pattern of the select signal in which the select signal becomes HIGH in the order of S1, S2, and S3 in one horizontal period is referred to as a first pattern. A generation pattern of a select signal in which the select signal becomes HIGH in the order of S2, S3, and S1 in one horizontal period is referred to as a second pattern, and a select signal in which the select signal becomes HIGH in the order of S3, S1, and S2 in one horizontal period. The signal generation pattern is called a third pattern.
[0073]
In the (L + 1) -th horizontal period, the select signal S2 becomes HIGH during the first approximately 1/3 of the one horizontal period, the select signal S3 becomes HIGH during the next approximately 1/3, and the last approximately 1 / In the period of 3, the select signal S1 becomes HIGH (that is, the second pattern).
[0074]
In this case, writing to the pixel electrodes via the source lines X2, X5, X8,... Is performed for about 1H from the beginning of the (L + 1) th horizontal period, and via the source lines X3, X6, X9,. The writing to the pixel electrode is performed for about (2/3) H period from the middle of the (L + 1) -th horizontal period, and the writing to the pixel electrode via the source lines X1, X4, X7,. The last (約) H period of the horizontal period is performed. Thereafter, by the same operation, matrix display of n rows and m columns (n and m are integers) on the display device is performed.
[0075]
After all, in the three horizontal periods (L-1) to (L + 1) horizontal periods, writing to the pixel electrodes via the source lines X1, X4, X7,... Is performed for a total of 2H periods, and the source lines X2, X5 , X8,... Are written for a total of 2H periods, and writing to the pixel electrodes via source lines X3, X6, X9,.
[0076]
Thereafter, the select signals S1, S2, S3 repeat the first to third patterns in a cycle of three horizontal periods. That is, when viewed in a predetermined three consecutive horizontal periods, that is, in three consecutive lines, the writing time to each pixel electrode is equal in any of the source lines. As a result, luminance unevenness occurring in each line is averaged for every three lines, and an image without luminance unevenness as a whole can be displayed.
[0077]
As described above, in the present embodiment, the timing of supplying the image data to each source line in the block is switched for each line at the time of sequential driving in the block, and writing of the pixel electrode by each source line is performed in a plurality of lines. The time is made uniform. In this manner, a change in luminance in the screen due to the writing time is averaged over a plurality of lines by dispersing pixels having the same luminance, and display unevenness is hardly seen.
[0078]
In the above embodiment, the pixel timing is changed by changing all the timings of the select signals S1, S2, and S3 so that the generation pattern of the select signals S1, S2, and S3 is restored in three horizontal periods. The writing time for the electrodes was made uniform over three horizontal periods. However, it is clear that the time period for equalizing the writing time need not be three horizontal periods. Further, the generation pattern of the select signal is not limited to FIG. 3, and various modifications are possible.
[0079]
The same effect can be obtained by changing the timing of any one or two select signals instead of changing all the timings of the select signals S1, S2, S3. For example, in the example of FIG. 3, the generation pattern of the select signal S2 may not be changed, and the generation patterns of the select signals S1 and S3 may be switched over in one horizontal period cycle. In this case, the writing time of all pixels can be made uniform in two horizontal periods.
[0080]
That is, as long as the generation pattern of the select signals S1, S2, and S3 is changed on the time axis, the writing time to the pixels can be made more or less uniform.
[0081]
When the HIGH period of the select signal can be set to a time shorter than １ ／ of one horizontal period, as in the case where the drive capability of the drive circuit is high, the select signals S1, S2, Even if only one of the generation timings of S3 is changed, some effects can be obtained.
[0082]
FIG. 4 is a flowchart showing the second embodiment of the present invention. LP in FIG. 4 indicates a latch timing signal, and S1, S2, and S3 indicate select signals.
[0083]
This embodiment is different from the first embodiment only in the generation pattern of the select signals S1, S2, S3, and the hardware configuration for realizing this embodiment is the same as that of FIGS. The signals other than the select signal are the same as those in FIG.
[0084]
In the first embodiment, the select signals S1, S2, and S3 are switched every line (one horizontal period) and returned to the original pattern in three horizontal periods. On the other hand, in the present embodiment, the select signal is switched every frame period, and returns to the original pattern in three frame periods.
[0085]
That is, as shown in FIG. 4, in each horizontal period within the predetermined (F-1) -th frame period, the select signals S1, S2, and S3 become HIGH (first pattern) in this order, and the next (first pattern). In each horizontal period in the F frame period, the select signals S3, S1, and S2 become HIGH in the order of the third pattern (third pattern), and in each horizontal period in the next (F + 1) th frame period, the select signal S2, It becomes HIGH in the order of S3 and S1 (second pattern).
[0086]
Thus, during the first approximately 1/3 of each horizontal period of the (F-1) -th frame period in FIG. 4, the 1, 4, 7,... Are supplied to the respective TFTs 16 via the source lines X1, X4, X7,..., And the next approximately 1/3 of each horizontal period in the (F-1) -th frame period is supplied. In the period, the HIGH signal of the select signal S2 causes the second, fifth, eighth,... TFTs 16 of the gate line L-1 to output image data DATA2, 5, 8,. Are supplied, and during the last approximately 1/3 of each horizontal period of the (F-1) th frame period, the third, sixth, ninth,. Source lines X3, X6 X9, image data DATA3,6,9 through ..., ... is supplied, the writing to the pixel electrode is performed.
[0087]
Then, in the next F-th frame period, in each horizontal period, first, during the first １ ／ period, the image data is transmitted via the source lines X3, X6, X9,. Are supplied through the source lines X1, X4, X7,... During the next approximately 1/3 period by the HIGH of the select signal S1. Are supplied through the source lines X2, X5, X8,... In response to the HIGH of the select signal S2 in the last period of about 1/3.
[0088]
Further, in the next (F + 1) -th frame period, in each horizontal period, first, in the first approximately 1/3 period, the select signal S2 is HIGH through the source lines X2, X5, X8,. The image data DATA2, 5, 8,... Are supplied, and during the next approximately 1/3, the image data DATA3, 6, 9, via the source lines X3, X6, X9,. Are supplied through the source lines X1, X4, X7,... Through the source signal X1, X4, X7,.
[0089]
In the embodiment configured as described above, in the (F-1) -th frame, the writing time is longer in the order of the first, second, and third source lines of each block. In the (F + 1) frame, the writing time is longer in the order of the second, third, and first source lines of each block in the third, first, and second source lines. Therefore, the writing time of the pixel electrode of each pixel is made uniform in three frames.
[0090]
As described above, also in the present embodiment, the writing time of the pixel electrode is made uniform on the time axis, and display unevenness is suppressed.
[0091]
Also in the present embodiment, various modifications can be made as the generation pattern of the select signal. For example, the generation pattern may be changed every two frame periods, and the cycle of returning to the original state is not limited to the three frame cycle.
[0092]
Further, in the first embodiment, the generation pattern of the select signal is changed every horizontal period, and in the second embodiment, the generation pattern of the select signal is changed every frame period. Obviously, they may be combined.
[0093]
FIG. 5 is an explanatory diagram showing an example of a select signal generation pattern adopted in this case.
[0094]
In the example of FIG. 5, in the (F-1) th frame period, the select signal is set to HIGH (first pattern) in the order of S1, S2, and S3 in the (L-1) th horizontal period, and the next Lth horizontal period. In the period, the select signal is set to HIGH in the order of S2, S3, and S1 (second pattern), and in the next (L + 1) th horizontal period, the select signal is set to HIGH in the order of S3, S1, and S2 (third pattern). Then, in the next F-th frame, the second pattern is used in the (L-1) -th horizontal period, the third pattern is used in the L-th horizontal period, and the first pattern is used in the (L + 1) -th horizontal period. Is adopted. In the next (F + 1) -th frame, the third pattern is employed in the (L-1) -th horizontal period, the first pattern is employed in the L-th horizontal period, and the second pattern is employed in the (L + 1) -th horizontal period. Adopt the pattern of
[0095]
By changing the generation pattern of the select signal every one horizontal period, the writing time between the vertically adjacent pixels changes. By making the generation pattern of the select signal complete in three lines as shown in FIG. In this case, the writing time of each pixel becomes uniform in any of the source lines, and the luminance unevenness occurring in each line is averaged for every three lines. However, with this control alone, the writing time of the pixel at the same pixel position in each frame is constant, and a writing time difference occurs between the pixels.
[0096]
Therefore, in the example of FIG. 5, the generation pattern of the select signal is further changed every frame period. As a result, the writing time of each pixel at the same position in each frame changes. By causing the select signal generation pattern to make one cycle in three frames, the writing time for the pixel at the same pixel position becomes uniform in three frames.
[0097]
As described above, in the example of FIG. 5, the writing time for each pixel is equalized every three lines in the screen, and is equalized every three frames in the screen. As a result, the change in luminance due to the writing time of each pixel electrode is averaged in the screen and between the screens, so that display unevenness can be made more difficult to see.
[0098]
Further, in each of the above-described embodiments, the example in which the order of selecting the source lines is changed on the time axis in the point sequential driving in the block has been described. Is also possible. That is, in the above embodiments, the source line selection order is the same in all blocks, but the source line selection order is changed for each block and the source line selection order is changed on the time axis. To do it. Also in this case, the writing time of each pixel electrode can be made uniform, and the occurrence of display unevenness can be reduced.
[0099]
Further, in each of the above embodiments, an example has been described in which three source lines constitute one block, and three source lines in each block are sequentially selected in one horizontal period. Can be set as appropriate. For example, it is apparent that the present invention is applicable to a case where one block is constituted by six source lines and six source lines of each block are sequentially selected and driven in one horizontal period.
[0100]
In each of the above-described embodiments, the generation pattern of the select signal for controlling the signal switching process from a plurality of signals to one signal and the signal switching process from one signal to a plurality of signals in the point-in-block sequential driving. Is changed to change the driving order of the source lines in each block, thereby making the writing time of each pixel electrode uniform. However, within a predetermined time range, the source The same effect can be obtained by changing the driving order of the lines, not only by changing the generation pattern of the select signal, but also by using another method.
[0101]
The above description is an example of a liquid crystal display device. However, the present invention can be applied to a matrix-structured organic EL (electroluminescence) display device, an electrophoretic display device, and the like.
[0102]
FIG. 6 is a schematic configuration diagram showing a third embodiment of the present invention. This embodiment shows a projection display device which is an example of an electronic apparatus using the electro-optical device according to the first or second embodiment.
[0103]
6, a light source 210 includes a lamp 211 such as a metal halide and a reflector 212 that reflects light from the lamp 211. A dichroic mirror 213 and a reflection mirror 217 for reflecting blue light and green light are provided on an optical path of light emitted from the light source 210. The dichroic mirror 213 transmits red light of the light flux from the light source 210 and reflects blue light and green light. The reflection mirror 217 reflects the red light transmitted through the dichroic mirror 213.
[0104]
On the optical path of the reflected light of the dichroic mirror 213, a dichroic mirror 214 and a reflecting mirror 215 for reflecting green light are arranged, and the dichroic mirror 214 reflects green light of incident light and transmits blue light. The reflection mirror 215 reflects the light transmitted through the dichroic mirror 214. A reflection mirror 216 is provided on the optical path of the light reflected by the reflection mirror 215, and the reflection mirror 216 further reflects the light reflected by the reflection mirror 215 (blue light).
[0105]
Liquid crystal devices 222, 223, which are light modulators and are electro-optical devices similar to those of the first and second embodiments, are provided on the output optical paths of the reflection mirror 217, the dichroic mirror 214, and the reflection mirror 216, respectively. 224 are provided. Red light, green light, or blue light enters the liquid crystal devices 222 to 224, respectively. The liquid crystal devices 222 to 224 light-modulate the incident light in accordance with the R, G, and B image signals, respectively. The G and B image lights are emitted to the dichroic prism 225.
[0106]
The dichroic prism 225 is formed by laminating four right-angle prisms, and a dielectric multilayer film that reflects red light and a dielectric multilayer film that reflects blue light are formed in a cross shape on its inner surface. The dichroic prism 225 combines the three R, G, and B light components with these dielectric multilayers, and emits image light of a color image.
[0107]
A projection lens 226 that constitutes a projection optical system is provided on the exit optical path of the dichroic prism 225, and the projection lens 226 projects the combined image light onto a screen 227. Thus, an enlarged image is displayed on the screen 227.
[0108]
In the embodiment configured as described above, display unevenness of the liquid crystal devices 222, 223, and 224 is suppressed. Accordingly, the image projected on the screen 227 by the liquid crystal devices 222, 223, and 224 is a high-quality image free from display unevenness, flickering, and the like.
[0109]
FIG. 7 shows an example in which the electro-optical device is applied to a mobile personal computer and a mobile phone. FIG. 7A is a perspective view illustrating a configuration of a personal computer. In the figure, a computer 1200 includes a main body 1204 having a keyboard 1202 and a display unit 1206. This display unit 1206 is configured to include the electro-optical device 100 having the same configuration as in each of the above embodiments.
[0110]
FIG. 7B is a perspective view showing an example in which the electro-optical device is applied to a mobile phone. In the figure, a mobile phone 1300 includes, in addition to a plurality of operation buttons 1302, an earpiece 1304, a mouthpiece 1306, and a display unit including the electro-optical device 100 having the same configuration as in the above embodiments. is there.
[0111]
In addition to the electronic devices described with reference to FIGS. 6 and 7, a liquid crystal television, a viewfinder type, a monitor direct-view type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator, a word processor , A workstation, a videophone, a POS terminal, a device equipped with a touch panel, and the like.
[0112]
The present invention is not limited to the above-described embodiment, and various changes and modifications can be made without departing from the spirit of the present invention.
[0113]
【The invention's effect】
As described above, according to the present invention, there is an effect that display unevenness of a display device can be reduced.
[Brief description of the drawings]
FIG. 1 is an exemplary block diagram showing a configuration of a display device which is an electronic apparatus according to a first embodiment of the present invention.
FIG. 2 is a block diagram showing a specific circuit configuration of a TFT element substrate 1 and a driver IC 5 in FIG.
FIG. 3 is a timing chart of the circuit configuration of FIG. 2;
FIG. 4 is a flowchart showing a second embodiment of the present invention.
FIG. 5 is an explanatory view showing a modification.
FIG. 6 is a schematic configuration diagram showing a third embodiment of the present invention.
FIG. 7 is an explanatory view showing a modification of the third embodiment of the present invention.
[Explanation of symbols]
1 ... TFT element substrate
2 ... Pixel part
3 ... Signal switching unit
4 ... Y driver section
5 ... Driver IC
6 ... Timing control circuit
7 ... data supply line group
11 shift register section
12 first latch circuit
13... Second latch circuit
14 ... Selector section
15 ... Driver section
16 ... TFT
17 ・ ・ ・ Liquid crystal

Claims (14)

A data line for supplying an image signal to pixels arranged in a matrix is divided into a plurality of blocks, and a plurality of data lines in each block are sequentially selected in one horizontal period to provide a signal switching circuit for supplying an image signal. A plurality of select circuits for supplying an image signal, sequentially selecting an image signal corresponding to each pixel of one line in one horizontal period in a block unit, and applying the image signals to the plurality of signal switching circuits, respectively;
The plurality of signal switching circuits and the plurality of select circuits are controlled in conjunction with each other to supply an image signal corresponding to each pixel of the one line to a corresponding data line, and select the data line in the one horizontal period. And a control means for changing the order on a time axis. 2. The control unit according to claim 1, wherein the control unit changes a selection order of the data lines in the one horizontal period on a time axis such that a writing time of an image signal to each pixel is made uniform. Drive circuit for electro-optical device. 2. The driving circuit according to claim 1, wherein the control unit switches a selection order of the data lines in the one horizontal period every one horizontal period. 2. The driving circuit according to claim 1, wherein the control unit switches the selection order of the data lines in the one horizontal period every frame period. 2. The driving circuit according to claim 1, wherein the control unit switches the selection order of the data lines in the one horizontal period every one horizontal period and every one frame period. 2. The driving circuit according to claim 1, wherein the control unit changes a generation pattern of a select signal for controlling operations of the signal switching circuit and the select circuit on a time axis. The image processing apparatus further comprises a plurality of drive circuits which digitally / analog-convert image signals from the plurality of select circuits and apply the digital / analog signals to the plurality of signal switching circuits via a plurality of data supply lines corresponding to the respective blocks. The driving circuit for an electro-optical device according to claim 1. 2. The driving circuit for an electro-optical device according to claim 1, further comprising a latch circuit for simultaneously supplying an image signal corresponding to each pixel of one line to the select circuit. A drive circuit for the electro-optical device according to claim 1,
A display unit comprising: a pixel unit having pixels arranged in a matrix; and the plurality of signal switching circuits that supply image signals in a point-sequential manner within a block through the data lines divided into the plurality of blocks. ,
An electro-optical device comprising: An electronic apparatus comprising the electro-optical device according to claim 9. A driving method for dividing a data line for supplying an image signal to pixels arranged in a matrix into a plurality of blocks and sequentially selecting a plurality of data lines in each block in one horizontal period to supply an image signal, A method for driving an electro-optical device, wherein a selection order of the data lines in a horizontal period is changed on a time axis. 12. The method according to claim 11, wherein the selection order of the data lines in the one horizontal period is switched every one horizontal period. 12. The method according to claim 11, wherein a selection order of the data lines in the one horizontal period is switched every frame period. 12. The driving method for an electro-optical device according to claim 11, wherein the order of selecting the data lines in the one horizontal period is switched every one horizontal period and every one frame period.

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