JP5027976B2 - Electro-optical device, electronic apparatus, and driving method of electro-optical device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a driving circuit for an electro-optical device, an electro-optical device, an electronic apparatus, and a driving method for the electro-optical device.
[0002]
[Prior art]
Conventionally, display devices having a matrix configuration such as a liquid crystal display device have been widely used. The quality of display devices that are electro-optical devices is also increasing. In particular, display devices have been improved in definition, and various improvements have been made with the increase in definition. However, so-called drive circuits for driving each pixel circuit have also been improved.
[0003]
As one of the improvements, there is a technique disclosed in Japanese Patent Application Laid-Open No. 61-145597. According to the technique disclosed in the publication, a plurality of source lines are combined into one group, a group of source lines is divided into a plurality of groups, and a selection signal for sequentially selecting the source lines in each group is supplied. The circuit is configured. Then, the number of connection wirings between circuits is reduced by providing a configuration in which image signals are supplied in units of units and the source lines corresponding to the respective groups are selected by the selection signals. As a result, the number of connection wirings between circuits does not increase even if the number of pixels increases with the increase in definition of display devices.
[0004]
In such a liquid crystal display device, an image signal is written to a pixel electrode constituting each pixel by supplying an image signal from a source line to a pixel electrode turned on by a scanning line. The arrangement of liquid crystal molecules between the pixel electrode and the common electrode is controlled by the image signal written to the pixel electrode, and image display is performed.
[0005]
[Problems to be solved by the invention]
In the proposal of Japanese Patent Laid-Open No. 61-145597, as described above, an image signal is supplied to each source line by sequentially selecting the source lines in each group. The image signal once supplied to the source line is held by the wiring capacitance of the source line having a sufficiently large value compared to the liquid crystal capacitance constituted by the liquid crystal, and within a horizontal period that is turned on by the scanning line, It is written in the pixel electrode.
[0006]
However, since the source lines are selected in order within one horizontal period, the period during which an image signal is held within one horizontal period differs for each source line. Such a difference in writing time to the pixel electrode causes display unevenness. In particular, the proposal of Japanese Patent Application Laid-Open No. 61-145597 has a problem in that unevenness of vertical stripes appears on the screen because the writing time to the pixel electrode differs for each source line.
[0007]
An object of the present invention is to provide an electro-optical device driving circuit, an electro-optical device, an electronic apparatus, and an electro-optical device driving method capable of reducing display unevenness of a display device.
[0008]
[Means for Solving the Problems]
The drive circuit of the electro-optical device according to the present invention divides a data line for supplying an image signal to pixels arranged in a matrix into a plurality of blocks, and At least three A driving circuit for an electro-optical device that sequentially supplies a plurality of data lines in a horizontal period and supplies the image signals to a signal switching circuit that supplies the image signals. Image signals corresponding to each pixel in one line A plurality of select circuits sequentially selected in one horizontal period in block units and supplied to the plurality of signal switching circuits, respectively, and the plurality of signal switching circuits and the plurality of select circuits are controlled in conjunction with a plurality of select signals. Control means for supplying an image signal corresponding to each pixel of the one line to a corresponding data line, and the control means changes the generation timing of a plurality of select signals in one horizontal period in all combinations. According to the generated pattern, the plurality of signal switching circuits and the plurality of select circuits are controlled in conjunction with each other, Characterized in that to supply the image signal corresponding to each pixel of the on to the corresponding data line.
[0009]
According to such a configuration, the select circuit sequentially selects the image signal corresponding to each pixel of one line in one horizontal period for each block. The image signals from the select circuits corresponding to the number of blocks are supplied to the signal switching circuit. The data switching circuit sequentially switches the data lines in one horizontal period by the signal switching circuit, and the image signals are supplied to the data lines. . In such intra-block point sequential driving, the control means changes the selection order of the data lines in one horizontal period on the time axis. As a result, the writing time of each data line to the pixel changes on the time axis, the writing time is made uniform, and display unevenness is suppressed.
[0010]
The control unit may change the selection order of the data lines in the one horizontal period on the time axis so that the writing time of the image signal to each pixel is made uniform.
[0011]
According to such a configuration, for example, by changing the selection order of each data line in the block so that all the data lines are uniform, the writing time of the image signal to each pixel is made uniform. be able to.
[0012]
Further, the control means switches the selection order of the data lines in the one horizontal period every horizontal period.
[0013]
According to such a configuration, since the writing time of the image signal by each data line is changed for each line, the luminance is made uniform in the screen and display unevenness is suppressed.
[0014]
Further, the control means switches the selection order of the data lines in the one horizontal period every frame period.
[0015]
According to such a configuration, since the writing time of the image signal by each data line is changed for each frame, the luminance is made uniform among a plurality of screens and display unevenness is suppressed.
[0016]
Further, the control means switches the selection order of the data lines in the one horizontal period every horizontal period and every frame period.
[0017]
According to such a configuration, since the writing time of the image signal by each data line is changed for each line and for each frame, the luminance is made uniform in the screen and between the plurality of screens, and display unevenness is suppressed.
[0018]
Further, the control means changes a generation pattern of a select signal for controlling operations of the signal switching circuit and the select circuit on a time axis.
[0019]
According to such a configuration, the selection order of the image signal selected by the select circuit and the data line selected by the signal switching circuit is changed in one horizontal period by changing the generation pattern of the select signal on the time axis. can do.
[0020]
The image processing apparatus further includes a plurality of drive circuits for supplying the image signals from the plurality of select circuits to the plurality of signal switching circuits via a plurality of data supply lines corresponding to the respective blocks.
[0021]
According to such a configuration, it is only necessary to prepare a plurality of drive circuits and data supply lines for supplying image signals to the signal switching circuit by the number of blocks, and the apparatus can be miniaturized.
[0022]
The selection circuit may further include a latch circuit that simultaneously supplies an image signal corresponding to each pixel for one line.
[0023]
According to such a configuration, an image signal corresponding to each pixel for one line supplied to the select circuit can be obtained at the same time, so that writing can be performed in units of blocks, and writing time by each source line can be lengthened. Thus, a high-definition image can be obtained.
[0024]
The electro-optical device according to the present invention is dot-sequentially within a block via the driving circuit of the electro-optical device, a pixel portion having pixels arranged in a matrix, and a data line divided into the plurality of blocks. And a display unit including the plurality of signal switching circuits for supplying image signals.
[0025]
According to such a configuration, since the driving circuit of the electro-optical device can make the writing time to each pixel by the data line uniform, it is possible to prevent display unevenness in the image display in the display unit. it can.
[0026]
An electronic apparatus according to the present invention includes the electro-optical device.
[0027]
According to such a configuration, display unevenness does not occur in the electro-optical device, and thus a device capable of displaying a high-definition image can be obtained.
[0028]
According to the electro-optical device driving method of the present invention, a data line for supplying an image signal to pixels arranged in a matrix is divided into a plurality of blocks. At least three In the driving method of sequentially selecting a plurality of data lines in one horizontal period and supplying an image signal, the selection order of the data lines in the one horizontal period is changed in all combinations and switched.
[0029]
According to such a configuration, one line is divided into a plurality of blocks, and image signals are sequentially selected for each of the divided blocks. The selected image signal is supplied to the corresponding data line. The image signal and the corresponding data line are sequentially selected in one horizontal period for each block. Then, the selection order of the data lines in one horizontal period is changed on the time axis. Thereby, the writing time to the pixel by each data line is changed on the time axis to be uniform, and display unevenness is suppressed.
[0030]
Further, the selection order of the data lines in the one horizontal period is switched every horizontal period.
[0031]
According to such a configuration, since the writing time of the image signal by each data line is changed for each line, the luminance is made uniform in the screen and display unevenness is suppressed.
[0032]
The selection order of the data lines in the one horizontal period is switched every frame period.
[0033]
According to such a configuration, since the writing time of the image signal by each data line is changed for each frame, the luminance is made uniform among a plurality of screens and display unevenness is suppressed.
[0034]
Further, the selection order of the data lines in the one horizontal period is switched every horizontal period and every frame period.
[0035]
According to such a configuration, the writing time of the image signal by each data line is changed for each line and the writing time of the image signal by each data line is changed for each frame. The brightness is uniform between the screens, and the effect of suppressing display unevenness is excellent.
[0036]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0037]
First, the configuration of the electro-optical device according to the present embodiment will be described with reference to FIG. In this embodiment, the present invention is applied to a liquid crystal display device using a thin film transistor (hereinafter referred to as TFT). FIG. 2 is a block diagram showing specific circuit configurations of the TFT element substrate 1 and the driver IC 5 in FIG.
[0038]
In the present embodiment, all source lines (data lines) are divided into k blocks of u (three in FIG. 2) and one data supply line is provided for each u block from the drive circuit. This is applied to a liquid crystal display device that supplies a single image signal, a process of switching the image signal for m pixels in one line to k drive circuits, and the output of each drive circuit as a source line for m pixels Thus, the image signal can be supplied to all the source lines. That is, in the present embodiment, all source lines are divided into blocks, and dot-sequential driving (hereinafter referred to as intra-block point sequential driving) is performed within each block. Further, in the present embodiment, in the signal switching circuit processing, the selection order in one horizontal period of the source line to which the image signal is distributed is switched on the time axis, for example, for each line, thereby preventing display unevenness. Like to do.
[0039]
Reference numeral 1 denotes a TFT element substrate, which includes a pixel unit 2, a signal switching unit (DMPX) 3, and a Y driver 4 that are video display areas. The pixel unit 2 is a matrix display unit including pixels of n rows and m columns (n and m are integers), and forms m pixel matrixes of m in the X direction and n in the Y direction. . The pixel unit 2, the signal switching unit 3, and the Y driver 4 are provided on the TFT element substrate 1. Reference numeral 5 denotes a driver IC as an external drive circuit. A timing control circuit 6 controls the TFT element substrate 1 and the driver IC 2. Reference numeral 7 denotes a data supply line group which is a data line provided in the X direction of the pixel unit 2. The pixel unit 2 is driven by a signal switching unit 3, a Y driver 4, a driver IC 5, and a timing control circuit 6 that are driving circuits provided in the periphery. It is also conceivable that the Y driver 4 is constituted by a driver IC as an external drive circuit.
[0040]
Image data DATA, latch timing signal LP, shift register start signal ST, data clock signal CLX, and select signals S1, S2, and S3 are supplied from the timing control circuit 6 to the driver IC 5. A Y driver start signal DY and a line shift signal CLY are supplied from the timing control circuit 6 to the TFT element substrate 1.
[0041]
In FIG. 1, the shift register unit 11, the first and second latch circuits 12 and 13, the selector unit 14 and the driver 15 shown in FIG. 2, which will be described later, are included in the driver IC 5. However, all or A part may be included in the TFT element substrate 1.
[0042]
FIG. 2 is a diagram showing a circuit configuration of the TFT element substrate 1 and the driver IC 5. 11 is a shift register unit, 12 is a first latch circuit, 13 is a second latch circuit, 14 is a selector unit, and 15 is a driver unit. Are included in the driver IC 5.
[0043]
A clock signal CLX and a start signal ST are input to the shift register unit 11. The start signal ST is sequentially shifted in the shift register unit 11 according to the clock signal CLX. An output signal from each unit register of the shift register unit 11 is input to each unit latch circuit of the first latch circuit 12. On the other hand, image data DATA, which is an image signal, is supplied to all unit latch circuits simultaneously. When the output signal from the unit register is input, the image data DATA is stored in order in each unit latch circuit of the first latch circuit 12. Thus, m image data for one line, that is, one horizontal scanning line is stored in the first latch circuit 12. The image data DATA is, for example, a 6-bit digital signal.
[0044]
The second latch circuit 13 is a circuit that latches the image data DATA of the first latch circuit 12 as it is according to the latch timing signal LP. Therefore, the second latch circuit 13 simultaneously latches m pieces of data, which is data for one line. Note that each latch circuit 13 (1), 13 (2),... 13 (m) of the second latch circuit 13 latches an image signal corresponding to source lines X1, X2,. It has become.
[0045]
The selector unit 14 includes a plurality of select circuits 14 (1), 14 (2),..., 14 (k). By dividing the image data DATA for one line from the beginning or end of the data for one line into data corresponding to three consecutive pixels, a plurality of sets (blocks) are formed. Three sets of data are input to the corresponding select circuits. Specifically, image data DATA 1, 2, and 3 are input to select circuit 14 (1), and image data DATA 4, 5, and 6 are input to select circuit 14 (2). The circuit 14 (k) receives m-2, m-1, and m of the image data DATA. The selector unit 14 is supplied with select signals S1, S2, and S3, and each select circuit receives one image data predetermined from the three input image data according to the select signals S1, S2, and S3. The output signal is selected and supplied to the corresponding drive circuit of the driver unit 15.
[0046]
The driver unit 15 includes a plurality of drive circuits 15 (1), 15 (2),..., 15 (k). For example, when the select signal S1 is supplied, the image data DATA1 is output from the select circuit 14 (1) to the drive circuit 15 (1), and the image data DATA4 is output from the select circuit 14 (2). 15 (2), and the image data DATAm-2 is output from the select circuit 14 (k) to the drive circuit 15 (k). Each drive circuit includes a digital-analog converter, an amplifier circuit, and the like.
[0047]
The image signal from each drive circuit converted to an analog signal is supplied to the corresponding signal switching circuit of the signal switching unit 3 via the data supply line group 7. The signal switching unit 3 includes a plurality of signal switching circuits 3 (1), 3 (2),..., 3 (k). Each signal switching circuit has three switch circuits SW1, SW2, and SW3. The supplied image signal from each drive circuit is supplied to one end of three switch circuits SW1, SW2, and SW3 of the corresponding signal switching circuit. The other end of each switch circuit serving as an output is connected to the corresponding source lines (data lines) X1, X2,..., Xm of the data line group in the X direction of the pixel unit 2. The signal switching unit 3 is supplied with select signals S1, S2, and S3 for turning on / off each switch circuit. The switch circuits SW1, SW2, and SW3 of the signal switching unit 3 are selectively turned on sequentially in response to the select signals S1, S2, and S3, and supply image signals from the corresponding drive circuits to the corresponding source lines.
[0048]
For example, when the select signal S1 for turning on the switch circuit SW1 is supplied, the switch circuit SW1 of the signal switching circuit 3 (1) is turned on, and the image signal corresponding to the image data DATA1 is supplied to the source line X1. Is output. Similarly, the switch circuit SW1 of the signal switching circuit 3 (2) is also turned on, and an image signal corresponding to the image data DATA4 is output to the source line X4. Similarly, the switch circuit SW1 of the signal switching circuit 3 (k) is turned on, and an image signal corresponding to the image data DATAm-2 is output to the source line Xm-2.
[0049]
For example, when the select signal S2 for turning on the switch circuit SW2 is supplied, the switch circuit SW2 of the signal switching circuit 3 (1) is turned on, and the image signal corresponding to the image data DATA2 is supplied to the source line. Output to X2. Similarly, the switch circuit SW2 of the signal switching circuit 3 (2) is turned on, and an image signal corresponding to the image data DATA5 is output to the source line X5. Similarly, the switch circuit SW2 of the signal switching circuit 3 (k) is also turned on, and an image signal corresponding to the image data DATAm-1 is output to the source line Xm-1.
[0050]
Further, when the select signal S3 for turning on the switch circuit SW3 is supplied, the switch circuit SW3 of the signal switching circuit 3 (1) is turned on, and the image signal corresponding to the image data DATA3 is supplied to the source line X3. Is output. Similarly, the switch circuit SW3 of the signal switching circuit 3 (2) is also turned on, and an image signal corresponding to the image data DATA6 is output to the source line X6. Similarly, the switch circuit SW3 of the signal switching circuit 3 (k) is turned on, and an image signal corresponding to the image data DATAm is output to the source line Xm.
[0051]
As described above, each signal switching circuit sequentially selects the image signal from each drive circuit and outputs it to the corresponding source line by switching so as to turn on a predetermined switch circuit according to the select signal. . The switch circuits SW1, SW2, and SW3 are sequentially turned on within one horizontal period, and image signals are supplied to all source lines within one horizontal period in all blocks. Thus, in FIG. 2, dot-sequential driving is performed for each block using three source lines.
[0052]
In the present embodiment, the timing control circuit 6 is configured to switch the turn-on order of the switch circuits SW1, SW2, and SW3 on the time axis, for example, line by select signals S1 to S3.
[0053]
For example, in a predetermined horizontal period, the switch circuits SW1, SW2, and SW3 are sequentially turned on in this order by the select signals S1 to S3, and in one horizontal period, first, image signals are supplied to the source lines X1, X4, X7,. Next, it is assumed that an image signal is supplied to the source lines X2, X5, X8,..., And finally an image signal is supplied to the source lines X3, X6, X9,. In this case, in the next horizontal period, the timing control circuit 6 sequentially turns on the switch circuits SW1, SW2, and SW3, for example, in the order of the switch circuits SW2, SW1, and SW3 in response to the select signals S1 to S3. First, an image signal is supplied to the source lines X2, X5, X8,..., Then an image signal is supplied to the source lines X1, X4, X7,. A signal is supplied.
[0054]
In FIG. 2, 16 is a TFT corresponding to each pixel, and 17 is a transparent electrode (pixel electrode) electrically connected to the drain of the TFT 16 and a transparent electrode (counter electrode) on the translucent substrate. ) Shows the liquid crystal injected between. The Y driver 4 is connected to the pixel unit 2 by n gate lines (scanning lines) Y1, Y2,. Each gate line is connected to the gates of all the TFTs 16 in each row. When the gate signal is supplied to the gate line, the image data DATA for one line of the corresponding row can be written to the pixel portion 2.
[0055]
Each select circuit of the selector unit 14 operates in conjunction with each demultiplex circuit based on the select signals S1 to S3 so as to supply the output of the latch circuit corresponding to each pixel to the corresponding source line. It has become.
[0056]
Next, the state of signals in the above-described circuit configuration will be described with reference to FIG. FIG. 3 is a timing chart of the circuit configuration of FIG.
[0057]
In FIG. 3, ST is a pulse of a start signal indicating the start of operation to the shift register 11. CLX is a pulse of the data clock signal. DATA is a signal of image data. LP is a pulse of a latch timing signal for transferring the data stored in the first latch circuit 12 to the second latch circuit 13. S1, S2, and S3 are select signal pulses. YL-1 and YL are gate signals of the (L-1) th row and the Lth row generated by the Y driver 4 based on the start signal DY and the shift signal CLY, respectively. Here, L is an integer.
[0058]
Image data DATA1, 2,..., M corresponding to each pixel of the pixel unit 2 is supplied to the latch circuit 12 at a transfer rate corresponding to the data clock CLX. The start pulse ST sequentially shifts the shift register unit 11 according to the data clock CLX, and supplies a latch pulse to each unit latch of the latch circuit 12. Accordingly, each unit latch sequentially latches the image data DATA1, 2,..., M corresponding to each pixel in the horizontal direction of the pixel unit 2.
[0059]
The image data DATA1, 2,..., M for one line held in the latch circuit 12 is latched by the latch circuit 13 and output at the timing of the latch timing signal LP. The image data for one line output from the latch circuit 13 is written in each pixel electrode of the gate line (scanning line) turned on by the gate signal within one horizontal period.
[0060]
Now, it is assumed that it is a period during which the gate line of the (L-1) th row among the n rows is selected, that is, the (L-1) th horizontal period of FIG. In this case, the gate signal YL-1 having a signal waveform as shown in FIG. 3 is output to the corresponding gate line YL-1. Since the gate signal YL-1 becomes high level (hereinafter referred to as HIGH), the TFT 16 in the YL-1 row is turned on. In this case, one line of image data supplied to each pixel electrode in the (L-1) th row is output from the latch circuit 13.
[0061]
The image data for one line from the latch circuit 13 is divided into k blocks each having three adjacent pixels, and the image data of one pixel in each block is selected by the select circuits 14 (1), 14 (2), .., selected by 14 (k). This selection is performed based on select signals S1, S2, S3. As shown in FIG. 3, all of the select signals S1, S2, and S3 are signals that become HIGH only for about 1/3 of one horizontal period. The select circuits 14 (1), 14 (2),..., 14 (k) select one set of image data for each group according to the HIGH of the select signals S1, S2, and S3.
[0062]
That is, the select circuits 14 (1), 14 (2),..., 14 (k) receive the image data DATA 1, 4, 7 of the pixels (1), (4), (7) according to the HIGH of the select signal S 1. ,... Are selected and output, and the image data DATA2, 5, 8,... Of the pixels (2), (5), (8) are selected and output by the HIGH of the select signal S2, and the HIGH of the select signal S3 is output. To select and output the image data DATA3, 6, 9,... Of the pixels (3), (6), (9).
[0063]
Image data from the select circuits 14 (1), 14 (2),..., 14 (k) are converted into analog signals by the drive circuits 15 (1), 15 (2),. After being amplified, the signal is supplied to the signal switching circuits 3 (1), 3 (2),..., 3 (k). The signal switching circuits 3 (1), 3 (2),..., 3 (k) respectively branch the input image data to the source lines X1, X2,.
[0064]
The signal switching circuits 3 (1), 3 (2),..., 3 (k) are also controlled by the select signals S1, S2, and S3, and one input is output to one of three outputs. That is, the signal switching circuits 3 (1), 3 (2),..., 3 (k) are HIGH of the select signal S1, and output image data to the first output among the three outputs, and the select signal S2. The image data is output to the second output of the three outputs at the HIGH level, and the image data is output to the third output of the three outputs at the HIGH level of the select signal S3.
[0065]
That is, during the period when the select signal S1 is HIGH, the image data selected by the select circuits 14 (1), 14 (2),..., 14 (k) is supplied to the source lines X1, X4, X7,. When the select signal S2 is HIGH, the image data selected by the select circuits 14 (1), 14 (2),..., 14 (k) is supplied to the source lines X2, X5, X8,. When the select signal S3 is HIGH, the image data selected by the select circuits 14 (1), 14 (2),..., 14 (k) is supplied to the source lines X3, X6, X9,. Is done.
[0066]
Thus, in the first approximately one third period of the (L-1) horizontal period in FIG. 3, the image data DATA1, 4, 7,... Are converted into the source lines X1, X4, X7 by the HIGH of the select signal S1. , ... are supplied. In the (L-1) horizontal period, the gate signal YL-1 is HIGH, and each of the first, fourth, seventh,... TFTs 16 of the gate line L-1 has source lines X1, X4, X7. ,... Are supplied via image data DATA1, 4, 7,..., And then writing to the pixel electrodes is performed until the end of the (L-1) th horizontal period.
[0067]
In the next approximately one third period of the (L-1) horizontal period, the source line X2 is supplied to the second, fifth, eighth,... TFTs 16 of the gate line L-1 by HIGH of the select signal S2. , X5, X8,... Are supplied through image data DATA2, 5, 8,..., And then writing to the pixel electrodes is performed until the end of the (L-1) horizontal period. Further, in the last approximately one third period of the (L-1) horizontal period, the third, sixth, ninth,..., TFTs 16 of the gate line L-1 are supplied to the source by the HIGH of the select signal S3. Image data DATA3, 6, 9,... Are supplied via lines X3, X6, X9,..., And then writing to the pixel electrodes is performed until the end of the (L-1) horizontal period.
[0068]
As described above, each TFT 16 of the gate line L-1 has image data from the timing when the image data is input through the source line until the gate signal YL-1 becomes low level (hereinafter referred to as LOW). Is supplied and writing to the pixel electrode is performed. Therefore, the writing time to the pixel electrode via the source lines X1, X4, X7,... Is about 1H (horizontal) period, and the writing time to the pixel electrode via the source lines X2, X5, X8,. The (2/3) H period, and the writing time to the pixel electrode via the source lines X3, X6, X9,... Is about (1/3) H period.
[0069]
Thereafter, the image data selected based on the select signals S1, S2 and S3 is supplied to the corresponding source line and written to the pixel electrode via the turned-on TFT 16 by the same operation.
[0070]
In the present embodiment, in the next Lth horizontal period, the order of the source lines for writing image data is set differently from the (L−1) th horizontal period. That is, as shown in FIG. 3, in the L-th horizontal period in which the gate signal YL is HIGH, the select signal S3 becomes HIGH in the first approximately 1/3 period of one horizontal period, and the next approximately 1/3. The select signal S1 becomes HIGH during the period, and the select signal S2 becomes HIGH during the last approximately one third period.
[0071]
Therefore, writing to the pixel electrodes via the source lines X3, X6, X9,... Is performed for about 1H from the beginning of the Lth horizontal period, and writing to the pixel electrodes via the source lines X1, X4, X7,. Is performed for about (2/3) H period from the middle of the Lth horizontal period, and writing to the pixel electrode via the source lines X2, X5, X8,... 3) Performed for H period.
[0072]
Hereinafter, the generation pattern of the select signal in which the select signal becomes HIGH in the order of S1, S2, and S3 in one horizontal period is referred to as a first pattern. A selection signal generation pattern in which the select signal is HIGH in the order of S2, S3, and S1 in one horizontal period is referred to as a second pattern, and the select signal is HIGH in the order of S3, S1, and S2 in one horizontal period. A signal generation pattern is referred to as a third pattern.
[0073]
In the (L + 1) th horizontal period, the select signal S2 becomes HIGH in the first approximately 1/3 period of one horizontal period, the select signal S3 becomes HIGH in the next approximately 1/3 period, and the last approximately 1 /. In the period 3, the select signal S1 becomes HIGH (that is, the second pattern).
[0074]
In this case, writing to the pixel electrode via the source lines X2, X5, X8,... Is performed for about 1H period from the beginning of the (L + 1) horizontal period, and via the source lines X3, X6, X9,. Writing to the pixel electrode is performed for about (2/3) H period from the middle of the (L + 1) th horizontal period, and writing to the pixel electrode via the source lines X1, X4, X7,. The last approximately (1/3) H period of the horizontal period is performed. Thereafter, a matrix display of n rows and m columns (n and m are integers) on the display device is performed by the same operation.
[0075]
Eventually, in the three horizontal periods of the (L-1) to (L + 1) horizontal periods, writing to the pixel electrodes via the source lines X1, X4, X7,... Is performed for a total of 2H periods, and the source lines X2, X5 , X8,... Is written for a total period of 2H, and writing to the pixel electrodes via source lines X3, X6, X9,.
[0076]
Thereafter, the select signals S1, S2, and S3 repeat the first to third patterns in a period of three horizontal periods. That is, when viewed in a predetermined three consecutive horizontal periods, that is, in three consecutive lines, the writing time to each pixel electrode is equal in any source line. As a result, the luminance unevenness occurring in each line is averaged every three lines, and an image having no luminance unevenness as a whole can be displayed.
[0077]
As described above, in the present embodiment, the timing of supplying image data to each source line in the block is switched for each line at the time of intra-block dot sequential driving, and pixel electrodes are written by each source line in a plurality of lines. The time is made uniform. Thus, the change in luminance within the screen due to the writing time is averaged over a plurality of lines by dispersing pixels having the same luminance, and display unevenness is less visible.
[0078]
In the above embodiment, all the timings of the select signals S1, S2, and S3 are changed, and the generation pattern of the select signals S1, S2, and S3 is set to be restored to the original in three horizontal periods, so that the pixels The writing time for the electrodes was made uniform over 3 horizontal periods. However, it is clear that the time period for making the writing time uniform need not be three horizontal periods. The generation pattern of the select signal is not limited to that shown in FIG. 3, and various modifications can be made.
[0079]
Further, the same effect can be obtained by changing the timing of any one or two select signals instead of changing all the timings of the select signals S1, S2, and S3. For example, in the example of FIG. 3, the generation pattern of the select signal S2 may not be changed, and the generation patterns of the select signals S1 and S3 may be switched to each other in one horizontal period cycle. In this case, the writing time of all the pixels can be made uniform in two horizontal periods.
[0080]
That is, as long as the generation pattern of the select signals S1, S2, and S3 is changed on the time axis, the writing time to the pixels can be made uniform to some extent.
[0081]
Further, when the HIGH period of the select signal can be set to a time shorter than 1/3 of one horizontal period as in the case where the drive capability of the drive circuit is high, the select signals S1, S2, Even if only one of the generation timings of S3 is changed, some effects can be obtained.
[0082]
FIG. 4 is a flowchart showing the second embodiment of the present invention. In FIG. 4, LP indicates a latch timing signal, and S1, S2, and S3 indicate select signals.
[0083]
The present embodiment is different from the first embodiment only in the generation pattern of the select signals S1, S2, and S3, and the hardware configuration for realizing the present embodiment is the same as that shown in FIGS. Signals other than the select signal are the same as in FIG.
[0084]
In the first embodiment, the select signals S1, S2, and S3 are switched every line (one horizontal period) and returned to the original pattern in three horizontal periods. On the other hand, in the present embodiment, the select signal is switched every frame period and returned to the original pattern in three frame periods.
[0085]
That is, as shown in FIG. 4, in each horizontal period within a predetermined (F-1) th frame period, the select signals S1, S2, S3 become HIGH in this order (first pattern), and the next second In each horizontal period in the F frame period, the selection signals S3, S1, and S2 are HIGH in the order (third pattern), and in each horizontal period in the next (F + 1) frame period, the selection signals S2, It becomes HIGH in the order of S3 and S1 (second pattern).
[0086]
Thus, in the first approximately one third period of each horizontal period of the (F-1) th frame period of FIG. 4, the first, fourth, seventh,... The image data DATA1, 4, 7,... Are supplied to the TFTs 16 via the source lines X1, X4, X7,..., And the next approximately 1/3 of each horizontal period of the (F-1) th frame period. During the period, the second, fifth, eighth,..., TFT 16 of the gate line L-1 is transferred to the second, fifth, eighth,... TFT 16 of the gate line L-1 via the source lines X2, X5, X8,. .. Are supplied, and the third, sixth, ninth,... Of the gate line L-1 is supplied by HIGH of the select signal S3 in the last approximately one third period of each horizontal period of the (F-1) th frame period. Source line X3, X6 to each TFT16 X9, image data DATA3,6,9 through ..., ... is supplied, the writing to the pixel electrode is performed.
[0087]
In the next F-th frame period, in each horizontal period, first, in the first approximately 1/3 period, image data is transmitted via the source lines X3, X6, X9,... DATA3, 6, 9,... Are supplied, and in the next approximately 1/3 period, the image signal DATA1, 4, 7,... Is transmitted via the source lines X1, X4, X7,. Are supplied through the source lines X2, X5, X8,... By the HIGH of the select signal S2 during the last approximately 1/3 period.
[0088]
Further, in the next (F + 1) th frame period, in each horizontal period, first, in the first approximately 1/3 period, the select signal S2 is HIGH through the source lines X2, X5, X8,. Image data DATA2, 5, 8,... Are supplied, and in the next approximately 1/3 period, the image data DATA3, 6, 9 are transmitted via source lines X3, X6, X9,. ,... Are supplied, and image data DATA1, 4, 7,... Are supplied through the source lines X1, X4, X7,.
[0089]
In the embodiment configured as described above, in the (F-1) th frame, the writing time is longer in the order of the first, second and third source lines of each block, and in the Fth frame, each block The third, first, and second source lines have a long write time. In the (F + 1) th frame, the second, third, and first source lines in each block have a long write time. Accordingly, the writing time of the pixel electrode of each pixel is made uniform in three frames.
[0090]
Thus, also in this embodiment, the writing time of the pixel electrode is made uniform on the time axis, and display unevenness is suppressed.
[0091]
Also in the present embodiment, various modifications can be made to the selection signal generation pattern. For example, the generation pattern may be changed every two frame periods, and the period for returning to the original period is not limited to three frame periods.
[0092]
In the first embodiment, the selection signal generation pattern is changed for each horizontal period. In the second embodiment, the selection signal generation pattern is changed for each frame period. Obviously, they may be combined.
[0093]
FIG. 5 is an explanatory diagram showing an example of a select signal generation pattern employed in this case.
[0094]
In the example of FIG. 5, in the (F-1) th frame period, the select signal is set to HIGH in the order of S1, S2, S3 in the (L-1) horizontal period (first pattern), and the next Lth horizontal period. In the period, the select signal is set to HIGH in the order of S2, S3, and S1 (second pattern), and in the next (L + 1) horizontal period, the select signal is set to HIGH in the order of S3, S1, and S2 (third pattern). In the next Fth frame, the second pattern is adopted in the (L-1) horizontal period, the third pattern is adopted in the L horizontal period, and the first pattern is used in the (L + 1) horizontal period. Is adopted. In the next (F + 1) th frame, the third pattern is employed in the (L−1) horizontal period, the first pattern is employed in the Lth horizontal period, and the second pattern is employed in the (L + 1) horizontal period. The pattern is adopted.
[0095]
By changing the selection signal generation pattern for each horizontal period, the writing time between the pixels adjacent to each other in the upper and lower directions changes, and as shown in FIG. Then, the writing time of each pixel is uniform in any source line, and the luminance unevenness generated in each line is averaged every three lines. However, with this control alone, the writing time of the pixels at the same pixel position in each frame is constant, and a writing time difference occurs between the pixels.
[0096]
Therefore, in the example of FIG. 5, the generation pattern of the select signal is further changed every frame period. As a result, the writing time of each pixel at the same position in each frame changes for each frame. Then, by making one cycle of the generation pattern of the select signal in three frames, the writing time for the pixels at the same pixel position becomes uniform in three frames.
[0097]
As described above, in the example of FIG. 5, the writing time for each pixel is made uniform every three lines in the screen and is made uniform every three frames between the screens. As a result, the change in luminance due to the writing time of each pixel electrode is averaged within the screen and between the screens, and the display unevenness can be made more difficult to see.
[0098]
Further, each of the above embodiments has described the example of changing the selection order of the source lines on the time axis in the intra-block dot sequential driving. However, the above embodiments are applied to, for example, changing the selection order of the source lines in the line. Is also possible. That is, in the above embodiments, the source line selection order is the same in all blocks, but the source line selection order is changed for each block and the source line selection order is changed on the time axis. To do. Also in this case, the writing time of each pixel electrode can be made uniform, and the occurrence of display unevenness can be reduced.
[0099]
In each of the above embodiments, one block is constituted by three source lines, and three source lines in each block are sequentially selected in one horizontal period. However, the source lines constituting the blocks are described. The number of can be set as appropriate. For example, it is apparent that the present invention can be applied to a case where one block is composed of six source lines and the six source lines of each block are sequentially selected and driven in one horizontal period.
[0100]
In each of the above-described embodiments, in the block intra-sequential driving, a signal switching process for changing a signal from a plurality of signals to one signal and a generation pattern of a select signal for controlling the signal switching process from one signal to a plurality of signals In this example, the driving order of the source lines in each block is changed to change the writing time of each pixel electrode, so that the source in each block is within a predetermined time range. The line driving order may be changed, and the same effect can be obtained not only by changing the generation pattern of the select signal but also by using other methods.
[0101]
The above description is an example of a liquid crystal display device, but the present invention can also be applied to an organic EL (electroluminescence) display device, an electrophoretic display device, or the like having a matrix configuration.
[0102]
FIG. 6 is a schematic configuration diagram showing a third embodiment of the present invention. This embodiment shows a projection display device which is an example of an electronic apparatus using the electro-optical device of the first or second embodiment.
[0103]
In FIG. 6, the light source 210 includes a lamp 211 such as a metal halide and a reflector 212 that reflects light from the lamp 211. A dichroic mirror 213 and a reflection mirror 217 for reflecting blue light and green light are disposed on an optical path from the light source 210. The dichroic mirror 213 transmits red light out of the light flux from the light source 210 and reflects blue light and green light. The reflection mirror 217 reflects the red light transmitted through the dichroic mirror 213.
[0104]
On the optical path of the reflected light of the dichroic mirror 213, a dichroic mirror 214 and a reflective mirror 215 that reflect green light are disposed, and the dichroic mirror 214 reflects green light out of incident light and transmits blue light. The reflection mirror 215 reflects the transmitted light from the dichroic mirror 214. A reflection mirror 216 is disposed on the optical path of the reflected light of the reflection mirror 215, and the reflection mirror 216 further reflects the reflected light (blue light) of the reflection mirror 215.
[0105]
Liquid crystal devices 222, 223, which are light modulators and electro-optical devices similar to those in the first and second embodiments, are respectively provided on the output light paths of the reflecting mirror 217, the dichroic mirror 214, and the reflecting mirror 216. 224 is disposed. Red light, green light, or blue light is incident on the liquid crystal devices 222 to 224, respectively. The liquid crystal devices 222 to 224 light-modulate the incident light according to the R, G, and B image signals, respectively. The G and B image lights are emitted to the dichroic prism 225.
[0106]
The dichroic prism 225 is configured by bonding four right-angle prisms, and a dielectric multilayer film that reflects red light and a dielectric multilayer film that reflects blue light are formed in a cross shape on the inner surface thereof. The dichroic prism 225 synthesizes three R, G, and B color lights by these dielectric multi-layered beams and emits image light of a color image.
[0107]
A projection lens 226 constituting a projection optical system is disposed on the outgoing light path of the dichroic prism 225, and the projection lens 226 projects the combined image light on the screen 227. Thus, an enlarged image is displayed on the screen 227.
[0108]
In the embodiment configured as described above, display unevenness is suppressed in the liquid crystal devices 222, 223, and 224. Thus, the image projected on the screen 227 by the liquid crystal devices 222, 223, and 224 is a high-quality image that does not cause display unevenness, flickering, and the like.
[0109]
FIG. 7 shows an example in which the electro-optical device is applied to a mobile personal computer and a mobile phone. FIG. 7A is a perspective view illustrating a configuration of a personal computer. In the figure, a computer 1200 includes a main body 1204 provided with a keyboard 1202 and a display unit 1206. The display unit 1206 includes the electro-optical device 100 having the same configuration as that of each of the above embodiments.
[0110]
FIG. 7B is a perspective view showing an example in which the electro-optical device is applied to a mobile phone. In the figure, a mobile phone 1300 includes a plurality of operation buttons 1302, an earpiece 1304, a mouthpiece 1306, and a display unit including the electro-optical device 100 having the same configuration as that of each of the above embodiments. is there.
[0111]
In addition to the electronic devices described with reference to FIGS. 6 and 7, the electronic devices include a liquid crystal television, a viewfinder type, a monitor direct-view type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator, and a word processor. , Workstations, videophones, POS terminals, devices equipped with touch panels, and the like.
[0112]
The present invention is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the scope of the present invention.
[0113]
【Effect of the invention】
As described above, according to the present invention, it is possible to reduce the display unevenness of the display device.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a display device that is an electronic apparatus according to a first embodiment of the invention.
FIG. 2 is a block diagram showing a specific circuit configuration of a TFT element substrate 1 and a driver IC 5 in FIG.
FIG. 3 is a timing chart of the circuit configuration of FIG.
FIG. 4 is a flowchart showing a second embodiment of the present invention.
FIG. 5 is an explanatory diagram showing a modification.
FIG. 6 is a schematic configuration diagram showing a third embodiment of the present invention.
FIG. 7 is an explanatory diagram showing a modification of the third embodiment of the present invention.
[Explanation of symbols]
1 ... TFT element substrate
2 ... Pixel part
3. Signal switching part
4 ... Y driver part
5 ... Driver IC
6 ... Timing control circuit
7: Data supply line group
11: Shift register section
12: First latch circuit
13: Second latch circuit
14 ... Selector section
15 ... Driver section
16 ... TFT
17 ... Liquid crystal

Claims (5)

A plurality of pixels provided corresponding to the intersection of the scanning line and the plurality of data lines;
A data line driving circuit connected to the plurality of data lines,
The data line is divided into a plurality of data line blocks each consisting of n data lines,
The data line driving circuit includes:
A first signal switching unit that sequentially connects one data line of the n data lines included in the first data line block of the plurality of data line blocks and the first data supply line;
A first image signal supply unit for supplying an image signal to the first data supply line;
A second signal switching unit that sequentially connects one data line of the n data lines included in the second data line block of the plurality of data line blocks and the second data supply line;
A second image signal supply unit for supplying an image signal to the second data supply line;
Including
The first image signal supply unit includes:
A first latch unit for storing n image signals corresponding to n data lines included in the first data line block;
A first select unit for sequentially selecting one image signal corresponding to one data line among n image signals corresponding to n data lines stored in the first latch unit;
A first supply unit that supplies one image signal corresponding to the selected one data line to the first data supply line;
The second image signal supply unit includes:
A second latch unit for storing n image signals corresponding to n data lines included in the second data line block;
A second select unit for sequentially selecting one image signal corresponding to one data line among n image signals corresponding to n data lines stored in the second latch unit;
A second supply unit for supplying one image signal corresponding to the selected one data line to the second data supply line;
In the first signal switching unit, the first data supply line is output so that one image signal corresponding to one data line selected by the first select unit is output to the selected one data line. And the selected one data line are connected to each other,
The order of selection of the one image signal in the first selection unit is changed every time n image signals corresponding to the n data lines are selected, and the first signal switching unit selects the first image signal. The order of connection of the one data line connected to one data supply line is controlled to change every time the n data lines are connected;
In the second signal switching unit, the second data supply line is output so that one image signal corresponding to one data line selected by the second select unit is output to the selected one data line. And the selected one data line are connected to each other,
The selection order of the one image signal in the second select unit is changed every time n image signals corresponding to the n data lines are selected, and the second signal switching unit selects the first image signal. Control the order of connection of the one data line connected to two data supply lines to be changed each time the n data lines are connected;
The selection order of the one image signal is different between the first selection unit and the second selection unit, and the connection order of the one data line is different between the first signal switching unit and the second signal switching unit. An electro-optical device that is controlled differently . The first switching signal replacement portion before SL via the front Symbol said first data supply line image signals respectively digital / analog conversion and corresponding to the first data line block from the first cell recto portion electro-optical equipment according to claim 1, characterized in that were further comprising first drive unit Ru provided. The electro-optical device according to claim 1 , further comprising a latch circuit corresponding to each of the plurality of data line blocks . An electronic apparatus comprising the electro-optical device according to claim 1 . A plurality of pixels provided corresponding to the intersection of the scanning line and the plurality of data lines;
A data line driving circuit connected to the plurality of data lines,
The data line is divided into a plurality of data line blocks each consisting of n data lines,
The data line driving circuit includes:
A first signal switching unit that sequentially connects one data line of the n data lines included in the first data line block of the plurality of data line blocks and the first data supply line;
A first image signal supply unit for supplying an image signal to the first data supply line;
A second signal switching unit that sequentially connects one data line of the n data lines included in the second data line block of the plurality of data line blocks and the second data supply line;
A second image signal supply unit for supplying an image signal to the second data supply line;
Including
The first image signal supply unit includes:
A first latch unit for storing n image signals corresponding to n data lines included in the first data line block;
A first select unit for sequentially selecting one image signal corresponding to one data line among n image signals corresponding to n data lines stored in the first latch unit;
A first supply unit that supplies one image signal corresponding to the selected one data line to the first data supply line;
The second image signal supply unit includes:
A second latch unit for storing n image signals corresponding to n data lines included in the second data line block;
A second select unit for sequentially selecting one image signal corresponding to one data line among n image signals corresponding to n data lines stored in the second latch unit;
A method of driving an electro-optical device, comprising: a second supply unit that supplies one image signal corresponding to the selected one data line to the second data supply line;
In the first signal switching unit, the first data supply line is output so that one image signal corresponding to one data line selected by the first select unit is output to the selected one data line. And the selected one data line are connected to each other,
The order of selection of the one image signal in the first selection unit is changed every time n image signals corresponding to the n data lines are selected, and the first signal switching unit selects the first image signal. The order of connection of the one data line connected to one data supply line is controlled to change every time the n data lines are connected;
In the second signal switching unit, the second data supply line is output so that one image signal corresponding to one data line selected by the second select unit is output to the selected one data line. And the selected one data line are connected to each other,
The selection order of the one image signal in the second select unit is changed every time n image signals corresponding to the n data lines are selected, and the second signal switching unit selects the first image signal. Control the order of connection of the one data line connected to two data supply lines to be changed each time the n data lines are connected;
The selection order of the one image signal is different between the first selection unit and the second selection unit, and the connection order of the one data line is different between the first signal switching unit and the second signal switching unit. A method of driving an electro-optical device, characterized by performing control differently .

Images