JP2005099872A - Liquid crystal display, display device and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable a user of a device to freely set a partial display area to some extent in a liquid crystal display having a function capable of making only a part of a screen into a display state and making the remaining part into a non-display state. <P>SOLUTION: When an area which is desired to be partially displayed is considered as a surrounded area from L1 to L2 row and M1 to M2 row of a liquid crystal display panel 1, it is constituted so that values corresponding to L1, L2, M1, M2 can be written by providing a control circuit with a register and the area is partially displayed according to the values written there. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a liquid crystal device having a function of allowing only a part of a region to be in a display state and other regions to be in a non-display state.

  Display devices used in mobile electronic devices such as mobile phones have been increasing the number of display dots year by year so that more information can be displayed, and accordingly, power consumption by the display devices has also increased. . Since the power source of the portable electronic device is a battery, low power consumption is strongly required so that the battery life can be extended. Therefore, in a display device with a large number of display dots, the entire screen is displayed when necessary, but only a part of the area of the display panel is displayed so that the necessary minimum display is possible in normal times. A method for reducing the power consumption by making the area non-displayed is being studied.

Many conventional liquid crystal display devices have a function that can control display / non-display of the entire screen, but those that have a function of setting only a certain area of the screen to a display state and other areas to a non-display state are still available. Not put into practical use. As a method for realizing such a function, JP-A-6-95621, Example 1 and JP-A-7-281632 have been proposed. Both of these conventional examples describe the case where the liquid crystal display panel is a simple matrix type.

  An embodiment of Japanese Patent Laid-Open No. 6-95621 will be described below with reference to FIGS. FIG. 7 is a block diagram of the liquid crystal display device of this embodiment. A block 51 is a liquid crystal display panel, in which a substrate on which a plurality of scanning electrodes are formed and a substrate on which a plurality of signal electrodes are formed are arranged facing each other at intervals of several μm, and liquid crystal is sealed in the gaps. Block 55 is a Y driver that drives the scan electrodes, and block 56 is an X driver that drives the signal electrodes. A plurality of voltage levels necessary for driving the liquid crystal are formed by the drive voltage forming circuit of the block 54 and applied to the liquid crystal display panel via the X driver and the Y driver. Block 57 is a scan control circuit for controlling the number of scan electrodes to be scanned. A block 52 is an LCD controller that forms timing signals, display data signals, and control signals necessary for these circuits, and a block 53 is a power supply source of the above circuits. A selection voltage is sequentially applied to the scan electrodes row by row, and a non-selection voltage is applied to the other rows. A signal voltage according to on / off of each pixel in the selected row is sequentially applied to the signal electrode.

  In this embodiment, the case where the partial display is the left half screen and the case where the partial display is the upper half is described. First, the case where the partial display is the left half screen will be described. The number of signal electrodes is 640. Before shifting to the partial display state of the left half screen, data in which all pixels for one row are off is written in the X driver. After that, the LCD controller doubles the cycle of the clock CLX that operates the shift register inside the X driver, halves the number of clocks in one selection period, and transfers only display data for 320 pixels per row accordingly. To do. At this time, even if there is only data transfer for 320 pixels on the left half screen, the X driver has a circuit for storing display data for one row, so the right half of the X driver was transferred first. The data of OFF is continuously stored, and 320 outputs in the right half of the X driver continue to output a voltage for turning off the display. Thus, the right half screen can be turned off. Since the operation clock frequency of the X driver is halved and half of the panel is turned off, the power consumption of the display device is slightly reduced compared to the full screen display state.

  Next, the case where the partial display is only the upper half of the left half screen will be described. The number of scan electrodes is 400. First, only the left half screen is set to the display state by the method described above. Subsequently, the LCD controller sets the partial display control signal PD to the “H” level so that the lower half is not displayed. When the PD is at the “L” level, the entire screen is displayed by scanning all the scanning electrodes at 1/400 duty. When the PD is at the “H” level, only the upper half of the scanning electrode is set to 1 By scanning at / 200 duty, the upper half screen is in the display state and the remaining lower half screen is in the non-display state. Switching to 1/200 duty is performed by doubling the cycle of the clock CLY for operating the shift register in the Y driver to halve the number of clocks in one frame period. Although details of the scanning stop method for the scanning electrodes of the lower half screen in the partial display state are not described, judging from the internal circuit diagram of the scanning control circuit block 54, if PD is set to “H” level, the shift register in the Y driver The data transferred from the 200th stage to the 201st stage is fixed to the “L” level, and as a result, the 201st to 400th outputs of the Y driver are kept at the non-selection voltage level.

  The on / off state of the pixel is determined by the effective value of the voltage applied to the liquid crystal. The effective voltage applied to the liquid crystal in the lower half screen is considerably smaller than the effective voltage applied to the liquid crystal in the off display state of the upper right quarter screen because no selection voltage is applied to the scan electrodes. The screen is completely hidden.

  In the simple matrix type liquid crystal display panel, when the display duty is switched, it is necessary to change the setting of the drive voltage. This point will be described below with reference to FIG. 8 which is an internal circuit of the drive voltage forming block 53.

  First, the configuration and functions of FIG. 8 will be described. In order to drive a liquid crystal display panel having a duty higher than about 1/30 duty, six levels of voltages V0 to V5 are required. The maximum voltage applied to the liquid crystal is V0-V5, and the input power supply voltage of + 5V is used as it is for V0. A voltage V5 at which the contrast is optimized is taken out from the input power supply of 0V and −24V by the variable resistor RV1 for contrast adjustment and the transistor Q1. The resistors R1 to R5 divide the voltage V0 to V5 to form an intermediate voltage, and the intermediate voltages are increased in driving capability by operational amplifiers OP1 to OP4 to output V1 to V4. The switches S2a and S2b are interlocking switches, and one of R3a and R3b is connected according to the level of the signal PD. By making the resistance values of R3a and R3b different, V0 to V5 having different voltage division ratios can be formed according to the PD level.

  Between V0 and V5, there is a relationship of V0−V1 = V1−V2 = V3−V4 = V4−V5, and the voltage division ratio (V0−V1) / (V0−V5) is called a bias ratio. Japanese Patent Publication No. 57-57718 discloses that a preferable bias ratio is 1 / (1 + √N) when the duty is 1 / N. Accordingly, if the resistance values of R3a and R3b are set for 1/400 duty and 1/200 duty, respectively, it is possible to drive with a preferable bias ratio at each duty.

  When switching the duty, it is necessary not only to switch the bias ratio but also to change the drive voltage = V0−V5 at the same time. If the duty is switched from 1/400 to 1/200 with the drive voltage fixed, even if the bias ratio is switched to a preferable value, the contrast becomes extremely poor. This is because the effective voltage applied to the liquid crystal becomes too high because the time during which the selection voltage is applied to the liquid crystal is doubled. In this embodiment, the necessity for switching the bias ratio and the means for realizing it are described in detail, while the necessity for switching the drive voltage and the means for realizing it are not described in detail.

  Specifically, assuming that the duty is 1 / N, it is necessary to adjust V0−V5 in proportion to √N when N >> 1. For example, if the optimum V0-V5 in the case of 1/400 duty is 28V, it is necessary to adjust V0-V5 to 28V / √2≈20V in the case of 1/200 duty. This voltage adjustment is performed by adjusting the variable resistor RV1 for contrast adjustment every time the full screen display state and the upper half screen display state are switched, which is very inconvenient for the device user. It is. Although it is essential to add the drive voltage automatic setting means, the drive voltage forming circuit is greatly complicated because it is not as easy as the bias ratio switching means.

  When the partial display is as small as about 10 to 20 lines, the preferred bias ratio becomes 1/3 or 1/4 when the duty is switched accordingly. The voltage required for driving the liquid crystal is not 6 levels but 5 levels in the case of 1/4 bias and 4 levels in the case of 1/3 bias. If a voltage of 5 levels is required, the resistance value on the side connected during partial display of R3a and R3b may be set to 0Ω. However, if a voltage of 4 levels is required, R2 and not R3 * A means for setting R4 to 0Ω is required. Japanese Patent Application Laid-Open No. 7-281632 describes the bias ratio switching means and the drive voltage switching means in this case in the embodiment, but further description of the embodiment is omitted here.

  According to the methods proposed so far, the function of setting only a part of the area of the liquid crystal display panel to the display state and setting the other areas to the non-display state becomes possible. However, switching the clock cycle or switching the bias ratio or drive voltage corresponding to the partial display area is limited to the settings for which the partial display area is prepared. Accompanying the drawback of very poor nature.

  Many liquid crystal drivers have a display-off function by a control input terminal. Although it is possible to set a partial display area for each IC chip by individually controlling the display-off control input for each driver IC using this function, a setting is also provided in which a partial display area is prepared. Therefore, it is a method lacking in versatility.

  Accordingly, an object of the present invention is to provide a highly versatile liquid crystal display device in which a partial display area can be set in a software manner.

  The liquid crystal display device according to claim 1, wherein a plurality of scanning electrodes and a plurality of signal electrodes are arranged to intersect with each other, and a control circuit that partially controls a display area of a display screen is provided. The circuit has a value corresponding to the start line and a value corresponding to the end line of the partial display unit so that the width and position of the partial display unit partially displayed in the display area of the display screen can be varied. Two series of registers set separately and a circuit block for forming a timing signal for controlling the partial display based on a set value in the two series of registers, and controlled by the timing signal A scanning signal and a clock for transferring the scanning signal are output during the partial display period, and the clock is output during the period corresponding to the non-display portion from the first row of the display screen to the start row of the partial display portion. And wherein the operating the click.

  For example, when the area to be partially displayed is an area surrounded by the display dots from the L1 line to the L2 line and from the M1 column to the M2 column, a register is provided in the control circuit and L1, L2, M1, It is technically possible to write a value corresponding to M2 and to partially display the value according to the value written therein. The liquid crystal device having such means is highly versatile because the user can set the area he / she wants to partially display.

  The liquid crystal display device according to claim 2, wherein the display area and the non-display area are divided by the signal electrode, and the voltage applied to the signal electrode in the non-display area is fixed to a voltage at which display is turned off. And means for stopping transfer of display data corresponding to the non-display area.

  Even during partial display, the period of the data transfer clock in the display part is the same as that during full screen display, and at least one of the data transfer clock or data is stopped during the data transfer period of the non-display part. It is possible to maintain versatility when the display area is divided by the signal electrodes.

  The liquid crystal display device according to claim 3 is a row direction in which the display area and the non-display area are divided by the scanning electrodes, and the display area is divided into a case where the display area is displayed on all lines and a case where the display area is displayed on a part of the lines. The time for applying the selection voltage to the scan electrodes is the same.

  Even in the partial display, the display area and the non-display area are divided by the scan electrodes by the method of applying the selection voltage to the scan electrodes in the display area, the bias ratio, and the drive voltage the same as in the full screen display. Generality in the case of direction can be maintained.

  5. The liquid crystal display device according to claim 4, wherein a pixel electrode is formed in a matrix form on the display panel to form a pixel portion, a switching element is formed on the pixel electrode, and a pixel in a row in a non-display area. Means for writing the applied voltage to the liquid crystal at approximately 0V.

  In the case of the simple matrix method, the row can be brought into a non-display state only by applying a non-selection voltage to the scan electrode. However, in the case of the active matrix method such as TFT or MIM, the non-selection period is in the pixel portion. In order to keep the voltage, it is necessary to write an off-voltage to the pixels in the non-display row before shifting to the partial display state. If it is written at 0V, the AC drive specific to the liquid crystal becomes unnecessary. By such means, even in an active matrix type liquid crystal device, versatility can be maintained when the display area and the non-display area are divided by the scanning electrodes.

  An electronic apparatus according to the present invention includes the above-described liquid crystal display device.

  The display device according to the present invention is a display device that includes a plurality of scanning electrodes and a plurality of signal electrodes that are arranged to intersect each other, and includes a control circuit that partially controls a display area of a display screen. The circuit includes a value corresponding to the start line and a value corresponding to the end line of the partial display unit so that the width and position in the row direction of the partial display unit partially displayed in the display area of the display screen can be changed. Are divided and set, and a circuit block that forms a timing signal for controlling the partial display based on a set value in the two series of registers, and is controlled by the timing signal. In the period corresponding to the non-display portion from the first row of the display screen to the start row of the partial display portion, the scanning signal and a clock for transferring the scanning signal are output during the partial display period. Characterized in that to operate the serial clock.

  According to the present invention, since the device user can set the required width and position of the partial display area with the register, a highly versatile liquid crystal device can be provided.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a partial display state in the liquid crystal display device of the present invention, where a shaded portion is in a display state and a white portion is in a non-display state. When necessary, the white background portion is also displayed, but during standby, it is displayed only in a partial region of the liquid crystal display panel 1 as shown in the figure.

  1A shows a case where the display area and the non-display area are divided by the signal electrodes. FIG. 1B shows a case where the display area and the non-display area are divided by the scan electrodes. Is a diagram showing a case of the combination. Hereinafter, the direction divided by the signal electrodes is represented as a column direction, and the direction divided by the scanning electrodes is represented as a row direction. As will be described in the following embodiments, the size and position of the partial display area can be set through values set in a register in the control circuit (LCD controller).

  FIG. 2 is a block diagram showing the configuration of the liquid crystal display device of the present invention. 1 is a liquid crystal display panel, 2 is an LCD controller, 3 is a power supply source, 4 is a drive voltage forming circuit, 5 is a driver for driving a scan electrode, and 6 is a driver for driving a signal electrode. Since the basic elements are the same as those in FIG. 6 described in the prior art, description of each element is omitted. The function of the LCD controller, which is the point of the present invention, will be described in an individual embodiment together with the contents of each signal. In the figure, the LCD controller is shown as an independent circuit block, but may be built in any of the driver IC chips.

(Example 1)
An example of a method for realizing the partial display state as shown in FIG. 1A will be described with reference to FIGS. FIG. 3 is a circuit diagram showing a part of the LCD controller built in the liquid crystal display device, and is a circuit block for controlling the partial display state in the column direction. FIG. 4 is a timing chart showing the operation of the circuit of FIG.

7 is a register of about 8 bits, in which information indicating whether or not to perform partial display in the column direction and information corresponding to the number of columns to be partially displayed are set. Normally, display data for a plurality of dots is transferred for each clock of the data transfer clock. Therefore, the register 7 may be set with the number of data transfer clocks corresponding to the number of columns for partial display. If display data for 8 dots is transferred for each data transfer clock, if 7 bits, partial display up to 2 ⁷ × 8 dots = 1024 dots can be set in units of 8 dots.

  Reference numeral 8 denotes a circuit block mainly composed of a counter, which is a timing signal for controlling partial display in the column direction based on timing signals such as a scanning start signal FRM, a display data latch signal LP, and a data transfer clock CLXI and a set value of the register 7. CNT1 and CNT2 are formed. FRM, LP, and CLXI are timings as shown in FIG. In order to make the figure easier to understand, the number of clocks of CLXI per LP cycle is shown smaller than the actual number. For example, when the number of display dots in the column direction is 320 and the display data transfer is parallel for 8 dots, the number of CLXI clocks per LP cycle is 40. CLXI and DataI are signals that become a data transfer clock and display data when not in partial display. CLX and Data are signals sent from the LCD controller to the signal electrode driver, and are a data transfer clock and display data, respectively.

  T1 in FIG. 4 indicates a time when the state is not the partial display state and is switched to the partial display state. To be precise, the partial display process starts from t1.

  Before t1, CNT1 and CNT2 are constantly at the H level. At this time, the AND gates 9 and 10 remain open, and the same signals as CLXI and DataI are sent to CLX and Data as they are. In the partial display state, CNT1 and CNT2 are made to have timing signals as shown on the right side of FIG. 4 so that CLX and Data corresponding to the non-displayed portion are stopped.

A period in which one row is selected, that is, one period of LP is represented as a 1H period. While a row is selected, the X driver outputs a voltage according to the display data of each dot in that row, but the display data of that row is transferred to the X driver 1H before that. To be done. Since 1H immediately after FRM and LP becomes H level, the first row is selected, display data of the first row is transferred to the X driver 1H before that. As the display data on the first line, it is necessary to transfer the off-display data of the non-display part together with the data of the display part. Therefore, CLX in the 1H period immediately after t1, that is, the period in which the display data for the first row is transferred requires the number of clocks for sending data for all the dots in one row as before t1, so during this period CNT1 is at H level. On the other hand, the CNT2 in the 1H period is set to the L level only during the transfer of the off display data, and the display data is fixed to the L level.

  If such data transfer is performed only for 1H immediately after t1, the X driver continues to store the off-data that has been transferred previously for the portion that has not been transferred, and thereafter the period corresponding to the non-display portion The non-display portion can be turned off without performing data transfer.

  By the above method, a partial display in which the display area and the non-display area are divided by the signal electrodes as shown in FIG. 1A can be performed. According to the present embodiment, the width of the partial display can be freely changed, for example, in units of 8 dots in correspondence with the value set in the register.

  In the partial display state, partial display is possible only by stopping one of CLX and Data corresponding to the non-display part. However, if both are stopped as in this embodiment, lower power consumption is achieved. This is preferable.

  The method described above is an example in which the partial display unit starts from the first column of the display panel. However, two registers are provided so that values corresponding to the start column and the end column of the partial display unit can be set respectively. Then, not only the width of the partial display unit in the column direction but also the position can be set freely. However, in this case, it is necessary to operate CLX for a period corresponding to the non-display portion from the first row of the display panel to the start row of the partial display portion.

(Example 2)
An example of a method for realizing the partial display state as shown in FIG. 1B will be described with reference to FIGS. FIG. 5 is a circuit diagram showing a part of the LCD controller built in the liquid crystal display device, and is a circuit block for controlling the partial display state in the row direction. FIG. 6 is a timing chart showing the operation of the circuit of FIG. The display panel is line-sequentially driven row by row and has a total of 200 rows. In the partial display state, only the first 32 rows are displayed. In FIG. 6, portions A and B are diagrams for a simple matrix type and an active matrix type liquid crystal display device, respectively.

Reference numeral 11 denotes a register of about 8 bits, in which information indicating whether or not to perform partial display in the row direction and information corresponding to the number of rows to be partially displayed are set. If the number of rows is set by 7 bits, a partial display up to 2 ⁷ = 128 rows can be set for each row in a panel of line sequential drive for each row, and 2 ⁷ × 4 in a panel of 4 rows simultaneous selection drive. = Partial display up to 512 lines can be set in units of 4 lines.

  A circuit block 12 mainly includes a counter, which forms timing signals PDY and CNT3 for controlling partial display in the row direction based on timing signals such as a scanning start signal FRM and a scanning signal transfer clock CLYI and a set value of the register 11. To do. FRM and CLYI are timings as shown in FIG. CLYI is a signal serving as a scanning signal transfer clock when the partial display is not performed. CLY is a scanning signal transfer clock sent from the LCD controller to the Y driver, and an AND output of CNT3 and CLYI by the AND gate 13 becomes CLY.

  Usually, the Y driver has a control input for prohibiting the output of the selection voltage. PDY is a signal that becomes such a control input of the Y driver, and when it is at the L level, the selection voltage output is prohibited and all the outputs of the Y driver are at the non-selection voltage level.

  T2 in FIG. 6 indicates a time when the state is changed from the non-partial display state to the partial display state. To be precise, the partial display process starts from t2. One frame period immediately after t2 is represented as F1, and the next one frame period is represented as F2.

  Before t2, CNT3 is constantly at the H level. At this time, the AND gate 13 remains open, and the same signal as CLYI is sent to CLY as it is. Prior to t2, PDY is also constantly at the H level, and each output of the Y driver sequentially outputs a selection voltage, and the entire screen is in a display state. In the partial display state, CNT3 and PDY are signals having timings as shown in FIG. 6 so that the CLY corresponding to the non-displayed lines 33 to 200 stops and the selection voltage is not output from the Y driver. Like that.

  Since the CLY cycle is not changed even in the partial display state, the time for applying the selection voltage to the scan electrodes in the display area is the same as in full screen display. There is no need to change the bias ratio or the selection voltage.

  When the display panel is an active matrix system, the voltage of the pixel portion is continuously held during the non-selection period. Therefore, it is necessary to write an off-voltage to the pixels in the non-display row when shifting to the partial display. In the figure, VCT is a signal voltage control signal, and it is assumed that when VCT is set to L level, the signal voltage for writing to the pixel can be reduced to almost 0V. For example, in the case of a TFT panel, if the same voltage as the common potential is written, the write signal voltage to the pixel can be made almost 0V. In the case of the active matrix system, CNT3 and PDY are set to the H level so that the application of CLY and the selection voltage is not stopped only during the period F1, and substantially 0V is written to the pixels while the non-display row is selected, and after F2 The CLY corresponding to the non-display portion is stopped and the selection voltage is not output from the Y driver. In the case of the simple matrix system, the same timing signal may be repeated for each frame after t2.

  By the above method, a partial display in which the display area and the non-display area are divided by the scan electrodes as shown in FIG. 1B can be performed. According to this embodiment, the width of the partial display is made to correspond to the value set in the register, one line at a time in the case of line-sequential driving line by line, and simultaneously selected lines in the case of multiple-line simultaneous selection driving. It can be freely changed in units of numbers.

  In the partial display state, the partial display can be performed only by stopping the application of the selection voltage without stopping the CLY corresponding to the non-display portion. However, the CLY should be stopped as in this embodiment. This is preferable in terms of low power consumption. When CLY during partial display is stopped using a Y driver whose internal is not reset by FRM, a selection voltage must be applied for one frame to avoid abnormal display when shifting from the partial display state to the full screen display state. It is preferable to stop.

  The method described above is an example in the case where the partial display unit starts from the first line of the display panel. However, two registers are provided so that values corresponding to the start line and the end line of the partial display unit can be set respectively. Then, not only the width of the partial display unit in the row direction but also the position can be set freely. However, in this case, it is necessary to operate CLY during a period corresponding to the non-display portion from the first row of the display panel to the start row of the partial display portion.

  In addition, when Example 1 and Example 2 are combined, a partial display as shown in FIG. 1C is possible when each register is one series, and a part as shown in FIG. 1D is shown when each register is two series. Display is possible.

(Example 3)
Next, an electronic apparatus equipped with the liquid crystal device of the present invention will be described below.

  An electronic apparatus configured using the liquid crystal display device of the above-described embodiment includes a display information output source 1000, a display information processing circuit 1002, a display driving circuit 1004, a display panel 1006 such as a liquid crystal panel, and a clock generation circuit shown in FIG. 1008 and the power supply circuit 1010 are comprised. The display information output source 1000 is configured to include a memory such as a ROM and a RAM, a tuning circuit that tunes and outputs a television signal, and outputs display information such as a video signal based on the clock from the clock generation circuit 1008. To do. The display information processing circuit 1002 processes display information based on the clock from the clock generation circuit 1008 and outputs it. The display information processing circuit 1002 can include, for example, an amplification / polarity inversion circuit, a phase expansion circuit, a rotation circuit, a gamma correction circuit, or a clamp circuit. The display driving circuit 1004 includes a scanning side driving circuit and a data side driving circuit, and drives the liquid crystal panel 1006 to display. The power supply circuit 1010 supplies power to each of the circuits described above.

  As an electronic apparatus having such a configuration, a liquid crystal projector shown in FIG. 10, a personal computer (PC) and an engineering workstation (EWS) corresponding to multimedia shown in FIG. 11, a pager shown in FIG. 12, a mobile phone, a word processor, Examples include a television, a viewfinder type or a monitor direct view type video tape recorder, an electronic notebook, an electronic desk calculator, a car navigation device, a POS terminal, and a device equipped with a touch panel.

  FIG. 10 is a schematic configuration diagram showing a main part of the projection display device. In the figure, 10 is a light source, 13 and 14 are dichroic mirrors, 15, 16 and 17 are reflection mirrors, 18, 19 and 20 are relay lenses, 22, 23 and 24 are liquid crystal light valves, 25 is a cross dichroic prism, and 26 is A projection lens is shown. The light source 10 includes a lamp 11 such as a metal halide and a reflector 12 that reflects the light of the lamp. The blue / green light reflecting dichroic mirror 13 transmits red light of white light flux from the light source 10 and reflects blue light and green light. The transmitted red light is reflected by the reflection mirror 17 and enters the red light liquid crystal light valve 22. On the other hand, green light out of the color light reflected by the dichroic mirror 13 is reflected by the dichroic mirror 14 reflecting green light and is incident on the liquid crystal light valve 23 for green light. On the other hand, the blue light also passes through the second dichroic mirror 14. For blue light, in order to prevent light loss due to a long optical path, a light guide means 21 comprising a relay lens system including an incident lens 18, a relay lens 19, and an output lens 20 is provided, through which blue light is blue. The light enters the light liquid crystal light valve 24. The three color lights modulated by the respective light valves enter the cross dichroic prism 25. In this prism, four right-angle prisms are bonded together, and a dielectric multilayer film that reflects red light and a dielectric multilayer film that reflects blue light are formed in a cross shape on the inner surface. These dielectric multilayer films combine the three color lights to form light representing a color image. The synthesized light is projected onto the screen 27 by the projection lens 26 which is a projection optical system, and the image is enlarged and displayed.

  A personal computer 1200 shown in FIG. 11 includes a main body 1204 provided with a keyboard 1202 and a liquid crystal display screen 1206.

  12 includes a liquid crystal display substrate 1304, a light guide 1306 having a backlight 1306a, a circuit substrate 1308, first and second shield plates 1310 and 1312, and two elastic conductive members. It has a body 1314, 1316 and a film carrier tape 1318. Two elastic conductors 1314 and 1316 and a film carrier tape 1318 connect the liquid crystal display substrate 1304 and the circuit substrate 1308.

  Here, the liquid crystal display substrate 1304 is obtained by sealing liquid crystal between two transparent substrates 1304a and 1304b, thereby forming at least a dot matrix type liquid crystal display panel. A driving circuit 1004 shown in FIG. 9 or a display information processing circuit 1002 can be formed on one transparent substrate. A circuit that is not mounted on the liquid crystal display substrate 1304 is an external circuit of the liquid crystal display substrate, and can be mounted on the circuit substrate 1308 in the case of FIG.

  FIG. 12 shows the configuration of the pager, and thus a circuit board 1308 is required in addition to the liquid crystal display board 1304. In the case where a liquid crystal display device is used as a component for electronic equipment, When a display driving circuit or the like is mounted, the minimum unit of the liquid crystal display device is a liquid crystal display substrate 1304. Alternatively, a liquid crystal display substrate 1304 fixed to a metal frame 1302 as a housing can be used as a liquid crystal display device which is a component for electronic equipment. Further, in the case of the backlight type, a liquid crystal display device can be configured by incorporating a liquid crystal display substrate 1304 and a light guide 1306 provided with a backlight 1306a in a metal frame 1302. Instead of these, as shown in FIG. 13, a TCP in which an IC chip 1324 is mounted on a polyimide tape 1322 having a metal conductive film formed on one of two transparent substrates 1304a and 1304b constituting a liquid crystal display substrate 1304. (Tape Carrier Package) 1320 can be connected to be used as a liquid crystal display device which is one component for electronic equipment.

  In addition, this invention is not limited to the said Example, A various deformation | transformation implementation is possible within the range of the summary of this invention. For example, the present invention can be applied not only to driving the above-described various liquid crystal panels but also to electroluminescence and plasma display devices.

The figure which shows the partial display state in the liquid crystal display device of this invention. 1 is a block diagram of a liquid crystal display device of the present invention. FIG. 3 is a partial diagram of a control circuit of a liquid crystal display device showing an embodiment of the present invention. FIG. 4 is a timing chart showing the operation of the circuit of FIG. 3. FIG. 6 is a partial view of a control circuit of a liquid crystal display device showing another embodiment of the present invention. FIG. 6 is a timing chart showing the operation of the circuit of FIG. 5. FIG. 10 is a block diagram of a conventional liquid crystal display device having a partial display function. FIG. 8 is a detailed circuit diagram of the liquid crystal drive voltage generation circuit in FIG. 7. 1 is a schematic diagram of an electronic device using a liquid crystal device of the present invention. 1 is a schematic diagram of an electronic device showing a configuration in which a liquid crystal device of the present invention is mounted. 1 is a schematic diagram of an electronic device showing a configuration in which a liquid crystal device of the present invention is mounted. 1 is a schematic diagram of an electronic device showing a configuration in which a liquid crystal device of the present invention is mounted. 1 is a schematic diagram of an electronic device showing a configuration in which a liquid crystal device of the present invention is mounted.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,51 ... Liquid crystal display panel 2,52 ... LCD controller 3,53 ... Power supply 4,54 ... Drive voltage formation part 5,55 ... Scanning electrode drive driver 6,56 ... Signal electrode drive driver 57 ... Scan control circuit 7 , 11 ... Register 8 ... Column direction control signal forming unit 9, 10, 13 ... AND gate 12 ... Row direction control signal forming unit FRM ... Scan start signal LP ... Data latch signal CLXI, CLX ... Data transfer clock CLYI, CLY ... Scanning signal transfer clock Data I, Data ... Display data CNT1 to CNT3, PDY, VCT ... Partial display control signal RV1 ... Variable resistance R, R1, R2, R3a, R3b, R4, R5 ... Resistance S2a, S2b ... Switch Q1 ... Bipolar transistors OP1 to OP4 ... Operational amplifier V0 V5 ... liquid crystal driving voltage

Claims (6)

In a liquid crystal display device having a control circuit configured by partially arranging a plurality of scanning electrodes and a plurality of signal electrodes, and partially controlling a display area of a display screen,
The control circuit includes:
The value corresponding to the start line and the value corresponding to the end line of the partial display part are separated so that the width and position of the partial display part to be partially displayed in the display area of the display screen can be varied. Two series of registers to be set;
A circuit block for forming a timing signal for controlling the partial display based on a set value in the two series of registers,
A scanning signal and a clock for transferring the scanning signal are output in a partial display period controlled by the timing signal, and in a period corresponding to a non-display portion from the first row of the display screen to the start row of the partial display portion A liquid crystal display device which operates the clock. The liquid crystal display device according to claim 1,
Means for fixing a voltage applied to the signal electrode in the non-display area to a voltage at which display is turned off, in which the display area and the non-display area are divided by the signal electrodes in a column direction;
A liquid crystal display device comprising: means for stopping transfer of display data corresponding to a non-display area. The liquid crystal display device according to claim 1,
The time in which the selection voltage is applied to the scan electrodes in the display area in the row direction in which the display area and the non-display area are divided by the scan electrodes, in the case of displaying in all lines and in the case of displaying in a part of the lines. A liquid crystal display device characterized by having the same. 4. The liquid crystal display device according to claim 3, wherein a pixel electrode is formed in a matrix in the display panel to form a pixel portion, a switching element is formed in the pixel electrode, and a row in a non-display area is formed. A liquid crystal display device comprising means for writing a voltage applied to a liquid crystal in a pixel portion to approximately 0V. An electronic apparatus comprising the liquid crystal display device according to claim 1. In a display device having a control circuit that is configured by crossing a plurality of scanning electrodes and a plurality of signal electrodes and partially controlling a display area of a display screen,
The control circuit includes:
The value corresponding to the start line and the value corresponding to the end line of the partial display unit are separated so that the width and position of the partial display unit partially displayed in the display area of the display screen can be varied. Two series of registers set by
A circuit block for forming a timing signal for controlling the partial display based on a set value in the two series of registers,
A scanning signal and a clock for transferring the scanning signal are output in a partial display period controlled by the timing signal, and in a period corresponding to a non-display portion from the first row of the display screen to the start row of the partial display portion A display device which operates the clock.

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