JP2004006875A - Manufacturing method of semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a simple manufacturing method of a high-performance J-FET element by forming the N-channel type J-FET element in a P-well region, and by so forming the respective regions of an NPN transistor as to use the P-well region in common with the J-FET element. <P>SOLUTION: A P-type well region 26 is formed in an N-type epitaxial layer 25. In the region 26, a gate contact region 29 of a J-FET element is formed concurrently with the formation of a base region 28 of an NPN transistor. Further, source/drain regions 31, 32 of the J-FET element are formed concurrently with the formation of an emitter region 30. Then, a mask layer 41 having an opening 40 is so formed on the region surrounded by the gate contact region 29 as to form an N-type channel region 33 and a top gate region 34 through the opening 40. Further, a P+ buried layer 23 is formed below the well region 26. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having a junction field effect transistor (hereinafter, referred to as a J-FET) formed in a BIP-IC.
[0002]
[Prior art]
J-FETs are used for condenser microphones and the like because they have higher input impedance than BIP type devices and higher electrostatic breakdown strength than MOS type FET devices. In addition, it has characteristics such as low low frequency noise and good high frequency characteristics for small signal amplification. In addition to the discrete type, a J-FET integrated on a BIP-IC has been developed.
[0003]
For example, Japanese Patent Application Laid-Open No. 58-197885 is an example thereof, and is shown in FIG. First, an N-type epitaxial layer 2 is laminated on a P-type semiconductor substrate 1, and an N + -type buried layer 3 is formed therebetween. A P + type isolation region 4 is formed to penetrate the semiconductor substrate 1 from the surface of the epitaxial layer 2 so as to surround the buried layer 3, thereby forming an island region 5.
[0004]
An N + type top gate region 6 is formed on the surface of the island region 5, and a P type channel region 7 is formed below the top gate region 6. A P-type source region 8 and a P-type drain region 9 are formed at both ends of the channel region, and a high-concentration gate contact region 10 is formed outside.
[0005]
Further, a source electrode, a drain electrode, and a gate electrode are laid through an insulating film to form a P-channel J-FET.
[0006]
Since a PN junction is formed in the gate region, the PN junction is reverse-biased, and the drain current is controlled according to the size of the depletion layer (for example, see Patent Document 1).
[0007]
[Patent Document 1]
JP-A-53-149773 (page 2-3, FIG. 2-3)
[0008]
[Problems to be solved by the invention]
However, the P-channel J-FET has a problem that the SN ratio is poor due to the problem of carrier (hole) mobility. Therefore, it has been desired to integrate an N-channel J-FET having a good SN ratio in an integrated circuit.
[0009]
[Means for Solving the Problems]
SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and is firstly solved by forming an N-channel J-FET in a well region of one conductivity type which is formed in an island region and serves as a bottom gate region. is there.
[0010]
Further, by forming the well region, an N-channel type J-FET can be formed, and furthermore, it can be built in a BIP-IC.
[0011]
Further, by providing a buried layer of one conductivity type between the well region and the buried layer of the opposite conductivity type provided below the well region, a portion where a depletion layer is generated due to a reverse bias is formed. In addition, it can be lowered from between the well region and the island region to between the buried layer of the opposite conductivity type and the buried layer of one conductivity type, so that punch-through of the depletion layer hardly occurs.
[0012]
Further, a simplified manufacturing process is established by forming the gate lead-out region of the J-FET by the base diffusion of the NPN transistor and forming the source / drain region by the emitter diffusion.
[0013]
Furthermore, by forming the channel region and the top gate region through the same mask, the process can be further simplified.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described.
[0015]
First step: A P-type semiconductor substrate 20 is prepared as shown in FIG. An oxide film is formed by thermally oxidizing the surface, and an opening is formed in the oxide film by a photoetching technique. Antimony (Sb) is diffused on the surface of the semiconductor substrate 20 exposed at the opening to form N + type buried layers 21 and 22. Subsequently, the oxide film is formed again, an opening is formed in the oxide film again by a photoetching method, and boron (B) is ion-implanted into the surface of the substrate 20 to form a P + type buried layer 23 and an isolation region 24. I do.
[0016]
Second step: Refer to FIG. 1B. Subsequently, after removing the oxide film mask for ion implantation, an N-type epitaxial layer 25 is formed by a vapor growth method. The film thickness is 5 to 12 μm, and the specific resistance ρ is 5 to 20 Ω · cm.
[0017]
After forming the epitaxial layer, a Si oxide film is formed on the surface of the epitaxial layer 25, and an opening is formed in the Si oxide film by a photo-etching technique. Boron (B, BF2) is ion-implanted through this opening to form a P-type well region 26. Then, the lower isolation region 24 is diffused above the epitaxial layer 25 by applying a heat treatment at 1100 ° C. for about 1 to 3 hours.
[0018]
Third step: Refer to FIG. 2A. Subsequently, a resist mask for ion implantation is formed on the Si oxide film grown on the surface of the epitaxial layer 25 by this heat treatment, and an opening corresponding to the upper isolation region 27 is formed. P-type impurities, here, boron are ion-implanted through the portion. Then, after removing the resist mask, 1100 ° C. for 1 to 3 hours until the upper and lower isolation regions 24 and 27 are combined and the P-type buried layer 23 and the P-type well region 26 are combined. Diffuse heat diffusion. By the isolation regions 24 and 27, the epitaxial layer 25 is junction-isolated into a first region where a junction FET (J-FET) is to be formed and a second region where an NPN transistor is to be formed.
[0019]
Fourth step: After removing the SiO2 film grown on the surface of the epitaxial layer 25 by the heat treatment shown in FIG. 2B, a SiO2 film having a thickness of about 500 ° is formed again. A mask for ion implantation is provided on the SiO2 film with a photoresist film, a portion corresponding to the base region 28 and the gate contact region 29 of the NPN transistor is opened, and boron as a base impurity is ion-implanted therein. After removing the resist mask, base diffusion is performed by heat treatment at 1100 ° C. for 1 to 2 hours. The base region 28 and the gate contact region 29 are diffusion regions shallower than the P-type well region 26, and the gate contact region 29 is arranged so as to cover the upper part of the PN junction between the P-type well region 26 and the N-type epitaxial layer 25. ing. That is, the gate contact region 29 annularly surrounds the peripheral portion of the well region 26. Then, the ion implantation mask is reattached, and portions corresponding to the emitter region 30, the source region 31, the drain region 32, and the contact region 35 to be formed are opened, and arsenic or phosphorus, which is an N-type impurity, is ionized here. inject.
[0020]
Fifth Step: See FIG. 3 (A) Further, a mask layer 41 having an opening 40 is formed on the portion of the Si oxide film corresponding to the channel region 33 by re-attaching the resist mask. The end of the opening 40 is located above the gate contact region 29 and exposes the surface of the well region 26 and the surface near the inner peripheral end of the annularly formed gate contact region 29. Then, arsenic or phosphorus, which is an N-type impurity forming the channel region 33, is ion-implanted through the opening of the mask layer 41 at 1 × 10 ¹² to 10 ¹³ atoms / cm ³ .
[0021]
Sixth step: B or BF ₂ , which is a P-type impurity for forming the top gate region 34 through the opening 40, is kept at 1 × 10 ¹³ to 10 ¹⁴ atoms / cm ^{3 while} leaving the mask layer 41 of FIG. 3B as it is. Ion implantation.
[0022]
Thereafter, the mask for ion implantation is removed, and the emitter is diffused at 1000 ° C. for 30 to 1 hour to thermally diffuse the emitter region 30, the source region 31, and the drain region 32, and simultaneously remove N-type impurities and P-type impurities. The channel region 33 and the top gate region 34 are formed by thermal diffusion. The channel region 33 and the top gate region 34 may be simultaneously formed by performing ion implantation of impurities and heat treatment after the emitter diffusion.
[0023]
Seventh step: Refer to FIG. 4 (A) Finally, a contact hole is opened in the SiO2 film on the surface of the epitaxial layer, and a drain electrode, a source electrode, a gate electrode, a VCC application electrode, an emitter electrode, a base electrode and a collector electrode are formed. I do.
[0024]
In the semiconductor integrated circuit manufactured by these steps, an NPN transistor and a J-FET element are formed in the first and second regions separated by the separation regions 24 and 27, respectively. The J-FET element is an element configured by using the well region 26 as a bottom gate. The gate contact region 29 reaches the well region 26 to apply a gate potential to the bottom gate and the top gate. The source / drain regions 31 and 32 are It is formed to a depth penetrating the channel region 33.
[0025]
FIG. 4B shows a plan view of the J-FET device. The gate contact region 29 has an annular shape, overlaps the top gate region 34, the channel region 33, and the peripheral portion of the well region 26, and has a higher impurity concentration than the well region 26, the channel region 33, and the top gate region 34. Designed. This prevents the PN junction in each region from being exposed on the surface of the epitaxial layer 25. A source region 31 and a drain region 32 are formed in a band shape in a portion surrounded by the annular gate contact region 29. A depletion layer formed at the PN junction between the well region 26 and the channel region 33 and a PN junction between the top gate region 34 and the channel region 33 are formed in accordance with the voltage applied through the gate contact region 29. And a channel current flowing between the source region 31 and the drain region 32. Further, a voltage (for example, power supply voltage Vcc) higher than the voltage applied to the gate electrode is applied to the epitaxial layer 25 around the well region 26 by the N + type contact region 35 or the gate layer is short-circuited with the gate contact region 29. The same potential as the gate, the ground potential (GND), or a floating state in which no potential is applied. The circuit is designed such that the gate potential is lower than the source potential. When a large amplitude signal having an amplitude of, for example, about 1 V or more is applied as a gate signal, a VCC potential is applied to prevent the operation of the parasitic PNP transistor including the well region 26, the epitaxial layer 25, and the isolation regions 24 and 27. Is good. Conversely, when a weak amplitude signal of, for example, about ± 0.01 V to 0.5 V is applied as a gate signal, a large potential difference between the epitaxial layer 25 and the well region 26 causes a PN junction when a reverse bias is applied. There is a possibility that the weak signal cannot be recognized due to the dark current. In this case, it is preferable to set the epitaxial layer 25 in a floating state in which no potential is applied.
[0026]
The first feature of the present invention resides in the well region 26. By forming the P-type well region 26, an N-type channel region 33 can be formed in this region, and an N-channel J-FET can be formed in the BIP-IC. Therefore, an N-channel type J-FET having a high SN ratio, which has conventionally been commercialized only as a discrete type, can be integrated into one chip, the ease of assembling a set or the like using the same is improved, and the cost merit increases.
[0027]
A second feature lies in the P + type buried layer 23. For example, the epitaxial layer 25 is VCC-biased by the contact region 35, and a reverse bias is applied to the bottom / top gate by applying a potential lower than VCC, but the depletion layer due to the reverse bias forms the epitaxial layer 25 and the well region 26. Spread between. If the P + type buried layer 23 is omitted, since the remaining film thickness of the well region 26 is small, the depletion layer reaches the channel region 33 and is likely to punch through. In the present invention, since the P + buried layer 23 is provided, a depletion layer is generated at the PN junction between the P + buried layer 23 and the N + type buried layer 21, which is farther from the channel region 33, and punches through. Since it becomes difficult, the withstand voltage characteristics between the channel region 33 and the bottom gate (well region) 26 can be improved.
[0028]
In addition, by forming the gate contact region 29 simultaneously with the formation of the base region 28 of the NPN transistor, it is possible to measure the sharing of the manufacturing process.
[0029]
Then, the gate contact region 29 is superimposed on the end of the PN junction formed by the well region 26, the channel region 33, and the top gate region 34, so that these are formed on the surface of the epitaxial layer 25 (the interface with the Si oxide film). Without exposing the PN junction, it is possible to prevent generation of a leak current due to contact with the Si oxide film. Separating the low impurity concentration channel region 33 from the oxide film interface by the top gate region 34 also has the effect of reducing leakage (low noise).
[0030]
Further, by simultaneously forming the source / drain regions 31 and 32 simultaneously with the formation of the emitter region 30, the manufacturing process can be further simplified.
[0031]
Further, by forming the channel region 33 and the top gate region 34 with the common mask layer 41, the manufacturing process can be further simplified.
[0032]
【The invention's effect】
According to the present invention, an N-channel J-FET having an excellent SN ratio is formed in a BIP-IC by forming an N-channel J-FET in a well region of one conductivity type serving as a bottom gate. It has the advantage that it can be built.
[0033]
Further, by providing a buried layer of one conductivity type below the well region, the formation portion of the depletion layer generated by the reverse bias can be made far from the channel region 33, and the punch-through of the depletion layer occurs. And the withstand voltage characteristics between the channel and the bottom gate can be improved.
[0034]
Further, by forming the gate contact region 29 and the source / drain regions 31 and 32 by forming each region of the NPN transistor, there is an advantage that the manufacturing process can be simplified.
[0035]
Further, by forming the channel region 33 and the top gate region 34 using the common mask layer 41, there is an advantage that the simplification of the manufacturing process can be further promoted.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view for explaining the present invention.
FIG. 2 is a cross-sectional view for explaining the present invention.
FIG. 3 is a cross-sectional view for explaining the present invention.
FIG. 4 is a sectional view (A) and a plan view (B) for explaining the present invention.
FIG. 5 is a cross-sectional view illustrating a conventional semiconductor integrated circuit device.

Claims (2)

Forming a reverse conductivity type epitaxial layer on a one conductivity type semiconductor substrate,
Forming a well region of one conductivity type in a first region of the epitaxial layer;
Forming a base region of one conductivity type in a second region of the epitaxial layer, and simultaneously forming the gate contact region on a surface of the well region;
Forming a reverse conductivity type emitter region on the surface of the base region, and simultaneously forming source / drain regions on the surface of the well region;
Forming, on the surface of the well region, a channel region of an opposite conductivity type whose end overlaps the gate contact region;
Forming a one-conductivity-type top gate region whose end overlaps the gate contact region on the surface of the well region. Forming a reverse conductivity type epitaxial layer on a one conductivity type semiconductor substrate,
Forming a well region of one conductivity type in a first region of the epitaxial layer;
Forming a base region of one conductivity type in a second region of the epitaxial layer, and simultaneously forming the gate contact region on a surface of the well region;
Forming a reverse conductivity type emitter region on the surface of the base region, and simultaneously forming source / drain regions on the surface of the well region;
Forming a mask layer having an opening on the surface of the well region such that an end thereof is located above the gate contact region;
Ion-implanting impurities of the opposite conductivity type using the mask layer as a mask, and forming a channel region whose end overlaps the gate contact region;
Ion-implanting one conductivity type impurity using the mask layer as a mask, and forming a top gate region whose end overlaps the gate contact region. .

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