JP2004000796A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a game machine surely storing data in cutoff of a power supply and preventing a loss from inflicting on a player. <P>SOLUTION: A first power supply monitor circuit introduces +30V power supply voltage and detects an occurrence of a power supply cutoff by monitoring the +30V power supply voltage. That is to say, when the +30V power supply voltage becomes +14V or less, it issues a voltage lowering signal for preventing the occurrence of the power supply cutoff. A prize ball control CPU 371 executes a prescribed power supply cutoff according to the voltage lowering signal. A second power supply monitor circuit monitors +5V power supply voltage, or the voltage lower than the voltage monitored by the first power supply monitor circuit and, when the voltage value becomes a prescribed value or less, issues a low-level voltage lowering signal. The voltage lowering signal from the second power supply monitor circuit is inputted in a reset terminal of the prize ball control CPU 371. The power supply monitor mode is the same as the power supply monitor mode in CPU 56. <P>COPYRIGHT: (C)2004,JPO

Description

The present invention relates to a gaming machine such as a pachinko gaming machine or a coin gaming machine in which a game is performed in accordance with an operation of a player, and more particularly to a gaming machine in which a game is performed in accordance with an operation of a player in a gaming area of a gaming board. .

As a gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium wins a winning area such as a winning opening provided in the game area, a predetermined number of prize balls are paid out to the player. There is something to be done. Further, a variable display unit whose display state can be changed is provided, and when a display result of the variable display unit becomes a predetermined specific display mode, a predetermined game value is provided to the player. There is.

{Circle around (5)} The fact that the display result of the variable display unit that displays a special symbol is a combination of a predetermined specific display mode is usually referred to as a “big hit”. In addition, the game value is a right to make the state of the variable prize ball device provided in the game area of the gaming machine advantageous for a player who is easy to win a hit ball, or to a state advantageous to the player. Or to generate.

す る と When a big hit occurs, for example, the big winning opening is opened a predetermined number of times, and the state shifts to a big hit game state where a hit ball is easy to win. Then, in each open period, when a predetermined number (for example, 10) of the winning prizes is won, the winning prize opening is closed. The number of opening of the special winning opening is fixed to a predetermined number (for example, 16 rounds). An opening time (for example, 29.5 seconds) is determined for each opening, and if the opening time elapses even if the number of winnings does not reach a predetermined number, the winning opening is closed. If the predetermined condition (for example, winning in the V zone provided in the special winning opening) is not satisfied at the time when the special winning opening is closed, the big hit gaming state ends.

Also, among the combinations of display modes other than the combination of “big hits”, at the stage where some of the display results of the plurality of variable display units have not yet been derived and displayed, the variable display in which the display results have already been derived and displayed. A state in which the display mode of the section satisfies the display condition that is a combination of the specific display modes is referred to as “reach”. If the display result of the identification information variably displayed on the variable display unit does not satisfy the condition of “reach”, the result is “out” and the variable display state ends. A player plays a game while enjoying how to generate a big hit.

{Circle around (4)} When a game ball wins in a winning opening provided on the game board, a predetermined number of payout balls are paid out. Since the progress of the game is controlled by the game control means mounted on the main board, the number of prize balls based on the winning is determined by the game control means and transmitted to the prize ball control board. Hereinafter, the game control means and other control means may be respectively referred to as game device control means.

As a prior art document describing a conventional gaming machine, for example, Patent Document 1 is cited. As a document published after the filing date of the present application, which is a divisional application (that is, the so-called parent application filing date of September 22, 1999), there is, for example, Japanese Patent No. 3354534.
Japanese Utility Model Publication No. 6-17458

As described above, the gaming machine is equipped with various gaming machine control means including the game control means. Generally, each game device control means is constituted by a microcomputer. That is, a program is stored in a ROM or the like, and data that temporarily occurs in control or data that changes as the control progresses is stored in the RAM. Then, when a power-off state occurs due to a power failure or the like in the gaming machine, data in the RAM is lost. Therefore, at the time of restoration from a power failure or the like, the player must return to the initial state (for example, the state when the game machine is first turned on at the game store on the day), which may be disadvantageous to the player. There is. For example, if a power failure occurs during a jackpot game and the gaming machine returns to the initial state, the player cannot enjoy the benefits based on the jackpot occurrence.

In order to avoid such a situation, when an unexpected power failure such as a power failure occurs, the necessary data is saved in the power backup RAM, and the data saved when the power is restored is restored. Should be restarted. However, if an error occurs in the data stored in the power backup RAM when the power is turned off, an erroneous state restoration process is performed when the power is restored. For example, when the power is restored, a game state different from the game state when the power is turned off is set, or the prize ball payout is restarted based on the prize ball number different from the original prize ball number. In such a case, an unexpected disadvantage is given to the player.

In view of the above, the present invention provides a gaming machine capable of performing a gaming state return control for returning a gaming state based on the contents backed up when the power is turned on. It is an object of the present invention to provide a gaming machine that can prevent a disadvantage from being brought to a player.

A gaming machine according to the present invention is provided with a variable display unit (for example, a variable display unit 9) in which a game is played using a game ball and a display state of which can be changed, and a display result of the variable display unit is specified in advance. Is a game machine that gives a predetermined game value (for example, payout of game balls) to a player when a display mode (for example, a jackpot symbol) is displayed, and a display on which a CPU for performing display control of a variable display unit is mounted. A control board (for example, the display control board 80), a special winning opening that is opened when the display result of the variable display unit has a specific display mode (for example, a special winning opening that is opened and closed by the opening and closing plate 20), and a game A starting winning opening (for example, starting winning opening 14) for changing the display state of the variable display section according to the winning of the ball, and a winning opening (for example, starting openings 19 and 24) for paying out the prize ball by winning the game ball. ), And a grand prize A count switch (for example, count switch 23) for detecting a winning of a game ball to the game, a starting port switch (for example, starting switch 17) for detecting a winning of a game ball to a starting winning port, and a game for a winning port. When a winning opening switch (for example, winning opening switch 19a, 24a) for detecting a winning of a ball, and a count switch, a start opening switch, and a winning opening switch detect a winning, a payout number instruction command for instructing the payout number of the winning ball is issued. A game control board (for example, main board 53) on which a CPU (for example, CPU 56) for outputting is mounted, a ball payout device (for example, ball payout device 97) for paying out prize balls, and ball payout in response to a payout number instruction command. A prize ball control board (for example, a prize ball control board 37) on which a prize ball control CPU (for example, a prize ball control CPU 371) for driving the device is mounted; A first power supply that monitors a first predetermined power supply voltage (for example, +30 V power supply voltage) used by the first power supply and detects that the first predetermined power supply voltage has dropped below a first predetermined value (for example, +14 V). The monitoring circuit monitors a second predetermined power supply voltage used by the gaming machine, and the second predetermined power supply voltage drops below a second predetermined value (for example, +8 V) lower than the first predetermined value. And a detection output of the first power supply monitoring circuit and the second power supply monitoring circuit is input to a prize ball control CPU, and the prize ball control CPU outputs a payout number instruction. A backup RAM area (for example, a backup RAM area shown in FIG. 24) in which the total number of payouts specified by the command is stored and the contents of which are retained even when the power to the gaming machine is turned off, is backed up. The payout number designated by the payout number instruction command is added to the total number of payout numbers stored in the RAM area, and the payout number stored in the backup RAM area every time one payout is completed by driving the ball payout apparatus. Is subtracted by one, and when the detection output from the first power supply monitoring circuit is input, the RAM access is disabled, and when the detection output from the second power supply monitoring circuit is input. When the system resets and the CPU mounted on the game control board starts the symbol change in the variable display section, the CPU outputs the change start command including information indicating the symbol change time to the CPU mounted on the display control board. Further, a symbol designating command indicating a determined symbol is output to the CPU mounted on the display control board, and when the symbol variation in the variable display section is determined, a variation stop command is issued. And outputs to the CPU mounted on the display control board.

The first power supply monitoring circuit and the second power supply monitoring circuit may be configured to monitor the same power supply voltage.

The second predetermined power supply voltage monitored by the second power supply monitoring circuit is a driving power supply voltage of the prize ball control CPU, and the second power supply monitoring circuit determines that the driving power supply voltage is the prize ball control CPU. (For example, a threshold value lower than the normal voltage but a voltage at which the prize ball control CPU 371 can operate for a while) The level may be set, and when the voltage drops to the threshold level, it is detected that the power supply voltage has dropped).

The detection output of the first power supply monitoring circuit is input to the input port of the prize ball control CPU, and the prize ball control CPU is configured to execute the setting of the RAM access prohibition state by monitoring the input port. You may.

According to the first aspect of the invention, it is possible to reliably store data when the power is turned off, and to prevent a disadvantage to the player.

According to the second aspect of the present invention, the difference between the timing at which the first power supply monitoring circuit outputs the voltage drop signal and the timing at which the second power supply monitoring circuit outputs the voltage drop signal can be reliably set to a desired value. it can.

According to the third aspect of the present invention, the execution time of the RAM access prohibition setting has a sufficient time, and the RAM access prohibition setting is reliably executed.

According to the fourth aspect of the invention, the setting of the RAM access prohibition state can be surely executed without using the interrupt.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
First, the overall configuration of a pachinko gaming machine, which is an example of a gaming machine, will be described. 1 is a front view of the pachinko gaming machine 1 as viewed from the front, FIG. 2 is an overall rear view showing the internal structure of the pachinko gaming machine 1, and FIG. 3 is a rear view of the gaming board of the pachinko gaming machine 1 as viewed from the back. Here, a pachinko gaming machine is shown as an example of a gaming machine, but the present invention is not limited to a pachinko gaming machine, and may be, for example, a coin gaming machine. Further, the present invention can be applied to a game machine or a slot machine of an image type.

パ As shown in FIG. 1, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2 is a hit ball supply tray 3. A surplus ball tray 4 for storing prize balls overflowing from the hit ball supply tray 3 and a hit ball operation handle (operation knob) 5 for firing a hit ball are provided below the hit ball supply tray 3. A game board 6 is detachably mounted behind the glass door frame 2. A game area 7 is provided on the front of the game board 6.

A variable display device 8 including a variable display unit 9 for variably displaying a plurality of types of symbols and a variable display 10 using 7-segment LEDs is provided near the center of the game area 7. In this embodiment, the variable display section 9 has three symbol display areas of “left”, “middle”, and “right”. On the side of the variable display device 8, a passing gate 11 for guiding a hit ball is provided. The hit ball that has passed through the passing gate 11 is guided to the starting winning opening 14 via the ball exit 13. In a passage between the passage gate 11 and the ball outlet 13, there is a gate switch 12 for detecting a hit ball that has passed through the passage gate 11. The winning ball that has entered the starting winning port 14 is guided to the back of the game board 6 and detected by the starting port switch 17. In addition, a variable winning ball device 15 that performs opening and closing operations is provided below the starting winning port 14. The variable winning ball device 15 is opened by the solenoid 16.

An opening / closing plate 20 which is opened by the solenoid 21 in a specific game state (big hit state) is provided below the variable winning ball device 15. In this embodiment, the opening and closing plate 20 serves as a means for opening and closing the special winning opening. A winning ball that has entered one (V zone) of the winning balls guided from the opening / closing plate 20 to the back of the game board 6 is detected by the V count switch 22. The winning ball from the opening / closing plate 20 is detected by the count switch 23. At the lower part of the variable display device 8, there is provided a starting prize storage display 18 having four display portions for displaying the number of winning balls entering the starting prize port 14. In this example, the start winning prize storage display 18 increases the number of lit display units by one each time there is a starting prize, with the upper limit being four. Then, each time the variable display of the variable display unit 9 is started, the number of the lit display units is reduced by one.

The game board 6 is provided with a plurality of winning ports 19 and 24, and winning of the gaming balls to the winning ports 19 and 24 is detected by the winning port switches 19a and 24a. Decorative lamps 25 that blink during the game are provided around the left and right sides of the game area 7, and the lower part has an out opening 26 for absorbing a hit ball that has not won. In addition, two speakers 27 that emit sound effects are provided at upper left and right sides of the game area 7. A game effect LED 28a and game effect lamps 28b and 28c are provided on the outer periphery of the game area 7.

In this example, a prize ball lamp 51 that is lit when a prize ball is paid out is provided near one of the speakers 27, and a ball out lamp 52 that is lit when a supply ball runs out is near the other speaker 27. Is provided. Further, FIG. 1 also shows a card unit 50 that is installed adjacent to the pachinko gaming table 1 and enables lending of balls by inserting a prepaid card.

The card unit 50 has a usable indicator lamp 151 for indicating whether or not the card is in a usable state. If there is a fraction (a number less than 100 yen) in the remaining amount information recorded in the card, the fraction is displayed on the hitting plate. 3, a fraction display switch 152 for displaying on a frequency display LED provided in the vicinity of 3, a connection board direction indicator 153 indicating which side of the pachinko gaming machine 1 the card unit 50 corresponds to, and the inside of the card unit 50. A card insertion indicator 154 indicating that a card has been inserted into the card, a card insertion slot 155 into which a card as a recording medium is inserted, and a mechanism of a card reader / writer provided on the back of the card insertion slot 155 are checked. A card unit lock 156 is provided for releasing the card unit 50 in some cases.

打 The hit ball fired from the hit ball launching device enters the game area 7 through the hitting ball rail, and then descends from the game area 7. When a hit ball is detected by the gate switch 12 through the passing gate 11, the display number of the variable display 10 is changed continuously. When a hit ball enters the start winning opening 14 and is detected by the start opening switch 17, the symbols in the variable display section 9 start rotating if the symbols can be changed. If it is not possible to start changing the symbol, the start winning memory is increased by one.

(4) The rotation of the image in the variable display section 9 stops when a certain time has elapsed. If the combination of images at the time of stoppage is a combination of big hit symbols, the game shifts to a big hit game state. That is, the opening / closing plate 20 is opened until a predetermined time elapses or until a predetermined number (for example, 10) of hit balls is won. Then, when a hit ball wins in the specific winning area while the opening and closing plate 20 is opened and is detected by the V count switch 22, a continuation right is generated and the opening and closing plate 20 is opened again. Generation of the continuation right is permitted a predetermined number of times (for example, 15 rounds).

場合 If the combination of images in the variable display unit 9 at the time of stop is a combination of big hit symbols with probability fluctuation, the probability of the next big hit becomes high. In other words, a high probability state, which is more advantageous for the player, is obtained. When the stop symbol on the variable display 10 is a predetermined symbol (hit symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the high probability state, the probability that the stop symbol on the variable display 10 hits the symbol is increased, and the opening time and the number of times the variable winning ball device 15 is opened are increased.

Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG.
On the back of the variable display device 8, as shown in FIG. 2, a prize ball tank 38 is provided above the mechanism plate 36, and when the pachinko gaming machine 1 is installed on the gaming machine installation island, a prize ball is provided from above. The prize ball tank 38 is supplied. The prize ball in the prize ball tank 38 reaches the ball payout device through the guiding gutter 39.

On the mechanism plate 36, a variable display control unit 29 for controlling the variable display unit 9 via the relay board 30, a game control board (main board) 31, which is covered with a board case 32 and on which a game control microcomputer and the like are mounted, A relay board 33 for relaying a signal between the variable display control unit 29 and the game control board 31 and a prize ball control board 37 on which a microcomputer for controlling a prize ball for controlling payout of prize balls are installed. Have been. Further, below the mechanism plate 36, a hitting ball firing device 34 for shooting a hitting ball into the game area 7 using the rotational force of the motor, a game effect lamp / LEDs 28a, 28b, 28c, a prize ball lamp 51, and a ball cut lamp A lamp control board 35 for sending a signal to 52 is provided.

FIG. 3 is a rear view of the gaming board of the pachinko gaming machine 1 as viewed from the rear. As shown in FIG. 3, the ball that has passed through the guiding gutter 39 passes through the ball cutout detectors 187a and 187b and reaches the ball dispensing device 97 via the ball supply gutters 186a and 186b. The prize ball paid out from the ball payout device 97 is supplied to the hitting ball supply tray 3 provided on the front surface of the pachinko gaming machine 1 through the communication port 45. On the side of the communication port 45, a surplus ball passage 46 communicating with the surplus ball tray 4 provided on the front face of the pachinko gaming machine 1 is formed. A large number of prize balls based on the prize are paid out, and the hitting ball supply tray 3 becomes full. Finally, after the prize balls reach the communication port 45, further prize balls are paid out. It is led to the ball tray 4. When the prize ball is further paid out, the sensing lever 47 presses the full tank switch 48 and the full tank switch 48 is turned on. In this state, the rotation of the stepping motor in the ball payout device 97 stops, the operation of the ball payout device 97 stops, and the driving of the hit ball firing device 34 also stops as necessary. In this embodiment, a ball payout device 97 that pays out game balls by rotating a stepping motor is illustrated as a ball payout device 97 that pays out game balls by driving an electric drive source. A ball payout device having a structure in which a ball is sent out may be used, or a ball payout device having a structure in which a stopper is removed by driving an electric drive source to pay out the ball by its own weight may be used.

Signals from the winning opening switches 19a and 24a, the starting opening switch 17 and the V count switch 22 are sent to the main board 31 in order to perform the prize ball payout control. When the starting port switch 17 is turned on, the CPU 56 of the main board 31 knows that a winning corresponding to the payout of six winning balls has occurred. Further, when the count switch 23 is turned on, it is known that a winning corresponding to the payout of 15 prize balls has occurred. Then, when the winning opening switch is turned on, it is known that a winning corresponding to the payout of 10 winning balls has occurred. In this embodiment, for example, a game ball that has won the winning opening 24 is detected by a winning opening switch 24 a provided in a winning ball flow path from the winning opening 24, and the game ball that has won the winning opening 19 is detected. Is detected by a winning opening switch 19a provided in a winning ball flow path from the winning opening 19.

FIG. 4 is a block diagram showing an example of a circuit configuration of the main board 31. FIG. 4 also shows the prize ball control board 37, the lamp control board 35, the sound control board 70, the emission control board 91, and the display control board 80. On the main board 31, a basic circuit 53 for controlling the pachinko gaming machine 1 in accordance with a program, and signals from the gate switch 12, the starting port switch 17, the V count switch 22, the count switch 23, and the winning port switches 19a and 24a are provided. 53, a solenoid circuit 59 that drives the solenoid 16 that opens and closes the variable winning ball device 15 and the solenoid 21 that opens and closes the opening and closing plate 20 in accordance with commands from the basic circuit 53, and turns on and off the start storage display 18. A lamp / LED circuit 60 that extinguishes the lights and drives the variable indicator 10 and the decorative lamps 25 by 7-segment LEDs is mounted.

Also, according to the data provided from the basic circuit 53, jackpot information indicating occurrence of a jackpot, effective start information indicating the number of start winning balls used for starting image display of the variable display section 9, and indicating that a probability change has occurred. It includes an information output circuit 64 that outputs probability change information and the like to a host computer such as a hall management computer.

The basic circuit 53 includes a ROM 54 for storing a game control program and the like, a RAM 55 used as a work memory, a CPU 56 for performing a control operation in accordance with the control program, and an I / O port unit 57. In this embodiment, the ROM 54 and the RAM 55 are built in the CPU 56. That is, the CPU 56 is a one-chip microcomputer. The one-chip microcomputer only needs to include at least the RAM 55, and the ROM 54 and the I / O port unit 57 may be externally or internally provided. The I / O port unit 57 is a terminal capable of inputting and outputting information in the microcomputer.

Further, the main board 31 has an initial reset circuit 65 for resetting the basic circuit 53 when the power is turned on, and decodes an address signal given from the basic circuit 53 to output any one of the I / O port units 57. An address decode circuit 67 for outputting a signal for selecting an / O port is provided.
There is also switch information input from the ball dispensing device 97 to the main board 31, but these are omitted in FIG.

The hit ball launching device that hits and launches a game ball is driven by a drive motor 94 controlled by a circuit on a launch control board 91. Then, the driving force of the driving motor 94 is adjusted according to the operation amount of the operation knob 5. That is, the circuit on the launch control board 91 is controlled so that the hit ball is launched at a speed corresponding to the operation amount of the operation knob 5.

FIG. 5 is a block diagram showing a configuration example around the CPU 56 for power supply monitoring and power supply backup. As shown in FIG. 5, the power supply monitoring IC 902 detects the occurrence of power interruption by introducing a + 30V power supply voltage and monitoring the + 30V power supply voltage. Specifically, when the + 30V power supply voltage becomes equal to or lower than a predetermined value, a voltage drop signal is output on the assumption that power is cut off. In this embodiment, the predetermined value is + 16V. Note that the +30 V power supply voltage is a voltage immediately after conversion from AC to DC. A voltage drop signal from the power supply monitoring IC 902 is input to an input port 570 connected to the CPU 56. Therefore, the CPU 56 can confirm the power-off state via the input port 570.

Note that the input port 570 is provided with an output signal of a game ball detecting means (a starting port switch 17, a count switch 23, a winning port switch 19a, 24a and the like in this example) for detecting a game ball provided in the gaming machine. Is input to a vacant bit of the input port. That is, the voltage drop signal is input to the input port 570 as detection input means for inputting detection information of the game ball detection means.

The voltage drop signal from the power supply monitoring IC 902 as the power supply monitoring means may be connected to the CPU 56 so as to be able to transmit information. The input port 570 may be a built-in port of the CPU 56 or an external port. It may be. The input port 570 is also connected to a switch input signal indicating the state of the initialization operation switch provided on the power supply board.

The predetermined value for the power supply monitoring IC 902 to detect the power-off is lower than the normal voltage, but is a voltage at which the CPU 56 can operate for a while. Further, since the power supply monitoring IC 902 is configured to monitor a voltage higher than the voltage for driving the CPU 56 (+5 V in this example) and immediately after the voltage is converted from AC to DC, the CPU 56 The monitoring range can be extended for the required voltage. Therefore, more precise monitoring can be performed. Further, when +30 V is used as the monitoring voltage, since the voltage supplied to the various switches of the gaming machine is +12 V, it can be expected to prevent erroneous switch-on detection at the moment of a power interruption. That is, if the voltage of the +30 V power supply is monitored, it is possible to detect a decrease in the voltage of +12 V at a stage before +12 V generated after the generation of +30 V starts to fall. Therefore, when the voltage of the + 12V power supply decreases, the switch output comes to the on state. However, if the + 30V power supply voltage that drops earlier than the + 12V is monitored and the power cutoff is recognized, the power supply is turned on before the switch output turns on. It is possible to enter a state of waiting for restoration and to enter a state in which the switch output is not detected.

{Circle around (2)} On the main board 31, a second power supply monitoring circuit 903 is mounted in addition to the first power supply monitoring circuit by the power supply monitoring IC 902. In this example, in the second power supply monitoring circuit 903, the power supply monitoring IC 904 monitors a + 5V power supply voltage that is lower than the voltage monitored by the first power supply monitoring circuit, and when the voltage value falls below a predetermined value. Generates a low-level brownout signal. Note that the + 5V power supply voltage is a drive power supply voltage for the gaming machine control microcomputer (such as the CPU 56).

(4) The voltage drop signal from the second power supply monitoring circuit 903 is logically ORed with the initial reset signal from the initial reset circuit 65 and then input to the reset terminal of the CPU 56. Therefore, when the initial reset signal from the initial reset circuit 65 is at a low level, or when the voltage drop signal from the second power supply monitoring circuit 903 is at a low level, the CPU 56 is in the reset state ( Non-operating state).

When the power supply voltage decreases, the power supply monitoring IC 904 generates a low-level voltage drop signal such that the timing at which the power supply monitoring IC 904 generates a voltage drop signal is delayed with respect to the timing at which the power supply monitoring IC 902 generates the voltage drop signal. A threshold level (voltage level at which a voltage drop signal is generated) is set. For example, the threshold is 4.25V. 4.25 V is lower than the normal voltage, but is a voltage at which the CPU 56 can operate for a while.

The reset IC 651 of the initial reset circuit 65 sets the output signal to a high level when the power of the gaming machine is turned on and the voltage of the + 5V power supply rises when the + 5V power supply voltage exceeds a predetermined value. That is, the initial reset signal is turned off. Although the power supply monitoring ICs 902 and 904 monitor different power supply voltages here, the same power supply voltage may be monitored. For example, both may monitor the + 30V power supply voltage. Then, for example, one detection voltage (a voltage at which a voltage drop signal is output) is set to +16 V, and the other detection voltage is set to +8 V. In such a configuration, since the same voltage is monitored, the difference between the timing at which the first voltage monitoring means outputs the voltage drop signal and the timing at which the second voltage monitoring means outputs the voltage drop signal is obtained. The predetermined period can be reliably set to a desired value.

{Circle around (1)} Further, one power supply monitoring IC set to output each voltage drop signal when each monitoring voltage drops to each predetermined value may be used. For example, one power supply monitoring IC may monitor both + 16V and + 8V. In that case, the first power supply monitoring means and the second power supply monitoring means can be realized by one power supply monitoring IC. Further, in this embodiment, the power supply monitoring means is provided on the main board 31, but may be mounted on the power supply board.

While power is not being supplied from the + 5V power supply, at least a portion of the RAM is backed up by a backup power supply supplied from a power supply board, and the contents are preserved even when the power to the gaming machine is cut off. Then, when the + 5V power supply is restored, a reset signal is issued from the initial reset circuit 65, so that the CPU 56 returns to the normal operation state. At that time, since necessary data has been backed up, it is possible to return to the gaming state at the time of the occurrence of the power failure when recovery from a power failure or the like.

FIG. 6 is a block diagram showing a configuration example of the power supply board 910. The power supply board 910 is installed independently of the gaming machine control boards such as the main board 31, the display control board 80, the sound control board 70, the lamp control board 35, and the prize ball control board 37, and is provided for each gaming machine in the gaming machine. Generates voltages used by control boards and mechanical components. In this example, AC24V, DC + 30V, DC + 21V, DC + 12V and DC + 5V are generated. Further, the capacitor 916 serving as a backup power supply is charged from DC + 5V, that is, a power supply line for driving an IC or the like on each substrate.

(5) The transformer 911 converts an AC voltage from an AC power supply to 24V. The AC 24 V voltage is output to connector 915. The rectifier circuit 912 generates a DC voltage of +30 V from AC 24 V and outputs the DC voltage to the DC-DC converter 913 and the connector 915. The DC-DC converter 913 generates + 21V, + 12V, and + 5V and outputs the generated voltage to the connector 915. The connector 915 is connected to, for example, a relay board, and the relay board supplies power of a voltage necessary for each game machine control board and mechanical components. Note that a power switch 918 for stopping and starting power supply to the gaming machine is provided on the input side of the transformer 911.

＋ The + 5V line from DC-DC converter 913 branches to form a backup + 5V line. A large-capacity capacitor 916 is connected between the backup + 5V line and the ground level. The capacitor 916 serves as a backup power supply for a backup RAM (power-backed-up RAM, that is, a variable data storage unit that can be in a storage content holding state) of the gaming machine control board when power supply to the gaming machine is cut off. Further, a diode 917 for preventing backflow is inserted between the + 5V line and the backup + 5V line.

Note that a battery that can be charged from a + 5V power supply may be used as the backup power supply. In the case of using a battery, a rechargeable battery is used which runs out of capacity when power is not supplied from a + 5V power supply for a predetermined time.

電源 Further, an initialization operation switch 919 is mounted on the power supply board 910. A signal indicating the state of the initialization operation switch is input to the main board 31, and its role will be described later in detail. In this embodiment, the power switch 918 and the initialization operation switch 919 are mounted on the power board 910 which is installed independently of the other control boards. Even if the power supply board 910 is used as it is for the board, a power failure process using a power switch 918 and an initialization operation switch 919 described later can be executed on the game board after replacement.

Next, the operation of the gaming machine will be described.
FIG. 7 is a flowchart illustrating a main process executed by the CPU 56 on the main board 31. When the power to the gaming machine is turned on, in the main process, the CPU 56 first checks whether or not it has been time to recover from a power failure (step S1). Whether or not recovery from a power failure has occurred is confirmed, for example, by a power-off flag set in the backup RAM area when the power is turned off. That is, at the time of recovery from a power failure, while the predetermined data is stored in the backup RAM area, otherwise, the power-off flag is set based on the fact that the contents of the RAM are undefined. It can be confirmed whether or not the power was restored from the power failure.

If it is time to recover from a power failure, the CPU 56 checks the state of the initialization operation switch 919 via the input port 570 (step S3). In this embodiment, when the initialization operation switch 919 is turned on, the output goes low (see FIG. 6). If the initialization operation switch 919 is on, a normal initialization process is performed (step S2). If the initialization operation switch 919 is in the off state, the CPU 56 executes a power failure recovery process described later (step S4). Note that the initialization operation switch 919 may be set to an on state before the power switch 918 is turned on, or may be pressed simultaneously with the power switch 918. Further, it may be turned on after the power switch 918 is pressed. Considering that the power switch 918 is turned on after being pressed, a delay time may be provided before the determination in step S3.

If it is not time to recover from a power failure, the CPU 56 executes a normal initialization process (steps S1 and S2). Thereafter, in the main process, the process shifts to a loop process in which monitoring of the timer interrupt flag (step S6) is confirmed. In the loop, a display random number update process (step S5) is also executed.

In a normal initialization process, as shown in FIG. 8, after a register and RAM clearing process (step S2a) and a necessary initial value setting process (step S2b) are performed, a timer is set periodically every 2 ms. The timer register provided in the CPU 56 is initialized (setting that the timeout is 2 ms and the timer operates repeatedly) so that the timer is operated (step S2c). That is, in step S2c, a process of activating a timer interrupt and a process of setting a timer interrupt interval are executed.

Therefore, in this embodiment, the internal timer of the CPU 56 is set to repeatedly generate a timer interrupt. In this embodiment, the repetition period is set to 2 ms. Then, as shown in FIG. 9, when a timer interrupt occurs, the CPU 56 sets a timer interrupt flag (step S11).

When the CPU 56 detects that the timer interrupt flag has been set in step S6, the CPU 56 resets the timer interrupt flag (step S7) and monitors for abnormal voltage (step S8). The voltage abnormality is monitored by monitoring a voltage drop signal from the power supply monitoring IC 902 via the input port 570. When detecting an abnormal voltage, that is, a decrease in the power supply voltage, the CPU 56 executes a power failure generation process (power-off process: step S9) described later.

If no abnormal voltage is detected, the CPU 56 executes a game control process (step S9). According to the above control, in this embodiment, the game control process is started every 2 ms.

FIG. 10 is a flowchart showing a game control process. In the game control process, the CPU 56 first performs a process of setting a display control command transmitted to the display control board 80 in a predetermined area of the RAM 55 (display control data setting process: step S21), and then executes the display control command. Output processing is performed (display control data output processing: step S22).

Next, a process of outputting the contents of the storage area for various output data to each output port is performed (data output process: step S23). Further, an output data setting process for setting output data such as big hit information, start information, and probability variation information output to the hall management computer in the storage area is performed (step S24). Further, various abnormality diagnosis processes are performed by a self-diagnosis function provided inside the pachinko gaming machine 1, and an alarm is issued if necessary according to the result (error process: step S25).

Next, a process of updating each counter indicating a random number for determination such as a random number for big hit determination used in game control is performed (step S26).

Further, the CPU 56 performs a special symbol process (step S27). In the special symbol process control, a corresponding process is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to a gaming state. Then, the value of the special symbol process flag is updated during each processing according to the gaming state. Further, a normal symbol process is performed (step S28). In the normal symbol process process, a corresponding process is selected and executed according to a normal symbol process flag for controlling the variable display 10 using the 7-segment LED in a predetermined order. Then, the value of the normal symbol process flag is updated during each processing according to the gaming state.

Further, the CPU 56 inputs the states of the gate sensor 12, the starting port sensor 17, the count sensor 23, and the winning port switches 19a and 24a via the switch circuit 58, and determines whether or not each of the winning ports and the prize apparatus has won. (Switch processing: step S29). The CPU 56 further performs a process of updating a display random number such as a random number that determines the type of stop symbol (step S30).

{Circle around (5)} The CPU 56 performs signal processing with the award ball control board 37 (step S31). That is, when a predetermined condition is satisfied, a prize ball control command is output to the prize ball control board 37. The prize ball control CPU mounted on the prize ball control board 37 drives the ball payout device 97 according to the prize ball control command.

As described above, the main process includes the process of determining whether or not to shift to the game control process, and the internal timer of the CPU 56 performs the timer control process based on the timer interrupt that is periodically generated. Since the flag for determining whether or not to shift is set, all of the game control processing is reliably executed. That is, until all of the game control processing is executed, it is not determined whether or not to shift to the next game control processing, so that it is guaranteed that all the processing during the game control processing is completed. ing.

In the conventional general game control processing, the external game is forcibly returned to the initial state by an external interrupt that occurs periodically. Explaining with reference to the example shown in FIG. 10, for example, even during the process of step S31, the process is forcibly returned to the process of step S21. In other words, there is a possibility that the next game control process will be started before all the processes in the game control process are completed.

In this embodiment, the determination of the power supply voltage drop (step S8) is performed before executing the game control process started by the timer interrupt generated periodically, but the game control process is executed. It may be done later. At any time, the power supply voltage drop is determined at a time when the game control means is not performing information input / output with another game apparatus control means or a game apparatus. The power failure occurrence process (step S9) is not performed when the power failure is being performed. That is, information input / output is not interrupted halfway. For example, a control command sent to another board is completely sent.

Here, the game control process executed by the CPU 56 of the main board 31 is executed in accordance with the flag set in the timer interrupt process based on the timer interrupt generated by the internal timer of the CPU 56 periodically. A hardware circuit that periodically generates a signal (for example, every 2 ms) is provided, a signal from the circuit is introduced to an external interrupt terminal of the CPU 56, and it is determined whether or not to shift to the game control process based on the interrupt signal. May be set. Even in such a configuration, the flag is not determined until all the game control processes are executed, so that execution of all the processes in the game control process is guaranteed to be completed.

FIG. 11 is a flowchart showing an example of the power failure occurrence processing (step S9). In the power failure occurrence processing, the CPU 56 first sets the interruption to be prohibited (step S41). In the power failure generation process, a checksum generation process is performed to ensure that the contents of the RAM are preserved. If another interrupt process is performed during that process, the voltage may drop to a level at which the CPU cannot operate before the checksum generation process is completed. The setting is made so that no interrupt occurs.

Next, the CPU 56 turns off all the output ports (step S42). Then, if necessary, the contents of each register are stored in the backup RAM area (step S43). Further, a power-off flag is set (step S44). Further, an appropriate initial value is set in the backup check data area of the backup RAM area (step S45), and exclusive OR is sequentially performed on the initial value and the data of the backup RAM area (step S46) to obtain a final operation value. Is set in the backup parity data area (step S47). Thereafter, a loop is made with the RAM access prohibited (step S48). When the power supply voltage decreases, the levels of various signal lines may become unstable and the contents of the RAM may be corrupted. However, if the RAM access is prohibited in this manner, the data in the backup RAM may be corrupted. There is no.

The power-off flag set before the RAM access is prohibited is used to determine whether or not to recover from a power failure when the power is turned on, as described above. Further, the processing of steps S41 to S48 is completed before the second power supply monitoring unit generates the voltage drop signal. In other words, the detection voltages of the first voltage monitoring means and the second voltage monitoring means are set such that the detection is completed before the second power supply monitoring means generates the voltage drop signal.

FIG. 12 is a flowchart showing an example of the power outage restoration process (step S4). In the power failure recovery processing, the CPU 56 first performs data check (parity check in this example) of the backup RAM area (step S51). If the power is restored after an unexpected power failure, the data in the backup RAM area should have been saved, and the check result becomes normal. If the check result is not normal, the internal state cannot be returned to the state at the time of power failure, so that the same initialization processing as the initialization processing (step S2) executed at the time of power-on without power recovery is performed. (Steps S52 and S54).

If the check result is normal, the CPU 56 performs a game state restoring process for returning the internal state to the state at the time of power-off (step S53), and clears the power-off flag (step S55).

In this case, in step S1, it is confirmed whether or not the power is restored from the power failure. If the power is restored from the power failure, the parity check is performed. However, first, the parity check is performed. It is determined that the recovery is not the recovery from the power failure, the initialization process of step S2 is executed, and if the check result is normal, the game state return process may be executed. That is, it may be determined whether or not the power is restored from the power failure based on the result of the parity check.

FIG. 13 is an explanatory diagram for explaining a backup parity data creating method. However, in the example shown in FIG. 13, the size of the data in the backup data RAM area is 3 bytes for simplicity. In the power failure generation process based on the power supply voltage drop, as shown in FIG. 13A, initial data (00H in this example) is set in the backup check data area. Next, an exclusive OR of “00H” and “F0H” is obtained, and an exclusive OR of the result and “16H” is obtained. Further, an exclusive OR of the result and “DFH” is obtained. Then, the result (in this example, “39H”) is set in the backup parity data area.

(7) When the power is turned on again, the parity diagnosis is performed in the power failure recovery process. FIG. 13B is an explanatory diagram showing an example of the parity diagnosis. If all the data in the backup area is stored as it is, the data as shown in FIG. 13A is set in the backup area when the power is turned on again.

In the processing in step S51, the CPU 56 sequentially exclusive-ORs each data in the backup data area with the data (39H in this example) set in the backup parity data area of the backup RAM area as initial data. Perform processing. If all the data in the backup area is stored as it is, the final operation result matches “00H”, that is, the data set in the backup check data area. If a bit error has occurred in the data in the backup RAM area, the final calculation result does not become “00H”.

Therefore, the CPU 56 compares the final operation result with the data set in the backup check data area, and if they match, determines that the parity diagnosis is normal. If they do not match, it is determined that the parity diagnosis is abnormal.

In this embodiment, check data (parity data in this example) is generated in the power failure generation process, but the check data is not generated, and only the power-off flag is set. Good.

As described above, in this embodiment, the game control means is provided with the variable data storage means (backup RAM in this example) which is backed up for a predetermined period even if the power of the gaming machine is turned off. At times, the CPU 56 (specifically, a program executed by the CPU 56) is configured to perform a game state restoration process (step S53) for restoring the game state based on the backup data if the variable data storage unit is in the backup state. You.

At this time, if the initialization operation switch 919 is in the ON state, the game state restoration processing is not executed, and the normal initialization processing (step S2) is executed. Therefore, the game clerk operates the initialization operation switch 919 at the time of turning on the power of the gaming machine based on the turning on of the power switch 918 or the like, thereby executing the game state restoration processing based on the backup data stored in the variable data storage means. Can be selected. Therefore, there is provided a gaming machine which can prevent a disadvantage from being brought to a player even if a power failure occurs, and can also improve convenience in operating a gaming machine in a gaming arcade.

Note that, when the power is turned on, the initialization process is performed when the backup data is not stored in the variable data storage unit, and the initialization operation switch 919 is turned off even if the backup data is stored in the variable data storage unit. The initialization process executed in a certain case is shared with the program (see step S2 in FIG. 7). Therefore, even if control for improving the operational convenience in the game arcade is added, the program capacity does not increase so much.

Hereinafter, the game state restoration processing will be described.
First, in this embodiment, a display control command, a sound control command, and a lamp control command that the CPU 56 of the main board 31 sends to the display control board 80, the sound control board 70, and the lamp control board 35 will be described. Each control command is determined to be sent in accordance with the progress of the game in the special symbol process process (step S28) in the game control process shown in FIG. 10, and specific data is displayed in the display control data setting process (step S21). Is set, and is transmitted by being output from the output port in the display control data output process (step S22).

FIG. 14A is an explanatory diagram showing an example of the transmission timing of each control command relating to the symbol variation on the variable display unit 9. In this embodiment, the CPU 56 of the main board 31 sends a change start command to each of the display control board 80, the sound control board 70, and the lamp control board 35 when starting the symbol change. To the display control board 80, a symbol designating command indicating a fixed symbol of the middle left and right symbols is further transmitted.

{Circle around (4)} When a symbol change is determined, a change stop command is sent to each of the display control board 80, the sound control board 70, and the lamp control board 35. Each CPU mounted on the display control board 80, the sound control board 70, and the lamp control board 35 performs display control, sound generation control, and lamp lighting control according to the variation mode specified by the variation start command. The change start command includes information indicating the change time.

FIG. 14B is an explanatory diagram showing an example of the transmission timing of each control command related to the big hit game executed when the display result of the variable display section 9 is a predetermined big hit symbol. In this embodiment, the CPU 56 of the main board 31 sends a jackpot start command to each of the display control board 80, the sound control board 70, and the lamp control board 35 at the start of the big hit game. After a lapse of a predetermined time, a one-round (1R) designation command is transmitted. When each CPU mounted on the display control board 80, the sound control board 70, and the lamp control board 35 receives the big hit start command, it performs display control, sound generation control, and lamp lighting control at the start of the big hit. When a one-round designation command is received, display control, sound generation control, and lamp lighting control during a big hit are performed. However, the CPU of the display control board 80 performs the first round of display.

After that, the CPU 56 of the main board 31 sequentially sends commands indicating each round to the display control board 80. The CPU of the display control board 80 performs corresponding display control according to these commands.

At the end of the big hit game, the CPU 56 of the main board 31 sends a big hit end command to each of the display control board 80, the sound control board 70, and the lamp control board 35. Then, after a predetermined time has elapsed, a normal screen display command is transmitted. Upon receiving the normal screen display command, each game device control means changes the control state to a game waiting state.

FIG. 15 is a flowchart showing an example of the game state restoring process performed in the power outage restoring process shown in FIG. In this example, if it is necessary to restore the contents of the register, the CPU 56 restores the value stored in the backup RAM to the register (step S61). Then, the game state at the time of the power failure is confirmed based on the data stored in the backup RAM. For example, the gaming state can be confirmed by the value of the special symbol process flag corresponding to the progress of the special symbol process.

If the game state is changing symbols (step S62), control is performed to send a change start command to the display control board 80, the sound control board 70, and the lamp control board 35 (step S63). When the gaming state is the jackpot game (step S64), control is performed to transmit the last transmitted control command to the display control board 80, the sound control board 70, and the lamp control board 35 before the power failure. (Step S65). Then, when the game state is any other game state, for example, a control for transmitting a control command for a normal screen display command to the display control board 80, the sound control board 70, and the lamp control board 35 is performed (step S66). In addition, for example, the state of the variable prize ball device 15 in the case of a big hit is automatically performed in a later game control process because the data in the RAM is stored.

FIG. 16 is an explanatory diagram showing an example of a control state when the power is restored after a power failure occurs. In FIG. 16, the state of the variable display is realized by the CPU (display control means) of the display control board 80, the state of the sound is realized by the CPU (sound control means) of the sound control board 70, and the state of the lamp is the lamp control board. This is realized by 35 CPUs (lamp control means).

FIG. 16 (A) shows an example in which the power is restored after a power failure occurs during the symbol change. In this case, when the power is restored, a change start command is sent from the main board 31 (step S63 in FIG. 15). Since the change start command is a command sent at the start of the symbol change, the state of the variable display control, the sound control, and the lamp control returns to the state at the start of the change. In this embodiment, the fluctuation start command includes information for specifying the fluctuation time, and after transmitting the fluctuation start command, the CPU 56 of the main board 31 does not transmit anything until the final change end command (the fluctuation stop command) ( Except for the symbol designating command). Therefore, if a power failure occurs during the symbol change, the change cannot be resumed from the state in the middle of the change, but the display control, sound control, and lamp control are synchronized by resending the change start command. Return to

In the main board 31, various parameters used at the start of the fluctuation are stored in the backup RAM. Therefore, the display result (fixed symbol) and the like in the fluctuation after the power restoration is the same as the display result and the like that would have been made in the fluctuation interrupted by the power failure. Therefore, no disadvantage is given to the player.

FIG. 16 (B) shows an example of a case where the power is restored after a power failure occurs during the big hit game. In this case, when the power is restored, the command sent from the main board 31 to the display control board 80, the sound control board 70, and the lamp control board 35 last before the power failure is sent again (step S65 in FIG. 15). Therefore, the sound control and the lamp control return to the control state during the big hit game. In addition, the display control also returns to the state performed at the time of the power failure.

In addition, on the main board 31, various parameters during the big hit game (the number of times of opening the special winning opening, the number of winning balls of the special winning opening, etc.) are stored in the backup RAM. Therefore, since the game state for the player also returns to the state before the power failure, there is no disadvantage to the player.

In the above-described embodiment, the case where the power monitoring process, the data saving process, and the restoration process are performed in the game control unit has been described. The backup control, the display control means, the sound control means, and the lamp control means may also perform the processing described above. However, the display control means, the sound control means, and the lamp control means do not need to perform the command transmission processing at the time of restoration.

In addition, in this embodiment, as shown in FIG. 5, two power supply monitoring means are mounted on the main board 31. When the power supply voltage decreases, the timing at which the second power supply monitoring means (the power supply monitoring IC 904 in this example) generates the voltage drop signal is determined by the first power supply monitoring means (the power supply monitoring means in this example). IC 902) is set to be later than the time when the voltage drop signal is generated. Further, the voltage drop signal from the second power supply monitoring means is input to the reset terminal of the CPU 56.

Then, as shown in FIG. 17, the CPU 56 executes a power failure generation process (power-off process) based on a voltage drop signal from the first power-supply monitoring unit (power-supply monitoring IC 902), and then enters a power-off wait state. However, in a power-off wait state, the apparatus enters a reset state. That is, the operation of the CPU 56 stops. In the power supply waiting state, the input / output state becomes unstable because the +5 V power supply voltage value gradually decreases, but since the CPU 56 is in the reset state, abnormal operation based on the undefined data is prevented.

As described above, in this embodiment, the CPU 56 executes the power-off processing in response to the input of the detection output from the first power supply monitoring unit, and performs the processing when the detection output from the second power supply monitoring unit is input. Since the system is configured to be reset in response, the data can be reliably stored when the power is turned off, and it is possible to prevent the player from being disadvantaged.

Next, a description will be given of the state of voltage supply to the game control means, that is, the CPU 56 of the main board 31 and the CPU of the control means for another game apparatus when the power is turned off. Here, a prize ball control unit that controls the ball payout device 97 will be described as an example of the game device control unit.

FIG. 18 is a block diagram showing an example of a configuration around the CPU 371 for controlling the prize ball for power supply monitoring and power supply backup. As shown in FIG. 18, the power supply monitoring IC 932 detects the occurrence of power interruption by introducing a +30 V power supply voltage and monitoring the +30 V power supply voltage. Specifically, when the +30 V power supply voltage becomes equal to or lower than a predetermined value, it is determined that the power is cut off, and an interrupt signal is given to the CPU 371 for award ball control. In this embodiment, the predetermined value is + 14V. In the prize ball control CPU 371, this interrupt is input to a non-maskable interrupt (NMI) terminal. The signal input to the NMI terminal is also input to the input port. Therefore, in the NMI processing, the CPU 371 for controlling the prize ball can confirm the power-off state by confirming the level of the input port.

The predetermined value for the power supply monitoring IC 932 to detect a power-off is lower than the normal voltage, but is a voltage at which the prize ball control CPU 371 can operate for a while. In addition, since the power supply monitoring IC 932 is configured to monitor a voltage higher than the voltage (+5 V in this example) required by the prize ball control CPU 371, the voltage required by the prize ball control CPU 371 is reduced. In contrast, the monitoring range can be extended. Therefore, more precise monitoring can be performed.

While power is not being supplied from the + 5V power supply, at least a part of the built-in RAM of the prize ball control CPU 371 is backed up by connecting a backup power supply supplied from a power supply board to a backup terminal, so that power for the gaming machine is maintained. Even if you refuse, the contents will be saved. Then, when the + 5V power supply is restored, a reset signal is issued from the initial reset circuit 935, so that the winning ball control CPU 371 returns to a normal operation state. At that time, since necessary data has been backed up, it is possible to return to the gaming state at the time of the occurrence of the power failure when recovery from a power failure or the like.

FIG. 19 is an explanatory diagram showing an example of a bit configuration of a prize ball control command transmitted from the main board 31 to the prize ball control board 37. As shown in FIG. 19, the upper four bits in one byte are used as a control designator, and the lower four bits are used as an area indicating the number of award balls.

As shown in FIG. 20, if the bits 7, 6, 5, and 4 are "0, 1, 0, 0" in the control designation section, it indicates that the command is the payout number designation command, and "0, 1, 0, "1" indicates a payout designation command. The payout number designation command is sent to the prize ball control board 37 immediately after the CPU 56 of the main board 31 detects a winning.

The command to designate a broken ball, in which the bits 7, 6, 5, and 4 are "1, 0, 0, 0", is transmitted from the main board 31 when it is detected that there are no more supply balls. The firing stop designation command in which the bits 7, 6, 5, and 4 are “1, 0, 0, 1” is issued when the surplus ball tray 4 is full and the full switch 48 is turned on (the full tank state). (When the flag is turned on).

The award ball control command is output from the main board 31 to the award ball control board 37 as 1-byte (8 bits: award ball control commands D7 to D0) data. The award ball control commands D7 to D0 are output in positive logic. When the prize ball control commands D7 to D0 are output, a negative logic prize ball control INT signal is output.

In this embodiment, as shown in FIG. 21, when the prize ball control commands D7 to D0 are output from the main board 31, the prize ball control INT signal goes low for 5 μs or more. The award ball control INT signal is connected to an interrupt terminal of the award ball control CPU 371 on the award ball control board 37. Therefore, if there is an interrupt, the award ball control CPU 371 can recognize that the award ball control commands D7 to D0 have been transmitted from the main board 31, and perform the award ball control command receiving process in the interrupt process.

Note that the command configuration shown in FIG. 19 is an example, and another configuration may be used. For example, the upper and lower parts in one byte may be reversed from the configuration shown in FIG.

FIG. 22 is a flowchart showing the main processing of the award ball control CPU 371. In the main process, the award ball control CPU 371 first performs an initial value setting process such as clearing a RAM area (step S701). If data is set in the RAM area (backup RAM area) of the internal RAM that has been backed up by power, those areas are not cleared. Thereafter, in this embodiment, the prize ball control CPU 371 performs prize ball payout control by an interrupt process by a timer interrupt generated every predetermined period (for example, 2 ms) (step S702). In the timer interruption process, as shown in FIG. 23, the prize ball control CPU 371 executes a prize ball payout control process (step S711).

FIG. 24 is an explanatory diagram showing an example of use of the RAM built in the CPU 371 for controlling a prize ball. In this example, the total number storage (for example, 2 bytes) is formed in the backup RAM area. The total number storage stores the total number of payout numbers instructed from the main board 31 side.

FIG. 25 is a flowchart showing a prize ball control command receiving process by the interrupt process. The award ball control INT signal from the main board 31 is input to an interrupt terminal of the award ball control CPU 371. Therefore, when the award ball control INT signal from the main board 31 is turned on, the award ball control CPU 371 is interrupted, and the receiving process of the award ball control command shown in FIG. 25 is started.

In the receiving process of the award ball control command, the award ball control CPU 371 first reads 1-byte data from the input port assigned to the input of the award ball control command data (step S852). If the read data is a payout number instruction command (step S853), the number specified by the payout number instruction command is added to the total number storage (step S855). Otherwise, a communication end flag is set (step S854). In this example, the communication end flag is a flag indicating that a command other than the payout number instruction command has been received.

As described above, the prize ball control CPU 371 mounted on the prize ball control board 37 stores the prize ball number included in the payout number instruction command sent from the CPU 56 of the main board 31 in the backup RAM area (total number storage). Remember.

If the value of the total number storage is not 0 in the prize ball control process (step S711) activated by the timer interrupt, the prize ball control CPU 371 drives the ball payout device 97 to perform the prize ball payout, Each time one payout is completed, the value of the total number storage is reduced by one.

FIG. 26 is a flowchart showing the NMI interrupt processing executed by the award ball control CPU 371. When the power supply monitoring IC 932 shown in FIG. 18 detects a drop in the power supply voltage, an NMI interrupt occurs, and the NMI interrupt processing is started. Accordingly, in the NMI interrupt process, a power failure occurrence process (process at the time of power failure) is executed. In the power-off processing, the prize ball control CPU 371 sets the RAM access to a prohibited state (step S801), and then loops. Therefore, when the voltage drop signal is output from the power supply monitoring IC 932, the award ball payout control is not performed.

FIG. 27 is a flowchart showing a part of the initialization process executed by the CPU 371 for controlling the prize ball when the power is turned on. When the power is turned on or the power is restored, the award ball control CPU 371 first checks whether or not the value of the total number storage formed in the backup RAM area is 0 (step S901). If it is 0, it means that there were no unpaid prize balls at the time of the previous power-off, so that normal initialization processing is performed. That is, the register and the entire RAM area are cleared (step S903), and the stack pointer is initialized (step S904).

If the value of the total number storage is not 0, the address is designated to clear the register and the non-backup RAM area (step S905). Then, setting for restarting the prize ball is performed. For example, a flag during processing of award balls is set (step S906). If the backup RAM area is an area irrespective of the number of prize balls, those addresses may be designated and cleared.

As described above, the prize ball control CPU 371 can determine whether to perform the normal initialization process or restore the state during the prize ball simply by checking the data in the backup RAM area when the power is turned on. That is, the prize ball processing can be restarted for the unpaid prize balls by a simple determination.

In this embodiment, the power supply monitoring IC 932 mounted on the prize ball control board 37 outputs a voltage drop signal when the +30 V power supply voltage becomes +14 V or less. Then, the prize ball control CPU 371 executes a power failure generation process (NMI process in this example) according to the voltage drop signal. On the other hand, the power supply monitoring IC 902 mounted on the main board 31 outputs a voltage drop signal when the +30 V power supply voltage becomes equal to or lower than +16 V. Then, the CPU 56 executes a power failure generation process according to the voltage drop signal. Therefore, as shown in FIG. 28, when a power failure or the like occurs, the timing at which the game control means starts the power failure occurrence processing is earlier than the time at which the prize ball control means starts the power failure occurrence processing. That is, when a power failure or the like occurs, the game control means stops the game control before the prize ball control means stops the prize ball payout control.

Therefore, for example, even if the game control means sends out a prize ball control command indicating the number of prize balls to be paid immediately before the start of the power failure generation process, the prize ball control command is reliably received by the prize ball control means. Then, the winning ball control means stores the winning ball payout number based on the received command as total number memory. Since the total number storage is formed in the backup RAM area, the prize ball payout control is restarted when the power is restored. That is, in the present embodiment, even when a power failure or the like occurs, the number of prize balls to be paid out is reliably stored and paid out at the time of restoration, so that no disadvantage is given to the player.

In this embodiment, the prize ball control CPU 371 executes the power-off process by the NMI process. However, the power-off process may be executed by a normal interrupt process, or the CPU 56 of the main board 31 may execute the power-off process. Similarly to the above, the detection output of the first power supply monitoring circuit may be introduced to the input port, and the power-off processing may be executed by monitoring the input port without using the interrupt processing. The prize ball control means may store the number of prize balls for each number of prize balls without collectively managing the number of prize balls paid out as the total number storage.

The prize ball control board 37 is also provided with a second power supply monitoring circuit similar to the circuit provided on the main board 31, and the second power supply monitoring circuit supplies a + 5V power supply for driving the prize ball control CPU 371. The voltage may be monitored, and the detection output of the second power supply monitoring circuit may be connected to the reset terminal of the prize ball control CPU 371. In that case, the two power supply monitoring circuits may monitor the same power supply voltage. For example, both may monitor the + 30V power supply voltage. Then, for example, one detection voltage is set to + 14V, and the other detection voltage is set to + 8V. Further, two potentials may be monitored by one power supply monitoring IC.

When two power supply monitoring circuits are provided, the prize ball control CPU 371 executes the power-off processing in response to the input of the detection output from the first power supply monitoring means, and performs the second power supply monitoring. Since the system is reset in response to the input of the detection output from the means, when the power is turned off, the data such as the number of prize balls to be paid out is more reliably stored, and it is possible to prevent the player from being disadvantaged.

In the above-described embodiment, the case where the RAM is used as the variable data storage means has been described. However, as the variable data storage means, any other electrically rewritable storage means other than the RAM may be used. Good.

Furthermore, here, the prize ball control means has been exemplified as the control means for the gaming device other than the game control means, but the display control means, the sound control means, and the lamp control means also have a voltage for generating a voltage drop signal. A power supply monitoring IC whose value is set lower than the voltage value in the game control means may be provided.

It is the front view which looked at the pachinko gaming machine from the front. It is the front view which looked at the game board of the pachinko gaming machine from the front. It is the back view which looked at the pachinko gaming machine from the back. It is a block diagram showing the example of circuit composition of a game control board (main board). FIG. 3 is a block diagram showing an example of a configuration around a CPU for power supply monitoring and power supply backup. FIG. 3 is a block diagram illustrating a configuration example of a power supply board. 6 is a flowchart showing the operation of the basic circuit on the main board. It is a flowchart which shows an initialization process. It is a flowchart which shows a 2ms timer interruption process. It is a flowchart showing a game control process. It is a flowchart which shows a power failure generation process. It is a flowchart which shows a power failure recovery process. FIG. 4 is an explanatory diagram for describing a backup parity data creation method. FIG. 9 is an explanatory diagram showing an example of a transmission timing of each control command from the main board. It is a flow chart which shows an example of game state restoration processing. It is explanatory drawing which shows an example of the control state when it recovers after a power failure occurs. FIG. 9 is a timing chart showing an example of an operation state of a CPU based on an output of a voltage monitoring unit. It is a block diagram showing an example of 1 composition of CPU around a prize ball control for power supply monitoring and power supply backup. It is an explanatory view showing a configuration example of a prize ball control command. It is an explanatory view showing a bit configuration of a prize ball control command. FIG. 9 is a timing chart showing how a winning ball control command data is output. It is a flowchart which shows the main process which CPU for award ball control performs. It is a flowchart which shows the 2ms timer interruption process of CPU for award ball control. FIG. 9 is an explanatory diagram showing a configuration example of a RAM in a prize ball control means. It is a flowchart which shows the command receiving process of CPU for award ball control. It is a flowchart which shows the NMI interruption process of CPU for award ball control. It is a flow chart which shows an example of initialization processing of CPU for award ball control. It is a timing chart which shows an example of the relation between the time when game control means starts a power failure occurrence process and the time when the prize ball control means starts the power failure occurrence process.

Explanation of reference numerals

1 Pachinko gaming machine 31 Main board 35 Lamp control board 37 Winning ball control board 70 Sound control board 80 Display control board 53 Basic circuit 56 CPU
371 CPU for controlling prize balls
570 Input port 902, 932 Power supply monitoring IC
903 Second power supply monitoring circuit 910 Power supply board 916 Capacitor 918 Power switch 919 Initialization operation switch

Claims (4)

A game is played using a game ball, and a variable display unit whose display state is changeable is provided, and when a display result of the variable display unit becomes a predetermined specific display mode, a predetermined game value is played. Machine to give to the
A display control board equipped with a CPU that performs display control of the variable display unit,
A special winning opening that is opened when the display result of the variable display unit becomes the specific display mode,
A starting winning port for changing the display state of the variable display section by winning a game ball,
A winning port for paying out a prize ball by winning a game ball,
A count switch for detecting winning of a game ball to the special winning opening,
A starting port switch for detecting a winning of a game ball to the starting winning port,
A winning opening switch for detecting a winning of a game ball to the winning opening;
When the count switch, the starting port switch and the winning port switch detects a winning, a game control board equipped with a CPU that outputs a payout number instruction command for instructing the payout number of winning balls,
A ball payout device that pays out prize balls,
A prize ball control board equipped with a prize ball control CPU for driving the ball payout device in response to the payout number instruction command;
A first power supply monitoring circuit that monitors a first predetermined power supply voltage used by the gaming machine and detects that the first predetermined power supply voltage has dropped below a first predetermined value;
A second power supply for monitoring a second predetermined power supply voltage used by the gaming machine and detecting that the second predetermined power supply voltage has dropped below a second predetermined value lower than the first predetermined value. With a monitoring circuit,
Detection outputs of the first power supply monitoring circuit and the second power supply monitoring circuit are input to the prize ball control CPU,
The prize ball control CPU,
A backup RAM area in which the total number of payouts instructed by the payout number instruction command is stored and the contents of which are stored even when the power to the gaming machine is turned off,
The payout number designated by the payout number instruction command is added to the total number of payout numbers stored in the backup RAM area, and each time one ball is paid out by driving the ball payout apparatus, the backup RAM area is added. Subtracts 1 from the total number of payouts stored by
When a detection output from the first power supply monitoring circuit is input, a RAM access prohibition state is set, and when a detection output from the second power supply monitoring circuit is input, a system reset is performed.
The CPU mounted on the game control board,
When starting the symbol change in the variable display section, a change start command including information indicating the change time of the symbol is output to the CPU mounted on the display control board, and the symbol designation command indicating the fixed symbol is further displayed on the display. A game machine which outputs a change stop command to a CPU mounted on the display control board when outputting to a CPU mounted on a control board to determine a symbol change in the variable display section. The gaming machine according to claim 1, wherein the first power supply monitoring circuit and the second power supply monitoring circuit monitor the same power supply voltage. The second predetermined power supply voltage monitored by the second power supply monitoring circuit is a voltage of a power supply for driving the CPU for controlling the prize ball,
The gaming machine according to claim 1 or 2, wherein the second power supply monitoring circuit detects that the voltage of the driving power supply has dropped to a second predetermined value or less within an operable range of the prize ball control CPU. . The detection output of the first power supply monitoring circuit is input to the input port of the CPU for controlling the prize ball,
The gaming machine according to any one of claims 1 to 3, wherein the CPU for controlling the prize ball executes the setting of the RAM access prohibition state by monitoring the input port.

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