JP2005287772A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a game machine of which the memory for storing variation data of the game machine is surely not initiated even when power source noises or the like are input in a system resetting terminal of a game controlling means (CPU). <P>SOLUTION: The CPU 461 constituted of a microcomputer is arranged on a main board 46. Also, on the main board 46, a power source monitoring system reset generating circuit 65 which is connected with the system resetting terminal of the CPU 461, and outputs a supply starting signal when the supply start of power to the main board 46 is detected is arranged. Also, the main board 46 has an arrangement of a reset interruption generating circuit 66, which is connected with a user resetting terminal of the CPU 461, and outputs an interruption signal of a high level with a specified time interval. In addition, on a power source unit 57, a RAM clearing switch 58 one terminal of which is grounded on the power source unit 57, and the other terminal of which is connected with a RAM clearing terminal of the CPU 461 is arranged. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a gaming machine such as a pachinko machine that allows a player to play a predetermined game.

Recent gaming machines such as pachinko machines are provided with various objects (special devices for facilitating winnings) in the game board in order to increase the player's interest by changing the game content. For example, in a pachinko machine, when the pachinko ball wins the starting opening, the changing symbols displayed on the symbol display device such as a CRT start changing, and the symbols displayed after a certain period of time are aligned with a certain probability. (For example, a doublet such as “7, 7, 7”, etc.) As a big win, there is a case where a big winning opening is continuously opened a predetermined number of times and a big win video is displayed on the symbol display device. Such a pachinko machine incorporates a large number of electronic control circuits for various controls, and various circuits such as a display circuit or a prize ball payout control circuit are controlled by an electronic control circuit including a microcomputer or the like. The These control programs are repeatedly executed at regular intervals. Further, at the start of power supply, a system reset signal is input, and by input of the system reset signal, as a variation data storage means for storing variation data such as count values of various counters at the time of winning the start opening under a predetermined condition Memory (RAM) is initialized.
For example, a conventional gaming machine includes a game control unit (CPU) that performs an electrical component control process for controlling electrical components provided in the gaming machine, and the game control unit (CPU) performs an initial preparation process at startup. After the execution, the electrical component control process is executed, and the initial preparation process is a memory related to the gaming state immediately before the power supply is stopped, and performs control based on the contents of the backup memory that is retained even while the power supply is stopped. And a control state determination process for determining whether or not the control state is determined, and the control based on the contents of the backup storage can be executed according to the determination result of the control state determination process. The game control means (CPU) is set so that the internal timer repeatedly generates a timer interrupt. This repetition period is set to 2 ms. And when a timer interruption generate | occur | produces, a game control means (CPU) is comprised so that a game control process may be performed (for example, refer patent document 1).
JP 2001-190749 A (paragraphs (0054) to (0080), FIGS. 6 to 10)

  However, in a conventional gaming machine, a system reset signal due to power supply noise or the like is input to a system reset terminal of a game control means (CPU) during a game, and a memory for storing variation data of the gaming machine is initialized. There is a problem of fear. Further, when it is desired to initialize a memory for storing variation data of gaming machines during a game, there is a problem that power supply must be stopped once.

  Accordingly, the present invention has been made to solve the above-described problems, and even if a system reset signal due to power supply noise or the like is input to a system reset terminal of a game control means (CPU) during a game, the gaming machine An object of the present invention is to provide a gaming machine in which the memory for storing the fluctuation data is not initialized reliably. It is another object of the present invention to provide a gaming machine capable of initializing a memory for storing variation data of gaming machines without stopping power supply during gaming.

  In order to achieve the above object, a gaming machine according to claim 1 is a gaming machine in which a player can play a predetermined game, and fluctuation data storage means for storing fluctuation data that fluctuates according to the progress of the game. A game control means for controlling the progress of the game and a state of a predetermined power source used in the gaming machine, and when the start of power supply is detected, a first detection signal is sent to the game control means. Power supply monitoring means for outputting, interrupt signal output means for outputting an interrupt signal for causing the game control means to start execution of game control at predetermined time intervals, and initializing the fluctuation data storage means in the game control means And a first initialization instruction means for outputting an instruction signal for instructing the game, wherein the game control means receives the first detection signal from the power supply monitoring means and receives the first initialization signal. An instruction signal is input from the instruction means. If it is determined whether the instruction signal is not input from the first initialization instruction means, the execution of the game control is started without initializing the variation data storage means, If it is determined that the instruction signal is input from the first initialization instruction means, the game data control means is started after the variable data storage means is initialized, and the interrupt signal output means When a signal is input, it is determined whether or not an instruction signal is input from the first initialization instruction means, and when it is determined that an instruction signal is not input from the first initialization instruction means When the execution of the game control is started without initializing the fluctuation data storage means, and when it is determined that the instruction signal is input from the first initialization instruction means, the fluctuation data storage means is initialized. After that, execute the game control Characterized in that it started.

  The gaming machine according to claim 2 is a gaming machine in which a player can perform a predetermined game, and has a variation data storage means for storing variation data that varies according to the progress of the game. A game control means for controlling the progress of the game, and a power supply monitor for monitoring the state of a predetermined power source used in the gaming machine and outputting a first detection signal to the game control means when the start of power supply is detected Means, an interrupt signal output means for outputting an interrupt signal for causing the game control means to start executing game control at a predetermined time interval, and initializing the variation data storage means in the game control means. First initialization instruction means for outputting an instruction signal for instructing, and first signal output means for outputting a second detection signal to the game control means on condition that the supply start voltage of the power supply becomes equal to or higher than a predetermined voltage And the game system When the first detection signal is inputted from the power supply monitoring means, the instruction signal is inputted from the first initialization instruction means, and the second detection signal is inputted from the first signal output means. If it is determined that at least one of the instruction signal and the second detection signal is not input, the execution of the game control is started without initializing the variation data storage unit, When it is determined that the instruction signal is inputted and the second detection signal is inputted, the execution of the game control is started after the variable data storage means is initialized, and the interruption signal output means When the instruction signal is input, it is determined whether the instruction signal is input from the first initialization instruction means and the second detection signal is input from the first signal output means. At least of the second detection signal If it is determined that the direction is not input, the execution of game control is started without initializing the variation data storage means, while the instruction signal is input and the second detection signal is input. When the determination is made, the game data control is started after the variable data storage means is initialized.

  A gaming machine according to claim 3 is the gaming machine according to claim 2, wherein the power monitoring means and the first signal output means are arranged on a control board on which the gaming control means is mounted. It is characterized by being.

  The gaming machine according to claim 4 is the gaming machine according to claim 2, wherein the power monitoring means and the first signal output means are arranged in a power supply unit that supplies power to the gaming control means. It is characterized by.

  The gaming machine according to claim 5 is a gaming machine in which a player can perform a predetermined game, and has a variation data storage means for storing variation data that varies according to the progress of the game. A game control means for controlling the progress of the game, and a power supply monitor for monitoring the state of a predetermined power source used in the gaming machine and outputting a first detection signal to the game control means when the start of power supply is detected Means, an interrupt signal output means for outputting an interrupt signal for causing the game control means to start executing game control at a predetermined time interval, and initializing the variation data storage means in the game control means. First initialization instruction means for outputting an instruction signal for instructing; second signal output means for outputting a third detection signal to the game control means on condition that the power supply monitoring means has output the first detection signal; The game control means When the first detection signal is inputted from the power monitoring means, whether the instruction signal is inputted from the first initialization instruction means and the third detection signal is inputted from the second signal output means If it is determined that at least one of the instruction signal and the third detection signal has not been input, execution of game control is started without initializing the variation data storage means, When it is determined that a signal is input and a third detection signal is input, the execution of game control is started after initialization of the variation data storage means, and an interrupt signal is output from the interrupt signal output means. Is input, an instruction signal is input from the first initialization instruction means, and it is determined whether a third detection signal is input from the second signal output means. At least one of the detection signals If it is determined that it is not applied, the game control is started without initializing the variation data storage means, while it is determined that the instruction signal is input and the third detection signal is input. In this case, after the variable data storage means is initialized, execution of game control is started.

  Further, in the gaming machine according to claim 6, in the gaming machine according to claim 5, the power monitoring means and the second signal output means are arranged on a control board on which the gaming control means is mounted. It is characterized by being.

  The gaming machine according to claim 7 is the gaming machine according to claim 5, wherein the power monitoring means and the second signal output means are arranged in a power supply unit that supplies power to the gaming control means. It is characterized by.

  The gaming machine according to claim 8 is the gaming machine according to claim 5, wherein the power monitoring means is disposed in a power supply unit that supplies power to the game control means, and the second signal output means is The game control means is disposed on a control board on which the game control means is mounted.

  The gaming machine according to claim 9 is a gaming machine in which a player can perform a predetermined game, and has a variation data storage means for storing variation data that varies according to the progress of the game. A game control means for controlling the progress of the game, and a power supply monitor for monitoring the state of a predetermined power source used in the gaming machine and outputting a first detection signal to the game control means when the start of power supply is detected Means, an interrupt signal output means for outputting an interrupt signal for causing the game control means to start executing game control at a predetermined time interval, and initializing the variation data storage means in the game control means. A second initialization instruction means for outputting an instruction signal for instructing; a third signal output means for outputting a fourth detection signal on condition that the voltage for starting the supply of power has become equal to or higher than a predetermined voltage; and the game control Provided separately from the means The fourth signal for outputting the fifth detection signal to the game control means when the fourth detection signal is inputted from the third signal output means and the instruction signal is inputted from the second initialization instruction means Output means, and the game control means determines whether or not the fifth detection signal is inputted from the fourth signal output means when the first detection signal is inputted from the power supply monitoring means. When it is determined that the fifth detection signal is not input, the execution of the game control is started without initializing the variation data storage means, while it is determined that the fifth detection signal is input. In this case, after the variable data storage means is initialized, the game control is started. When an interrupt signal is input from the interrupt signal output means, the fourth signal output means 5 Determine whether a detection signal is input, When it is determined that the fifth detection signal is not input, the execution of the game control is started without initializing the variation data storage means, while when it is determined that the fifth detection signal is input. Is characterized by starting execution of game control after initializing the variation data storage means.

  The gaming machine according to claim 10 is the gaming machine according to claim 9, wherein the power control means, the third signal output means, and the fourth signal output means are mounted with the game control means. It is arranged on the control board.

  The gaming machine according to claim 11 is a gaming machine in which a player can play a predetermined game, and has a variation data storage means for storing variation data that varies according to the progress of the game. A game control means for controlling the progress of the game, and a power supply monitor for monitoring the state of a predetermined power source used in the gaming machine and outputting a first detection signal to the game control means when the start of power supply is detected Means, an interrupt signal output means for outputting an interrupt signal for causing the game control means to start executing game control at a predetermined time interval, and initializing the variation data storage means in the game control means. Second initialization instruction means for outputting an instruction signal for instructing, fifth signal output means for outputting a sixth detection signal on condition that the power supply monitoring means has output the first detection signal, and the game control means, Is provided separately, The sixth signal output for outputting the seventh detection signal to the game control means when the sixth detection signal is inputted from the fifth signal output means and the instruction signal is inputted from the second initialization instruction means. And when the first detection signal is input from the power supply monitoring unit, the game control unit determines whether the seventh detection signal is input from the sixth signal output unit, When it is determined that the seventh detection signal is not input, execution of game control is started without initializing the variation data storage means, while it is determined that the seventh detection signal is input After the initialization of the variation data storage means, execution of game control is started, and when an interrupt signal is input from the interrupt signal output means, the sixth signal output means It is determined whether or not a detection signal is input, and the first When it is determined that the detection signal is not input, the game control execution is started without initializing the variation data storage means. On the other hand, when it is determined that the seventh detection signal is input, After the variable data storage means is initialized, game control execution is started.

  A gaming machine according to claim 12 is the gaming machine according to claim 11, wherein the power monitoring means, the fifth signal output means, and the sixth signal output means are mounted with the game control means. It is arranged on the control board.

  A gaming machine according to a thirteenth aspect is the gaming machine according to the eleventh aspect, wherein the power monitoring means is disposed in a power supply unit that supplies power to the gaming control means, and the fifth signal output means The sixth signal output means is arranged on a control board on which the game control means is mounted.

  A gaming machine according to claim 14 is the gaming machine according to any one of claims 1 to 13, wherein the first initialization instruction means or the second initialization instruction means supplies power to the game control means. The interrupt signal output means is provided on a control board on which the game control means is mounted.

  Furthermore, the gaming machine according to claim 15 is the gaming machine according to any one of claims 1 to 14, wherein the game control means determines whether a program for executing the control is regular. Including a microcomputer capable of executing a security check for determining whether or not the first detection signal is input, the security check is executed.

In the gaming machine according to claim 1, when the first detection signal is input from the power supply monitoring unit, the game control unit determines whether the instruction signal is input from the first initialization instruction unit, If it is determined that the instruction signal is not input from the first initialization instruction means, execution of the game control is started without initializing the variation data storage means, while the instruction signal is received from the first initialization instruction means. When it is determined that is input, after the variable data storage means is initialized, execution of game control is started.
Thereby, in the case of the start of power supply, that is, at the time of start-up or restoration of a power failure, the variable data storage means is initialized only when the user inputs an instruction signal from the first initialization instruction means to the game control means. Therefore, when the user does not input an instruction signal from the first initialization instruction means to the game control means at the start of power supply, the game is performed with the data stored in the variable data storage means before the power supply is stopped. Execution of control can be started, and the gaming state of the gaming machine can be reliably restored to the gaming state before the power supply is stopped. Further, even if power supply noise or the like is erroneously input as the first detection signal to the game control means, if the user does not input the instruction signal from the first initialization instruction means to the game control means, it is stored in the fluctuation data storage means. Since the stored data is not initialized, the gaming state of the gaming machine can be reliably restored to the gaming state before the power supply noise is input.
The game control means determines whether or not an instruction signal is inputted from the first initialization instruction means when an interrupt signal is inputted from the interrupt signal output means, and the first initialization instruction means When it is determined that the instruction signal is not input from, the execution of the game control is started without initializing the fluctuation data storage means, while it is determined that the instruction signal is input from the first initialization instruction means. In such a case, after the variable data storage means is initialized, execution of game control is started.
Thereby, the game student control means, when the interrupt signal is input from the interrupt signal output means at a predetermined time interval (for example, about 2 msec to 4 msec interval), the user receives an instruction signal from the first initialization instruction means. Only when the game control means is input to the game control means, after the variable data storage means is initialized, the execution of the game control is started. Therefore, even during the game, the user does not stop the power supply and the first initialization instruction means. By inputting an instruction signal to the game control means, the variation data storage means can be initialized and the game state can be initialized. Even if power supply noise or the like is erroneously input as an interrupt signal to the game control means, if the user does not input an instruction signal from the first initialization instruction means to the game control means, it is stored in the variation data storage means. Therefore, the game state of the gaming machine is surely restored to the game state before the power supply noise is input, that is, the game state before the power supply noise is input is maintained and the game is maintained. Can continue reliably.

In the gaming machine according to claim 2, when the first detection signal is input from the power supply monitoring unit, the game control unit receives the instruction signal from the first initialization instruction unit and outputs the first signal. It is determined whether or not the second detection signal is input from the means, and if it is determined that at least one of the instruction signal and the second detection signal is not input, the game is performed without initializing the fluctuation data storage means. On the other hand, when it is determined that the instruction signal is input and the second detection signal is input, the execution of the game control is started after the variable data storage means is initialized.
As a result, when power supply is started, that is, at the time of start-up or power failure recovery, the user inputs an instruction signal from the first initialization instruction means to the game control means, and the second detection signal indicating the power-up Since the variable data storage means is initialized only when the command is input, if the user does not input the instruction signal from the first initialization instruction means to the game control means at the start of power supply, the power supply is stopped. The execution of the game control can be started with the data previously stored in the variable data storage means, and the gaming state of the gaming machine can be reliably restored to the gaming state before the power supply is stopped. Further, even if power supply noise or the like is erroneously input as the first detection signal to the game control means, if the user does not input the instruction signal from the first initialization instruction means to the game control means, it is stored in the fluctuation data storage means. Since the stored data is not initialized, the gaming state of the gaming machine can be reliably restored to the gaming state before the power supply noise is input. Further, when power supply is started, that is, at the time of start-up or power failure recovery, the user inputs an instruction signal from the first initialization instruction means to the game control means, and a second detection signal indicating power-up is displayed. Only when input, the game control means initializes the fluctuation data storage means, so that the execution of initialization of the fluctuation data storage means can be started after the power supply voltage supplied to the game control means has risen sufficiently, The variable data storage means can be reliably initialized.
In addition, when the game control means receives an interrupt signal from the interrupt signal output means, the instruction signal is input from the first initialization instruction means, and the second detection signal is input from the first signal output means. If it is determined that at least one of the instruction signal and the second detection signal has not been input, the execution of the game control is started without initializing the variation data storage means, When it is determined that the instruction signal is input and the second detection signal is input, the execution of the game control is started after the variable data storage means is initialized.
Thereby, the game student control means, when the interrupt signal is input from the interrupt signal output means at a predetermined time interval (for example, about 2 msec to 4 msec interval), the user receives the instruction signal from the first initialization instruction means. Is input to the game control means, and the execution of the game control is started after the variable data storage means is initialized only when the second detection signal indicating the power-up is input. For this reason, if at least one of the instruction signal from the first initialization instruction means and the second detection signal is not input even if power supply noise or the like is erroneously input as an interrupt signal to the game control means, Since the data stored in the fluctuation data storage means is not initialized, the gaming state of the gaming machine is surely restored to the gaming state before the power supply noise is input, that is, before the power supply noise is input. The game state can be maintained and the game can be continued reliably. Further, even if the user mistakenly inputs the instruction signal from the first initialization instruction means during the game, the second detection signal is not input from the first signal output means, so that it is stored in the fluctuation data storage means. Data is not initialized, and the gaming state of the gaming machine is surely restored to the gaming state before the instruction signal is input, that is, the gaming state before the instruction signal is input is maintained to ensure the game. You can continue to.

  Further, in the gaming machine according to claim 3, since the power monitoring means and the first signal output means are arranged on the control board on which the game control means is mounted, the wiring length to the game control means is shortened. Therefore, input of power supply noise can be more reliably prevented.

  In the gaming machine according to claim 4, since the power monitoring means and the first signal output means are arranged in the power supply unit that supplies power to the game control means, the power supply start and the power supply voltage are predetermined. It is possible to more reliably and accurately detect a rise above the voltage.

In the gaming machine according to claim 5, when the first detection signal is input from the power supply monitoring unit, the game control unit receives the instruction signal from the first initialization instruction unit and outputs the second signal. It is determined whether or not the third detection signal is input from the means, and if it is determined that at least one of the instruction signal and the third detection signal is not input, the game is performed without initializing the fluctuation data storage means. On the other hand, when it is determined that the instruction signal is input and the third detection signal is input, the execution of the game control is started after the variable data storage means is initialized.
Thereby, at the start of power supply, that is, at the time of start-up or restoration of power failure, the user inputs an instruction signal from the first initialization instruction means to the game control means, and the start of power supply is detected. The variable data storage means is initialized only when the third detection signal indicating is input, and therefore when the user does not input the instruction signal from the first initialization instruction means to the game control means at the start of power supply The execution of the game control can be started with the data stored in the fluctuation data storage means before the power supply is stopped, and the gaming state of the gaming machine is reliably restored to the gaming state before the power supply is stopped. be able to. Further, even if power supply noise or the like is erroneously input as the first detection signal to the game control means, if the user does not input the instruction signal from the first initialization instruction means to the game control means, it is stored in the fluctuation data storage means. Since the stored data is not initialized, the gaming state of the gaming machine can be reliably restored to the gaming state before the power supply noise is input. Further, at the start of power supply, that is, at the time of start-up or power failure recovery, the user inputs an instruction signal from the first initialization instruction means to the game control means and indicates that the start of power supply has been detected. Only when the third detection signal is input, the game control means initializes the fluctuation data storage means. Therefore, after the power supply voltage supplied to the game control means rises sufficiently, Execution can be started, and the fluctuation data storage means can be reliably initialized.
The game control means receives an instruction signal from the first initialization instruction means and receives a third detection signal from the second signal output means when an interrupt signal is inputted from the interrupt signal output means. If it is determined that at least one of the instruction signal and the third detection signal has not been input, the execution of the game control is started without initializing the variation data storage means, When it is determined that the instruction signal is input and the third detection signal is input, the execution of the game control is started after the variable data storage means is initialized.
Thereby, the game student control means, when the interrupt signal is input from the interrupt signal output means at a predetermined time interval (for example, about 2 msec to 4 msec interval), the user receives an instruction signal from the first initialization instruction means. Is input to the game control means, and only when a third detection signal indicating that the start of power supply has been detected is input, the power supply for starting the execution of the game control after initializing the variable data storage means If at least one of the instruction signal from the first initialization instruction means and the third detection signal is not inputted even if noise or the like is erroneously inputted as an interrupt signal to the game control means, the fluctuation data storage means Since the data stored in is not initialized, the gaming state of the gaming machine is surely restored to the gaming state before the power supply noise is input, that is, the gaming state before the power supply noise is input. It is possible to proceed reliably game by lifting. Further, even if the user mistakenly inputs an instruction signal from the first initialization instruction means during the game, the third detection signal is not input from the second signal output means, so that it is stored in the fluctuation data storage means. The data is not initialized, and the gaming state of the gaming machine is reliably restored to the gaming state before the instruction signal is input, that is, the gaming state before the instruction signal is input is maintained and the game is ensured. You can continue to.
Further, the second signal output means outputs the third detection signal on condition that the power supply monitoring means outputs the first detection signal, and therefore monitors whether or not the power supply start voltage has become a predetermined voltage or more. This eliminates the need for a circuit for reducing the size and cost.

  Further, in the gaming machine according to claim 6, since the power monitoring means and the second signal output means are arranged on the control board on which the game control means is mounted, the wiring length to the game control means is shortened. Therefore, input of power supply noise can be surely prevented.

  In the gaming machine according to claim 7, since the power monitoring means and the second signal output means are disposed in the power supply unit that supplies power to the game control means, the power supply start can be more reliably and It can be detected accurately.

  In the gaming machine according to the eighth aspect, since the power supply monitoring means is disposed in the power supply unit that supplies power to the game control means, it is possible to more reliably and accurately detect the start of power supply. . In addition, since the second signal output means is disposed on the control board on which the game control means is mounted, the wiring length to the game control means can be shortened, and input of power supply noise is reliably prevented. be able to.

In the gaming machine according to claim 9, when the first detection signal is input from the power supply monitoring unit, the game control unit determines whether the fifth detection signal is input from the fourth signal output unit. If it is determined that the fifth detection signal is not input, the game control is started without initializing the fluctuation data storage means, while it is determined that the fifth detection signal is input. In this case, after the variable data storage means is initialized, execution of game control is started.
As a result, when power supply is started, that is, at the time of start-up or power failure recovery, the user inputs an instruction signal from the second initialization instruction unit to the fourth signal output unit, and the fourth signal indicating the power-up. Only when the detection signal is input to the fourth signal output means, the fifth detection signal is input from the fourth signal output means to the game control means, and the variable data storage means is initialized. When the instruction signal is not input to the fourth signal output means from the second initialization instruction means at the start of supply, the game control is started with the data stored in the variable data storage means before the power supply is stopped. Therefore, the gaming state of the gaming machine can be reliably restored to the gaming state before the power supply is stopped. If the user does not input the instruction signal from the second initialization instruction means to the fourth signal output means even if power supply noise or the like is erroneously input as the first detection signal to the game control means, the fluctuation data storage means Since the data stored in is not initialized, the gaming state of the gaming machine can be reliably restored to the gaming state before the power supply noise is input. Further, when power supply is started, that is, at the time of start-up or restoration of a power failure, the user inputs an instruction signal from the second initialization instruction means to the fourth signal output means, and the fourth detection indicating the power-up Only when a signal is input to the fourth signal output means, the fifth detection signal is input to the game control means, and the game control means is supplied to the game control means to initialize the variation data storage means. After the power supply voltage is sufficiently increased, the execution of initialization of the fluctuation data storage means can be started, and the fluctuation data storage means can be reliably initialized.
In addition, when an interrupt signal is input from the interrupt signal output means, the game student control means determines whether or not the fifth detection signal is input from the fourth signal output means, and the fifth detection signal If it is determined that the control signal is not input, the execution of the game control is started without initializing the variable data storage means. On the other hand, if it is determined that the fifth detection signal is input, the variable data storage is started. After initializing the means, execution of game control is started.
As a result, when the game student control means receives an interrupt signal from the interrupt signal output means at a predetermined time interval (for example, at intervals of about 2 msec to 4 msec), the user receives an instruction signal from the second initialization instruction means. Is input to the fourth signal output means, and the game control means receives the fifth detection signal from the fourth signal output means only when the fourth detection signal indicating the power-up is input to the fourth signal output means. Then, after the variable data storage means is initialized, execution of game control is started. Therefore, even if power supply noise or the like is erroneously input to the game control means as an interrupt signal, at least one of the instruction signal from the second initialization instruction means and the fourth detection signal is input to the fourth signal output means. If not, since the data stored in the variable data storage means is not initialized, the gaming state of the gaming machine is surely restored to the gaming state before the power noise is input, that is, the power noise. The game state can be maintained and the game can be continued without fail. Further, when the user mistakenly inputs an instruction signal from the second initialization instruction means to the fourth signal output means during the game, a fourth detection signal is input from the third signal output means to the fourth signal output means. Since the fifth detection signal is not output from the fourth signal output means to the game control means, the data stored in the variation data storage means is not initialized, and the instruction signal is input to the gaming state of the gaming machine. It is possible to reliably restore the gaming state before being played, that is, to maintain the gaming state before the instruction signal is input and to continue the game with certainty.
Further, by providing the fourth signal output means, the game control means determines whether or not the fourth detection signal is input from the third signal output means and the instruction signal is input from the second initialization instruction means. It is not necessary to perform the determination process, the game control processing program can be downsized, and the memory capacity can be downsized.

  In the gaming machine according to claim 10, since the power monitoring means, the third signal output means, and the fourth signal output means are arranged on the control board on which the game control means is mounted, Therefore, the input of power supply noise can be prevented more reliably.

In the gaming machine according to claim 11, when the first detection signal is input from the power supply monitoring unit, the game control unit determines whether the seventh detection signal is input from the sixth signal output unit. If it is determined that the seventh detection signal is not input, the game control is started without initializing the variable data storage means, while it is determined that the seventh detection signal is input. In this case, after the variable data storage means is initialized, execution of game control is started.
Thus, at the start of power supply, that is, at the time of start-up or power failure recovery, the user inputs an instruction signal from the second initialization instruction means to the sixth signal output means and detects the start of power supply Only when the sixth detection signal indicating the fact is input to the sixth signal output means, the seventh detection signal is input from the sixth signal output means to the game control means, and the variation data storage means is initialized. Therefore, when the user does not input the instruction signal from the second initialization instruction means to the sixth signal output means at the start of power supply, the game is performed with the data stored in the fluctuation data storage means before the power supply is stopped. Execution of control can be started, and the gaming state of the gaming machine can be reliably restored to the gaming state before the power supply is stopped. If the user does not input the instruction signal from the second initialization instruction means to the sixth signal output means even if power supply noise or the like is erroneously input as the first detection signal to the game control means, the fluctuation data storage means Since the data stored in is not initialized, the gaming state of the gaming machine can be reliably restored to the gaming state before the power supply noise is input. Further, when power supply is started, that is, at the time of start-up or power failure recovery, the user inputs an instruction signal from the second initialization instruction means to the sixth signal output means, and the start of power supply is detected. Only when the sixth detection signal indicating the effect is input to the seventh signal output means, the seventh detection signal is input to the game control means, and the game control means initializes the variation data storage means. After the power supply voltage supplied to the game control means has risen sufficiently, the execution of initialization of the fluctuation data storage means can be started, and the fluctuation data storage means can be reliably initialized.
In addition, when an interrupt signal is input from the interrupt signal output means, the game student control means determines whether or not a seventh detection signal is input from the sixth signal output means, and the seventh detection signal When it is determined that the control signal is not input, the execution of the game control is started without initializing the variable data storage means. On the other hand, when it is determined that the seventh detection signal is input, the variable data storage is started. After initializing the means, execution of game control is started.
As a result, when the game student control means receives an interrupt signal from the interrupt signal output means at a predetermined time interval (for example, at intervals of about 2 msec to 4 msec), the user receives an instruction signal from the second initialization instruction means. Is input to the sixth signal output means, and only when the sixth detection signal indicating that the start of power supply is detected is input to the sixth signal output means, the game control means After the seventh detection signal is input and the variation data storage means is initialized, execution of the game control is started. For this reason, even if power supply noise or the like is erroneously input as an interrupt signal to the game control means, at least one of the instruction signal from the second initialization instruction means and the sixth detection signal is input to the sixth signal output means. If not, since the data stored in the variable data storage means is not initialized, the gaming state of the gaming machine is surely restored to the gaming state before the power noise is input, that is, the power noise. The game state can be maintained and the game can be continued without fail. Further, when the user mistakenly inputs an instruction signal from the second initialization instruction means to the sixth signal output means during the game, a sixth detection signal is input from the fifth signal output means to the sixth signal output means. Since the sixth detection signal is not output from the sixth signal output means to the game control means, the data stored in the variable data storage means is not initialized, and the instruction signal is input to the gaming state of the gaming machine. It is possible to reliably restore the gaming state before being played, that is, to maintain the gaming state before the instruction signal is input and to reliably continue the game.
The fifth signal output means outputs the sixth detection signal on condition that the power supply monitoring means outputs the first detection signal, and therefore monitors whether or not the power supply start voltage has become a predetermined voltage or more. This eliminates the need for a circuit for reducing the size and cost.
Further, by providing the sixth signal output means, the game control means determines whether or not the sixth detection signal is input from the fifth signal output means and the instruction signal is input from the second initialization instruction means. It is not necessary to perform the determination process, the game control processing program can be downsized, and the memory capacity can be downsized.

  In the gaming machine according to claim 12, since the power monitoring means, the fifth signal output means, and the sixth signal output means are disposed on the control board on which the game control means is mounted, the game control means Therefore, the input of power supply noise can be surely prevented.

  In the gaming machine according to the thirteenth aspect, since the power monitoring means is disposed in the power supply unit that supplies power to the game control means, it is possible to detect the start of power supply more reliably and accurately. . Further, since the fifth signal output means and the sixth signal output means are disposed on the control board on which the game control means is mounted, the wiring length to the game control means can be shortened, Noise input can be surely prevented.

  In the gaming machine according to the fourteenth aspect, since the first initialization instruction means or the second initialization instruction means is disposed in the power supply unit that supplies power to the game control means, the power switch of the gaming machine The user can easily operate the first initialization instruction means or the second initialization instruction means. In addition, since the interrupt signal output means is disposed on the control board on which the game control means is mounted, the wiring length to the game control means can be shortened, thereby reliably preventing the input of power supply noise. can do.

  Furthermore, in the gaming machine according to claim 15, the game control means includes a microcomputer capable of executing a security check for determining whether or not each program for executing the control is legitimate, and the first detection When a signal is input, the microcomputer performs a security check. Thereby, when the power supply is started, that is, at the time of start-up or when the power failure is restored, the microcomputer of the game raw control means performs a security check, so that it is possible to reliably prevent malfunction of the game raw control means. it can.

  Hereinafter, a first embodiment to a ninth embodiment in which a gaming machine according to the present invention is embodied for a pachinko machine will be described in detail with reference to the drawings.

First, a schematic configuration of the pachinko machine according to the first embodiment will be described with reference to FIGS. 1 to 3.
As shown in FIGS. 1 to 3, the pachinko machine 1 according to the first embodiment is a so-called first type pachinko machine that pays out a predetermined amount of pachinko balls as a prize ball, and is generally a CR machine (card reading machine). The card-type ball lending machine and the pachinko machine 1 are configured as a pair, but the card-type ball lending machine is not shown in FIGS. 1 and 3. In the pachinko machine 1, a synthetic resin front frame 3 is attached to a wooden outer frame 21 so as to be freely opened and closed with respect to the outer frame 21 via an upper hinge 3A and a lower hinge 3B constituting a front frame attachment hinge. It has been. A front cover member 4 made of synthetic resin is attached to the front side of the substantially upper half of the front frame 3 so that it can be opened and closed by being pivotally supported at the top and bottom of the left end edge. Further, a substantially circular window portion 5 is opened at the substantially central portion of the front cover member 4, and the game board 2 is passed through two glasses attached to a glass holding frame formed on the outer peripheral edge portion of the window portion 5. The upper game area 11 can be seen. Further, a full-color light emitting diode is built in the upper edge of the window portion 5 of the front cover member 4, and an error display illumination lamp 6A for displaying an error during the game is attached. Further, on the left and right outer sides of the error display illumination lamp 6A, each illumination lamp 6B for notifying the occurrence of “winning” or the like or performing a light effect during the game is attached. Further, the front surface portion of the front cover member 4 is covered with an opaque synthetic resin front member 4A, and between the electric lamps 6A and 6B and the upper peripheral edge of the window portion 5 (not shown). Full color diodes are built in the left and right direction, and light effects are performed during the game.

  In addition, a key insertion portion 4B for operating a locking device (not shown) that locks the front frame 3 and the front cover member 4 is provided at the center on the right side of the front cover member 4. In order to open the front cover member 4, if a predetermined key is inserted into the key insertion portion 4B and rotated in a predetermined direction, the locked state of the locking device is released and only the front cover member 4 is opened.

  Further, below the front cover member 4, an upper dish 7 for receiving a prize ball paid out via a prize ball case 52 is provided on a synthetic resin plate 8 with a built-in speaker 7 </ b> A. The plate 8 is pivotally supported on the upper and lower sides of the left end edge, and is attached so that it can be opened by lowering a lever (not shown) provided inside after opening the front cover member 4. Further, operation buttons 7B and 7C of a card type ball lending machine and a card balance display device 7D are provided on the central front portion of the upper plate 7. A lower plate 9 is disposed under the upper plate 7. Further, the pachinko ball of the upper plate 7 is configured to be sent to the launching device 10 </ b> A connected to the operation handle 10 via a ball feeding mechanism (not shown) communicating with the upper plate 7.

  Next, referring to FIG. 2, the configuration of the game area on the game board 2 in the pachinko machine 1 will be described. The game area 11 is configured by arranging each structure such as a prize opening on a game board 2 made of a plate material having a predetermined thickness, and an annular rail 12 standing so as to surround the structure. This rail 12 forms an overlapping guide path 13 that guides the launched pachinko ball into the game area 11, and restricts the progress of the pachinko ball driven along the rail 12 on the right shoulder. Step 14.

  An opening is established in the approximate center of the game area 11, and a special symbol display device 18 is disposed on the front side of the opening. The special symbol display device 18 includes a decorative member 17 attached from the front side of the game board 2, a liquid crystal display (LCD) 19 attached from the back side of the game board 2, and the like. The liquid crystal display 19 is a liquid crystal panel that displays three variable symbols on the left, middle, and right, and a normal symbol display unit 20 that displays a normal symbol divided into left and right is formed in the lower left corner. Has been. An upper decorative member 17 </ b> A in which a frog character is formed on the front surface is attached to the front surface of the frame body member 17 </ b> B constituting the decorative member 17 above the front surface of the decorative member 17. A guide member 33 is attached to the inner bottom surface of the frame body member 17B.

  On the other hand, gates 23 and 24 are arranged on the left and right of the special symbol display device 18, respectively. Further, normal windmills 25 and 26 are provided between the gates 23 and 24 and the special symbol display device 18, and windmills in which electric lamps 27 </ b> A and 28 </ b> A are built in on both shoulder sides of the special symbol display device 18. 27 and 28 are provided. Further, shoulder electric decoration members 29 and 30 in which electric lamps 29A and 30A are incorporated are arranged outside the gates 23 and 24, respectively.

  Also, immediately below the special symbol display device 18, a start port 31 with a snake character drawn on the front is provided. The start port 31 is provided with a start port switch (not shown) for detecting the winning of the pachinko ball, and the special symbol displayed on the liquid crystal display 19 is changed by detecting the winning of the pachinko ball. When the special symbol is changed and the winning opening 31 is won, the winning number is stored in a first holding counter of a RAM provided on a main board 46 (see FIG. 3) described later and the number of confirmed changes is four. As deferred. Two first hold LEDs 34 for displaying the count value stored in the first hold counter are arranged on each of the left and right sides of the liquid crystal display 19.

  Each of the gates 23 and 24 is provided with a gate switch (not shown) for detecting the passage of the pachinko sphere, and the normal symbol of the normal symbol display unit 20 is changed by detecting the passage of the pachinko sphere. Then, when a pachinko ball enters the gate 23 or the gate 24 and the normal symbol of the normal symbol display unit 20 changes and then stops in a predetermined display mode (for example, “11”, “77” are aligned) In such a case, the tulip type accessory 31A provided at the upper part of the start port 31 is opened for a predetermined time (in the first embodiment, about 1 second), and the probability that a pachinko ball wins a prize at the start port 31 increases. .

  If the pachinko ball passes through the gates 23 and 24 while the normal symbol is changing, the number of passages is stored in the second hold counter of the RAM provided on the main board 46 (see FIG. 3). Held as a fixed number of changes. Then, four second hold LEDs 35 for displaying the count value stored in the second hold counter are arranged in the left-right horizontal direction at the upper edge of the upper decorative member 17A.

  A special winning device 41 is provided below the starting port 31. The special winning device 41 is formed with a large winning port 40 whose front surface is covered with an open / close door 39 having a wide lateral opening. In addition, on each of the left and right sides of the large winning opening 40, winning openings 42 and 43 that open upward are formed so as to protrude to the front side. In addition, under the winning holes 42 and 43, electric lamps 42A and 43A are built in, respectively.

  In addition, lower winning holes 44 and 45 having electric lamps 44A and 45A are arranged above both sides of the special winning device 41 and communicated with a not-shown prize ball bowl on the back of the game board 2. A lower prize opening switch (not shown) for detecting a prize at the lower prize winning openings 44 and 45 is provided. Further, an out port 15 is opened along the rail 12 directly under the special prize winning device 41. Further, in such a game area 11 surrounded by the rails 12, a plurality of nails are driven together with the above components to form a complicated flow path of the pachinko ball.

As shown in FIG. 3, a prize ball tank 50 opened upward is fixed to a mechanism set board 51 at the uppermost back side of the pachinko machine 1. The prize ball tank 50 has a communication hole formed in an inclined bottom surface, and a tank rail 53 that forms a passage through which the pachinko balls are aligned and flowed out in two rows below the communication hole to send the pachinko ball to the prize ball case 52. Installed.
A resin center cover 54 that covers a liquid crystal display (LCD) 19 and the like is attached to the lower side of the tank rail 53. On the inner side of the back surface of the center cover 54, a sound control board 64 for driving and controlling the speaker 7A, a lamp control board 65 for driving and controlling the electric lamps 6A and 6B, and a display control for driving and controlling the LCD 19 and the like. A substrate 66 is attached. In addition, a substrate case 55 in which a main substrate 46 for controlling the gaming operation of the pachinko machine 1 is built is disposed below the center cover 54. Also, below the substrate case 55, a lower tray box 56 that receives a prize ball overflowing from the upper plate 7 and guides it to the lower plate 9 is attached to the back side of the front frame 3 with bolts.

  In addition, on the lower right rear side of the board case 55 in which the main board 46 is stored, control boards such as the main board 46, the sound control board 64, the lamp control board 65, the display control board 66, and the electric components are used. A power supply unit 57 that generates and supplies a plurality of predetermined voltages (in the first embodiment, AC 24V, DC + 21V, DC + 12V, DC + 5V) is provided. In addition, a power switch 59, a RAM clear switch 58, which will be described later, and a power unit fuse 60 are disposed in the lower right corner of the rear side surface of the power unit 57.

Next, a schematic circuit configuration relating to system reset and user reset of the main board 46 and the power supply unit 57 of the pachinko machine 1 configured as described above will be described with reference to FIG.
As shown in FIG. 4, a CPU 461 composed of a microcomputer is disposed on the main board 46. The CPU 461 is provided with a ROM 462 in which parameters and various control programs are stored in advance. Further, a RAM 463 provided with a storage area for temporarily storing various counter values when the pachinko ball wins at the start port 31 or when the pachinko ball passes through the gates 23 and 24, and a work area for various data processing. Is provided.
The main board 46 is connected to the + 5V power supply of the main board 46 supplied from the power supply unit 57, monitors the supply state of the + 5V power supply, and detects the start of power supply to the main board 46. Outputs a supply start signal (for example, a normal low level voltage is output, and when a supply start of power is detected, a high level voltage pulse signal is output). Has been placed. The output terminal of the power monitoring system reset generation circuit 65 is connected to the system reset terminal of the CPU 461. When the supply start signal is input from the power monitoring system reset generation circuit 65, the CPU 461 executes a system reset process described later (see FIG. 5).

  The main board 46 is provided with a reset interrupt generation circuit 66 that outputs a high-level interrupt signal at a predetermined time interval (in the first embodiment, the time interval is approximately 2 msec to 4 msec). Yes. The output terminal of the reset interrupt generation circuit 66 is connected to the user reset terminal of the CPU 461. Then, when an interrupt signal is input from the reset interrupt generation circuit 66, the CPU 461 executes a user reset process described later (see FIG. 5).

The power supply unit 57 is provided with a RAM clear switch 58. One terminal of the RAM clear switch 58 is grounded to the power supply unit 57, and the other terminal is connected to the RAM clear terminal of the CPU 461. When the user presses the RAM clear switch 58, the RAM clear terminal of the CPU 461 is grounded to the power supply unit 57 and a low level voltage signal is input.
Further, the power supply unit 57 is provided with a +5 V output terminal for backup power supply, and is connected to the RAM backup terminal of the CPU 461.
The ground terminal (GND terminal) of the CPU 461 is grounded to the power supply unit 57. Further, the backup power source + 5V power source of the power source unit 57 is grounded via the electrolytic capacitor 67.

Next, system reset processing and user reset processing executed by the CPU 461 will be described with reference to FIG.
First, a system reset process executed by the CPU 461 when a supply start signal is input from the power monitoring system reset generation circuit 65 to the system reset terminal will be described.
As shown in FIG. 5, when a supply start signal is input from the power monitoring system reset generation circuit 65 to the system reset terminal, the CPU 461 first performs a security check in step (hereinafter referred to as S) 1. This security check is a check for determining whether each program (such as a program used for executing the game control process) stored in the ROM 462 is genuine. If the power supply is stopped during the security check in S1, the processes after S1 are executed again at the start of power supply.
Subsequently, in S2, the CPU 461 executes determination processing for determining whether or not the RAM clear switch 58 has been pressed. When it is determined that the RAM clear switch 58 has been pressed, that is, a low level voltage signal has been input to the RAM clear terminal (S2: YES), the CPU 461 performs initialization processing of the RAM 463 in S3. . That is, “0” is assigned to various counters of the RAM 463 to be initialized, and the count values of the various counters when the pachinko ball wins the start opening 31 or when the pachinko ball passes through the gates 23 and 24 are stored. The parameter storage area to be initialized is initialized, and various data stored in the RAM 463 are erased before the power is stopped. Therefore, the pachinko machine 1 returns to the state at the time of activation. If the power supply is stopped during the initialization process in S3, the processes after S1 are executed again at the start of power supply.

In S4, the CPU 461 executes game-related processing in accordance with various game programs stored in the ROM 462 (for example, acquisition processing program for count values of various counters when winning the starting port 31), and then in S5 described later. Execute the process. If the power supply is stopped during the game related process in S4, the processes after S1 are executed again at the start of power supply.
On the other hand, if it is determined in S2 that the RAM clear switch 58 has not been pressed, that is, a low level voltage signal has not been input to the RAM clear terminal (S2: NO), the CPU 461 initializes the RAM 463. Without performing this, the processes after S4 are executed. Therefore, the pachinko game is continued based on various data stored in the RAM 463 before the power supply is stopped.

Next, a user reset process executed by the CPU 461 when an interrupt signal is input from the reset interrupt generation circuit 66 to the user reset terminal will be described.
As shown in FIG. 5, when an interrupt signal is input from the reset interrupt generation circuit 66 to the user reset terminal, the CPU 461 performs a determination process for determining whether or not the RAM clear switch 58 is pressed in S2. Execute. When it is determined that the RAM clear switch 58 has been pressed, that is, a low level voltage signal has been input to the RAM clear terminal (S2: YES), the CPU 461 performs initialization processing of the RAM 463 in S3. . That is, “0” is assigned to various counters of the RAM 463 to be initialized, and the count values of the various counters when the pachinko ball wins the start opening 31 or when the pachinko ball passes through the gates 23 and 24 are stored. The parameter storage area to be initialized is initialized, and various data stored in the RAM 463 are erased before the power is stopped. Therefore, the pachinko machine 1 returns to the state at the time of activation.

In S <b> 4, the CPU 461 executes game-related processing in accordance with various game programs stored in the ROM 462 (for example, a process for acquiring count values of various counters when winning at the start port 31).
In S5, the CPU 461 waits for an interrupt signal to be input from the reset interrupt generation circuit 66. When the interrupt signal is input, the CPU 461 executes the processing from S2 onward again.
On the other hand, if it is determined in S2 that the RAM clear switch 58 has not been pressed, that is, a low level voltage signal has not been input to the RAM clear terminal (S2: NO), the CPU 461 initializes the RAM 463. Without performing this, the processes after S4 are executed. Therefore, the pachinko game is continued based on various data stored in the RAM 463 before the interrupt signal is input.

  Here, the RAM 463 functions as a fluctuation data storage unit. The CPU 461 functions as game control means. The power monitoring system reset generation circuit 65 functions as power monitoring means. The reset interrupt generation circuit 66 functions as an interrupt signal output unit. The RAM clear switch 58 functions as first initialization instruction means.

  Therefore, in the pachinko machine 1 according to the first embodiment, the RAM 463 is initialized only when the user depresses the RAM clear switch 58 at the start of power supply, that is, at the time of start-up or power recovery. Therefore, if the user does not press down the RAM clear switch 58 at the start of power supply, the CPU 461 can start executing the game control with the data stored in the RAM 463 before the power supply is stopped. The gaming state of 1 can be reliably restored to the gaming state before the power supply is stopped. Even if power supply noise or the like is erroneously input to the system reset terminal of the CPU 461, if the user does not press the RAM clear switch 58, the data stored in the RAM 463 is not initialized, so the game of the pachinko machine 1 The state can be reliably restored to the gaming state before the power supply noise is input.

Further, when an interrupt signal is input from the reset interrupt generation circuit 66 at a predetermined time interval (for example, approximately 2 msec to 4 msec interval), the CPU 461 stores the RAM 463 only when the user presses the RAM clear switch 58. Since the game control is started after the initialization, the user can initialize the RAM 463 by depressing the RAM clear switch 58 and initialize the game state without stopping the power supply even during the game. it can. Even if power supply noise or the like is erroneously input as an interrupt signal to the user reset terminal of the CPU 461, if the user does not press the RAM clear switch 58, the data stored in the RAM 463 is not initialized. The gaming state of the machine 1 can be reliably restored to the gaming state before the power supply noise is input, that is, the gaming state before the power supply noise is input can be maintained and the pachinko game can be reliably continued. .
Furthermore, the CPU 461 performs a security check at the start of power supply, that is, at the time of start-up or restoration of a power failure, so that the malfunction of the CPU 461 can be reliably prevented.

Next, a pachinko machine according to a second embodiment will be described with reference to FIGS. In addition, the same code | symbol as the pachinko machine 1 which concerns on the said 1st Embodiment shows the same part as the pachinko machine 1 which concerns on the said 1st Embodiment, or an equivalent part.
The overall configuration of the pachinko machine according to the second embodiment and the configuration of the control system are substantially the same as the pachinko machine 1 according to the first embodiment. The control process of the pachinko machine according to the second embodiment is substantially the same control process as the control process of the pachinko machine 1 according to the first embodiment.
However, as shown in FIG. 6, the main board 46 of the pachinko machine according to the second embodiment is connected to a + 5V power source supplied from the power supply unit 57, and the + 5V power source voltage is equal to or higher than a predetermined voltage (for example, about 3V When it is detected that the voltage has reached ˜4.5 V or higher, a voltage detection signal is output (for example, a normal low level voltage is output. A level voltage pulse signal is output once.) A power-on-rising monitoring one-shot pulse circuit 68 is arranged. The output terminal of the power supply rise monitoring one-shot pulse circuit 68 is connected to the power supply rise monitoring terminal of the CPU 461.

Next, system reset processing and user reset processing executed by the CPU 461 on the main board 46 configured as described above will be described with reference to FIG.
First, a system reset process executed by the CPU 461 when a supply start signal is input from the power monitoring system reset generation circuit 65 to the system reset terminal will be described.
As shown in FIG. 7, when a supply start signal is input from the power monitoring system reset generation circuit 65 to the system reset terminal, the CPU 461 first performs a security check in S11. This security check is a check for determining whether each program (such as a program used for executing the game control process) stored in the ROM 462 is genuine. If the power supply is stopped during the security check in S11, the processes after S11 are executed again at the start of power supply.

  Subsequently, in S12, the CPU 461 executes a determination process for determining whether or not the RAM clear switch 58 has been pressed. When it is determined that the RAM clear switch 58 has been pressed, that is, a low level voltage signal has been input to the RAM clear terminal (S12: YES), in S13, the CPU 461 causes the power supply rise monitoring one-shot pulse circuit. A determination process for determining whether a high-level voltage pulse signal is input from 68 is executed. If it is determined that a high-level voltage pulse signal has been input from the power supply rise monitoring one-shot pulse circuit 68 (S13: YES), the CPU 461 performs initialization processing of the RAM 463 in S14. That is, “0” is substituted into various counters of the RAM 463 to be initialized, and the count values of the various counters when the pachinko ball wins the start opening 31 or when the pachinko balls pass through the gates 23 and 24 are stored. The parameter storage area to be initialized is initialized, and various data stored in the RAM 463 are erased before the power is stopped. Therefore, the pachinko machine returns to the state at startup. If the power supply is stopped during the initialization process in S14, the processes after S11 are executed again at the start of power supply.

In S15, the CPU 461 executes game-related processing in accordance with various game programs stored in the ROM 462 (for example, a process for acquiring count values of various counters when winning at the start port 31), and then in S16 described later. Execute the process. If the power is stopped during the game-related process in S15, the processes after S11 are executed again at the start of power supply.
On the other hand, if it is determined in S12 that the RAM clear switch 58 has not been pressed, that is, no low level voltage signal is input to the RAM clear terminal (S12: NO), the CPU 461 initializes the RAM 463. Without performing this, the processes after S15 are executed. Therefore, the pachinko game is continued based on various data stored in the RAM 463 before the power supply is stopped.
On the other hand, when a high-level voltage pulse signal is not input from the power-on-rising monitoring one-shot pulse circuit 68 at S13 (S13: NO), the CPU 461 does not initialize the RAM 463 and performs the processes after S15. Execute. Therefore, the pachinko game is continued based on various data stored in the RAM 463 before the power supply is stopped.

Next, a user reset process executed by the CPU 461 when an interrupt signal is input from the reset interrupt generation circuit 66 to the user reset terminal will be described.
As shown in FIG. 7, when an interrupt signal is input from the reset interrupt generation circuit 66 to the user reset terminal, the CPU 461 performs a determination process for determining whether or not the RAM clear switch 58 is pressed in S12. Execute. When it is determined that the RAM clear switch 58 has been pressed, that is, a low level voltage signal has been input to the RAM clear terminal (S12: YES), in S13, the CPU 461 causes the power supply rise monitoring one-shot pulse circuit. A determination process for determining whether a high-level voltage pulse signal is input from 68 is executed. If it is determined that a high-level voltage pulse signal is input from the power supply rise monitoring one-shot pulse circuit 68 (S13: YES), the CPU 461 performs initialization processing of the RAM 463 in S14. That is, “0” is assigned to various counters of the RAM 463 to be initialized, and the count values of the various counters when the pachinko ball wins the start opening 31 or when the pachinko ball passes through the gates 23 and 24 are stored. The parameter storage area to be initialized is initialized, and various data stored in the RAM 463 are erased before the power is stopped. Therefore, the pachinko machine returns to the state at startup.

In S <b> 15, the CPU 461 executes game-related processing in accordance with various game programs stored in the ROM 462 (for example, a process for acquiring count values of various counters when winning at the start port 31).
In S16, the CPU 461 waits for the interrupt signal from the reset interrupt generation circuit 66 to be input to the user reset terminal. If the interrupt signal is input, the CPU 461 executes the processing from S12 again. To do.
On the other hand, if it is determined in S12 that the RAM clear switch 58 has not been pressed, that is, no low level voltage signal is input to the RAM clear terminal (S12: NO), the CPU 461 initializes the RAM 463. Without performing this, the processes after S15 are executed. Therefore, the pachinko game is continued based on various data stored in the RAM 463 before the interrupt signal is input.
On the other hand, when a high-level voltage pulse signal is not input from the power-on-rising monitoring one-shot pulse circuit 68 at S13 (S13: NO), the CPU 461 does not initialize the RAM 463 and performs the processes after S15. Execute. Therefore, the pachinko game is continued based on various data stored in the RAM 463 before the interrupt signal is input.

  Here, the RAM 463 functions as a fluctuation data storage unit. The CPU 461 functions as game control means. The power monitoring system reset generation circuit 65 functions as power monitoring means. The reset interrupt generation circuit 66 functions as an interrupt signal output unit. The RAM clear switch 58 functions as first initialization instruction means. The power supply rising monitoring one-shot pulse circuit 68 functions as first signal output means.

  Therefore, in the pachinko machine according to the second embodiment, the user presses the RAM clear switch 58 and starts the power supply monitoring one-shot pulse circuit 68 at the start of power supply, that is, at the time of start-up or power recovery. Since the RAM 463 is initialized only when a high-level voltage pulse signal is input to the power supply rise monitoring terminal, if the user does not press the RAM clear switch 58 at the start of power supply, the CPU 461 supplies power. The game control can be started with the data stored in the RAM 463 before the game stops, and the game state of the pachinko machine can be reliably restored to the game state before the power supply is stopped. Even if power supply noise or the like is erroneously input to the system reset terminal of the CPU 461, if the user does not press the RAM clear switch 58, the data stored in the RAM 463 is not initialized. Can be reliably restored to the gaming state before the power supply noise is input. Further, at the time of starting the supply of power, that is, at the time of starting or recovering from a power failure, the user depresses the RAM clear switch 58 and a high-level voltage pulse signal is supplied from the power-on monitoring one-shot pulse circuit 68. Since the CPU 461 initializes the RAM 463 only when it is input to the monitoring terminal, the initialization of the RAM 463 can be started after the power supply voltage supplied to the CPU 461 has sufficiently increased, and the RAM 463 is surely initialized. be able to.

When the interrupt signal is input to the user reset terminal from the reset interrupt generation circuit 66 at a predetermined time interval (for example, approximately 2 msec to 4 msec interval), the user presses the RAM clear switch 58, and Only when a high-level voltage pulse signal is input from the power supply rise monitoring one-shot pulse circuit 68 to the power supply rise monitoring terminal, the execution of game control is started after the RAM 463 is initialized. Therefore, even if power supply noise or the like is erroneously input as an interrupt signal to the user reset terminal of the CPU 461, at least one of the low level signal to the RAM clear terminal and the high level voltage pulse signal of the power supply rise monitoring terminal is If it is not input, the data stored in the RAM 463 is not initialized. Therefore, the gaming state of the pachinko machine is surely restored to the gaming state before the power supply noise is input, that is, the power supply noise is reduced. The game state before being input can be maintained and the game can be surely continued. Further, even if a user accidentally presses the RAM clear switch 58 and a low level signal is input to the RAM clear terminal during the game, a high level voltage pulse signal is monitored from the power source rise monitoring one-shot pulse circuit 68. Since it is not input to the terminal, the data stored in the RAM 463 is not initialized, and the gaming state of the pachinko machine is reliably restored to the gaming state before the low level signal is input to the RAM clear terminal, That is, it is possible to maintain the game state before the low level signal is input to the RAM clear terminal and to continue the game with certainty.
Further, since the power supply monitoring system reset generation circuit 65, the reset interrupt generation circuit 66, and the power supply rise monitoring one-shot pulse circuit 68 are provided on the main board 46 on which the CPU 461 is mounted, the wiring length to the CPU 461 is shortened. Therefore, the input of power supply noise can be prevented more reliably.
Furthermore, the CPU 461 performs a security check at the start of power supply, that is, at the time of start-up or restoration of a power failure, so that the malfunction of the CPU 461 can be reliably prevented.

Next, a pachinko machine according to a third embodiment will be described with reference to FIGS. In addition, the same code | symbol as the pachinko machine 1 which concerns on the said 1st Embodiment shows the same part as the pachinko machine 1 which concerns on the said 1st Embodiment, or an equivalent part.
The overall configuration of the pachinko machine according to the third embodiment and the configuration of the control system are substantially the same as the pachinko machine 1 according to the first embodiment. Moreover, the control process of the pachinko machine according to the third embodiment is substantially the same as the control process of the pachinko machine 1 according to the first embodiment.

  However, as shown in FIG. 8, the main board 46 of the pachinko machine according to the third embodiment is connected to a + 5V power supply supplied from the power supply unit 57, and the + 5V power supply voltage is equal to or higher than a predetermined voltage (for example, about 3V When it is detected that the voltage is higher than or equal to 4.5V or higher, a voltage detection signal is output (for example, a normal low level voltage is output. A level voltage pulse signal is output once.) A power-on-rising monitoring one-shot pulse circuit 68 is arranged. An AND circuit 69 is arranged on the main board 46. A NAND circuit 70 is disposed on the main board 46.

The output terminal of the power supply rising monitoring one-shot pulse circuit 68 is connected to one input terminal of the AND circuit 69. The other terminal of the RAM clear switch 58 is connected to the input terminal of the NAND circuit 70, and the output terminal of the NAND circuit 70 is connected to one input terminal of the AND circuit 69. The output terminal of the AND circuit 69 is connected to the RAM clear terminal of the CPU 461. The other terminal of the RAM clear switch 58 connected to the input terminal of the NAND circuit 70 is connected to the +5 V power supply of the main board 46 on the input terminal side of the NAND circuit 70 on the main board 46. Has been pulled up through.
As a result, a high-level voltage pulse signal is input to one input terminal of the AND circuit 69 from the power-on-rising monitoring one-shot pulse circuit 68, and the RAM clear switch 58 is pressed and one input of the AND circuit 69 is input. Only when a high level voltage signal is input to the terminal, a high level voltage pulse signal is output from the AND circuit 69 to the RAM clear terminal of the CPU 461.

Next, system reset processing and user reset processing executed by the CPU 461 on the main board 46 configured as described above will be described with reference to FIG.
First, a system reset process executed by the CPU 461 when a supply start signal is input from the power monitoring system reset generation circuit 65 to the system reset terminal will be described.
As shown in FIG. 9, when a supply start signal is input from the power monitoring system reset generation circuit 65, the CPU 461 first performs a security check in S21. This security check is a check for determining whether each program (such as a program used for executing the game control process) stored in the ROM 462 is genuine. If the power supply is stopped during the security check in S21, the processes after S21 are executed again at the start of power supply.

Subsequently, in S22, the CPU 461 inputs a high-level voltage pulse signal from the power-on-rising monitoring one-shot pulse circuit 68 to one input terminal of the AND circuit 69, and the RAM clear switch 58 is pressed down to perform the AND operation. A determination process is performed to determine whether a high level voltage signal is input to one input terminal of the circuit 69, that is, to determine whether a high level voltage pulse signal is input to the RAM clear terminal.
If a high-level voltage pulse signal is input to the RAM clear terminal (S22: YES), the CPU 461 performs initialization processing of the RAM 463 in S23. That is, “0” is assigned to various counters of the RAM 463 to be initialized, and the count values of the various counters when the pachinko ball wins the start opening 31 or when the pachinko ball passes through the gates 23 and 24 are stored. The parameter storage area to be initialized is initialized, and various data stored in the RAM 463 are erased before the power is stopped. Therefore, the pachinko machine returns to the state at startup. If the power supply is stopped during the initialization process in S23, the processes after S21 are executed again at the start of power supply.

In S24, the CPU 461 executes game-related processing in accordance with various game programs stored in the ROM 462 (for example, a process for acquiring count values of various counters when winning at the start port 31), and then in S25 described later. Execute the process. If the power is stopped during the game-related process in S24, the processes after S21 are executed again at the start of power supply.
On the other hand, if it is determined in S22 that the RAM clear switch 58 has not been pressed, that is, a high-level voltage pulse signal has not been input to the RAM clear terminal (S22: NO), the CPU 461 initializes the RAM 463. The processing after S24 is executed without conversion. Therefore, the pachinko game is continued based on various data stored in the RAM 463 before the power supply is stopped.

Next, a user reset process executed by the CPU 461 when an interrupt signal is input from the reset interrupt generation circuit 66 to the user reset terminal will be described.
As shown in FIG. 9, when an interrupt signal is input from the reset interrupt generation circuit 66 to the user reset terminal, the CPU 461 outputs a high-level voltage pulse signal from the power supply rise monitoring one-shot pulse circuit 68 in S22. Is input to one input terminal of the AND circuit 69, and whether or not the RAM clear switch 58 is pressed and a high-level voltage signal is input to the one input terminal of the AND circuit 69 is determined. A determination process for determining whether or not a high-level voltage pulse signal is input to the RAM clear terminal is executed.
Since it is not at the start of power supply, when a high-level voltage pulse signal is not input to the RAM clear terminal (S22: NO), in S24, the CPU 461 stores various game programs stored in the ROM 462 (for example, The game-related processing is executed in accordance with the count value acquisition processing program of the various counters when winning at the starting port 31).
In S25, the CPU 461 waits for the interrupt signal from the reset interrupt generation circuit 66 to be input to the user reset terminal. If the interrupt signal is input, the CPU 461 executes the processing from S22 onward again. To do.

  Here, the RAM 463 functions as a fluctuation data storage unit. The CPU 461 functions as game control means. The power monitoring system reset generation circuit 65 functions as power monitoring means. The reset interrupt generation circuit 66 functions as an interrupt signal output unit. The RAM clear switch 58, the pull-up resistor 71, and the NAND circuit 70 constitute second initialization instruction means. The power supply rising monitoring one-shot pulse circuit 68 functions as third signal output means. The AND circuit 69 functions as fourth signal output means.

  Therefore, in the pachinko machine according to the third embodiment, at the time of starting the supply of power, that is, at the time of starting or recovering from a power failure, the high-level voltage pulse signal is output from the power supply rising monitoring one-shot pulse circuit 68 to the AND circuit. The AND circuit 69 is connected to the CPU 461 only when a high-level voltage signal is input to one input terminal of the AND circuit 69 when the RAM clear switch 58 is pressed. Since a high-level voltage pulse signal is output to the RAM clear terminal, if the user does not press down the RAM clear switch 58 at the start of power supply, the game control is performed using the data stored in the RAM 463 before the power supply is stopped. The game state of the pachinko machine can be reliably restored to the state before the power supply was stopped. Can. Even if power supply noise or the like is erroneously input to the system reset terminal of the CPU 461, if the user does not press the RAM clear switch 58, the data stored in the RAM 463 is not initialized. Can be reliably restored to the gaming state before the power supply noise is input. Further, at the start of power supply, that is, at the time of start-up or recovery from a power failure, a high-level voltage pulse signal is supplied from the power supply rise monitoring one-shot pulse circuit 68 to the AND circuit 69. Only when the RAM clear switch 58 is pressed and a high level voltage signal is input to one input terminal of the AND circuit 69, the AND circuit 69 outputs a high level to the RAM clear terminal of the CPU 461. Since the CPU 461 initializes the RAM 463 when the voltage pulse signal is inputted, the initialization of the RM 463 can be started after the power supply voltage supplied to the CPU 461 has sufficiently increased, and the RAM 463 is surely initialized. Can do.

In addition, when an interrupt signal is input from the reset interrupt generation circuit 66 at a predetermined time interval (for example, approximately 2 msec to 4 msec interval), the CPU 461 outputs a high level voltage pulse from the power supply rise monitoring one-shot pulse circuit 68. Only when a signal is input to one input terminal of the AND circuit 69 and a high-level voltage signal is input to one input terminal of the AND circuit 69 when the RAM clear switch 58 is pressed, the RAM of the CPU 461 After a high level voltage pulse signal is input from the AND circuit 69 to the clear terminal and the RAM 463 is initialized, execution of the game control is started. For this reason, even if power supply noise or the like is erroneously input to the user reset terminal of the CPU 461 as an interrupt signal, a high level voltage pulse signal from the power supply rise monitoring one-shot pulse circuit 68 and a high level voltage from the NAND circuit 70 are detected. If neither the voltage signal nor the voltage signal is input to the input terminal of the AND circuit 69, the data stored in the RAM 463 is not initialized. Therefore, the gaming state of the pachinko machine before the power supply noise is input. It is possible to reliably resume the game, that is, to maintain the game state before the power supply noise is input and to continue the game with certainty. In addition, when a user accidentally presses the RAM clear switch 58 and a high level voltage pulse signal is input to the AND circuit 69 during the game, a high level voltage pulse is output from the power supply rise monitoring one shot pulse circuit 68. Since no signal is input to one input terminal of the AND circuit 69 and a high-level voltage pulse signal is not input from the AND circuit 69 to the RAM clear terminal, the data stored in the RAM 463 is not initialized, and the pachinko machine Can be reliably restored to the game state before the RAM clear switch 58 is pressed, that is, the game state before the RAM clear switch 58 is pressed is maintained and the game is reliably continued. it can.
Further, by providing the AND circuit 69, the CPU 461 performs a process of determining whether or not the RAM clear switch 58 is pressed and a high-level voltage pulse signal is input from the power-on monitoring one-shot pulse circuit 68. There is no need to perform this, and the game control processing program can be reduced in size, and the memory capacity of the ROM 462 can be reduced.
In addition, the power supply monitoring system reset generation circuit 65, the power supply rise monitoring one-shot pulse circuit 68, the AND circuit 69, the NAND circuit 70, and the pull-up resistor 71 are disposed on the main board 46 on which the CPU 461 is mounted. Thus, the input of power supply noise can be more reliably prevented.
Furthermore, the CPU 461 performs a security check at the start of power supply, that is, at the time of start-up or restoration of a power failure, so that the malfunction of the CPU 461 can be reliably prevented.

Next, a pachinko machine according to a fourth embodiment will be described with reference to FIGS. In addition, the same code | symbol as the pachinko machine 1 which concerns on the said 1st Embodiment shows the same part as the pachinko machine 1 which concerns on the said 1st Embodiment, or an equivalent part.
The overall configuration of the pachinko machine according to the fourth embodiment and the configuration of the control system are substantially the same as the pachinko machine 1 according to the first embodiment. Moreover, the control process of the pachinko machine according to the fourth embodiment is substantially the same as the control process of the pachinko machine 1 according to the first embodiment.
However, as shown in FIG. 10, the main board 46 of the pachinko machine according to the fourth embodiment is connected to the output terminal of the power monitoring system reset generation circuit 65, and the supply start signal of the power monitoring system reset generation circuit 65 Is input (for example, when a high-level voltage pulse signal is input), a voltage detection signal is output (for example, a normal low-level voltage is output and the voltage exceeds a predetermined voltage) Is detected, a high-level voltage pulse signal is output once.) A power supply rise monitoring one-shot pulse circuit 68 is provided. The output terminal of the power supply rise monitoring one-shot pulse circuit 68 is connected to the power supply rise monitoring terminal of the CPU 461.

Next, system reset processing and user reset processing executed by the CPU 461 on the main board 46 configured as described above will be described with reference to FIG.
First, a system reset process executed by the CPU 461 when a supply start signal is input from the power monitoring system reset generation circuit 65 to the system reset terminal will be described.
As shown in FIG. 11, when a supply start signal is input from the power monitoring system reset generation circuit 65 to the system reset terminal, the CPU 461 first performs a security check in S31. This security check is a check for determining whether each program (such as a program used for executing the game control process) stored in the ROM 462 is genuine. If the power supply is stopped during the security check in S31, the processes after S31 are executed again at the start of power supply.

  Subsequently, in S32, the CPU 461 executes determination processing for determining whether or not the RAM clear switch 58 has been pressed. When it is determined that the RAM clear switch 58 has been pressed, that is, a low level voltage signal has been input to the RAM clear terminal (S32: YES), in S33, the CPU 461 causes the power supply rise monitoring one-shot pulse circuit. A determination process for determining whether a high-level voltage pulse signal from 68 has been input to the power supply rise monitoring terminal is executed. If it is determined that a high-level voltage pulse signal is input from the power supply rise monitoring one-shot pulse circuit 68 to the power supply rise monitoring terminal (S33: YES), in S34, the CPU 461 performs initialization processing of the RAM 463. . That is, “0” is substituted into various counters of the RAM 463 to be initialized, and the count values of the various counters when the pachinko ball wins the start opening 31 or when the pachinko balls pass through the gates 23 and 24 are stored. The parameter storage area to be initialized is initialized, and various data stored in the RAM 463 are erased before the power is stopped. Therefore, the pachinko machine returns to the state at startup. If the power supply is stopped during the initialization process in S34, the processes after S31 are executed again at the start of power supply.

In S35, the CPU 461 executes game-related processing in accordance with various game programs stored in the ROM 462 (for example, a process for acquiring count values of various counters when winning at the start port 31), and then in S36 described later. Execute the process. If the power supply is stopped during the game related process in S35, the processes after S31 are executed again when the power supply is started.
On the other hand, when it is determined in S32 that the RAM clear switch 58 is not pressed, that is, a low level voltage signal is not input to the RAM clear terminal (S32: NO), the CPU 461 initializes the RAM 463. Without performing this, the processing after S35 is executed. Therefore, the pachinko game is continued based on various data stored in the RAM 463 before the power supply is stopped.
On the other hand, when a high level voltage pulse signal is not input from the power supply rising monitoring one-shot pulse circuit 68 to the power supply rising monitoring terminal in S33 (S33: NO), the CPU 461 does not initialize the RAM 463, The processing after S35 is executed. Therefore, the pachinko game is continued based on various data stored in the RAM 463 before the power supply is stopped.

Next, a user reset process executed by the CPU 461 when an interrupt signal is input from the reset interrupt generation circuit 66 to the user reset terminal will be described.
As shown in FIG. 11, when an interrupt signal is input from the reset interrupt generation circuit 66 to the user reset terminal, the CPU 461 performs a determination process for determining whether or not the RAM clear switch 58 is pressed in S32. Execute. When it is determined that the RAM clear switch 58 has been pressed, that is, a low level voltage signal has been input to the RAM clear terminal (S32: YES), in S33, the CPU 461 causes the power supply rise monitoring one-shot pulse circuit. A determination process for determining whether a high-level voltage pulse signal from 68 has been input to the power supply rise monitoring terminal is executed. If it is determined that a high-level voltage pulse signal is input from the power supply rise monitoring one-shot pulse circuit 68 to the power supply rise monitoring terminal (S33: YES), in S34, the CPU 461 performs initialization processing of the RAM 463. . That is, “0” is assigned to various counters of the RAM 463 to be initialized, and the count values of the various counters when the pachinko ball wins the start opening 31 or when the pachinko ball passes through the gates 23 and 24 are stored. The parameter storage area to be initialized is initialized, and various data stored in the RAM 463 are erased before the power is stopped. Therefore, the pachinko machine returns to the state at startup.

In S <b> 35, the CPU 461 executes game-related processing in accordance with various game programs stored in the ROM 462 (for example, a process for acquiring count values of various counters when winning at the start port 31).
In S36, the CPU 461 waits for the interrupt signal from the reset interrupt generation circuit 66 to be input to the user reset terminal. When the interrupt signal is input, the CPU 461 executes the processing from S32 again. To do.
On the other hand, when it is determined in S32 that the RAM clear switch 58 is not pressed, that is, a low level voltage signal is not input to the RAM clear terminal (S32: NO), the CPU 461 initializes the RAM 463. Without performing this, the processing after S35 is executed. Therefore, the pachinko game is continued based on various data stored in the RAM 463 before the interrupt signal is input.
On the other hand, when a high level voltage pulse signal is not input from the power supply rising monitoring one-shot pulse circuit 68 to the power supply rising monitoring terminal in S33 (S33: NO), the CPU 461 does not initialize the RAM 463, The processing after S35 is executed. Therefore, the pachinko game is continued based on various data stored in the RAM 463 before the interrupt signal is input.

  Here, the RAM 463 functions as a fluctuation data storage unit. The CPU 461 functions as game control means. The power monitoring system reset generation circuit 65 functions as power monitoring means. The reset interrupt generation circuit 66 functions as an interrupt signal output unit. The RAM clear switch 58 functions as first initialization instruction means. The power supply rising monitoring one-shot pulse circuit 68 functions as second signal output means.

  Therefore, in the pachinko machine according to the fourth embodiment, the user depresses the RAM clear switch 58 and starts the power supply monitoring one-shot pulse circuit 68 at the start of power supply, that is, at the time of start-up or power recovery. Since the RAM 463 is initialized only when a high-level voltage pulse signal is input to the power supply rise monitoring terminal, if the user does not press the RAM clear switch 58 at the start of power supply, the CPU 461 supplies power. The game control can be started with the data stored in the RAM 463 before the game stops, and the game state of the pachinko machine can be reliably restored to the game state before the power supply is stopped. Even if power supply noise or the like is erroneously input to the system reset terminal of the CPU 461, if the user does not press the RAM clear switch 58, the data stored in the RAM 463 is not initialized. Can be reliably restored to the gaming state before the power supply noise is input. Further, at the time of starting the supply of power, that is, at the time of starting or recovering from a power failure, the user depresses the RAM clear switch 58 and a high-level voltage pulse signal is supplied from the power-on monitoring one-shot pulse circuit 68. Since the CPU 461 initializes the RAM 463 only when it is input to the monitoring terminal, the initialization of the RAM 463 can be started after the power supply voltage supplied to the CPU 461 has sufficiently increased, and the RAM 463 is surely initialized. be able to.

When the interrupt signal is input to the user reset terminal from the reset interrupt generation circuit 66 at a predetermined time interval (for example, approximately 2 msec to 4 msec interval), the user presses the RAM clear switch 58, and Only when a high-level voltage pulse signal is input from the power supply rise monitoring one-shot pulse circuit 68 to the power supply rise monitoring terminal, the execution of game control is started after the RAM 463 is initialized. Therefore, even if power supply noise or the like is erroneously input as an interrupt signal to the user reset terminal of the CPU 461, at least one of the low level signal to the RAM clear terminal and the high level voltage pulse signal of the power supply rise monitoring terminal is If it is not input, the data stored in the RAM 463 is not initialized. Therefore, the gaming state of the pachinko machine is surely restored to the gaming state before the power supply noise is input, that is, the power supply noise is reduced. The game state before being input can be maintained and the game can be surely continued. Further, even if a user accidentally presses the RAM clear switch 58 and a low level signal is input to the RAM clear terminal during the game, a high level voltage pulse signal is monitored from the power source rise monitoring one-shot pulse circuit 68. Since it is not input to the terminal, the data stored in the RAM 463 is not initialized, and the gaming state of the pachinko machine is reliably restored to the gaming state before the low level signal is input to the RAM clear terminal, That is, it is possible to maintain the game state before the low level signal is input to the RAM clear terminal and to continue the game with certainty.
The power supply rise monitoring one-shot pulse circuit 68 outputs a high level voltage pulse signal to the power supply rise monitoring terminal on condition that a supply start signal is input from the power supply monitoring system reset generation circuit 65. A circuit for monitoring whether or not the supply start voltage has become equal to or higher than a predetermined voltage is not required, and the power supply rise monitoring one-shot pulse circuit 68 can be reduced in size and cost.
Further, since the power supply monitoring system reset generation circuit 65 and the power supply rise monitoring one-shot pulse circuit 68 are disposed on the main board 46 on which the CPU 461 is mounted, the wiring length to the CPU 461 can be shortened. Thus, it is possible to more reliably prevent the input of power supply noise.
Furthermore, the CPU 461 performs a security check at the start of power supply, that is, at the time of start-up or restoration of a power failure, so that the malfunction of the CPU 461 can be reliably prevented.

Next, a pachinko machine according to a fifth embodiment will be described with reference to FIGS. In addition, the same code | symbol as the pachinko machine 1 which concerns on the said 1st Embodiment shows the same part as the pachinko machine 1 which concerns on the said 1st Embodiment, or an equivalent part.
The overall configuration of the pachinko machine according to the fifth embodiment and the configuration of the control system are substantially the same as the pachinko machine 1 according to the first embodiment. Moreover, the control process of the pachinko machine according to the fifth embodiment is substantially the same control process as the control process of the pachinko machine 1 according to the first embodiment.

  However, as shown in FIG. 12, the main board 46 of the pachinko machine according to the fifth embodiment is connected to the output terminal of the power monitoring system reset generation circuit 65, and the supply start signal of the power monitoring system reset generation circuit 65 Is input (for example, when a high-level voltage pulse signal is input), a voltage detection signal is output (for example, a normal low-level voltage is output and the voltage exceeds a predetermined voltage) Is detected, a high-level voltage pulse signal is output once.) A power supply rise monitoring one-shot pulse circuit 68 is provided. An AND circuit 69 is arranged on the main board 46. A NAND circuit 70 is disposed on the main board 46.

The output terminal of the power supply rising monitoring one-shot pulse circuit 68 is connected to one input terminal of the AND circuit 69. The other terminal of the RAM clear switch 58 arranged in the power supply unit 57 is connected to the input terminal of the NAND circuit 70, and the output terminal of the NAND circuit 70 is connected to one input terminal of the AND circuit 69. Yes. The output terminal of the AND circuit 69 is connected to the RAM clear terminal of the CPU 461. The other terminal of the RAM clear switch 58 connected to the input terminal of the NAND circuit 70 is connected to the +5 V power supply of the main board 46 on the input terminal side of the NAND circuit 70 on the main board 46. Has been pulled up through.
As a result, a high-level voltage pulse signal is input to one input terminal of the AND circuit 69 from the power-on-rising monitoring one-shot pulse circuit 68, and the RAM clear switch 58 is pressed and one input of the AND circuit 69 is input. Only when a high level voltage signal is input to the terminal, a high level voltage pulse signal is output from the AND circuit 69 to the RAM clear terminal of the CPU 461.

Next, system reset processing and user reset processing executed by the CPU 461 on the main board 46 configured as described above will be described with reference to FIG.
First, a system reset process executed by the CPU 461 when a supply start signal is input from the power monitoring system reset generation circuit 65 to the system reset terminal will be described.
As shown in FIG. 13, when a supply start signal is input from the power monitoring system reset generation circuit 65, the CPU 461 first performs a security check in S41. This security check is a check for determining whether each program (such as a program used for executing the game control process) stored in the ROM 462 is genuine. If the power supply is stopped during the security check in S41, the processing after S41 is executed again when the power supply is started.

Subsequently, in S42, the CPU 461 inputs a high-level voltage pulse signal from the power-on-rising monitoring one-shot pulse circuit 68 to one input terminal of the AND circuit 69, and the RAM clear switch 58 is pressed to perform the AND operation. A determination process is performed to determine whether a high level voltage signal is input to one input terminal of the circuit 69, that is, to determine whether a high level voltage pulse signal is input to the RAM clear terminal.
If a high-level voltage pulse signal is input to the RAM clear terminal (S42: YES), the CPU 461 performs initialization processing of the RAM 463 in S43. That is, “0” is assigned to various counters of the RAM 463 to be initialized, and the count values of the various counters when the pachinko ball wins the start opening 31 or when the pachinko ball passes through the gates 23 and 24 are stored. The parameter storage area to be initialized is initialized, and various data stored in the RAM 463 are erased before the power is stopped. Therefore, the pachinko machine returns to the state at startup. If the power supply is stopped during the initialization process in S43, the processes after S41 are executed again at the start of power supply.

In S44, the CPU 461 executes game-related processing in accordance with various game programs stored in the ROM 462 (for example, a process for acquiring count values of various counters when winning at the start port 31), and then in S45 described later. Execute the process. If the power is stopped during the game related process in S44, the process after S41 is executed again when the power supply is started.
On the other hand, if it is determined in S42 that the RAM clear switch 58 has not been pressed, that is, a high-level voltage pulse signal has not been input to the RAM clear terminal (S42: NO), the CPU 461 initializes the RAM 463. The processing after S44 is executed without conversion. Therefore, the pachinko game is continued based on various data stored in the RAM 463 before the power supply is stopped.

Next, a user reset process executed by the CPU 461 when an interrupt signal is input from the reset interrupt generation circuit 66 to the user reset terminal will be described.
As shown in FIG. 13, when an interrupt signal is input from the reset interrupt generation circuit 66 to the user reset terminal, the CPU 461 outputs a high-level voltage pulse signal from the power supply rise monitoring one-shot pulse circuit 68 in S42. Is input to one input terminal of the AND circuit 69, and whether or not the RAM clear switch 58 is pressed and a high level voltage signal is input to the one input terminal of the AND circuit 69 is determined. A determination process for determining whether or not a high-level voltage pulse signal is input to the RAM clear terminal is executed.
If the high-level voltage pulse signal is not input to the RAM clear terminal because the power supply is not started (S42: NO), in S44, the CPU 461 stores various game programs stored in the ROM 462 (for example, Game-related processing is executed in accordance with a count value acquisition processing program of various counters when winning at the start port 31).
In S45, the CPU 461 waits for the interrupt signal from the reset interrupt generation circuit 66 to be input to the user reset terminal. If the interrupt signal is input, the CPU 461 executes the processing from S42 onward again. To do.

  Here, the RAM 463 functions as a fluctuation data storage unit. The CPU 461 functions as game control means. The power monitoring system reset generation circuit 65 functions as power monitoring means. The reset interrupt generation circuit 66 functions as an interrupt signal output unit. The RAM clear switch 58, the pull-up resistor 71, and the NAND circuit 70 constitute second initialization instruction means. The power supply rising monitoring one-shot pulse circuit 68 functions as fifth signal output means. The AND circuit 69 functions as sixth signal output means.

  Therefore, in the pachinko machine according to the fifth embodiment, at the start of power supply, that is, at the time of start-up or restoration of a power failure, a high-level voltage pulse signal is output from the power-on monitoring one-shot pulse circuit 68 to the AND circuit. The AND circuit 69 is connected to the CPU 461 only when a high-level voltage signal is input to one input terminal of the AND circuit 69 when the RAM clear switch 58 is pressed. Since a high-level voltage pulse signal is output to the RAM clear terminal, if the user does not press down the RAM clear switch 58 at the start of power supply, the game control is performed using the data stored in the RAM 463 before the power supply is stopped. The game state of the pachinko machine can be reliably restored to the state before the power supply was stopped. Can. Even if power supply noise or the like is erroneously input to the system reset terminal of the CPU 461, if the user does not press the RAM clear switch 58, the data stored in the RAM 463 is not initialized. Can be reliably restored to the gaming state before the power supply noise is input. Further, at the start of power supply, that is, at the time of start-up or recovery from a power failure, a high-level voltage pulse signal is supplied from the power supply rise monitoring one-shot pulse circuit 68 to the AND circuit 69. Only when the RAM clear switch 58 is pressed and a high level voltage signal is input to one input terminal of the AND circuit 69, the AND circuit 69 outputs a high level to the RAM clear terminal of the CPU 461. Since the CPU 461 initializes the RAM 463 when the voltage pulse signal is inputted, the initialization of the RM 463 can be started after the power supply voltage supplied to the CPU 461 has sufficiently increased, and the RAM 463 is surely initialized. Can do.

In addition, when an interrupt signal is input from the reset interrupt generation circuit 66 at a predetermined time interval (for example, approximately 2 msec to 4 msec interval), the CPU 461 outputs a high level voltage pulse from the power supply rise monitoring one-shot pulse circuit 68. Only when a signal is input to one input terminal of the AND circuit 69 and a high-level voltage signal is input to one input terminal of the AND circuit 69 when the RAM clear switch 58 is pressed, the RAM of the CPU 461 After a high level voltage pulse signal is input from the AND circuit 69 to the clear terminal and the RAM 463 is initialized, execution of the game control is started. For this reason, even if power supply noise or the like is erroneously input to the user reset terminal of the CPU 461 as an interrupt signal, a high level voltage pulse signal from the power supply rise monitoring one-shot pulse circuit 68 and a high level voltage from the NAND circuit 70 are detected. If neither the voltage signal nor the voltage signal is input to the input terminal of the AND circuit 69, the data stored in the RAM 463 is not initialized. Therefore, the gaming state of the pachinko machine before the power supply noise is input. It is possible to reliably resume the game, that is, to maintain the game state before the power supply noise is input and to continue the game with certainty. In addition, when a user accidentally presses the RAM clear switch 58 and a high level voltage pulse signal is input to the AND circuit 69 during the game, a high level voltage pulse is output from the power supply rise monitoring one shot pulse circuit 68. Since no signal is input to one input terminal of the AND circuit 69 and a high-level voltage pulse signal is not input from the AND circuit 69 to the RAM clear terminal, the data stored in the RAM 463 is not initialized, and the pachinko machine Can be reliably restored to the game state before the RAM clear switch 58 is pressed, that is, the game state before the RAM clear switch 58 is pressed is maintained and the game is reliably continued. it can.
The power supply rise monitoring one-shot pulse circuit 68 outputs a high level voltage pulse signal to the power supply rise monitoring terminal on condition that a supply start signal is input from the power supply monitoring system reset generation circuit 65. A circuit for monitoring whether or not the supply start voltage has become equal to or higher than a predetermined voltage is not required, and the power supply rise monitoring one-shot pulse circuit 68 can be reduced in size and cost.
Further, by providing the AND circuit 69, the CPU 461 performs a process of determining whether or not the RAM clear switch 58 is pressed and a high-level voltage pulse signal is input from the power-on monitoring one-shot pulse circuit 68. There is no need to perform this, and the game control processing program can be reduced in size, and the memory capacity of the ROM 462 can be reduced.
In addition, the power supply monitoring system reset generation circuit 65, the power supply rise monitoring one-shot pulse circuit 68, the AND circuit 69, the NAND circuit 70, and the pull-up resistor 71 are disposed on the main board 46 on which the CPU 461 is mounted. Thus, the input of power supply noise can be more reliably prevented.
Furthermore, the CPU 461 performs a security check at the start of power supply, that is, at the time of start-up or restoration of a power failure, so that the malfunction of the CPU 461 can be reliably prevented.

Next, a pachinko machine according to a sixth embodiment will be described with reference to FIGS. The same reference numerals as those of the pachinko machine according to the second embodiment denote the same or corresponding parts as those of the pachinko machine according to the second embodiment.
The overall configuration of the pachinko machine according to the sixth embodiment and the configuration of the control system are substantially the same as those of the pachinko machine according to the second embodiment. Moreover, the control process of the pachinko machine according to the sixth embodiment is substantially the same control process as the control process of the pachinko machine according to the second embodiment.

However, as shown in FIG. 14, in the pachinko machine according to the sixth embodiment, a power supply monitoring system reset generation circuit 65 and a power supply rise monitoring one-shot pulse circuit 68 are arranged in the power supply unit 57, while on the main board 46. Is different from the pachinko machine according to the second embodiment in that a reset interrupt generation circuit 66 connected to the user reset terminal of the CPU 461 is arranged.
The power supply monitoring system reset generation circuit 65 is connected to a + 5V power supply on the power supply unit 57, monitors the supply state of the + 5V power supply of the power supply unit 57, and controls the control boards 46, 64, 65, When the start of power supply to 66 or the like is detected, a supply start signal is output (for example, when a low-level voltage is normally output and the start of power supply is detected, a high-level voltage pulse signal is output. Is output.) The output terminal of the power monitoring system reset generation circuit 65 is connected to the system reset terminal of the CPU 461.
Further, when the power supply rise monitoring one-shot pulse circuit 68 is connected to the + 5V power supply on the power supply unit 57 and detects that the + 5V power supply voltage is equal to or higher than a predetermined voltage (for example, about 3V to 4.5V or higher). In this case, a voltage detection signal is output (for example, a normal low level voltage is output, and if it is detected that the voltage exceeds a predetermined voltage, a high level voltage pulse signal is output once). The output terminal of the power supply rise monitoring one-shot pulse circuit 68 is connected to the power supply rise monitoring terminal of the CPU 461.

Next, system reset processing and user reset processing executed by the CPU 461 on the main board 46 configured as described above will be described with reference to FIG.
First, a system reset process executed by the CPU 461 when a supply start signal indicating that the power supply unit 57 has started supplying power from the power supply monitoring system reset generation circuit 65 is input to the system reset terminal will be described.
As shown in FIG. 15, when a supply start signal is input to the system reset terminal from the power monitoring system reset generation circuit 65, the CPU 461 first performs a security check in S51. This security check is a check for determining whether each program (such as a program used for executing the game control process) stored in the ROM 462 is genuine. If the power supply is stopped during the security check in S51, the processing after S51 is executed again at the start of power supply.

  Subsequently, in S52, the CPU 461 executes a determination process for determining whether or not the RAM clear switch 58 has been pressed. When it is determined that the RAM clear switch 58 has been pressed, that is, a low level voltage signal has been input to the RAM clear terminal (S52: YES), in S53, the CPU 461 causes the power supply rising monitoring one-shot pulse circuit. From 68, a determination process for determining whether or not a high-level voltage pulse signal indicating that the power supply voltage supplied by the power supply unit 57 has become equal to or higher than a predetermined voltage is input to the power supply rising monitoring terminal is executed. If it is determined that a high-level voltage pulse signal is input from the power supply rise monitoring one-shot pulse circuit 68 to the power supply rise monitoring terminal (S53: YES), the CPU 461 performs initialization processing of the RAM 463 in S54. . That is, “0” is substituted into various counters of the RAM 463 to be initialized, and the count values of the various counters when the pachinko ball wins the start opening 31 or when the pachinko balls pass through the gates 23 and 24 are stored. The parameter storage area to be initialized is initialized, and various data stored in the RAM 463 are erased before the power is stopped. Therefore, the pachinko machine returns to the state at startup. If the power supply is stopped during the initialization process in S54, the processes after S51 are executed again at the start of power supply.

In S55, the CPU 461 executes game-related processing in accordance with various game programs stored in the ROM 462 (for example, a process for acquiring count values of various counters when winning at the start port 31), and then in S56 described later. Execute the process. If the power supply is stopped during the game related process in S55, the process after S51 is executed again at the start of power supply.
On the other hand, if it is determined in S52 that the RAM clear switch 58 is not pressed, that is, a low level voltage signal is not input to the RAM clear terminal (S52: NO), the CPU 461 initializes the RAM 463. Without performing this, the processing after S55 is executed. Therefore, the pachinko game is continued based on various data stored in the RAM 463 before the power supply is stopped.
On the other hand, if a high-level voltage pulse signal is not input to the power supply rise monitoring terminal from the power supply rise monitoring one-shot pulse circuit 68 in S53 (S53: NO), the CPU 461 does not initialize the RAM 463, The process after S55 is executed. Therefore, the pachinko game is continued based on various data stored in the RAM 463 before the power supply is stopped.

Next, a user reset process executed by the CPU 461 when an interrupt signal is input from the reset interrupt generation circuit 66 to the user reset terminal will be described.
As shown in FIG. 15, when an interrupt signal is input from the reset interrupt generation circuit 66 to the user reset terminal, the CPU 461 performs a determination process for determining whether or not the RAM clear switch 58 is pressed in S52. Execute. When it is determined that the RAM clear switch 58 has been pressed, that is, a low level voltage signal has been input to the RAM clear terminal (S52: YES), in S53, the CPU 461 causes the power supply rise monitoring one-shot pulse circuit. From 68, a determination process for determining whether or not a high-level voltage pulse signal indicating that the power supply voltage supplied by the power supply unit 57 has become equal to or higher than a predetermined voltage is input to the power supply rising monitoring terminal is executed. If it is determined that a high-level voltage pulse signal is input from the power supply rise monitoring one-shot pulse circuit 68 to the power supply rise monitoring terminal (S53: YES), the CPU 461 performs initialization processing of the RAM 463 in S54. . That is, “0” is assigned to various counters of the RAM 463 to be initialized, and the count values of the various counters when the pachinko ball wins the start opening 31 or when the pachinko ball passes through the gates 23 and 24 are stored. The parameter storage area to be initialized is initialized, and various data stored in the RAM 463 are erased before the power is stopped. Therefore, the pachinko machine returns to the state at startup.

In S55, the CPU 461 executes game-related processing in accordance with various game programs stored in the ROM 462 (for example, an acquisition processing program for count values of various counters when winning at the start port 31).
In S56, the CPU 461 waits for an interrupt signal from the reset interrupt generation circuit 66 to be input to the user reset terminal. When the interrupt signal is input, the CPU 461 executes the processing from S52 again. To do.
On the other hand, if it is determined in S52 that the RAM clear switch 58 is not pressed, that is, a low level voltage signal is not input to the RAM clear terminal (S52: NO), the CPU 461 initializes the RAM 463. Without performing this, the processing after S55 is executed. Therefore, the pachinko game is continued based on various data stored in the RAM 463 before the interrupt signal is input.
On the other hand, if a high-level voltage pulse signal is not input to the power supply rise monitoring terminal from the power supply rise monitoring one-shot pulse circuit 68 in S53 (S53: NO), the CPU 461 does not initialize the RAM 463, The process after S55 is executed. Therefore, the pachinko game is continued based on various data stored in the RAM 463 before the interrupt signal is input.

  Here, the RAM 463 functions as a fluctuation data storage unit. The CPU 461 functions as game control means. The power monitoring system reset generation circuit 65 functions as power monitoring means. The reset interrupt generation circuit 66 functions as an interrupt signal output unit. The RAM clear switch 58 functions as first initialization instruction means. The power supply rising monitoring one-shot pulse circuit 68 functions as first signal output means.

  Therefore, in the pachinko machine according to the sixth embodiment, the user depresses the RAM clear switch 58 and is disposed in the power supply unit 57 at the start of power supply, that is, at the time of start-up or power recovery. Since the RAM 463 is initialized only when a high-level voltage pulse signal is input from the power supply rising monitoring one-shot pulse circuit 68 to the power supply rising monitoring terminal, the RAM clear switch 58 is set when the user starts supplying power to the power supply unit 57. If the button is not pressed, the CPU 461 can start the game control using the data stored in the RAM 463 before the power supply is stopped, and the game state before the power supply is stopped in the gaming state of the pachinko machine. The state can be reliably restored. Even if power supply noise or the like is erroneously input to the system reset terminal of the CPU 461, if the user does not press the RAM clear switch 58, the data stored in the RAM 463 is not initialized. Can be reliably restored to the gaming state before the power supply noise is input. Further, at the time of starting the supply of power, that is, at the time of starting or recovering from a power failure, the user depresses the RAM clear switch 58, and the power supply rising monitoring one-shot pulse circuit 68 arranged in the power supply unit 57 The CPU 461 initializes the RAM 463 only when a level voltage pulse signal is input to the power supply rise monitoring terminal. Therefore, the initialization of the RAM 463 is performed after the power supply voltage of the power supply unit 57 that supplies power to the CPU 461 is sufficiently increased. Execution can be started and the RAM 463 can be reliably initialized.

When the interrupt signal is input to the user reset terminal from the reset interrupt generation circuit 66 at a predetermined time interval (for example, approximately 2 msec to 4 msec), the CPU 461 depresses the RAM clear switch 58, and Only when a high-level voltage pulse signal is input to the power supply rise monitoring terminal from the power supply rise monitoring one-shot pulse circuit 68 arranged in the power supply unit 57, the execution of the game control is started after the RAM 463 is initialized. Therefore, even if power supply noise or the like is erroneously input as an interrupt signal to the user reset terminal of the CPU 461, at least one of a low level signal to the RAM clear terminal and a high level voltage pulse signal to the power supply rise monitoring terminal Is not input, the data stored in the RAM 463 is not initialized. Therefore, the gaming state of the pachinko machine is surely restored to the gaming state before the power supply noise is input, that is, the power supply noise. The game state can be maintained and the game can be continued without fail. Further, even if a user accidentally presses the RAM clear switch 58 and a low level signal is input to the RAM clear terminal during the game, a high level voltage pulse signal is monitored from the power source rise monitoring one-shot pulse circuit 68. Since it is not input to the terminal, the data stored in the RAM 463 is not initialized, and the gaming state of the pachinko machine is reliably restored to the gaming state before the low level signal is input to the RAM clear terminal, That is, it is possible to maintain the game state before the low level signal is input to the RAM clear terminal and to continue the game with certainty.
Since the power monitoring system reset generation circuit 65 and the power rising monitoring one-shot pulse circuit 68 are arranged in the power supply unit 57 that supplies power to the CPU 461, the supply of power to the CPU 461 is started and the supplied power is supplied. It is possible to more reliably and accurately detect the rising of the voltage above the predetermined voltage.
Furthermore, the CPU 461 performs a security check at the start of power supply, that is, at the time of start-up or restoration of a power failure, so that the malfunction of the CPU 461 can be reliably prevented.

Next, a pachinko machine according to a seventh embodiment will be described with reference to FIGS. The same reference numerals as those of the pachinko machine according to the fourth embodiment denote the same or corresponding parts as those of the pachinko machine according to the fourth embodiment.
The overall configuration of the pachinko machine according to the seventh embodiment and the configuration of the control system are substantially the same as those of the pachinko machine according to the fourth embodiment. Moreover, the control process of the pachinko machine according to the seventh embodiment is substantially the same as the control process of the pachinko machine according to the fourth embodiment.

However, as shown in FIG. 16, in the pachinko machine according to the seventh embodiment, a power supply monitoring system reset generation circuit 65 and a power supply rising monitoring one-shot pulse circuit 68 are arranged in the power supply unit 57, while on the main board 46. Is different from the pachinko machine according to the fourth embodiment in that a reset interrupt generation circuit 66 connected to the user reset terminal of the CPU 461 is arranged.
The power supply monitoring system reset generation circuit 65 is connected to a + 5V power supply on the power supply unit 57, monitors the supply state of the + 5V power supply of the power supply unit 57, and controls the control boards 46, 64, 65, When the start of power supply to 66 or the like is detected, a supply start signal is output (for example, when a low-level voltage is normally output and the start of power supply is detected, a high-level voltage pulse signal is output. Is output.) The output terminal of the power monitoring system reset generation circuit 65 is connected to the system reset terminal of the CPU 461.
Further, the power supply rise monitoring one-shot pulse circuit 68 is connected to the output terminal of the power supply monitoring system reset generation circuit 65. When the supply start signal of the power supply monitoring system reset generation circuit 65 is input (for example, high level) Voltage detection signal is output (for example, a low level voltage is normally output, and when it is detected that the voltage is equal to or higher than a predetermined voltage, a high level voltage pulse is output) The signal is output once.) The output terminal of the power supply rise monitoring one-shot pulse circuit 68 is connected to the power supply rise monitoring terminal of the CPU 461.

Next, system reset processing and user reset processing executed by the CPU 461 on the main board 46 configured as described above will be described with reference to FIG.
First, a system reset process executed by the CPU 461 when a supply start signal indicating that the power supply unit 57 has started supplying power from the power supply monitoring system reset generation circuit 65 is input to the system reset terminal will be described.
As shown in FIG. 17, when a supply start signal is input to the system reset terminal from the power monitoring system reset generation circuit 65, the CPU 461 first performs a security check in S61. This security check is a check for determining whether each program (such as a program used for executing the game control process) stored in the ROM 462 is genuine. If the power supply is stopped during the security check in S61, the processes after S61 are executed again when the power supply is started.

  Subsequently, in S62, the CPU 461 executes a determination process for determining whether or not the RAM clear switch 58 has been pressed. When it is determined that the RAM clear switch 58 has been pressed, that is, a low level voltage signal has been input to the RAM clear terminal (S62: YES), in S63, the CPU 461 causes the power supply rising monitoring one-shot pulse circuit. A determination process for determining whether a high-level voltage pulse signal from 68 has been input to the power supply rise monitoring terminal is executed. If it is determined that a high-level voltage pulse signal is input from the power supply rise monitoring one-shot pulse circuit 68 to the power supply rise monitoring terminal (S63: YES), in S64, the CPU 461 performs initialization processing of the RAM 463. . That is, “0” is substituted into various counters of the RAM 463 to be initialized, and the count values of the various counters when the pachinko ball wins the start opening 31 or when the pachinko balls pass through the gates 23 and 24 are stored. The parameter storage area to be initialized is initialized, and various data stored in the RAM 463 are erased before the power is stopped. Therefore, the pachinko machine returns to the state at startup. If the power supply is stopped during the initialization process in S64, the processes after S61 are executed again at the start of power supply.

In S65, the CPU 461 executes game-related processing in accordance with various game programs stored in the ROM 462 (for example, a process for acquiring count values of various counters when winning at the start port 31), and then in S66 described later. Execute the process. If the power supply is stopped during the game related process in S65, the process after S61 is executed again when the power supply is started.
On the other hand, if it is determined in S62 that the RAM clear switch 58 is not pressed, that is, a low level voltage signal is not input to the RAM clear terminal (S62: NO), the CPU 461 initializes the RAM 463. Without performing this, the processing after S65 is executed. Therefore, the pachinko game is continued based on various data stored in the RAM 463 before the power supply is stopped.
On the other hand, when a high-level voltage pulse signal is not input to the power supply rise monitoring terminal from the power supply rise monitoring one-shot pulse circuit 68 in S63 (S63: NO), the CPU 461 does not initialize the RAM 463, The processing after S65 is executed. Therefore, the pachinko game is continued based on various data stored in the RAM 463 before the power supply is stopped.

Next, a user reset process executed by the CPU 461 when an interrupt signal is input from the reset interrupt generation circuit 66 to the user reset terminal will be described.
As shown in FIG. 17, when an interrupt signal is input to the user reset terminal from the reset interrupt generation circuit 66, the CPU 461 performs a determination process for determining whether or not the RAM clear switch 58 is pressed in S62. Execute. When it is determined that the RAM clear switch 58 has been pressed, that is, a low level voltage signal has been input to the RAM clear terminal (S62: YES), in S63, the CPU 461 causes the power supply rise monitoring one-shot pulse circuit. A determination process for determining whether a high-level voltage pulse signal from 68 has been input to the power supply rise monitoring terminal is executed. If it is determined that a high-level voltage pulse signal is input from the power supply rise monitoring one-shot pulse circuit 68 to the power supply rise monitoring terminal (S63: YES), in S64, the CPU 461 performs initialization processing of the RAM 463. . That is, “0” is assigned to various counters of the RAM 463 to be initialized, and the count values of the various counters when the pachinko ball wins the start opening 31 or when the pachinko ball passes through the gates 23 and 24 are stored. The parameter storage area to be initialized is initialized, and various data stored in the RAM 463 are erased before the power is stopped. Therefore, the pachinko machine returns to the state at startup.

In S <b> 65, the CPU 461 executes game-related processing in accordance with various game programs stored in the ROM 462 (for example, a process for acquiring count values of various counters when winning at the start port 31).
In S66, the CPU 461 waits for an interrupt signal to be input to the user reset terminal from the reset interrupt generation circuit 66. When the interrupt signal is input, the CPU 461 executes the processing from S62 again. To do.
On the other hand, if it is determined in S62 that the RAM clear switch 58 is not pressed, that is, a low level voltage signal is not input to the RAM clear terminal (S62: NO), the CPU 461 initializes the RAM 463. Without performing this, the processing after S65 is executed. Therefore, the pachinko game is continued based on various data stored in the RAM 463 before the interrupt signal is input.
On the other hand, when a high-level voltage pulse signal is not input to the power supply rise monitoring terminal from the power supply rise monitoring one-shot pulse circuit 68 in S63 (S63: NO), the CPU 461 does not initialize the RAM 463, The processing after S65 is executed. Therefore, the pachinko game is continued based on various data stored in the RAM 463 before the interrupt signal is input.

  Here, the RAM 463 functions as a fluctuation data storage unit. The CPU 461 functions as game control means. The power monitoring system reset generation circuit 65 functions as power monitoring means. The reset interrupt generation circuit 66 functions as an interrupt signal output unit. The RAM clear switch 58 functions as first initialization instruction means. The power supply rising monitoring one-shot pulse circuit 68 functions as second signal output means.

  Therefore, in the pachinko machine according to the seventh embodiment, the user depresses the RAM clear switch 58 and is disposed in the power supply unit 57 at the start of power supply, that is, at the time of start-up or power recovery. Since the RAM 463 is initialized only when a high-level voltage pulse signal is input from the power supply rise monitoring one-shot pulse circuit 68 to the power supply rise monitoring terminal, the user does not press down the RAM clear switch 58 at the start of power supply. In other words, the CPU 461 can start executing the game control with the data stored in the RAM 463 before the power supply is stopped, so that the gaming state of the pachinko machine is surely changed to the game state before the power supply is stopped. It can be restored. Even if power supply noise or the like is erroneously input to the system reset terminal of the CPU 461, if the user does not press the RAM clear switch 58, the data stored in the RAM 463 is not initialized. Can be reliably restored to the gaming state before the power supply noise is input. Further, at the time of starting the supply of power, that is, at the time of starting or recovering from a power failure, the user depresses the RAM clear switch 58, and the power supply rising monitoring one-shot pulse circuit 68 arranged in the power supply unit 57 The CPU 461 initializes the RAM 463 only when a level voltage pulse signal is input to the power supply rise monitoring terminal. Therefore, the initialization of the RAM 463 is performed after the power supply voltage of the power supply unit 57 that supplies power to the CPU 461 is sufficiently increased. Execution can be started and the RAM 463 can be reliably initialized.

When the interrupt signal is input to the user reset terminal from the reset interrupt generation circuit 66 at a predetermined time interval (for example, approximately 2 msec to 4 msec), the CPU 461 depresses the RAM clear switch 58, and Only when a high-level voltage pulse signal is input to the power supply rise monitoring terminal from the power supply rise monitoring one-shot pulse circuit 68 arranged in the power supply unit 57, the execution of the game control is started after the RAM 463 is initialized. Therefore, even if power supply noise or the like is erroneously input as an interrupt signal to the user reset terminal of the CPU 461, at least one of a low level signal to the RAM clear terminal and a high level voltage pulse signal to the power supply rise monitoring terminal Is not input, the data stored in the RAM 463 is not initialized. Therefore, the gaming state of the pachinko machine is surely restored to the gaming state before the power supply noise is input, that is, the power supply noise. The game state can be maintained and the game can be continued without fail. Further, even if a user accidentally presses the RAM clear switch 58 and a low level signal is input to the RAM clear terminal during the game, a high level voltage pulse signal is monitored from the power source rise monitoring one-shot pulse circuit 68. Since it is not input to the terminal, the data stored in the RAM 463 is not initialized, and the gaming state of the pachinko machine is reliably restored to the gaming state before the low level signal is input to the RAM clear terminal, That is, it is possible to maintain the game state before the low level signal is input to the RAM clear terminal and to continue the game with certainty.
The power supply rise monitoring one-shot pulse circuit 68 outputs a high level voltage pulse signal to the power supply rise monitoring terminal on condition that a supply start signal is input from the power supply monitoring system reset generation circuit 65. A circuit for monitoring whether or not the supply start voltage has become equal to or higher than a predetermined voltage is not required, and the power supply rise monitoring one-shot pulse circuit 68 can be reduced in size and cost.
The power supply monitoring system reset generation circuit 65 and the power supply rise monitoring one-shot pulse circuit 68 are disposed in the power supply unit 57 that supplies power to the CPU 461, so that the supply of power to the CPU 461 can be started more reliably and. It can be detected accurately.
Furthermore, the CPU 461 performs a security check at the start of power supply, that is, at the time of start-up or restoration of a power failure, so that the malfunction of the CPU 461 can be reliably prevented.

Next, a pachinko machine according to an eighth embodiment will be described with reference to FIGS. The same reference numerals as those of the pachinko machine according to the fourth embodiment denote the same or corresponding parts as those of the pachinko machine according to the fourth embodiment.
The overall configuration of the pachinko machine according to the eighth embodiment and the configuration of the control system are substantially the same as those of the pachinko machine according to the fourth embodiment. Moreover, the control process of the pachinko machine according to the seventh embodiment is substantially the same as the control process of the pachinko machine according to the fourth embodiment.

However, as shown in FIG. 18, in the pachinko machine according to the eighth embodiment, the power monitoring unit reset generation circuit 65 is arranged in the power unit 57, and on the main board 46, connected to the user reset terminal of the CPU 461. This is different from the pachinko machine according to the fourth embodiment in that a reset interrupt generating circuit 66 and a power-on monitoring one-shot pulse circuit 68 are arranged.
The power supply monitoring system reset generation circuit 65 is connected to a + 5V power supply on the power supply unit 57, monitors the supply state of the + 5V power supply of the power supply unit 57, and controls the control boards 46, 64, 65, When the start of power supply to 66 or the like is detected, a supply start signal is output (for example, when a low-level voltage is normally output and the start of power supply is detected, a high-level voltage pulse signal is output. Is output.) The output terminal of the power monitoring system reset generation circuit 65 is connected to the system reset terminal of the CPU 461.
The power supply rise monitoring one-shot pulse circuit 68 disposed on the main board 46 is connected to the output terminal of the power supply monitoring system reset generation circuit 65, and the supply start signal of the power supply monitoring system reset generation circuit 65 is inputted. In this case (for example, when a high-level voltage pulse signal is input), a voltage detection signal is output (for example, a normal low-level voltage is output, and it is detected that the voltage exceeds a predetermined voltage) In this case, a high-level voltage pulse signal is output once.) The output terminal of the power supply rise monitoring one-shot pulse circuit 68 is connected to the power supply rise monitoring terminal of the CPU 461.

Next, system reset processing and user reset processing executed by the CPU 461 on the main board 46 configured as described above will be described with reference to FIG.
First, a system reset process executed by the CPU 461 when a supply start signal indicating that the power supply unit 57 has started supplying power from the power supply monitoring system reset generation circuit 65 is input to the system reset terminal will be described.
As shown in FIG. 19, when a supply start signal is input to the system reset terminal from the power monitoring system reset generation circuit 65, the CPU 461 first performs a security check in S71. This security check is a check for determining whether each program (such as a program used for executing the game control process) stored in the ROM 462 is genuine. If the power supply is stopped during the security check in S71, the processes after S71 are executed again at the start of power supply.

  Subsequently, in S72, the CPU 461 executes a determination process for determining whether or not the RAM clear switch 58 has been pressed. When it is determined that the RAM clear switch 58 has been pressed, that is, a low level voltage signal has been input to the RAM clear terminal (S72: YES), in S73, the CPU 461 causes the power supply rise monitoring one-shot pulse circuit. A determination process for determining whether a high-level voltage pulse signal from 68 has been input to the power supply rise monitoring terminal is executed. If it is determined that a high-level voltage pulse signal is input from the power supply rising monitoring one-shot pulse circuit 68 to the power supply rising monitoring terminal (S73: YES), in S74, the CPU 461 performs initialization processing of the RAM 463. . That is, “0” is substituted into various counters of the RAM 463 to be initialized, and the count values of the various counters when the pachinko ball wins the start opening 31 or when the pachinko balls pass through the gates 23 and 24 are stored. The parameter storage area to be initialized is initialized, and various data stored in the RAM 463 are erased before the power is stopped. Therefore, the pachinko machine returns to the state at startup. If the power supply is stopped during the initialization process in S74, the processes after S71 are executed again at the start of power supply.

In S75, the CPU 461 executes game-related processing in accordance with various game programs stored in the ROM 462 (for example, a process for acquiring count values of various counters when winning at the start port 31), and then in S76 described later. Execute the process. If the power supply is stopped during the game related process in S75, the processes after S71 are executed again at the start of power supply.
On the other hand, if it is determined in S72 that the RAM clear switch 58 has not been pressed, that is, no low level voltage signal is input to the RAM clear terminal (S72: NO), the CPU 461 initializes the RAM 463. Without performing this, the processes after S75 are executed. Therefore, the pachinko game is continued based on various data stored in the RAM 463 before the power supply is stopped.
On the other hand, when a high level voltage pulse signal is not input from the power supply rising monitoring one-shot pulse circuit 68 to the power supply rising monitoring terminal in S73 (S73: NO), the CPU 461 does not initialize the RAM 463, The process after S75 is executed. Therefore, the pachinko game is continued based on various data stored in the RAM 463 before the power supply is stopped.

Next, a user reset process executed by the CPU 461 when an interrupt signal is input from the reset interrupt generation circuit 66 to the user reset terminal will be described.
As shown in FIG. 19, when an interrupt signal is input from the reset interrupt generation circuit 66 to the user reset terminal, the CPU 461 performs a determination process for determining whether or not the RAM clear switch 58 is pressed in S72. Execute. When it is determined that the RAM clear switch 58 has been pressed, that is, a low level voltage signal has been input to the RAM clear terminal (S72: YES), in S73, the CPU 461 causes the power supply rising monitoring one-shot pulse circuit. A determination process for determining whether a high-level voltage pulse signal from 68 has been input to the power supply rise monitoring terminal is executed. If it is determined that a high-level voltage pulse signal is input from the power supply rise monitoring one-shot pulse circuit 68 to the power supply rise monitoring terminal (S73: YES), in S74, the CPU 461 performs initialization processing of the RAM 463. . That is, “0” is assigned to various counters of the RAM 463 to be initialized, and the count values of the various counters when the pachinko ball wins the start opening 31 or when the pachinko ball passes through the gates 23 and 24 are stored. The parameter storage area to be initialized is initialized, and various data stored in the RAM 463 are erased before the power is stopped. Therefore, the pachinko machine returns to the state at startup.

In S <b> 75, the CPU 461 executes game-related processing according to various game programs stored in the ROM 462 (for example, count value acquisition processing programs for various counters when winning at the start port 31).
In S76, the CPU 461 waits for an interrupt signal from the reset interrupt generation circuit 66 to be input to the user reset terminal. If the interrupt signal is input, the CPU 461 executes the processing from S72 onward again. To do.
On the other hand, if it is determined in S72 that the RAM clear switch 58 has not been pressed, that is, no low level voltage signal is input to the RAM clear terminal (S72: NO), the CPU 461 initializes the RAM 463. Without performing this, the processes after S75 are executed. Therefore, the pachinko game is continued based on various data stored in the RAM 463 before the interrupt signal is input.
On the other hand, when a high level voltage pulse signal is not input from the power supply rising monitoring one-shot pulse circuit 68 to the power supply rising monitoring terminal in S73 (S73: NO), the CPU 461 does not initialize the RAM 463, The process after S75 is executed. Therefore, the pachinko game is continued based on various data stored in the RAM 463 before the interrupt signal is input.

  Here, the RAM 463 functions as a fluctuation data storage unit. The CPU 461 functions as game control means. The power monitoring system reset generation circuit 65 functions as power monitoring means. The reset interrupt generation circuit 66 functions as an interrupt signal output unit. The RAM clear switch 58 functions as first initialization instruction means. The power supply rising monitoring one-shot pulse circuit 68 functions as second signal output means.

  Therefore, in the pachinko machine according to the eighth embodiment, the user presses the RAM clear switch 58 and is arranged on the main board 46 at the start of power supply, that is, at the time of start-up or power recovery. Since the RAM 463 is initialized only when a high-level voltage pulse signal is input from the power supply rise monitoring one-shot pulse circuit 68 to the power supply rise monitoring terminal, the user does not press down the RAM clear switch 58 at the start of power supply. In other words, the CPU 461 can start executing the game control with the data stored in the RAM 463 before the power supply is stopped, so that the gaming state of the pachinko machine is surely changed to the game state before the power supply is stopped. It can be restored. Even if power supply noise or the like is erroneously input to the system reset terminal of the CPU 461, if the user does not press the RAM clear switch 58, the data stored in the RAM 463 is not initialized. Can be reliably restored to the gaming state before the power supply noise is input. Further, at the time of starting the supply of power, that is, at the time of starting or recovering from a power failure, the user depresses the RAM clear switch 58, and the power supply rising monitoring one-shot pulse circuit 68 disposed on the main board 46 is switched to the high level. The CPU 461 initializes the RAM 463 only when a level voltage pulse signal is input to the power supply rise monitoring terminal. Therefore, the initialization of the RAM 463 is performed after the power supply voltage of the power supply unit 57 that supplies power to the CPU 461 is sufficiently increased. Execution can be started and the RAM 463 can be reliably initialized.

When the interrupt signal is input to the user reset terminal from the reset interrupt generation circuit 66 at a predetermined time interval (for example, approximately 2 msec to 4 msec interval), the user presses the RAM clear switch 58, and Only when a high-level voltage pulse signal is input to the power supply rise monitoring terminal from the power supply rise monitoring one-shot pulse circuit 68 arranged on the main board 46, the execution of the game control is started after the RAM 463 is initialized. Therefore, even if power supply noise or the like is erroneously input as an interrupt signal to the user reset terminal of the CPU 461, at least one of a low level signal to the RAM clear terminal and a high level voltage pulse signal to the power supply rise monitoring terminal Is not input, the data stored in the RAM 463 is not initialized. Therefore, the gaming state of the pachinko machine is surely restored to the gaming state before the power supply noise is input, that is, the power supply noise. The game state can be maintained and the game can be continued without fail. Further, even if a user accidentally presses the RAM clear switch 58 and a low level signal is input to the RAM clear terminal during the game, a high level voltage pulse signal is monitored from the power source rise monitoring one-shot pulse circuit 68. Since it is not input to the terminal, the data stored in the RAM 463 is not initialized, and the gaming state of the pachinko machine is reliably restored to the gaming state before the low level signal is input to the RAM clear terminal, That is, it is possible to maintain the game state before the low level signal is input to the RAM clear terminal and to continue the game with certainty.
The power supply rise monitoring one-shot pulse circuit 68 outputs a high level voltage pulse signal to the power supply rise monitoring terminal on condition that a supply start signal is input from the power supply monitoring system reset generation circuit 65. A circuit for monitoring whether or not the supply start voltage has become equal to or higher than a predetermined voltage is not required, and the power supply rise monitoring one-shot pulse circuit 68 can be reduced in size and cost.
Further, since the power monitoring system reset generation circuit 65 is disposed in the power supply unit 57 that supplies power to the CPU 461, the start of power supply to the CPU 461 can be detected more reliably and accurately. In addition, since the reset interrupt generation circuit 66 and the power supply rise monitoring one-shot pulse circuit 68 are provided on the main board 46 on which the CPU 461 is mounted, the wiring length to the CPU 461 can be shortened. Can be more reliably prevented.
Furthermore, the CPU 461 performs a security check at the start of power supply, that is, at the time of start-up or restoration of a power failure, so that the malfunction of the CPU 461 can be reliably prevented.

Next, a pachinko machine according to a ninth embodiment will be described with reference to FIGS. The same reference numerals as those of the pachinko machine according to the fifth embodiment denote the same or corresponding parts as those of the pachinko machine according to the fifth embodiment.
The overall configuration of the pachinko machine according to the ninth embodiment and the configuration of the control system are substantially the same as those of the pachinko machine according to the fifth embodiment. Moreover, the control process of the pachinko machine according to the ninth embodiment is substantially the same as the control process of the pachinko machine according to the fifth embodiment.

  However, as shown in FIG. 20, in the pachinko machine according to the ninth embodiment, the power monitoring unit reset generation circuit 65 is arranged in the power unit 57, and on the main board 46, connected to the user reset terminal of the CPU 461. Is different from the pachinko machine according to the fifth embodiment in that a reset interrupt generation circuit 66, a power-on monitoring one-shot pulse circuit 68, an AND circuit 69, a NAND circuit 70, and a pull-up resistor 71 are arranged.

The power monitoring system reset generation circuit 65 is connected to the + 5V power supply on the power supply unit 57, monitors the supply state of the + 5V power supply of the power supply unit 57, and controls the control boards 46, 64, 65, 66 of the power supply unit 57. When a supply start signal is detected, a supply start signal is output (for example, a normal low level voltage is output, and when a power supply start is detected, a high level voltage pulse signal is output. Output.). The output terminal of the power monitoring system reset generation circuit 65 is connected to the system reset terminal of the CPU 461.
The power supply rise monitoring one-shot pulse circuit 68 disposed on the main board 46 is connected to the output terminal of the power supply monitoring system reset generation circuit 65, and the supply start signal of the power supply monitoring system reset generation circuit 65 is inputted. In this case (for example, when a high-level voltage pulse signal is input), a voltage detection signal is output (for example, a normal low-level voltage is output, and it is detected that the voltage exceeds a predetermined voltage) In this case, a high-level voltage pulse signal is output once.) The output terminal of the power supply rising monitoring one-shot pulse circuit 68 is connected to one input terminal of the AND circuit 69.
The other terminal of the RAM clear switch 58 arranged in the power supply unit 57 is connected to the input terminal of the NAND circuit 70, and the output terminal of the NAND circuit 70 is connected to one input terminal of the AND circuit 69. Yes. The output terminal of the AND circuit 69 is connected to the RAM clear terminal of the CPU 461. The other terminal of the RAM clear switch 58 connected to the input terminal of the NAND circuit 70 is connected to the +5 V power supply of the main board 46 on the input terminal side of the NAND circuit 70 on the main board 46. Has been pulled up through.
As a result, a high-level voltage pulse signal is input to one input terminal of the AND circuit 69 from the power-on-rising monitoring one-shot pulse circuit 68, and the RAM clear switch 58 is pressed and one input of the AND circuit 69 is input. Only when a high level voltage signal is input to the terminal, a high level voltage pulse signal is output from the AND circuit 69 to the RAM clear terminal of the CPU 461.

Next, system reset processing and user reset processing executed by the CPU 461 on the main board 46 configured as described above will be described with reference to FIG.
First, a system reset process executed by the CPU 461 when a supply start signal indicating that the power supply unit 57 has started supplying power from the power supply monitoring system reset generation circuit 65 is input to the system reset terminal will be described.
As shown in FIG. 21, when a supply start signal is input from the power monitoring system reset generation circuit 65, the CPU 461 first performs a security check in S81. This security check is a check for determining whether each program (such as a program used for executing the game control process) stored in the ROM 462 is genuine. If the power supply is stopped during the security check in S81, the processes after S81 are executed again at the start of power supply.

Subsequently, in S82, the CPU 461 receives a high-level voltage pulse signal from the power supply rising monitoring one-shot pulse circuit 68 to one input terminal of the AND circuit 69, and the RAM clear switch 58 is pressed to perform the AND operation. A determination process is performed to determine whether a high level voltage signal is input to one input terminal of the circuit 69, that is, to determine whether a high level voltage pulse signal is input to the RAM clear terminal.
If a high-level voltage pulse signal is input to the RAM clear terminal (S82: YES), the CPU 461 performs initialization processing of the RAM 463 in S83. That is, “0” is assigned to various counters of the RAM 463 to be initialized, and the count values of the various counters when the pachinko ball wins the start opening 31 or when the pachinko ball passes through the gates 23 and 24 are stored. The parameter storage area to be initialized is initialized, and various data stored in the RAM 463 are erased before the power is stopped. Therefore, the pachinko machine returns to the state at startup. If the power supply is stopped during the initialization process in S83, the processes after S81 are executed again at the start of power supply.

In S84, the CPU 461 executes game-related processing in accordance with various game programs stored in the ROM 462 (for example, a process for acquiring count values of various counters when winning at the start port 31), and then in S85 described later. Execute the process. If the power is stopped during the game related process in S84, the processes after S81 are executed again at the start of power supply.
On the other hand, if it is determined in S82 that the RAM clear switch 58 has not been pressed, that is, no high level voltage pulse signal is input to the RAM clear terminal (S82: NO), the CPU 461 initializes the RAM 463. The process after S84 is executed without changing the process. Therefore, the pachinko game is continued based on various data stored in the RAM 463 before the power supply is stopped.

Next, a user reset process executed by the CPU 461 when an interrupt signal is input from the reset interrupt generation circuit 66 to the user reset terminal will be described.
As shown in FIG. 21, when an interrupt signal is input from the reset interrupt generation circuit 66 to the user reset terminal, the CPU 461 outputs a high-level voltage pulse signal from the power supply rise monitoring one-shot pulse circuit 68 in S82. Is input to one input terminal of the AND circuit 69, and whether or not the RAM clear switch 58 is pressed and a high level voltage signal is input to the one input terminal of the AND circuit 69 is determined. A determination process for determining whether or not a high-level voltage pulse signal is input to the RAM clear terminal is executed.
If the high-level voltage pulse signal is not input to the RAM clear terminal because the power supply is not started (S82: NO), in S84, the CPU 461 stores various game programs stored in the ROM 462 (for example, The game-related processing is executed in accordance with the count value acquisition processing program of the various counters when winning at the starting port 31).
In S85, the CPU 461 waits for an interrupt signal from the reset interrupt generation circuit 66 to be input to the user reset terminal. If the interrupt signal is input, the CPU 461 executes the processing subsequent to S82 again. To do.

  Here, the RAM 463 functions as a fluctuation data storage unit. The CPU 461 functions as game control means. The power monitoring system reset generation circuit 65 functions as power monitoring means. The reset interrupt generation circuit 66 functions as an interrupt signal output unit. The RAM clear switch 58, the pull-up resistor 71, and the NAND circuit 70 constitute second initialization instruction means. The power supply rising monitoring one-shot pulse circuit 68 functions as fifth signal output means. The AND circuit 69 functions as sixth signal output means.

  Therefore, in the pachinko machine according to the ninth embodiment, when power supply is started, that is, at the time of start-up or power failure recovery, a high-level voltage pulse signal is output from the power-on rise monitoring one-shot pulse circuit 68 to the AND circuit. The AND circuit 69 is connected to the CPU 461 only when a high-level voltage signal is input to one input terminal of the AND circuit 69 when the RAM clear switch 58 is pressed. Since a high-level voltage pulse signal is output to the RAM clear terminal, if the user does not press down the RAM clear switch 58 at the start of power supply, the game control is performed using the data stored in the RAM 463 before the power supply is stopped. The game state of the pachinko machine can be reliably restored to the state before the power supply was stopped. Can. Even if power supply noise or the like is erroneously input to the system reset terminal of the CPU 461, if the user does not press the RAM clear switch 58, the data stored in the RAM 463 is not initialized. Can be reliably restored to the gaming state before the power supply noise is input. Further, at the start of power supply, that is, at the time of start-up or recovery from a power failure, a high-level voltage pulse signal is supplied from the power supply rise monitoring one-shot pulse circuit 68 to the AND circuit 69. Only when the RAM clear switch 58 is pressed and a high level voltage signal is input to one input terminal of the AND circuit 69, the AND circuit 69 outputs a high level to the RAM clear terminal of the CPU 461. Since the CPU 461 initializes the RAM 463 when the voltage pulse signal is inputted, the initialization of the RM 463 can be started after the power supply voltage supplied to the CPU 461 has sufficiently increased, and the RAM 463 is surely initialized. Can do.

In addition, when an interrupt signal is input from the reset interrupt generation circuit 66 at a predetermined time interval (for example, approximately 2 msec to 4 msec interval), the CPU 461 outputs a high level voltage pulse from the power supply rise monitoring one-shot pulse circuit 68. Only when a signal is input to one input terminal of the AND circuit 69 and a high-level voltage signal is input to one input terminal of the AND circuit 69 when the RAM clear switch 58 is pressed, the RAM of the CPU 461 After a high level voltage pulse signal is input from the AND circuit 69 to the clear terminal and the RAM 463 is initialized, execution of the game control is started. For this reason, even if power supply noise or the like is erroneously input to the user reset terminal of the CPU 461 as an interrupt signal, a high level voltage pulse signal from the power supply rise monitoring one-shot pulse circuit 68 and a high level voltage from the NAND circuit 70 are detected. If neither the voltage signal nor the voltage signal is input to the input terminal of the AND circuit 69, the data stored in the RAM 463 is not initialized. Therefore, the gaming state of the pachinko machine before the power supply noise is input. It is possible to reliably resume the game, that is, to maintain the game state before the power supply noise is input and to continue the game with certainty. In addition, when a user accidentally presses the RAM clear switch 58 and a high level voltage pulse signal is input to the AND circuit 69 during the game, a high level voltage pulse is output from the power supply rise monitoring one shot pulse circuit 68. Since no signal is input to one input terminal of the AND circuit 69 and a high-level voltage pulse signal is not input from the AND circuit 69 to the RAM clear terminal, the data stored in the RAM 463 is not initialized, and the pachinko machine Can be reliably restored to the game state before the RAM clear switch 58 is pressed, that is, the game state before the RAM clear switch 58 is pressed is maintained and the game is reliably continued. it can.
The power supply rise monitoring one-shot pulse circuit 68 outputs a high level voltage pulse signal to the power supply rise monitoring terminal on condition that a supply start signal is input from the power supply monitoring system reset generation circuit 65. A circuit for monitoring whether or not the supply start voltage has become equal to or higher than a predetermined voltage is not required, and the power supply rise monitoring one-shot pulse circuit 68 can be reduced in size and cost.
Further, by providing the AND circuit 69, the CPU 461 performs a process of determining whether or not the RAM clear switch 58 is pressed and a high-level voltage pulse signal is input from the power-on monitoring one-shot pulse circuit 68. There is no need to perform this, and the game control processing program can be reduced in size, and the memory capacity of the ROM 462 can be reduced.
Further, since the power monitoring system reset generation circuit 65 is disposed in the power supply unit 57 that supplies power to the CPU 461, the start of power supply to the CPU 461 can be detected more reliably and accurately. Further, since the power supply rise monitoring one-shot pulse circuit 68, the AND circuit 69, the NAND circuit 70, and the pull-up resistor 71 are disposed on the main board 46 on which the CPU 461 is mounted, the wiring length to the CPU 461 is shortened. Therefore, input of power supply noise can be prevented more reliably.
Furthermore, the CPU 461 performs a security check at the start of power supply, that is, at the time of start-up or restoration of a power failure, so that the malfunction of the CPU 461 can be reliably prevented.

The present invention is not limited to the first to ninth embodiments described above, and various improvements and modifications can be made without departing from the scope of the present invention.
For example, in the first to ninth embodiments, the power supply monitoring system reset generation circuit 65, the reset interrupt generation circuit 66, and the power supply rise monitoring one-shot pulse circuit 68 output a high level voltage pulse signal. Alternatively, a low-level voltage pulse signal may be output. When the power supply rising monitoring one-shot pulse circuit 68 outputs a low-level voltage pulse signal, the NAND circuit 71 is excluded from the third embodiment, the fifth embodiment, and the ninth embodiment.
In the first to ninth embodiments, the RAM clear switch 58 is configured to be grounded when pressed, but is normally grounded and the RAM clear switch 58 is pressed. In some cases, a high-level voltage signal may be output.

It is the front view showing the whole pachinko machine concerning a 1st embodiment. It is the front view which showed the game area | region of the game board of the pachinko machine which concerns on 1st Embodiment. It is the rear view which showed the whole pachinko machine concerning a 1st embodiment. It is a circuit block diagram which shows the schematic circuit structure regarding the system reset and user reset of the main board | substrate and power supply unit of a pachinko machine which concern on 1st Embodiment. It is a flowchart which shows the system reset process and user reset process which CPU of the pachinko machine concerning a 1st embodiment performs. It is a circuit block diagram which shows the schematic circuit structure regarding the system reset of the main board | substrate of a pachinko machine, and a power supply unit which concerns on 2nd Embodiment. It is a flowchart which shows the system reset process and user reset process which CPU of the pachinko machine concerning a 2nd embodiment performs. It is a circuit block diagram which shows the schematic circuit structure regarding the system reset of the main board | substrate and power supply unit of a pachinko machine concerning a 3rd embodiment. It is a flowchart which shows the system reset process and user reset process which CPU of the pachinko machine concerning a 3rd embodiment performs. It is a circuit block diagram which shows the schematic circuit structure regarding the system reset of the main board | substrate of a pachinko machine, and a power supply unit which concerns on 4th Embodiment. It is a flowchart which shows the system reset process and user reset process which CPU of the pachinko machine concerning a 4th embodiment performs. It is a circuit block diagram which shows the schematic circuit structure regarding the system reset of the main board | substrate and power supply unit of a pachinko machine concerning a 5th embodiment. It is a flowchart which shows the system reset process and user reset process which CPU of the pachinko machine concerning a 5th embodiment performs. It is a circuit block diagram which shows the schematic circuit structure regarding the system reset of the main board | substrate and power supply unit of a pachinko machine concerning a 6th embodiment. It is a flowchart which shows the system reset process and user reset process which CPU of the pachinko machine concerning a 6th embodiment performs. It is a circuit block diagram which shows the schematic circuit structure regarding the system reset of the main board | substrate and power supply unit of a pachinko machine concerning a 7th embodiment. It is a flowchart which shows the system reset process and user reset process which CPU of the pachinko machine concerning a 7th embodiment performs. It is a circuit block diagram which shows the schematic circuit structure regarding the system reset of the main board | substrate and power supply unit of a pachinko machine concerning an 8th embodiment. It is a flowchart which shows the system reset process and user reset process which CPU of the pachinko machine concerning 8th Embodiment performs. It is a circuit block diagram which shows the schematic circuit structure regarding the system reset of the main board | substrate of a pachinko machine, and a power supply unit which concerns on 9th Embodiment. It is a flowchart which shows the system reset process and user reset process which CPU of the pachinko machine concerning 9th Embodiment performs.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Pachinko machine 46 Main board 57 Power supply unit 58 RAM clear switch 59 Power switch 65 Power supply monitoring system reset generation circuit 66 Reset interrupt generation circuit 68 Power supply rise monitoring one-shot pulse circuit 69 AND circuit 70 NAND circuit 71 Pull-up resistor 462 ROM
463 RAM

Claims (15)

A gaming machine in which a player can play a predetermined game,
Game control means for controlling the progress of the game, having a fluctuation data storage means for storing the fluctuation data that fluctuates according to the progress of the game,
A power supply monitoring means for monitoring a state of a predetermined power supply used in the gaming machine and outputting a first detection signal to the game control means when the start of power supply is detected;
Interrupt signal output means for outputting an interrupt signal for causing the game control means to start execution of game control at predetermined time intervals;
First initialization instruction means for outputting an instruction signal instructing the game control means to initialize the variation data storage means;
With
When the first detection signal is input from the power supply monitoring unit, the game control unit determines whether an instruction signal is input from the first initialization instruction unit, and the first initialization instruction unit If it is determined that the instruction signal is not input from, the execution of the game control is started without initializing the variation data storage means, while the instruction signal is input from the first initialization instruction means. If determined, the execution of game control is started after the variable data storage means is initialized, and when an interrupt signal is input from the interrupt signal output means, the first initialization instruction It is determined whether or not an instruction signal is input from the means, and if it is determined that no instruction signal is input from the first initialization instruction means, the game control process is performed without initializing the variation data storage means. Start running, while the first When the instruction signal from the initialization instruction means is determined to have been input, after initialization the variation data storage unit, a game machine, characterized in that to start the execution of the game control. A gaming machine in which a player can play a predetermined game,
Game control means for controlling the progress of the game, having a fluctuation data storage means for storing the fluctuation data that fluctuates according to the progress of the game,
A power supply monitoring means for monitoring a state of a predetermined power supply used in the gaming machine and outputting a first detection signal to the game control means when the start of power supply is detected;
Interrupt signal output means for outputting an interrupt signal for causing the game control means to start execution of game control at predetermined time intervals;
First initialization instruction means for outputting an instruction signal instructing the game control means to initialize the variation data storage means;
First signal output means for outputting a second detection signal to the game control means on the condition that the supply start voltage of the power supply becomes equal to or higher than a predetermined voltage;
With
When the first detection signal is input from the power supply monitoring unit, the game control unit receives an instruction signal from the first initialization instruction unit, and receives a second detection signal from the first signal output unit. When it is determined whether or not at least one of the instruction signal and the second detection signal is not input, the execution of the game control is started without initializing the variation data storage means. On the other hand, if it is determined that the instruction signal is input and the second detection signal is input, the execution of game control is started after the variable data storage means is initialized, and the interrupt signal output When an interrupt signal is input from the means, it is determined whether an instruction signal is input from the first initialization instruction means and a second detection signal is input from the first signal output means, Less instruction signal and second detection signal If it is determined that at least one is not input, the game control is started without initializing the variation data storage means, while the instruction signal is input and the second detection signal is input. When it is determined that the game data has been played, the game machine starts executing the game control after initializing the variation data storage means.   3. The gaming machine according to claim 2, wherein the power supply monitoring unit and the first signal output unit are disposed on a control board on which the game control unit is mounted.   The gaming machine according to claim 2, wherein the power monitoring means and the first signal output means are arranged in a power supply unit that supplies power to the game control means. A gaming machine in which a player can play a predetermined game,
Game control means for controlling the progress of the game, having a fluctuation data storage means for storing the fluctuation data that fluctuates according to the progress of the game,
A power supply monitoring means for monitoring a state of a predetermined power supply used in the gaming machine and outputting a first detection signal to the game control means when the start of power supply is detected;
Interrupt signal output means for outputting an interrupt signal for causing the game control means to start execution of game control at predetermined time intervals;
First initialization instruction means for outputting an instruction signal instructing the game control means to initialize the variation data storage means;
A second signal output means for outputting a third detection signal to the game control means on condition that the power supply monitoring means outputs a first detection signal;
With
When the first detection signal is input from the power supply monitoring unit, the game control unit receives an instruction signal from the first initialization instruction unit, and receives a third detection signal from the second signal output unit. When it is determined whether or not at least one of the instruction signal and the third detection signal is not input, execution of game control is started without initializing the variation data storage means. On the other hand, if it is determined that the instruction signal is inputted and the third detection signal is inputted, the execution of game control is started after the fluctuation data storage means is initialized, and the interrupt signal output When an interrupt signal is input from the means, it is determined whether an instruction signal is input from the first initialization instruction means and a third detection signal is input from the second signal output means, Less instruction signal and third detection signal If it is determined that at least one is not input, the game control is started without initializing the variation data storage means, while the instruction signal is input and the third detection signal is input When it is determined that the game data has been played, the game machine starts executing the game control after initializing the variation data storage means.   6. The gaming machine according to claim 5, wherein the power monitoring means and the second signal output means are disposed on a control board on which the game control means is mounted.   6. The gaming machine according to claim 5, wherein the power monitoring means and the second signal output means are arranged in a power supply unit that supplies power to the game control means.   The power monitoring means is disposed in a power supply unit that supplies power to the game control means, and the second signal output means is disposed on a control board on which the game control means is mounted. The gaming machine according to claim 5. A gaming machine in which a player can play a predetermined game,
Game control means for controlling the progress of the game, having a fluctuation data storage means for storing the fluctuation data that fluctuates according to the progress of the game,
A power supply monitoring means for monitoring a state of a predetermined power supply used in the gaming machine and outputting a first detection signal to the game control means when the start of power supply is detected;
Interrupt signal output means for outputting an interrupt signal for causing the game control means to start execution of game control at predetermined time intervals;
Second initialization instruction means for outputting an instruction signal instructing the game control means to initialize the variation data storage means;
A third signal output means for outputting a fourth detection signal on the condition that the supply start voltage of the power source is equal to or higher than a predetermined voltage;
The game control means is provided separately from the game control means, and when the fourth detection signal is input from the third signal output means and the instruction signal is input from the second initialization instruction means, the game control Fourth signal output means for outputting a fifth detection signal to the means;
With
When the first detection signal is input from the power supply monitoring unit, the game control unit determines whether the fifth detection signal is input from the fourth signal output unit, and the fifth detection signal is When it is determined that it has not been input, the execution of game control is started without initializing the variable data storage means. On the other hand, when it is determined that the fifth detection signal has been input, the variable data After the storage means is initialized, the game control is started. If an interrupt signal is input from the interrupt signal output means, is the fifth detection signal input from the fourth signal output means? If it is determined that the fifth detection signal is not input, the game control is started without initializing the variation data storage means, while the fifth detection signal is If it is determined that it has been input, After initializing the chromatography data storage means, a game machine, characterized in that to start the execution of the game control.   10. The gaming machine according to claim 9, wherein the power supply monitoring unit, the third signal output unit, and the fourth signal output unit are disposed on a control board on which the game control unit is mounted. . A gaming machine in which a player can play a predetermined game,
Game control means for controlling the progress of the game, having a fluctuation data storage means for storing the fluctuation data that fluctuates according to the progress of the game,
A power supply monitoring means for monitoring a state of a predetermined power supply used in the gaming machine and outputting a first detection signal to the game control means when the start of power supply is detected;
Interrupt signal output means for outputting an interrupt signal for causing the game control means to start execution of game control at predetermined time intervals;
Second initialization instruction means for outputting an instruction signal instructing the game control means to initialize the variation data storage means;
Fifth signal output means for outputting a sixth detection signal on condition that the power supply monitoring means has output the first detection signal;
Provided separately from the game control means, when the sixth detection signal is input from the fifth signal output means and the instruction signal is input from the second initialization instruction means, the game control Sixth signal output means for outputting a seventh detection signal to the means;
With
When the first detection signal is input from the power supply monitoring unit, the game control unit determines whether or not the seventh detection signal is input from the sixth signal output unit, and the seventh detection signal is If it is determined that it has not been input, the execution of game control is started without initializing the variable data storage means. On the other hand, if it is determined that the seventh detection signal has been input, the variable data After the storage means is initialized, the game control is started. If an interrupt signal is input from the interrupt signal output means, is the seventh detection signal input from the sixth signal output means? If it is determined that the seventh detection signal is not input, the game control is started without initializing the fluctuation data storage means, while the seventh detection signal is If it is determined that it has been input, After initializing the chromatography data storage means, a game machine, characterized in that to start the execution of the game control.   12. The gaming machine according to claim 11, wherein the power supply monitoring unit, the fifth signal output unit, and the sixth signal output unit are disposed on a control board on which the game control unit is mounted. .   The power monitoring means is disposed in a power supply unit that supplies power to the game control means, and the fifth signal output means and the sixth signal output means are disposed on a control board on which the game control means is mounted. The gaming machine according to claim 11, wherein the gaming machine is provided.   The first initialization instruction means or the second initialization instruction means is disposed in a power supply unit that supplies power to the game control means, and the interrupt signal output means is a control board on which the game control means is mounted. The gaming machine according to any one of claims 1 to 13, wherein the gaming machine is disposed in the box.   The game control means includes a microcomputer capable of executing a security check for determining whether or not a program for executing control is legitimate, and when the first detection signal is input, The gaming machine according to any one of claims 1 to 14, wherein the security check is executed.

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