JP2003511999A - Unsaturated magnetic element power converter and surge protection - Google Patents

Abstract

(57) [Summary] A tank resonance power conversion system using an NSME with a single, multi-stage, distributed magnetic switch. NSME, when implemented with the disclosed circuit strategy, has excellent protection against conducted lightning transients, a wide operating temperature band, higher magnetization efficiency, greater flux / power density possibilities, and greater. It provides flexibility of waveform ratio. Due to the effects of various feedback strategies, the output voltage is maintained substantially constant and without ripple, even in the presence of line and load fluctuations. By controlling the time and / or frequency of one or more switches, these mechanisms combine to create compensation. Implementation of the new function generator provides a signal that is a function of flux tracking, AC line fading and output voltage feedback, which results in power regulation, active ripple rejection, and power factor correction for the AC line. The optimal application of NSME achieves efficient energy storage and energy transfer. The use of efficient commutation flyback management techniques protects the switch and provides additional output. A second novel generator implementation provides a two-phase signal that is a function of the switching frequency / duty cycle and the output voltage, thereby effecting regulation. Higher efficiency is achieved by including a switching buffer that significantly reduces switching losses by providing a high slew rate, low source impedance, drive current that is attenuated to the limit to one or more main switches.

Description

Detailed Description of the Invention

CROSS REFERENCE APPLICATION This application is a continuation-in-part of US patent application Ser. No. 09/410/849 dated Jan. 10, 1999. FIELD OF THE INVENTION The present invention relates to converters, power supplies, and more specifically, not in a limiting sense,
Single-stage or multi-stage AC / DC or DC / DC isolated and non-isolated push-pull converters including forward, flyback, buck, boost, push-pull and resonant mode converters, and fast FET switching and efficient flyback management individual or distributed NSME (individual or
Power supply with distributed NSME and / or with input PFC (power factor correction) and input protection from lightning transients. The invention also makes it possible to disperse the magnetic element (s) to cope with packaging constraints, multiple secondary windings, or operation with very high winding voltages. BACKGROUND OF THE INVENTION There are several basic topologies that are commonly used to implement switching converters.

A DC-DC converter is a device that converts a DC voltage at one level into a DC voltage at another level. Converters generally include magnetic elements having primary and secondary windings wound around them to form a transformer. By opening and closing the primary circuit at appropriate intervals, control over energy transfer between the windings occurs. The magnetic element provides an alternating voltage and current whose amplitude can be adjusted by changing the number of turns and turns ratio in each winding set. The magnetic element provides galvanic isolation between the input and output of the converter.

One topology is a push-pull converter. The output signal is the output of the IC circuitry that alternately switches the transistors "on" and "off".
A high frequency square wave on the transistor output drives the magnetic element into an AC (alternating current) bias. The isolated secondary outputs a wave that is rectified to produce DC (direct current). Push-pull converters generally have more components than other topologies. The push-pull approach allows the magnetic elements to be used efficiently by generating an AC bias, but has a high component count, thermal derating, oversized magnetic elements and delicate cores. I am troubled by the reset mechanism. The destructive flyback voltage developed across the switch is controlled by using an energy dissipative snubber network located across the primary switch. Another one
One topology is a forward converter. When a voltage is applied to the primary side of the forward converter, energy is immediately transferred to the secondary winding. In addition to the problems mentioned above, forward converters suffer from the underutilization of magnetic elements (dc bias). Prior art power supplies use high permeability gapped ferrite magnetic elements. These are well known in the art and are widely used. The magnetic elements of prior art power supplies are generally designed to double the required power rating and require complex methods to reset and cool the magnetic elements, resulting in increased cost and limited operating temperature. It This is because the high-permeability magnetic element saturates during operation, producing heat in the core, which increases the permeability and lowers the saturation threshold. Therefore, runaway heating
), Current spikes and / or large leakage currents in the air gap, reduced efficiency, and ultimately reduced power at higher temperatures and / or higher loads. Overall, reliance on forced air cooling / heatsink which requires overrated ferrite magnetic elements for reduced efficiency, reduced power density, and given output over time, temperature and load It is affected by the power supply. Improvements The combined improvements of the present invention manifest in the form of higher system efficiency, higher power densities, lower operating temperatures and improved thermal tolerances, thus requiring forced air cooling per unit output. Reduce or eliminate. Unsaturated magnetic properties (no
n-saturating magnetic property is relatively insensitive to temperature (Fig. 1
7), thus allowing the converter to operate over a larger temperature range. In practice, operating temperature for NSME is 200 ° C due to wire / core insulation
However, the unsaturated magnetic material is capable of operating near its Curie temperature of 500 ° C.

What is needed is an individual and distributed NSME (individual and distributed).
NSME) is a converter with a circuit method that advantageously uses.

What is needed is a converter with a buffer circuit that provides fast, low impedance, critically damped switching of the main FET.

What is needed is an excessive node voltage (node vol) across the converter switch.
Efficient multiple "stressless (stress-l
ess) "is a converter that incorporates a flyback management technique.

What is needed is a converter with flux feedback frequency modulation.

[0008]   What is needed is a converter that corrects the AC power factor.

What is needed is a converter that meets or exceeds the requirements for Class B conducted EMI.

What is needed is a converter that can withstand lightning and harsh thermal environments. The present invention addresses these and more. SUMMARY OF THE INVENTION A primary aspect of the present invention implements a converter having a circuit method that advantageously uses discrete and distributed NSMEs to achieve the key performance enhancements disclosed herein. That is.

Another aspect of the present invention is the higher one in the generation of high frequency / high density magnetic flux.
Individual and distributed NSM using secondary circuit voltage excursion
It is to provide a unique resonant tank circuit converter method with E.

Another aspect of the invention is a high energy density, single stage frequency controlled resonant tank converter topology enabled by using discrete and distributed NSMEs. Another aspect of the present invention is a converter design utilizing an FET drive technique consisting of an ultra-fast, low RDS N-channel FET to charge the main FET gate and an ultra-fast P-channel transistor to discharge the main FET gate. Is to provide.

Another aspect of the invention is to provide a converter that incorporates an efficient multiple “stressless” flyback management technique to rectify and critically dampen excess node voltage across the converter switch. Is.

Another aspect of the present invention is a core-synchronized zero-cross frequency modulation (core).
(flux) synchronized zero crossing frequency modulation).

Another aspect of the invention is to provide a high power factor for the AC line.

Another aspect of the present invention is to provide protection against high voltage (incoming) transients.

Another aspect of the invention is the advantageous combination of distributed magnetic elements with other converter aspects.

Another aspect of the invention is the active ripple rejection (acti) provided by some high gain high speed isolated control and feedback systems.
ve ripple rejection).

Other aspects of the invention will be described below with reference to the accompanying drawings, in which the same reference characters refer to corresponding parts in the several views, which form a part of the specification. It seems to be clear from.

Before describing the disclosed embodiments of the invention in detail, the invention is capable of other embodiments and its application to the details of the particular arrangement shown or described. It should be understood that it is not limited.

The expression “distributed magnetic” shares a single series coupled primary winding to induce an output current isolated from multiple series or parallel secondary windings. It means the structure of multiple magnetic elements.

Similarly, the terminology used herein is for the purpose of description and not of limitation. Description of the Preferred Embodiments In this and other descriptions contained herein, the following symbols have the following meanings to them. That is, "+" represents a series connection, such as resistor A in series with resistor B shown as "A + B". 「｜｜
Is a resistor A in parallel with a resistor B shown as "A || B",
Indicates parallel connection.

[0023]   Reference is first made to FIG. 7, which is a schematic diagram of a preferred embodiment of the present invention.

FIG. 7 is a schematic diagram of a preferred embodiment of a sub-circuit TCSSC of a tank coupled single stage converter. The sub-circuit TCSSC includes resistors R20 and RLOAD, capacitors C10, transistors Q21 and Q11, sub-circuit CP (FIG. 26), sub-circuit PFT1 (FIG. 18), sub-circuit OUTA (FIG. 25), sub-circuit AMP (FIG. 29). , A sub-circuit IFB (FIG. 40B), and a sub-circuit PWFM (FIG. 33).

[0025]

[Table 1]

The TCSSC may be configured to operate as an AC-DC converter, a DC-DC converter, a DC-AC converter, and an AC-AC converter. The sub-circuit TCSSC includes resistors R20 and RLOAD, a capacitor C10, switches Q11 and Q21, an opto-isolator U12, a sub-circuit PFTI (FIG. 18),
Sub circuit OUTA (FIG. 25), sub circuit CP (FIG. 26), sub circuit AMP (FIG. 2)
9), the sub-circuit IFB (FIG. 40B) and the sub-circuit PWFM (FIG. 33).
The external power supply VBAT is connected to the pins DCIN + and DCIN-. Source power can also be derived from a rectified AC line voltage as in FIG. 20 or 21 to form a single stage power factor correction AC / DC converter with an isolated output. From DCIN +, resistor R20 is connected to pin CP + of subcircuit CP,
Connect to pin GA +, U12LED anode of sub-circuit AMP and pin PWFM + of sub-circuit PWFM. The resistor R20 is a sub-circuit C of the control power supply regulator.
Provide start-up power to the converter until P reaches the desired 18 volt output. The negative side of VBAT has pins PWFMB, Q11 of the sub-circuit PWFM.
Source, pin GA0 of sub-circuit AMP, pin CT0 of sub-circuit CP, pin DC
IN- and a ground return node connected to pin S1CT of sub-circuit PFT1. The node S1H of the magnetic element winding of the sub circuit PFT1 is connected to the pin CT1A of CP. The node S1L of the magnetic element winding of the sub circuit PFT1 is connected to the pin CT2A of the CP. The sub-circuit PWFM is designed as a variable frequency generator with a constant 50% duty-cycle. The clock output pin CLK of the sub circuit PWFM is connected to the input of the pin GA1 of the buffer sub circuit AMP. Buffer sub circuit A
The output of pin GA2 of MP is connected to the gate of Q11 and R21. Resistor R21 is connected to the cathode of the U12 LED. The emitter of Q21 and the drain of Q11 are connected to the pin P1A of the sub-circuit PFT1. The pin P1B of the sub-circuit PFT1 is connected to the collectors of the nodes DCIN +, Q21 through a tank capacitor C10 and to the collector of the U12 phototransistor through a resistor R61. The emitter of the U12 phototransistor is connected to the base of Q21. The pin CLK of PWFM is high (hi
gh), transistor Q11 conducts, charging capacitor C10 from VBAT through NSME's PFT1 to store energy in PFT1. Sub circuit P
WFM switches CLK low and Q11 is "off." CL
With K low, the LED of U12 turns "on" and injects base current into Q21. When the transistor Q21 is "on", the tank circuit is completed and the capacitor C1
0 will allow discharge into the NSME PFT1 winding 100 (FIG. 18). Energy not transferred to the load at this time is released from the NSME PFT1 into the now forward biased NPN switch Q21 and returns to the capacitor C10. Thus, any energy not used by the secondary load remains in the tank-coupled primary circuit (winding 100). When switching occurs at its resonant frequency, high voltage oscillations occur between C10 and winding 100, creating a high flux density AC excursion in PFT1. C10 and PFT1 exchange a variable AC current whose magnitude is controlled by the frequency modulation scheme IFB and PWFM. The large primary voltage produces a large RF bias in the NSME's PFT1 and thereby the high flux density AC excursion to be taken by the secondary windings 102 and 103 (FIG. 18) to support the load or rectifier subcircuit OUTA. To generate. The magnetic element winding node S2H of the sub-circuit PFT1 is connected to the pin C7B of OUTA. The magnetic element winding node SIL of the sub circuit PFT1 is connected to the pin C8B of OUTA. The magnetic element winding node S2CT of the sub circuit PFT1 is connected to the pin OUT- of OUTA. Node O
UT- is connected to RLOAD, pin B- and pin OUT- of subcircuit IFB. The rectified power is sent to pin OUT + of OUTA and is connected to RLOAD, pin B + and pin OUT + of sub-circuit IFB. Sub circuit IFB
Provides an isolated feedback signal to the subcircuit PWFM. The frequency control pin FM1 of the sub circuit PWFM is connected to the pin FBE of the sub circuit IFB. The internal reference pin REF of the sub-circuit PWFM is the pin F of the sub-circuit IFB.
It is connected to BC. PWFM is the resonant frequency of the tank (2 ^* Pi ^* (square root (
It is designed to work with C10 ^* 100 (inductance of FIG. 18))). When the sub circuit IFB detects that the converter output is at the target voltage, P
Current from the WFM pin REF is injected into FM1. Injecting current into FM1 commands the PWFM to a lower clock frequency on pin CLK. Driving the tank out of resonance reduces the amount of energy added to the tank,
Thus, the converter output voltage is reduced. If the feedback signal from the IFB commands PWFM off or 0 Hz, i.e. no load, all primary activity ceases. The input current from VBAT can be steady state or variable DC. High input (line) power factor and input transient protection is achieved when the TCSSC is operated from rectified AC (subcircuit LL, FIG. 20). 1 of PFT1
The secondary and secondary currents are sinusoidal and have no edge transitions, making the converter very quiet. Furthermore, the switches Q11 and Q21 are never exposed to the large circulating voltage induced in the tank (see FIG. 35). This allows the design to use lower voltage switches to reduce losses and increase MTBF. Sub circuit TC
SSC utilizes the desirable properties of NSME in this converter topology. TCSSC is well suited for implementation with the distributed NSME PFT1D (FIG. 18C). This combination of how distributed magnetic elements provides an advantageous high voltage converter design that supports flexibility in form factor and multiple parallel secondary outputs from a series-coupled and divided primary winding across multiple NSMEs. An example of how deformation is possible is shown. This magnetic strategy is useful in addressing wire / core isolation, form factor and packaging limitations, circuit complexity and manufacturability. These converter strategies are very useful for obtaining isolated high current density output from high voltage low current series coupled primary side. Adjusting the secondary turn's ratio allows the TCSSC to generate very large AC or DC output voltages as well as low voltage high current outputs. (Additional Embodiment) FIGS. 1 and 1A are schematic diagrams of a two-stage power factor corrected AC / DC converter. The invention consists of a line protection filter subcircuit LL (FIG. 20) and a full-wave rectifier subcircuit BR (FIG. 22). Sub circuit PFA2 (FIG. 23), snubber sub circuit SN (FIG. 30), magnetic element sub circuit PFT1 (FIG. 18), sub circuit CP (FIG. 2)
6), the buffer sub-circuit AMP (FIG. 29), the over-temperature sub-circuit OTP (FIG. 28)
), A power factor corrected regulated boost stage with an overvoltage feedback subcircuit IPFFB (FIG. 40) and a voltage feedback subcircuit IFB (FIG. 40B). Start-up resistor R2, filter capacitor C1, PFC capacitor C
2. Flyback diode D4, switch transistor Q1, hold up capacitors C17 and C16 and resistor R17. Sub-circuit CPA (FIG. 27), PPG (FIG. 43), AMP1 (FIG. 29), AMP2 (FIG. 29), snubber sub-circuit SNB (FIG. 32) and SNA (FIG. 31), resistor R
load, transistors Q6 and Q9, magnetic element PPT1 (FIG. 19), and OU
Efficient push-pull isolation stage with TA (Figure 25).

[0027]

[Table 2]

In a two-stage converter, the primary voltage to the second push-pull output stage is modulated by a power factor corrected input (boost) stage. Each stage is individual type and distributed type N
It can consist of SMEs. A graph of BH hysteresis for unsaturated magnetic elements is shown in FIG. The following description relates to specific converter topologies, namely flyback controlled primary and constant duty cycle push-pull secondary, the number of outputs of some of which,
The styles and arrangements are provided by way of example and not limitation. Furthermore, the unsaturated magnetic elements BL1, PFT1 and PPT1 can also be implemented as distributed NSMEs. As an example, PFT1 is shown as distributed magnetic element PFT1A (FIG. 18C). Distributed magnetic element, multiple NSME
Allows for a variation of the advantageous high voltage converter design that supports form factor flexibility and multiple parallel secondary outputs from a series coupled, voltage divided primary winding across. The negative side of the holdup capacitor (s) [C17 || C16] is connected to the positive side of the bridge. This allows the rectified line voltage to be excluded from the boost voltage at the holdup capacitor (s).
This, in turn, allows direct adjustment of the push (PFC) stage to the push-pull stage. This eliminates the typical PWM control of oversized, thermally derated transformers and many sub-circuit components from the known art. The AC line is a sub-circuit LL (see FIG. 2) between pins LL1 and LL2.
0). The AC / ground ground is connected to node LL0. The filtered and voltage limited AC line appears on node / pin LL5 of subcircuit LL and is connected to node BR1 of bridge rectifier subcircuit BR (FIG. 22). The filtered and voltage limited AC neutral / AC return leg appears at pin LL6 of subcircuit LL and is connected to the input pin BR2 of BR. The line voltage is full-wave rectified and the subcircuit BR (
It is converted into a positive haversine that appears on node BR + in FIG. 22). Start-up resistor R2 connects BR + to pin CP + of subcircuit CP. The node CP + is connected to the pin PFA + of the control element sub-circuit PFA (FIG. 23) and the pin GAP of the over-temperature switch sub-circuit OTP (FIG. 28). Resistor R2
Provides start-up power to the control element until the rectifier / regulator CP is at full power. The node S1H from the PFT1 is connected to the node PFVC of the sub circuit PFA. Zero crossing of the core is detected when the voltage at S1H is zero. The core zero crossing is used to reset the PFC and start a new cycle. The positive node on the DC side of bridge BR + is connected to BR- through capacitor C2. C2 is selected for various line and load conditions to de-couple switching currents from the line and improve power factor while reducing line harmonics and EMI. . Pins P1B and S2CT of NSME subcircuit PFT1 (FIG. 18)
Is connected to the pin SNL1 of the sub circuit SN (FIG. 30) of the snubber and the sub circuit BR.
, To pin BR + and to pin BR + (FIG. 1A). Rectified AC
The return line BR- for power is connected to the following pins. That is, the sub circuit B
BR- of R, pin BR- of PFA, pin GA0 of sub-circuit AMP, source of output switch Q1, capacitor C2, pin CT0 of sub-circuit CP, sub-circuit PFT
1 through pins S1CT and CT20, EMI filter capacitor C1 and connected to earth ground node LL0. Pin BR + from FIG. 1 is the pin of sub-circuit CPA of FIG. 1A, the pin SNL1 of SN, the pin P1B of sub-circuit PFT1,
And the pin S2CT of the sub-circuit PFT1. 1A, the pin BR + continues to the pin CT20 of the sub circuit CPA, the pin PPG0 of the PPG (FIG. 43), the pin GA0 of the sub circuit AMP1, the pin GA0 of the sub circuit AMP2, and the sub circuit IPFFB.
Pin PF-, capacitor [C16 || C17 || resistor R17], source of transistor Q6, source of transistor Q9, pin SNA2 of sub-circuit SNA and pin SNB2 of sub-circuit SNB. The drain of the output switch Q1 is connected to the anode of the diode D4, the pin SNL2 of the sub circuit SNB, and the sub circuit PF.
It is connected to the pin P1A of T1 and the pin SNL2 of the sub-circuit SN. Snubber circuit S
N reduces the high voltage stress on Q1 until the flyback diode D4 begins to conduct. The line coupled, power factor corrected, boost regulated output voltage of the AC / DC converter stage (FIG. 1) appears on node PF +. Additional efficiency can be achieved by connecting sub-circuit DSN (FIG. 30A) in parallel with D4. Adjusted boost output PF +
Connects to: That is, the pin SNOUT of the sub circuit SN, the pin SNOUT of the sub circuit DSN, and the cathode of the diode D4. Similarly for the node PF +, the capacitor [C16 || C17 || R17] and the sub-circuit IPFFB (
40) pin PF +, sub-circuit PPT1 (FIG. 19) pin P2CT, snubber sub-circuit SNA (FIG. 31) pin SNA3 and snubber SNB (FIG. 32) pin S.
Also connect to NB3. The pin S1H of the magnetic element winding of the sub circuit PFT1 is connected to the pin CT1A of the CP and the pin PFVC of the sub circuit PFA. Sub circuit PFT
The 1 magnetic element winding node S1L is connected to the pin CT2A of the CP. Sub circuit P
The magnetic element winding node S2H of FT1 is connected to pin 10 of FIG. 1A, then CP
It is connected to the A pin CT1B. Magnetic element winding node S2L of sub circuit PFT1
Is connected to pin 12 of FIG. 1A and then to pin CT2B of the CPA. The sub-circuit PFA using the AC line phase, load voltage, and magnetic element feedback generates the command pulse PFCLK. Pin P of sub-circuit PFA (Fig. 23)
FCLK is connected to the input terminal of pin GA1 of the buffer amplifier of sub-circuit AMPI (FIG. 29). High-speed gate drive output pin G through the buffer of sub-circuit AMP
A2 is connected to the gate of Q1 of the switch FET. Due to the buffering provided by the AMP, the on / off time of the switch Q1 is shortened and the switch loss is significantly reduced (see FIGS. 13 and 14). Q1 with pin GA0
Source is connected to the return node BR-. Power supply for sub-circuit AMP (po
wer) is connected from the pin TS + to the pin GA + of the sub circuit OTP. The thermal switch THS1 is connected to Q1. When the Q1 case reaches approximately 105C, THS1 opens, removing power to the subcircuit AMP and safely shutting down the first (input) stage. Normal operation resumes after the switch temperature has dropped 20-30 ° C. and THS1 has been closed. The drain of the output switch Q1 is connected to the primary winding pin P1A of the unsaturated magnetic element sub-circuit PFT1 (FIG. 18) and the pin SNL2 of the snubber sub-circuit SN (FIG. 30). The reference voltage from the pin PFA2 of the sub circuit PFA of the PFC is the pin F of the sub circuit IPFFB of the feedback circuit.
Connected to BC and pin FBC of sub-circuit IFB. The control current feedback circuit is summed at node PF1 of subcircuit PFA. The pin PF1 is connected to the pin FBE of the sub circuit IPFFB of the feedback circuit and the FBE of the sub circuit IFB pin. Non-ov of constant frequency / duty cycle
The erlapping) two-phase generator subcircuit PPG (FIG. 431A) generates the drive for the push-pull output stage. Phase 1 output pin PH1 is a sub-circuit AM
It is connected to the pin GA1 of P1 and the second phase output pin PH2 is connected to the subcircuit AMP2 pin GA1. The output of pin GAP2 of amplifier buffer subcircuit AMP1 is connected to the gate of push-pull output switch Q6. The output of pin GAP2 of amplifier buffer subcircuit AMP2 is connected to the gate of push-pull output switch Q9. Buffering current from AMP1 and AMP2
rrent) provides high speed, low impedance, critically damped switching for Q6 and Q9, greatly reducing on-off transition times and switching losses. The regulated 18 volt power supply from pin CP2 + of subcircuit CPA (FIG. 1A) is connected to pin GA of amplifier buffer subcircuit AMP1.
+, Connected to the pin GA + of the amplifier buffer subcircuit AMP2 and the pin PPG + of the subcircuit PPG. The drain of the transistor Q6 is connected to the pin SNB1 of the sub circuit SNB of the snubber circuit and the sub circuit PP of the primary magnetic element with the unsaturated center tap.
It is connected to pin P2H of T1. The drain of the transistor Q9 is the pin SNA1 of the sub circuit SNA (FIG. 31) of the snubber circuit and the pin P2 of the sub circuit PPT1.
It is connected to L. The source of the transistor Q6 is the sub circuit SN of the snubber circuit.
B pin SNB2, source of transistor Q9, sub-circuit SNA pin SNA2
And the return node BR +. The isolated output of pin SH of subcircuit PPT1 of NSME is at pin C7B of rectifier subcircuit OUTA (FIG. 25A).
And pin SL is connected to C8B of subcircuit OUTA. Pin S of PPT1
The center tap of CT is the output return or negative node OUT-, which is pin OUT- of subcircuit OUTA and pin OUT of subcircuit IFB (Fig. 40B).
-And RLOAD. The positive output of the converter from pin OUT + of subcircuit OUTA is connected to RLOAD and pin OUT + of subcircuit IFB.
Elements LL1, BR, PFA, AMP, Q1, IPFFB, IFB and PF of FIG.
T1 (input stage) implements AC / DC conversion with power factor correction. The regulated high voltage output of this converter is PPG, AMP1, AMP2, Q6, Q9, PPT.
Provides an efficient fixed frequency / duty cycle push-pull stage including 1 and OUTA (FIG. 1A). The magnetic element subcircuit PPT1 provides galvanic isolation and minimal voltage overshoot and ripple on the secondary side, thus minimizing the filtering requirements of the rectifier subcircuit OUTA. The 5 volt reference output from pin PFA2 of subcircuit PFA connects first to pin 15, and then to pin FBC of subcircuit IPFFB and pin FBC of subcircuit IFB of FIG. 1A. The pulse width control input from PF1 of the subcircuit PFA pin is to pin 14, then pin FBE and subcircuit IF of subcircuit IPFFB of FIG. 1A.
Connect to B pin FBE. The sub-circuit IFB provides fast feedback to the AC / DC converter and the speed of the boost stage provides fine output voltage regulation and active ripple rejection.
In the event of a sudden line or load change, the sub-circuit IPFFB compensates for internal boost to maintain regulation at the isolated output. Remote load sensing and other feedback methods known in the art can be implemented in sub-circuit IPFFB. This configuration provides power factor corrected input transient protection, rapid line-
Offers rapid line-load response, excellent regulation, isolated output and quiet, efficient operation at high temperatures.

FIG. 2 is a schematic diagram of one embodiment of a DC / AC converter. DCA of the present invention
C1 is an efficient push-pull converter. Sub-circuit PPG (FIG. 43),
AMP1 (FIG. 29), AMP2 (FIG. 29), SNB (FIG. 32), SNA (FIG. 31)
), PPT1 (FIG. 19) and OUTA (FIG. 25), and switches Q6 and Q9.

[0030]

[Table 3]

The converter ACDC1 receives the variable DC voltage and efficiently converts it to a variable AC voltage output at a fixed frequency. Variable frequency operation can be achieved with simple modifications to the PPG. In this embodiment, fixed frequency operation is required. The magnetic element includes an unsaturated magnetic element. A graph of BH hysteresis for unsaturated magnetic elements is shown in FIG. The variable DC voltage is applied to pin DC +. The pin DC + is the next pin P2CT of the sub circuit PPT1 (FIG. 19), the pin SNA3 of the snubber sub circuit SNA (FIG. 31), and the pin SN of the snubber SNB (FIG. 32).
Connect to B3. The constant frequency non-overlapping two-phase generator subcircuit PPG (FIG. 43) generates the drive for the push-pull output switch. Phase 1 output pin P
H1 is connected to the pin GA1 of the sub-circuit AMP1, and the second phase output pin PH2
Is connected to the pin GA1 of the sub-circuit AMP2. The output of pin GAP2 of amplifier buffer subcircuit AMP1 is connected to the gate of push-pull output switch Q6. The output of pin GAP2 of amplifier buffer subcircuit AMP2 is connected to the gate of push-pull output switch Q9. The buffering provided by AMP1 and AMP2 reduces the on / off time of switch Q1 and significantly reduces switching losses (see FIGS. 13 and 14). An externally regulated 18 volt power supply from pin P18V provides the amplifier buffer subcircuit AMP1 pin GA +, the amplifier buffer subcircuit AMP2 pin GA + and the subcircuit PPG pin PPG +.
Connected to. The drain of the transistor Q6 is connected to the pin SNB1 of the sub circuit SNB of the snubber circuit and the pin P2H of the sub circuit PPT1 of the unsaturated primary magnetic element with a center tap. The drain of the transistor Q9 is connected to the pin SNA1 of the sub circuit SNA (FIG. 31) of the snubber circuit and the pin P2L of the sub circuit PPT1. The source of the transistor Q6 is the pin SNB2 of the sub circuit SNB of the snubber circuit, the source of the transistor Q9, the pin SNA2 of the sub circuit SNA, the pin GA0 of the sub circuit AMP1, the pin GA0 of the sub circuit AMP2, the pin PPG0 of the sub circuit PPG, and the return. Connected to pin DC-. The AC output of the pin SH of the NSME subcircuit PPT1 is connected to the pin ACH and the pin SL is connected to the pin ACL.
The center tap of pin SCT of PPT1 is connected to pin AC0. The magnetic element subcircuit PPT1 provides galvanic isolation and minimal voltage overshoot and ripple on the secondary side, thus minimizing filtering requirements when a rectifier assembly is installed. The sub-circuit DCAC1 is an independent converter,
Alternatively, it can be used as a fast, quiet and efficient stage in a multi-stage converter system. Subcircuit DCAC1 achieves isolated output, quiet operation, efficient conversion, and high and low temperature operation.

3 and 3A show a three-step modification of the present invention. The device consists of an AC-DC or DC-DC boost converter stage, a DC-DC forward converter stage, and a push-pull stage. This system has a low current buck regulation (buck
regulation), switching through buffers, snubbing with rectification (recti
The loss is reduced by combining fied snubbering) and NSME at each stage. Power factor correction to ensure that any load connected to the converter looks like a resistive load to the AC line and eliminates unwanted harmonics and displacement currents in the AC power line. The boost stage is used. Minimize magnetizing loss and reduce coupling efficiency (
improve the coupling efficiency), minimize the heating of the magnetic element, eliminate the spike / gap leakage of the saturated core current, reduce the number of parts, reduce the thermal deterioration, MTB
In order to increase F (mean time before failure), NSMEs with lower magnetic permeability compared to the prior art are used. The present invention also includes a main FET
An emitter follower circuit with fast switching FETs is also used to slew the gate of the. The use of unsaturated magnetic elements allows for higher voltage operation, which reduces the current in direct proportion and further reduces the loss of switches, magnetic elements and conductors due to I ² R heating. High voltage FET switches have the added benefit that lower gate capacitance results in faster switching. At turn-on, the n-channel gate drive FET quickly charges the gate of the main FET. At turn off, the PNP Darlington transistor switch discharges the gate of the main FET quickly. The flyback effect in the PFC stage is an output diode with a diode additionally capacitor-coupled across the switched magnetic element to decouple and further weaken the inductive flyback. Rectification R positioned at both ends of
It is managed by using the C circuit. The invention consists of a sub-circuit LLI of the line protection filter (FIG. 21) and a sub-circuit BR of the full-wave rectifier (FIG. 22) and a power factor correction adjusting boost stage with capacitors C1 and C2. Sub-circuit PFB (
24), resistor R2, rectifier CP (FIG. 26), magnetic element PFT1 (FIG. 18),
Over temperature protection OTP (Fig. 28), snubber SN (Fig. 30), gate buffer AMP
(FIG. 29), switch transistor Q1, flyback diode D4, holdup capacitors C17 and C16, bleed resistor R17, and voltage feedback subcircuit FBA (FIG. 40A) are also included. Sub-circuit PWFM (Fig. 33
), Current detection resistor R26, rectifier CPA (FIG. 27), magnetic element BL1 (FIG. 18).
B), overvoltage protection OVP (FIG. 42), IPFFB (FIG. 40) gate buffer AM
P3 (FIG. 29), switch transistor Q2, flyback diode D70,
An efficient second preconditioning back stage with a storage capacitor C4 and a voltage feedback sub-circuit IFB (FIG. 40B) is also included. Sub-circuit CPA (Fig. 2
7) Two-phase generator PPG (FIG. 43), gate buffer AMP1 (FIG. 29) and A
MP2 (FIG. 29), switch transistors Q6 and Q9, snubber SNA (FIG. 31)
) And SNB (FIG. 32), magnetic element PPT1 (FIG. 19) and rectifier OUTA (FIG. 25), an efficient third push-pull isolation stage is also included.

[0033]

[Table 4]

The AC line is connected to the sub-circuit LLA (FIG. 21) between the pins LL1 and LL2. AC / earth ground is connected to node LL0. The filtered and voltage limited AC line is connected to the node / pin LL of the subcircuit LLA.
5 and is connected to the node BR1 of the bridge rectifier subcircuit BR.
The filtered and voltage limited AC neutral / AC return appears on pin LL6 of subcircuit LL and is connected to the input pin BR2 of BR. The line voltage is full-wave rectified and converted into a positive Haver sine appearing at node BR + of subcircuit BR. The start-up resistor R2 connects BR + to the pin CP of the sub-circuit CP.
Connect to +. The node CP + is connected to the pin PFA + of the control element sub-circuit PFB and the pin GAP of the over-temperature switch sub-circuit OTP. Resistor R2 provides start-up power to the control element until regulator CP is at full output. PFT
The node S1H from 1 is pin 31 (FIG. 31) first, then pin C of the subcircuit CP.
Connected to pin PFVC of T1A and subcircuit PFB. The zero crossing of the core bias is detected when the voltage at S1H is at zero with respect to BR-. This core zero crossing is used to reset the PFC and start a new cycle. The positive node on the DC side of bridge BR + is connected to BR- through capacitor C2. Capacitor C2 is selected for various line and load conditions to isolate switching current from the line and improve power factor. The pin BR + of the sub circuit BR is connected to the pin SNL1 of the sub circuit SN of the snubber and the pin BR + (FIG. 3A) of the sub circuit PFB, and then the sub circuit PFT1 of the NSME.
Is connected to the primary side pin P1B and the sub circuit OVP pin BR +. The return line for rectified AC power is connected to the following pins. That is, BR- of the sub-circuit BR, pin S1CT of the sub-circuit PFT1, pin BR- of the PFC sub-circuit PFB.
, The pin BR− of the sub circuit FBA, the capacitor C2, the pin CT0 of the sub circuit CP,
Earth ground node LL0 through pin FBE of subcircuit IPFFB and EMI filter capacitor C1. The node BR- continues to FIG. 3A, R26,
Capacitor [C16 || C17 || R17], pin BR− of sub-circuit OVP, pin PWFM0 of sub-circuit PWFM, pin GA0 of sub-circuit AMP3, switch Q2
Connect to the source of. The floating ground node PF− is a magnetic element sub-circuit PF.
Pin S2CT of T1, pin CT20 of rectifier subcircuit CPA, generator subcircuit P
Pin PPG0 of PG (FIG. 43), pin GA0 of sub-circuit AMP1, sub-circuit AM
Pin GA0 of P2, capacitor C4, magnetic element BL1 pin, source of transistor Q6, source of transistor Q9, pin SNA2 of sub-circuit SNA, pin SNB2 of sub-circuit SNB, pin PF- (FIG. 3), and then sub-circuit Connect to pin PF- of IPFFB. The drain of the output switch Q1 is connected to the anode of the diode D4, the pin SNL2 of the sub circuit SN, then the pin 34 of FIG. 3A, and then the sub circuit PF.
It is connected to the T1 pin P1A. Snubber SN reduces high voltage stress on Q1 until flyback diode D4 begins to conduct. By adding a sub-circuit DSN (FIG. 30A) across the flyback diode D4, additional rectification efficiency and protection is achieved. The feedback-corrected boost output voltage of the power factor correction AC / DC converter stage appears across nodes PF + and PF-. The regulated 385 volt boost output node PF + connects to: pin SNOUT of subcircuit SN, cathode of diode D4, pin PF + of subcircuit IPFFB (FIG. 40), pin PF + of subcircuit FBA, then 3A, pin PF +, capacitor [C16 || C17 || R17], magnetic element sub-circuit PTT1 (FIG. 19) pin P2CT, snubber sub-circuit SNA (FIG. 31).
Pin SNA3, and snubber SNB (FIG. 32) pin SNB3, sub-circuit OVP
Pin PF +, capacitor C4 and cathode of diode D70. The magnetic element winding node S1H of the sub circuit PFT1 is connected to the pin 31 (FIG. 3), and then to the pin CT1A of the sub circuit CP and the pin PFVC of the sub circuit PFB. The magnetic element winding node S1L of the sub circuit PFT1 is connected to the pin 33 (FIG. 3), and then the sub circuit CP
Is connected to the pin CT2A. The magnetic element winding node S2H of the sub circuit PFT1 is connected to the pin CT1B of the CPA. Magnetic element winding node S of sub-circuit PFT1
2L is connected to pin CT2B of CP. The sub-circuit PFB uses the feedback from the phase of the AC line, the Q1 switch current, the magnetic bias first stage and the output voltage feedback to generate the command pulse on pin PFCLK. Sub circuit PF
The pin PFCLK of B (FIG. 24) is connected to the input pin GA1 of the buffer AMP amplifier of the sub-circuit AMP1. The high speed low impedance gate drive output pin GA2 via the buffer of the sub circuit AMP is connected to the gate of the switch FET Q1. The buffering provided by AMP reduces the "on" and "off" times of switch Q1 and significantly reduces switch loss (FIG. 13).
And 14). The source of Q1 is connected to pin GA0 of subcircuit AMP, pin 35 of FIG. 3A, and then to a current sense resistor R26 connected to return node BR-.
The voltage developed across R26 is fed back to the PFB pin PFSC. This signal is used to protect the switch by reducing the pulse width in response to an overcurrent fault induced by a low line or high load. The return line of pin BR- of sub-circuit FBA is node BR- and pin B- of sub-circuit PFB.
Connected to R-. This feedback is non-isolated, ie the first stage is P
The circuit value is selected to produce an output of 385 volts at F +. The pin PF1 of the feedback circuit FBA (FIG. 40A) of the sub circuit is the pin PF1 of the sub circuit PFB.
It is connected to the. The controller PFB is independent of line and load conditions.
Modulate the PFCLK signal to maintain a substantially constant 385 volts at F +. If a component failure occurs in subcircuit FBA, the PBF may command the converter for very high voltages. The sub-circuit OVP is
The first stage boost is monitored so that if it exceeds 405 volts, the OVP will clamp the output of subcircuit BR and open fuse F1 in subcircuit LLA. An alternative overvoltage circuit OVP1 (FIG. 42A) can replace the OVP and clamp the 18 volt control power supply to stop the boosting action of the converter without opening the fuse. The output of the converter sampled at the node from pin PF1 of subcircuit FBA is connected to pin PF1 of subcircuit PFB. The HaverSine on BR + is used by the PFB with an internal multiplier to generate a variable width control pulse on pin PFCLK. The high frequency modulation of switch Q1 makes the load / converter appear to be resistive to the AC line. Over temperature protection subcircuit OTP pin TS +
Are connected to the pin GA + of the sub-circuit AMP. Thermal switch THS1
Are connected to Q1. When Q1 reaches approximately 105 ° C., THS1 removes power to the open subcircuit AMP, safely shutting down the first stage. After the temperature drops by 20 to 30 ° C. and THS1 is closed, normal operation resumes. The second stage is configured as a buck stage. This is the first stage 38
Receive 5 volt output. By utilizing the energy storage element capacitor C4 of the second floating reference node RF-, the voltage to the final push-pull stage can be adjusted with minimal losses. The power supply from pin CP18V + of subcircuit CP is connected to pin 30 of FIG. 3A, and then pins PWM + and A of subcircuit PWFM (FIG. 33).
Connected to pin GA + of MP3. The feedback current from pin FBC of subcircuit IPFFB is first to pin 36 (FIG. 3A) and then to pin F of subcircuit IFB.
It is connected to BC and pin PF1 of subcircuit PWFM. Subcircuit IPFFB diverts current from this node only if the output of the second stage is greater than 200 volts. When the converter reaches its designed output voltage, the IFB will
It diverts the current from pin PF1 of M and signals PWFM to reduce the pulse width on pin PWMCLK. The input pin of the sub circuit AMP3 is the sub circuit PWF.
It is connected to the M pin PWMCLK. The output of pin GA2 of the AMP3 buffer is connected to the gate of switch Q2. The drain of Q2 is connected to the anode of D70 and pin P2B (FIG. 18B) of the subcircuit BL1 of the unsaturated magnetic element. When the switch Q2 is turned on, C4 is also charged and energy is stored in the magnetic element BL1. By releasing the switch Q2, the energy stored in the magnetic element BL1 can pass through the flyback diode D70 to charge C4. A larger pulse width charges C4 to a larger voltage,
Thus effectively blocking a portion of the first stage voltage to the final push-pull stage. This action will provide a regulated voltage to the final converter stage. The third and final push-pull (transformer) converter stages are galvanically isolated,
It provides filtering and typically converts the internal high voltage busbar to a lower regulated output voltage. The efficient push-pull stage produces an alternating magnetizing current in the NSME for maximum loading on the core mass. A constant frequency non-overlapping two-phase generator subcircuit PPG (FIG. 43) generates the drive for the push-pull output stage. The output pin PH1 of phase 1 is connected to the pin GA1 of the sub-circuit AMP1,
The output pin PH2 is connected to the pin GA1 of the sub circuit AMP2. The output of the pin GAP2 of the amplifier buffer sub-circuit AMP1 is a push-pull output switch Q6.
Connect to the gate of. The output of pin GAP2 of amplifier buffer subcircuit AMP2 is connected to the gate of push-pull output switch Q9. The buffering provided by AMP1 and AMP2 shortens the on and off times of switch Q1 and significantly reduces switching losses. (See Figures 13 and 14). Sub circuit CP
A regulated 18 volt power supply from pin CP18 + of A provides pin GA + of amplifier buffer subcircuit AMP1 and pin GA + of amplifier buffer subcircuit AMP2.
And a pin PPG + of the sub-circuit PPG. The drain of the transistor Q6 has a pin SNB1 of the sub circuit SNB of the snubber circuit and a 1 with unsaturated center tap.
It is connected to the pin P2H of the sub circuit PPT1 of the next magnetic element. Transistor Q
The drain of 9 is connected to the pin SNA1 of the sub circuit SNA (FIG. 31) of the snubber circuit and the pin P2L of the sub circuit PPT1. The return node PF- connects the source of the transistor Q6 to the pin SNB3 of the sub circuit SNB of the snubber circuit, the source of the transistor Q9, the pin SNA3 of the sub circuit SNA and the return node GND2. The output of the pin SH of the sub circuit PPT1 of the NSME is the rectifier sub circuit OU.
Connect to pin C7B of TA (FIG. 25) and pin SL to C8B. PPT1
The center tap of the pin SCT of is the output return line or the node OUT− on the negative side,
It is a sub-circuit pin OUT- and a sub-circuit IFB pin OUT- and RLOA.
Connect to D. The positive output of the power supply from pin OUT + of sub-circuit OUTA is RLO
Connected to AD and pin OUT + of sub-circuit IFB. Elements LL1, BR, PF
A, AMP, Q1, IPFFB, IFB and PFT1 are power factor corrected AC /
It provides DC conversion and DC output regulation. The regulated high voltage output of this converter is an efficient fixed frequency push-pull stage PPG, AMP1, AMP2, Q6.
, Q9, PPT1 and OUTA. The magnetic element sub-circuit PPT1 provides galvanic isolation and minimum voltage overshoot on the secondary side, thus minimizing the filtering requirements of the rectifier sub-circuit OUTA. The sub-circuit IFB provides fast feedback to the AC / DC converter and the speed of the boost stage provides precise output voltage regulation and active ripple rejection. In the event of a sudden line or load change, subcircuit IPFFB compensates for internal boost. This system reduces power loss by focusing the output control in the middle (low current) stage of the converter and by using unsaturated magnetic elements, buffered switching, and rectifying snubbers throughout each stage. To reduce. This combined improvement results in higher system efficiency, higher power density, lower operating temperature, and improved thermal capability, thereby reducing or eliminating the need for forced air cooling per unit output. The unsaturated magnetic properties are relatively insensitive to temperature (see Figure 17), thus allowing the converter to operate over a larger temperature range. In fact, Kool
The operating temperature for Mu's NSME is limited to 200 ° C. by wire / core insulation, but the unsaturated magnetic material remains operational up to its Curie temperature of 500 ° C. This configuration provides power factor corrected input transient protection, rapid line-load and ripple compensation, excellent output regulation, output isolation and quiet, efficient operation at high temperatures.

FIG. 4 is a sub-circuit ACDCPF of the power stage corrected single-stage AC / DC converter.
FIG. The invention consists of a line protection filter subcircuit LL (FIG. 20) and a full-wave rectifier subcircuit BR (FIG. 22). Sub circuit PFB (FIG. 24), snubber sub circuit SN (FIG. 30), magnetic element sub circuit PET1A (FIG. 18A), sub circuit CP (FIG. 26), buffer sub circuit AMP (FIG. 29), overtemperature sub circuit A power factor corrected and regulated boost stage with OTP (FIG. 28) and voltage feedback subcircuit FBA (FIG. 40A) is also included. Start-up resistor R
2, filter capacitor C1, PFC capacitor C2, flyback diode D4, switch transistor Q1, hold-up capacitors C17 and C16
And resistor R17 are also included.

[0036]

[Table 5]

The AC line is connected to the sub-circuit LL (FIG. 20) between the pins LL1 and LL2. AC / earth ground is connected to node LL0. The filtered and voltage limited AC line appears on node / pin LL5 of subcircuit LL1 and is connected to node BR1 of bridge rectifier subcircuit BR (FIG. 22). The filtered and voltage limited AC neutral / AC return line appears on pin LL6 of subcircuit LL and is connected to the input pin BR2 of BR. The line voltage is full-wave rectified and converted into a positive Haver sine appearing at node BR + of subcircuit BR (FIG. 22). Start-up resistor R2 connects BR + to pin CP + of subcircuit CP. The node CP + is a sub-circuit PFA of the power factor controller (
24) pin PFA + and the over-temperature switch subcircuit OTP (FIG. 28) pin GAP. The resistor R2 provides start-up power to the control element until the rectifier and regulator CP are at full output. Node S1 from PFT1A
H is connected to the node PFVC (sub circuit PFB). When the voltage at S1H becomes zero, a zero cross of the core bias is detected. The zero cross of the core is P
Used to reset FC and start a new cycle. Bridge D
The positive node BR + on the C side is connected to BR- through a capacitor C2. C2 is selected for various line and load conditions to isolate switching current from the line and improve power factor. NSME sub-circuit PFT1A (see FIG. 18)
The primary side of the pin P1B of A) is the pin SNL1 of the sub circuit SN (FIG. 30) of the snubber.
, And to the node BR + of the sub-circuit PFB. The return line BR- for rectified AC power is connected to the following pins: BR- of subcircuit BR, pin BR- of subcircuit PFB, pin GA0 of subcircuit AMP.
, Sense resistor R26, capacitor [C16 || C17 || resistor R17], capacitor C2, pin CT0 of sub-circuit CP, pin SICT of sub-circuit PFTIA and EMI filter capacitor C1 through earth ground node LL0.
Connected to. The drain of the output switch Q1 is connected to the anode of the diode D4, the pin P1A of the sub circuit PFT1A, and the pin SNL2 of the sub circuit SN of the snubber. Additional rectification efficiency and protection is achieved by adding sub-circuit DSN (FIG. 30A) in parallel flyback diode D4. The subcircuit reduces high voltage stress on Q1 until the flyback diode D4 begins to conduct. The power factor corrected and boost regulated output voltage of the AC / DC converter stage (FIG. 1) connected to the line appears at node PF +. The regulated boost output PF + is connected to: the pin SNOUT of the subcircuit SN, the cathode of the diode D4, the capacitor [C16 || C17 || R17], and the pin of the snubber-DSN (FIG. 30A). Connect to SNOUT. The magnetic element winding node S1H of the sub circuit PFT1A has a pin CT1A of the CP and a pin P of the sub circuit PFB.
Connected to FVC. The magnetic element winding node S1L of the sub circuit PFT1A is CP
Is connected to the pin CT2A. Subcircuit P using AC line phase and load voltage
The FB generates the command pulse PFCLK. Pin PF of sub-circuit PFB (Fig. 24)
CLK is connected to the input of pin GA1 of the buffer amplifier of subcircuit AMP1 (FIG. 29). The high speed gate drive output pin GA2 via the buffer of the sub circuit AMP is connected to the gate of the switch FET Q1. The buffering provided by the AMP shortens the on and off times of the switch Q1 and greatly reduces the switch loss. The source of Q1 is connected to the current sensing resistor R26, pin PFSC of the subcircuit PFB, and then to the return node BR-. The voltage developed across R26 is fed back to the PFB pin PFSC. This signal is
Used to protect the switch in case of overcurrent failure. Thermal switch T
HS1 is connected to Q1. When Q1 reaches approximately 105 ° C., THS1 opens, removing power to the subcircuit AMP and safely shutting down the first stage. After the switch temperature drops by 20 to 30 ° C. and THS1 is closed, normal operation resumes. The pin PF1 of the feedback circuit FBA (FIG. 40A) of the sub circuit is connected to the pin PF1 of the sub circuit PFB. The converter output terminal at the node PF + (connection point between [C17 || C16] and D4) is connected to the pin PF + of the sub circuit FBA. The return line from pin BR- of subcircuit FBA is pin B of subcircuit PFB.
It is connected to R-. This feedback is non-isolated and the circuit value is BR-
Is selected for a substantially constant 385 volt output at PF +. The high voltage Haver sine from pin BR + of rectifier section BR is connected to pin BR + of subcircuit PFB. This haver sign is the converter ACDCPF
Is used with an internal multiplier by the PFB to make it appear to be resistive to the AC line. Sub-circuits LL1, BR, PFB, AMP, Q1,
OTP, FBA, IFB and PFT1A perform power factor correction type AC / DC conversion. The regulated high voltage output of this converter can be used to power one or more external converters connected to the PF + and BR- nodes.
The NSME subcircuit PPT1A provides an efficient boosting action at high power levels at very low form factors. Subcircuit FBA provides fast feedback to the converter, and the speed of the boost stage provides fine output voltage regulation and active ripple rejection. This configuration provides power factor corrected input transient protection, rapid line-load response, excellent regulation and quiet, efficient operation at high temperatures.

FIG. 4A shows a sub-circuit ACDCP for auto load leveling.
It is the schematic of the power factor correction converter which has F1. The present invention includes a line filter sub-circuit LF (FIG. 20A), a fast start sub-circuit FS1 (FIG. 45), transient diodes D460, D461 and D462 (FIG. 46).
And an inrush limiter subcircuit SS1 (FIG. 44). Sub circuit PF
B (FIG. 24), snubber sub-circuit SNBB (FIG. 30B), magnetic element sub-circuit PF
T1A (FIG. 18A), sub-circuit CP1 (FIG. 26A), buffer sub-circuit AMP
(FIG. 29), overtemperature subcircuit OTP (FIG. 28), overvoltage subcircuit FB2 (FIG. 4)
1A) and a voltage feedback sub-circuit FBD (FIG. 40D), also including a power factor corrected and regulated boost stage. Automatic load leveling resistor R345,
Filter capacitor C1, PFC capacitor C2, flyback diode D4
, Switch transistor Q1, hold-up capacitors C442 and C417
Is also included.

[0039]

[Table 6]

The AC line is connected to the sub circuit LF (FIG. 20A) between the nodes LL1 and LL2. AC / earth ground is connected to node LL0. The filtered and rectified AC line appears on pin BR + of subcircuit LF and connects to the anode of transient diode D460-462. Diode D460-
The cathode of 462 connects to node RF + and the main storage capacitor C442. The line voltage is a full-wave rectified voltage that has been converted to a positive Haver sine that appears on node B + of subcircuit LF (FIG. 20A). Node B of filter subcircuit LF
+ Is the positive side of the input pins BR2 and C2 of the PFB (FIG. 24) and the pin PB of the PFT1A
1, connected to pin B + of SS1. Capacitor C2 is selected for various line and load conditions to isolate switch current from the line and improve power factor. The node TP17 of the fast start sub circuit FS1 is the sub circuit CP.
1 to pin TP17. The node VCC of CP1 is connected to the pin PFA + of the sub-circuit PFA (FIG. 24) of the power factor controller and the self-load leveling resistor R
345 connects to pin PF1 of PFB and PF1 of FBD. The VCC of FS1 is connected on pin GAP of the over temperature switch subcircuit OTP (FIG. 28). The fast start FS1 provides start-up power until the converter is at full power. It also provides control power if the unboosted period is extended. PFT1
The node S1H from A is connected to the node PFVC (sub circuit PFB). The zero crossing of the core bias is detected when the voltage at SH1 is zero. The core zero crossing is used to reset U1B and start a new cycle. The primary side of pin P1B of NSME subcircuit PFTIA (FIG. 18A) is connected to pin SNL2 of snubber subcircuit SNBB (FIG. 30B), pin BR + of subcircuit PFB, and to node B +. The return line BR- for the rectified AC power is connected to the following pins: B of the sub-circuit LF.
R−, pin BR− of sub circuit PFB, pin GA0 of sub circuit AMP, sub circuit S
S1 pin BR-, sensing resistor R26, sub-circuit SS1 pin BR-, capacitors C417 and C2, sub-circuit CP1 pin CT0, sub-circuit FB2 pin BR.
-, Pin BR- of the sub circuit FBD, pin BR- of the sub circuit FS1, and sub circuit PF
It is connected to ground ground node LL0 through pin S1CT of T1A and EMI filter capacitor C1. The drain of the output switch Q1 is connected to the anode of the diode D4, the pin P1A of the sub circuit PFT1A and the pin SNL2 of the sub circuit SNBB of the snubber. Switch protection is achieved by adding subcircuit SNBB (FIG. 30B) in parallel flyback diode D4. The sub-circuit SNBB keeps the flyback diode D4 from becoming conductive.
Reduce high voltage stress on Q1. The regulated output voltage of the converter appears on node PF +. The regulated boost output PF + is connected to: the pin SNOUT of the subcircuit SNBB, the cathode of the diode D4,
Capacitor C417, pin PF + of sub-circuit FS1, pin PF of sub-circuit SS1
+ And connected to the cathode of diode D460-462. Sub circuit PFT1A
The magnetic element winding node S1H is connected to the pin CT1A of CP1 and the pin PFVC of the sub-circuit PFB. The magnetic element winding node S1L of the sub circuit PFTIA is C
It is connected to pin CT2A of P1. The sub-circuit PFB using the phase of the AC line and the load voltage generates the command pulse PFCLK. Pin PFCLK of subcircuit PFB (FIG. 24) is connected to the input of pin GA1 of the buffer amplifier of subcircuit AMP1 (FIG. 29). The high speed gate drive output pin GA2 via the buffer of the sub circuit AMP is connected to the gate of the main switch Q1. The buffering provided by AMP shortens the "on" and "off" times of switch Q1 and significantly reduces switch loss. The source of Q1 is the current sensing resistor R26, subcircuit P
It is connected to the FB pin PFSC and then to the return node BR-. R2
The voltage developed across 6 is fed back to pin PFSC of PFB. This signal is used to protect the switch in case of an overcurrent fault. The thermal switch THS1 is thermally connected to Q1. When Q1 reaches approximately 105 ° C., THS1 opens, removing power to the sub-circuit AMP and completely shutting down boost operation. After the switch temperature drops by 20 to 30 ° C. and THS1 is closed, normal operation resumes. Sub-circuit feedback circuit FBD (Fig. 40D)
Pin PF1 is connected to pin PF1 of sub-circuit PFB. The pin PF2 of the feedback circuit FB2 (FIG. 41A) of the sub circuit is connected to the pin PF2 of the sub circuit PFB. This feedback is non-isolated and the value of the circuit is P with respect to BR-.
Selected for a substantially constant 385 volt output at F +. The high voltage Haver sine from pin B + of the rectifier section is connected to pin BR + of subcircuit PFB. This Haver sine is used by the PFB with an internal multiplier to make the converter ACDCPF1 appear resistive to the AC line. The regulated high voltage output of this converter can be used for use with one or more external converters connected in parallel. The unique function of converter ACDCPF1 is automatic load-sharring.
feature). Assume that signal VCC changes as a function of load as shown in FIG. 26B. A connected load level ring resistor between node VCC and PF1 regulates the output voltage lower with increasing load / boost. This unique effect allows the units to operate in parallel without the typical master-slave connection. In this way, a lightly loaded converter will increase its output voltage and thus accept more load. Similarly, a heavily loaded converter will reduce the voltage and automatically drop the load towards the parallel converter. In this way, any number of converters can be connected in parallel for high power or redundant applications. In prior art master / slave configurations, master unit loss is a major problem. In the present invention, the failure or removal of one unit causes the remaining unit (s) to take on additional load. The NSME subcircuit PPT1A1 provides an efficient boosting action at high power levels with very low form factor. The inrush limiter subcircuit SS1 enables "hot swapping" with minimal system disturbance. The unique magnetic feature allows full power operation in the temperature range not possible with common technology converters. High power factor, transient protection,
It offers low inrush current, excellent regulation, automatic recovery from fault conditions and quiet, efficient operation at temperature limits.

FIG. 5 is a graph comparing typical currents in saturated and unsaturated magnetic devices. Since the inductance does not change inherently at high temperatures and currents in NSME, there are no large current spikes due to the rapid decrease in inductance typical of saturated magnetic elements. As a result, destructive current levels, excessive gap leakage, magnetization loss and magnetic element heating will be avoided in NSME.

FIG. 6 shows a non-isolated low side switchback converter (low side switch).
It is a schematic diagram about a sub circuit NILBK of a buck converter). Sub circuit N
ILBK includes a resistor R20, a diode D6, a capacitor C6, an FET transistor Q111, a sub circuit CP (FIG. 26), a sub circuit PFT1A (FIG. 18A), a sub circuit IFB (FIG. 40B), a sub circuit AMP (FIG. 29) and a sub circuit. Circuit PWFM
(FIG. 33).

[0043]

[Table 7]

External power supply VBAT is connected to pins DCIN + and DCIN-. From DCIN + through the resistor R20, pin CP + of the sub-circuit CP, pin G of the sub-circuit AMP
A + and pin PWFM + of subcircuit PWFM. Resistor R20 provides start-up power to the converter before the regulator subcircuit CP reaches its full 18 volt output. The negative side of VBAT is connected to pin DCIN-, which is pin PWFM0 of subcircuit PWFM and pin GA of subcircuit AMP.
0, source of Q111, pin FBE of sub-circuit IFB, pin CT of sub-circuit CP
0 and pin SICT of sub-circuit PFT1. The magnetic element winding node S1H of the sub circuit PFT1A is connected to the pin CT1A of CP. The magnetic element winding node S1CT of the sub circuit PFT1 is connected to the pin CT0 of CP. Sub circuit PFT
The magnetic element winding node SIH of 1A is connected to the pin CT2A of CP. Adjusted 18 volts from subcircuit CP + is R20, pin GA + of subcircuit AMP
, And to the pin PWFM + of the subcircuit PWFM. Subcircuit PWFM is designed for variable pulse width operation. PWFM is a pin FB of the sub circuit IFB.
Configured for maximum pulse width 90-95% without feedback current from C. Increasing the feedback current decreases the pulse width and output voltage from converter NILBK. Pin CL of the clock / PWM output of the sub circuit PWFM
K is connected to the input pin GA1 of the subcircuit AMP of the buffer. Sub circuit A
The output of pin GA2 of MP is connected to the gate of Q111. Input node DC
IN + is the cathode of the flyback diode D6, the pin OU of the sub circuit IFB
Connect to T +, resistor RLOAD, capacitor C6 and pin B +. The drain of Q111 is connected to the anodes of pins P1B and D6 of subcircuit PFT1. The pin P1A of the sub circuit PFT1A has capacitors C6, RLOAD, and the sub circuit IF.
B pin OUT- and node B-. Pin CLK of sub-circuit PWFM
High buffer AMP output pin GA2 is connected to transistor switch Q11
Charge the gate of 1. The switch Q111 switches the power supply VBAT to the NSME PF.
Charging capacitor C10 through T1A and storing energy in PFT1A. The feedback output pin FBC from the sub-circuit IFB is connected to the pulse width adjustment pin PW1 of the sub-circuit PWFM. Sub-circuit IFB commands the PWFM to remove the current from PW1 and reduce the pulse width or the on-time of signal CLK. After the sub-circuit PWFM has reached the commanded pulse width,
Switches the output pin CLK to low to turn off Q111, P
Stop the current to FT1A. The energy that was not transferred into the load of the regulator subcircuit CP is now forward-biased by the diode D from the NSME PFTIA.
6 is discharged into and charges the capacitor C6. By modulating the "on" time of switch Q111, the buck voltage of the converter is adjusted. The regulated voltage is developed across nodes B- and B +. The sub circuit IFB is
It provides an isolated feedback voltage to the subcircuit PWFM. The current from REF is removed from PM1 when the subcircuit IFB detects that the converter outputs (nodes B + and B-) are at the designed voltage. Sinking current from PM1 commands the PWFM to have a shorter pulse width, thus reducing the output voltage of the converter. It is assumed that the feedback signal from the IFB commands the PWFM for the minimum output. The gate drive to switch Q111 is removed to stop all bulk activity,
Capacitor C6 discharges through RLOAD. The input current from VBAT is a sine current, making the converter very quiet. In addition, switch Q111
Is not exposed to large flyback voltages. There is less stress on the switch, which increases MTBF. Sub-circuit NILBK takes advantage of the desirable properties of NSME in this converter topology. NSME 10
By adjusting the primary inductance of 0 (FIG. 18A) and the values of the components in the sub-circuit IFB, the output buck voltage is determined.

FIG. 8 is a schematic diagram of the sub-circuit TCTP of the tank-coupled single-stage converter. The sub-circuit TCTP includes resistors R20 and RLOAD and a capacitor C10.
, Darlington transistors Q10 and Q20, sub circuit CP (FIG. 26), sub circuit PFT1 (FIG. 18), sub circuit OUTB (FIG. 25A), sub circuit IFB (
40B) and the sub-circuit PWFM (FIG. 33).

[0046]

[Table 8]

The external power supply VBAT is connected to the pins DC1N + and DCIN−. From DCIN + to the collector of Q10 and then through resistor R20 to pin CP + of subcircuit CP.
To and to pin PWFM + of subcircuit PWFM. Resistor 20 provides start-up power to the converter before the regulator subcircuit CP reaches its full 18 volt output. The negative side of VBAT is connected to the ground / return node GND of pin DCIN-. The node GND is connected to the pins PWFFM0 and Q20 of the sub circuit PWFM0, the collector of C20, C10, the pin CT0 of the sub circuit CP, and the pin S1CT of the sub circuit PFT1. The magnetic element winding node S1H of the sub circuit PFT1 is connected to CT1A of CP. The magnetic element winding node S1L of the sub circuit PFT1 is connected to CT2A of CP. Magnetic element winding S1C of sub-circuit PFT1
T is connected to pin CT0 of CP. Magnetic element winding node S of sub-circuit PFT1
2H is connected to the pin CT2A of CP. The regulated 18 volt from subcircuit CP + is connected to R20 and pin PWFM + of subcircuit PWFM. The subcircuit PWFM is designed for a variable frequency generator with a constant 50% duty cycle. The clock output pin CLK of the sub circuit PWFM has Q10 and Q.
It is connected to 20 bases. The emitters of Q10 and Q20 are sub-circuits PFT
1 is connected to pin P1B. This forms the emitter follower configuration.
The pin P1A of the sub circuit PFT1 is connected to the node GND through the tank capacitor C10.
It is connected to the. Using the PWFM's CLK pin, a high forward biased transistor Q10 supplies current from BAT1 to its tank, charging capacitor C10 through NSME's PFT1 to transfer energy into PFT1. Move to. Sub-circuit PWFM sets CLK low
Switch Q10 to "off", shutting off current into PFT1. Energy not transferred into the load is released from NSME's PFT1 back into capacitor C10 into the now forward biased PNP transistor Q20. Thus, any energy not used by the secondary load is transferred back to the primary tank for use in the next cycle. A large circulating current occurs in the tank when switching occurs at the resonant frequency. Similarly, C10 is charged and discharged to a very large voltage. The oscillograph in FIG. 35 is the actual voltage developed across capacitor C10 at VBAT equal to 18 volts. NS
A very large 229 volt peak-to-peak voltage developed across nodes P1A and P1A of ME's PFT1. The large primary voltage is the magnetic flux obtained by windings 102 and 103 (FIG. 18), creating a large bias in NSME's PFT1 to be transferred to the load or rectifier subcircuit OUTB. The magnetic element winding node S2L of the sub circuit PFT1 is connected to C8b of OUTB. Sub circuit PFT1
The magnetic element winding node S2H is connected to C7B of the node OUT- of the sub circuit OUTB. The node OUT- is RLOAD, pin B-, and the sub-circuit IFB.
Is connected to the pin OUT-. The rectified power is delivered to pin OUT + of OUTB, which is connected to RLOAD, pin B + and pin OUT + of subcircuit IFB. Subcircuit IFB provides an isolated feedback signal to subcircuit PWFM. The frequency control pin FM1 of the sub-circuit PWFM is connected to the pin FBE of the sub-circuit IFB. The internal reference pin REF of the sub circuit PWFM is connected to the sub circuit IFB.
Connected to pin FBC. The PWFM is designed to operate at the resonant frequency of the tank. When the subcircuit IFB detects the converter output, the converter output is at the design voltage and the current from REF is injected into FM1. The injection of current into FM1 commands the PWFM to a lower frequency. Operating below resonance, the amount of energy applied to the primary tank is reduced, thus reducing the converter output voltage. If the feedback signal from the IFB commands the PWFM to 0 Hz,
All primary activity ceases. The input current from VBAT is a sine current, making the converter extremely quiet. In addition, switch Q
10 and Q20 are never exposed to large circulating voltages (Fig. 35). There is less stress on the switch, which increases MTBF. The sub-circuit TCTP is N in this converter topology.
It utilizes the desirable properties of SMEs. By tuning the secondary turns, TCTP is able to generate very large AC or DC output voltages as well as low voltage high current outputs.

FIG. 9 shows a sub-circuit NIL of the non-isolated low-side switch / boost converter.
It is a schematic diagram about SBST. The subcircuit NILSBST is a resistor R20.
And RLOAD, diode D6, capacitor C6, FET transistor Q11
1, sub-circuit CP (FIG. 26), sub-circuit PFT1A (FIG. 18A), sub-circuit FB
I (FIG. 41), sub-circuit AMP (FIG. 29) and sub-circuit PWFM (FIG. 33).

[0049]

[Table 9]

The external power supply VBAT connects to pins DCIN + and DCIN−. DCIN +
From resistor R20 to pin CP + of sub-circuit CP, pin GA + of sub-circuit AMP.
And the pin PWFM + of the sub-circuit PWFM. Resistor R20 provides start-up power to the converter before regulator subcircuit CP reaches its 18 volt full output. The negative side of VBAT is connected to pin DCIN- and ground return line node GND. The node GND is connected to the pin PWFM0 of the sub circuit PWFM.
, AMP pin GA0 of the sub circuit, source of Q111, pin B of the sub circuit FBA
R-, pin FBA of sub-circuit FBA, pin CT0 of sub-circuit CP, capacitor C
6. Connect to resistor RLOAD, source of transistor Q111 and pin S1CT of subcircuit PFT1. The magnetic element winding node S1H of the sub circuit PFT1A is C
It is connected to the P pin CT1A. Magnetic element winding node S1C of sub-circuit PFT1
T is connected to pin CT0 of CP. The magnetic element winding node S2H of the sub circuit PFT1A is connected to the pin CT2A of CP. The regulated 18 Volts from CP + of the subcircuit is connected to R20, pin GA + of subcircuit AMP and pin PWFM + of subcircuit PWFM. Subcircuit PWFM is designed for variable pulse width operation. The PWFM is configured for maximum pulse width 90-95% (maximum boost voltage) with no feedback current from the sub-circuit FBI. Increasing the feedback current decreases the pulse width, decreases the boost voltage and decreases the output from converter NILSBST. The clock / PWM output pin CLK of the sub-circuit PWFM is connected to the input pin GA1 of the sub-circuit AMP of the buffer. The output of the pin GA2 of the sub circuit AMP is connected to the gate of Q111. The input node DCIN + connects to pin P1A of PFT1A of NSME.
The drain of Q11 is connected to the anodes of pins P1B and D6 of subcircuit PFT1A. The cathode of the diode D6 is the pin PF + of the sub circuit FBA and the resistor RL.
It is connected to OAD, C6 and pin BK +. Pin CLK of sub-circuit PWFM
, The high buffer AMP output pin GA2 charges the gate of the transistor switch Q111. The switch Q111 turns on the reverse bias diode D6,
The capacitor C10 stops charging from the power supply VBAT through the NSME PFT1A. Energy is stored in the NSME subcircuit PFT1A while Q111 is conducting. The feedback output pin FBC from the sub circuit FBI is connected to the pulse width adjusting pin PW1 of the sub circuit PWFM. The sub circuit FB1 has a PW
P to remove the current from 1 and reduce the pulse width or on-time of the signal CLK.
Issue a command to WFM. After the sub-circuit PWFM reaches the commanded pulse width, PF
FM switches CLK low, turns Q111 “off”, PFT1
Stop the current into A. Energy not transferred into the load of the regulator subcircuit CP is discharged from the NSME PFT1A into the now forward biased diode D6, charging the capacitor C6. By modulating the "on" time of switch Q111, the converter boost voltage is adjusted. The adjusted voltage is
It is generated at both ends of nodes B- and B +. Sub-circuit IFB provides a feedback current to sub-circuit PWFM. Current is removed from PM1 when the sub-circuit IFB detects that the converter outputs (nodes B + and B-) are at or above the designed voltage. Reducing the current from PM1 commands a shorter pulse width to the PWFM, thus reducing the output voltage of the converter. It is assumed that the feedback signal from the IFB commands the PWFM for the minimum output. The gated drive to switch Q111 is removed, all boost activity is stopped, and capacitor C6 charges to VBAT. The input current from VBAT is sinusoidal, making the converter very quiet. In addition, switch Q11
1 is not exposed to a large flyback voltage. There is less stress on the switch, which increases MTBF. Sub-circuit NILBK takes advantage of the desirable properties of NSME in this converter topology. NSME 1
The output boost voltage is determined by adjusting the primary inductance of 00 (FIG. 18A) and the values of the components in the sub-circuit IFB.

FIG. 10 shows a two-stage isolated DC / DC boost control push-pull converter BST.
It is a schematic diagram about PP. The sub circuit BSTPP includes a diode D14, a capacitor C14, an FET transistor Q14, a sub circuit REG (FIG. 36), a sub circuit BL1 (FIG. 18B), a sub circuit IFB (FIG. 40B), and a sub circuit AMP (FIG. 29).
), A sub-circuit DCAC1 and a sub-circuit PWFM (FIG. 33). External power supply V
BAT connects to pins DCIN + and DCIN-.

[0052]

[Table 10]

The pin DCIN + is connected to the pin RIN + of the sub circuit REG and the pin P1A of the sub circuit BL1. Voltage regulator sub circuit output pin + 18V is the sub circuit AMP
To the pin GA + of the sub-circuit PWFM and the pin PWFM + of the sub-circuit PWFM. Sub circuit RE
G provides regulated low voltage power to the controller and the buffer of the main switch. The negative side of VBAT is pin DCIN- and the node GN of the ground return line.
Connected to D. The node GND has a pin PWFM0 of the sub circuit PWFM, a pin GA0 of the sub circuit AMP, a source of Q14, a capacitor C14, a pin FBE of the sub circuit IFB, a pin REG0 of the sub circuit REG, and a pin DC- of the sub circuit DCAC1.
Connect to. Subcircuit PWFM (FIG. 33) is designed for variable pulse width operation. The nominal frequency is between 20 and 600 kHz, the PWFM is a subcircuit FB
The maximum pulse width is 90% (maximum boost voltage) without a feedback current from I. Increasing the feedback current decreases the pulse width, decreases the boost voltage, and decreases the output from converter BSTPP. The clock / PWM output pin CLK of the sub-circuit PWFM is the sub-circuit AM of the buffer.
It is connected to the input pin GA1 of P (FIG. 29). The output of pin GA2 of switch speedup buffer subcircuit AMP is connected to the gate of Q14. The input node DCIN + is connected to the pin P1A of BL1 of NSME. Q14
Is connected to the anodes of the pins P1B and D14 of the sub-circuit BL1.
The cathode of the flyback diode D14 is connected to the pins DC + and C14 of the sub-circuit DCAC1. Using pin CLK of subcircuit PWFM, high buffer AMP output pin GA2 charges the gate of transistor switch Q14. The switch Q14 turns on the reverse bias diode D14, and the capacitor C14 stops charging from the power supply VBAT through BL1 of NSME. Energy is stored in the NSME subcircuit BL1 while Q14 is conducting. The feedback output pin FBC from the sub circuit IFB is connected to the pulse width adjustment pin PW1 of the sub circuit PWFM. Subcircuit IFB commands the PWFM to remove the current from PW1 and reduce the pulse width or on-time of signal CLK. After the subcircuit PWFM reaches the commanded pulse width, PFFM drives CLK low.
Switch Q14 to "off", stopping current to BL1. Energy is released from NSME BL1 into diode D14, now forward biased, charging capacitor C14. By modulating the "on" time of switch Q14, the converter boost voltage is adjusted. The adjusted voltage is C1
Nodes DC + and GND are provided to a sub-circuit DCAC1 (FIG. 2) of the isolated constant frequency push-pull DC / AC converter that occurs at both ends of 4. Subcircuit DCAC1 provides efficient conversion of the regulated boost voltage to higher or lower voltage set by the magnetic element turns ratio. The center tap of the push-pull output magnetic element is connected to pins OUT-, RLOAD of subcircuit OUTB, pins OUT- and OUT- of subcircuit IFB, and forms a return line for the load and feedback circuits. The output of the pin ACH of the sub circuit DCAC1 is connected to the pin C7b of the sub circuit OUTB. Pin AC of sub-circuit DCAC1
The output of L is connected to the pin C8b of the sub circuit OUTB. Sub circuit OUTB
Provides rectification of the AC power generated by the sub-circuit DCAC1. Since unsaturated magnetic converters have low output ripple, minimal filtering is required by OUTB. This further reduces costs and minimizes loss of filter components, thus improving efficiency. Sub circuit I
FB provides an isolated feedback current for subcircuit PWFM.
Current is removed from node PM1 when subcircuit IFB detects that the converter outputs (nodes OUT + and OUT-) are greater than the designed / desired voltage. Sinking current from PM1 commands the PWFM to have a shorter pulse width, thus reducing the output voltage of the converter. It is assumed that the feedback signal from the IFB commands the PWFM for the minimum output. The gate drive to switch Q14 is removed, all boost activity is stopped, and capacitor C14 charges to VBAT. Since the unsaturated magnetic element does not saturate, the destructive noise current "spikes" typical in the prior art are
kes "). The input current from VBAT is a sine current, making the converter very quiet. In addition, switch Q14 is not exposed to potentially destructive current spikes. The stress applied is low, which increases MTBF, and the subcircuit BSTPP takes advantage of the desirable properties of NSME, by adjusting BL1 of NSME (FIG. 18B) to the final push-pull isolation stage. The magnitude of the possible boost voltage is set, greater efficiency is achieved at higher voltages, and the final output voltage is set by the feedback set point and the turn ratio of the push-pull element PPT1 (FIG. 19).

FIG. 11 is a graph of permeability as a function of temperature for typical prior art transistor materials. The high permeability material in FIG. 11 is almost 100% over the range of 100 ° C., compared to less than 5% change for the material of FIG.
Indicates a large change in magnetic permeability. Increasing the permeability of prior art materials at high temperatures increases the magnetic flux density, resulting in core saturation for certain power levels. (See Figure 12). Thus, prior art cores must be at least 100% derated in order to operate over a wide range of temperatures. The present invention takes advantage of the desirable properties of NSME. The need for derating magnetic elements is eliminated. This is because this magnetic element performs better at the high temperatures currently limited by melting the wire insulation.

FIG. 12 is a graph of magnetic flux density as a function of temperature for typical prior art magnetic element materials. The decrease in maximum magnetic flux density with temperature is typical of prior art materials for magnetic elements that saturate. Thus, prior art cores are generally at least 100% derated for operation over a wide range of temperatures. The result is a larger, more expensive design and / or the need to cool the core. FIG. 12A is a graph of magnetic element loss for various magnetic flux densities and operating frequencies typical of prior art magnetic element materials.

FIG. 13 is a graph showing standard switching loss. The shaded area represents the time the switch is in the resistive state. The shaded area is directly proportional to the amount of energy lost each time the output switch is activated. The total power loss is
It is the switching frequency multiplied by the loss per switch.

FIG. 14 is a graph showing the switching loss of the present invention. The shaded area represents the time the switch is in the resistive state. The smaller shaded area is due to the buffer of FIG. 29 and the snubber isolation diode of FIG.
ode) due to the action of D805. NSMEs generally have a wider usable frequency band and can be magnetized from higher primary voltages. Higher operating voltages will have a proportionally smaller current for a given given power level, and thus a proportionally lower loss. Switching loss more closely resembles I ² R loss. Most switching losses are turn on and turn off.
Due to the lower switching frequency and faster transition times that occur during the "off" transition, which is a feature of the disclosed NSME converter, the total switching loss is reduced in direct proportion. In addition, the NSME properties allow operation at temperature extremes beyond the tolerances of standard prior art magnetic elements and their geometries. The above combined contributions result in a converter that requires little or no forced air cooling (see Figures 15, 16 and 17).

FIG. 15 is a graph of the NSME magnetization curve for the Kool Mu material. The present invention advantageously uses the available saturation range of NSME.

[0059]   FIG. 15A is a graph of the magnetization curve for the H material.

FIG. 16 shows Kool Mu's N for various magnetic flux densities and operating frequencies.
It is a graph of SME loss. The data show that much higher flux density per unit loss is available than in the prior art.

FIG. 17 is a plot of permeability versus temperature for several Kool Mu materials. This data demonstrates the utility and stability of magnetic properties over temperature.

FIG. 18 is a schematic representation of the unsaturated magnetic boost device PFT1. Sub circuit P
FT1 is an NSME 10 having two center tapped windings 102 and 103.
It consists of a primary winding 100 around one.

[0063]

[Table 11]

Primary winding 100 has nodes P1B and P1A for connection to an external AC power source. Secondary winding 102 has center tapped node S1CT and nodes S1H and S1L connections to the upper and lower halves, respectively. Secondary winding 103 has a center tapped node S2CT and nodes S2H and S2L connections to the upper and lower halves, respectively. Both 102 and 103 are connected to an external full wave rectifier assembly. The magnetic element 101 includes an unsaturated, low magnetic permeability magnetic material. This magnetic permeability is higher than that of the prior art in the range of 1500 to 5000u.
The order is 26u in the range of 1u to 550u. When the NSME is used in a boost converter, the magnetic element generates a high drain source voltage across the primary switch during the reverse recovery time of the flyback (output) diode. flyback management) becomes a problem. NSM
The magnitude of the flyback current from E per cycle is even greater for a given input magnetomotive force than in the prior art (see Figure 5). For example, Koo
l Mu toroloid (Magnetics material) is suitable for this application. This material is not specified in a limiting sense. This material comprises by weight 85% iron, 6% aluminum and 9% silicon. Furthermore, the magnetic element is air (permeability = 1), molypermalloy powder,
(MPP) High magnetic flux MPP, powder, ferrite with a gap, tape winding, cut magnetic element, laminated or amorphous magnetic element may be used. Unlike the prior art, NSME is that important parameters such as permeability and saturation remain substantially unaffected during extreme thermal operation over time.
It is temperature resistant. Some materials, such as air, also show little or no change in permeability or saturation level over time, temperature and conditions. The prior art often uses high permeability saturable materials with a permeability greater than 2000u. These magnetic elements exhibit undesired changes in permeability and saturation during operation at or near their rated output, making them difficult to operate at high power levels and high temperatures. See FIG. 11 for permeability versus temperature. This drawback has been overcome by the use of expensive and large size magnetic elements or the sharing of output current with multiple power supplies. (See graph of b _sat vs. temperature, FIG. 12). The present invention takes advantage of the desirable properties of NSME. See FIG. 17, which shows the permeability vs. temperature relationship. Prior art saturated magnetic elements generally operate at frequencies above 500 KHz to achieve higher power levels. As a result, the practitioner experiences exponentially greater core loss at high frequencies (see Figure 12A). NSME has lower frequencies of 20-6
It supports operation at 00 KHz, reduces switching loss and magnetic element loss, and enables operation at even higher temperatures. See the relationship between loss density and magnetic flux density in FIG. Unlike the prior art, the present invention uses voltage mode control with overcurrent shutdown. Material selection is also based on mass and efficiency. By increasing the mass of the magnetic element, more energy is coupled in more efficiently. The dissipation profile follows the loss of I2R / copper because the loss is reduced. The magnetic element operates with a duty cycle of 0% + to 90%, which results in an efficiency on the order of 90% when used to control the primary push-pull voltage.

FIG. 18A is a schematic representation of NSME's PFT1A. Sub-circuit transformer P
FT1A is one around NSME 101 with center tapped winding 102
It consists of a secondary winding 100.

[0066]

[Table 12]

Primary winding 100 has nodes P1B and P1A for connection to an external AC power source. Secondary winding 102 has a center tapped node S1CT and nodes S1H and S1L connected to the upper and lower halves, respectively. Winding 102 is typically connected to an external full wave rectifier assembly.

The magnetic element 101 includes a magnetic material that is unsaturated and has low magnetic permeability. Permeability is 2500
The order is 26u in the range of 1u to 550u as compared with the prior art which is the order of u. Flyback management becomes a problem when using such magnetic elements because the magnetic elements generate a high drain-source voltage across the primary switch during the reverse recovery time of the flyback diode. Flyback current is available for a longer period after the primary switch opens. (See Figure 5). For example, Koo
l Mu (material from Magnetics) is suitable for this application.
This material is not specified in a limiting sense. This material comprises by weight 85% iron, 6% aluminum and 9% silicon. Further, the magnetic element is air (permeability of air magnetic element = 1), molypermalloy powder, (MPP) magnetic element, high magnetic flux MPP magnetic element, powder magnetic element, ferrite magnetic element with gap, tape winding magnetic element, cut magnetic element. It may be an element, a laminated magnetic element or an amorphous magnetic element. During operation, the temperature of the NSME increases and the permeability decreases slowly, thereby increasing the saturation point. Some materials, such as air, show no or negligible change in permeability or saturation level. Unlike the prior art, which uses magnetic permeability materials greater than 2000u, whose magnetic permeability increases rapidly at high temperatures. Figure 11
See the relationship between magnetic permeability and temperature. The prior art may also suffer from the problem of reduced saturation levels of magnetic elements at high temperatures, making them difficult to operate at high power levels and high temperatures, and may require the use of expensive and oversized magnetic elements. See FIG. 12 for a graph showing the relationship between b _sat and temperature. The present invention takes advantage of desirable NSME properties. See FIG. 17, which shows the permeability vs. temperature relationship. Lower frequency 2
The operation at 0 to 600 KHz reduces the switching loss and the loss of the magnetic element and enables the operation at higher temperature. See FIG. 16 for loss density versus magnetic flux density. Unlike the prior art, the present invention uses voltage mode control with overcurrent shutdown. Material selection is also based on mass and efficiency. By increasing the mass of the magnetic element, more energy is coupled in more efficiently. Since the losses are reduced, the dissipation profile follows the I2R / copper losses. The magnetic element operates with a duty cycle of 0% + to 90%, which results in efficiencies on the order of 90% when used to control the primary push-pull voltage.

FIG. 18B is a schematic representation of the NS1 BL1. The sub circuit BL1 is NS
It consists of a winding 100 around the ME 101.

[0070]

[Table 13]

The magnetic element BL1 may be made up of one or more magnetic elements in series or in parallel. Assuming minimal mutual coupling, the total inductance is the arithmetic sum of the individual inductances. For paralleled elements (assuming minimum mutual coupling), the total inductance is the reciprocal of the arithmetic sum of the reciprocals of the individual inductances. In this way, a large number of magnetic elements can be arranged to meet packaging, manufacturing and power requirements. Primary winding 100 has nodes P2B and P2A for connection to an external AC power source. The magnetic element 101 includes an unsaturated, low-permeability magnetic material. Permeability is higher than that of the prior art, which is in the order of 2500-5000u.
The order is 26u in the range of 1u to 550u. Flyback management becomes a problem when using such a magnetic element because the magnetic element produces a high drain-source voltage across the primary switch during the reverse recovery time of the flyback diode. Flyback current is available for a longer period after the primary switch opens. (See Figure 5). For example, Kool Mu (a material from Magnetics) is suitable for this application. This material is not specified in a limiting sense. This material is 85% iron, 6% aluminum and 9% by weight.
% Silicon. Further, the magnetic elements are air (permeability of air magnetic element = 1), molypermalloy powder, (MPP) magnetic element, high magnetic flux MPP magnetic element, powder magnetic element, ferrite magnetic element with gap, tape winding magnetic element, cut magnetic element. It may be a device, a laminated magnetic device or an amorphous magnetic device. During operation, the temperature of the magnetic element rises and the permeability decreases slowly, thereby increasing the saturation point. Some materials, such as air, show no or negligible change in permeability or saturation level. Greater than 2000u, permeability increases rapidly at high temperature,
Unlike the prior art, which uses materials of high magnetic permeability. Relationship between permeability and temperature (Fig. 11)
checking ... The prior art may also suffer from the problem of reduced saturation levels of magnetic elements at high temperatures, making them difficult to operate at high power levels and high temperatures, and may require the use of expensive and oversized magnetic elements. (See FIG. 12 of the graph showing b _sat vs. temperature.) The present invention takes advantage of the desirable NSME characteristics. (See FIG. 17 showing the relationship between permeability and temperature.) Prior art often operates at high switching frequencies of 100-1000 KHz to avoid saturation problems.
This simply increases switching and core loss. (See Figure 12A). The present invention uses lower desirable NSME properties to achieve lower 20-60
It is possible to operate at a frequency of 0 KHz, which further reduces switching loss and magnetic elements. See the relationship between loss density and magnetic flux density in FIG. Unlike the prior art, the present invention uses voltage mode control with overcurrent shutdown. Material selection is also based on mass and efficiency. By increasing the mass of the magnetic element, more energy is coupled in more efficiently. Since the losses are reduced, the dissipation profile follows the I2R / copper losses.

FIG. 18C is a schematic representation of a distributed NSME PFT1D. This provides an advantageous high voltage converter design variation that supports flexibility in form factor and multiple parallel secondary outputs from a voltage-divided primary winding in series across multiple NSMEs. It is shown to exemplify a distributed magnetic element that enables it. This magnetic strategy is useful in addressing wire isolation, form factor and packaging limitations, circuit complexity and manufacturability. In this example, a 500W converter is needed that fits well in a low profile package. The sub-circuit PFTD1 includes three magnetic elements 12 each having a primary side connected in series.
It is composed of 0, 121 and 124.

[0073]

[Table 14]

An AC voltage is applied to pin P1B at 112 and then from pin P1C via conductor 115 to pin P1D at 116. The pin P1E of winding 116 is connected via conductor 119 to pin P1F of 118 and then to pin P1A. Original sub-circuit PFT
1 (FIG. 18) is an NS having two center tapped windings 122 and 123.
It consists of a primary winding 100 provided around the ME 101. For example, the sub circuit PFT
1D will be implemented as three magnetic elements. For a 500 watt display, a total inductance of 203 uH is required for winding 100 (Figure 18).
The primary inductance is divided by the number of elements, in this case the three elements 112, 11
6 and 118 need to have an inductance of 67uH. The energy store is evenly distributed across the magnetic assemblies 120, 121, 124. The (Figure 1) 500 watt converter employs two (Kool Mu, part number 77932-A7) 0.9 oz (25 grams) NSMEs.
(FIG. 18) is formed. The magnetic element 101 (FIG. 18) of subcircuit PFT1 can be represented as three 0.5-0.7 oz (14-19 gram) elements. Three 0.5oz Kool Mu devices (part number 77352-A)
7) was selected. 55 turns are required for elements 112, 116 and 118 to achieve a primary inductance of 67 uH. The primary circuit is the external A
It has nodes P1B and P1A for connection to the C power supply. Secondary winding 10
2 has a node S1CT with a center tap, and nodes S1H and S1L corresponding to the upper half and the lower half, respectively. The secondary winding 123 includes a node S2CT with a center tap and nodes S2H and S corresponding to the upper half and the lower half, respectively.
2L and. Both 122 and 123 are connected to an external full wave rectifying assembly. The magnetic elements 120, 121 and 124 are made of a magnetic material that is unsaturated and has low magnetic permeability. The magnetic permeability is 1 u to 5 when compared with the prior art in the order of 2500 u.
It is on the order of 26u in the range of 50u. Flyback management is important when using such magnetic elements. This is because the magnetic element produces a high drain-source voltage across the primary switch during the reverse recovery time of the flyback diode. Flyback current is available for a longer period after the primary switch opens (FIG. 5). For example, Kool Mu (a material from Magnetics) is suitable for such applications. This material is not specified due to limitations. This material consists of 85% iron, 6% aluminum, and 9% silicon by weight. Further, the magnetic element is air (magnetic permeability of air magnetic element = 1), molypermalloy powder, (MPP) magnetic element, high magnetic flux MPP magnetic element, powder magnetic element, ferrite magnetic element with gap, tape winding magnetic element, cut It may be a magnetic element, a laminated magnetic element, or an amorphous magnetic element. During operation, at the temperature of NSME, permeability decreases slowly, which raises the saturation point. Some materials, such as air, exhibit no or very little change in permeability or saturation level. It differs from the prior art which uses high permeability materials above 2000u where the permeability increases rapidly at high temperatures. See FIG. 11 showing permeability versus temperature. In the prior art, the saturation level of the magnetic element is reduced at a high temperature, which makes it difficult to operate at a high output level and a high temperature, and it is necessary to use an expensive and excessive magnetic element. Yes (see Figure 12 showing a graph of bsat vs. temperature). The present invention takes advantage of desirable NSME properties. FIG. 17 showing permeability versus temperature
Please refer to. Prior art saturated magnetic elements commonly operate at frequencies above 500 KHz to achieve higher output levels. As a result, the practitioner will experience an exponentially increasing core loss (see FIG. 12A) at high frequencies. NSME enables operation at lower frequencies of 20 to 600 KHz, further reduces switching loss and loss of magnetic elements, and enables operation at higher temperatures (see FIG. 16 showing loss density vs. magnetic flux density). reference). Unlike the prior art, the present invention uses voltage mode control with overcurrent shutdown. Material selection is again based on mass and efficiency. By increasing the mass of the magnetic element, more energy is more efficiently coupled. Since the loss is reduced,
The dissipation profile follows 12R / copper loss. The magnetic element is operated with a duty ratio of 0% + to 90% and when used to control the primary push-pull voltage results in an efficiency of the order of 90%.

FIG. 19 is a schematic diagram showing a sub circuit PPT1 of the unsaturated push-pull magnetic element.

The sub-circuit PPT1 is an NSM having one center-tapped secondary winding 105.
It consists of a primary winding 104 with a center tap provided around E106.

[0077]

[Table 15]

Primary winding 104 has nodes P2H and P2L for connection to an external AC power source.
And a common node P2CT with a center tap. The secondary 105 is a node SCT with a center tap and nodes SH for the upper half and the lower half, respectively.
And SL. The invention is not limited to a single output. More secondary windings may be added for additional output. The secondary 105 is connected to an external full wave rectifying assembly (eg, FIG. 25 or 26). Magnetic element 10
6 is an unsaturated unsaturated magnetic material. The permeability is on the order of 26u in the range of 1u to 550u, compared to the prior art which is on the order of 2500u. Flyback management is important when using magnetic elements where a high drain source voltage across the primary switch is generated during the reverse recovery time of the flyback diode. The falling flyback current is available for a longer period of time (see Figure 5).
For example, Kool Mu (a material from Magnetics) is suitable for such applications. This material is not specified due to limitations. This material is 85% by weight
Iron, 6% aluminum, and 9% silicon. Furthermore, the magnetic element
Air (including air magnetic element), molypermalloy powder, (MPP) magnetic element, high magnetic flux MPP magnetic element, powder magnetic element, ferrite magnetic element with gap, tape winding magnetic element, cut magnetic element, laminated magnetic element, or amorphous It may be a magnetic element. During operation, the temperature of the NSME rises and the permeability slowly decreases, which raises the saturation point. Permeability increases rapidly at high temperatures, 2000
Unlike the prior art, which uses highly magnetically permeable materials exceeding u. See FIG. 11 showing permeability versus temperature. The prior art may also reduce the saturation level of the magnetic element at high temperatures, making it difficult to operate at high power levels and high temperatures, which may require the use of expensive and oversized magnetic elements. Yes (see Figure 12 showing blast vs. temperature). The present invention takes advantage of desirable NSME properties. See FIG. 17, which shows permeability versus temperature. Operation at a lower frequency of 20 to 600 KHz reduces switching loss and magnetic element loss and enables operation at higher temperatures. See FIG. 16, which shows loss density versus magnetic flux density. Unlike the prior art, the present invention uses voltage mode control with overcurrent shutdown. Material selection is again based on mass and efficiency. By increasing the mass of the magnetic element, more energy is more efficiently coupled. The dissipation profile follows 12R / copper loss as the loss is reduced. The primary magnetic element is driven in a push-pull manner with a duty cycle of 48-49%, which results in an efficient use of the volume of the magnetic element.

FIG. 19A is a schematic diagram showing a sub circuit PPT1 of the unsaturated push-pull magnetic element. The sub-circuit PPT1 is an NS including one secondary winding 135 with a center tap.
It consists of a primary winding 134 with a center tap provided around the ME 136.

[0080]

[Table 16]

Primary winding 134 has nodes P2H and P2L for connection to an external AC power source.
And a common node P2CT with a center tap. The secondary winding 135 has a node SCT with a center tap and nodes SH and SL corresponding to the upper half and the lower half, respectively. The present invention is not limited to a single output winding. More secondary windings may be added for additional output. Secondary 135
Is an external full-wave rectifier assembly, such as OUTA (FIG. 25), OUTB (FIG. 26).
) And OUTBB (FIG. 25B). The magnetic element 136 includes a magnetic material having an unsaturated and low magnetic permeability. The permeability is on the order of 26u in the range 1u to 550u, compared to the prior art which is on the order of 2500u. Flyback management is 1
This is important when using magnetic elements where a high drain-source voltage across the next switch is generated during the reverse recovery time of the flyback diode. The falling flyback current is available for a longer period of time (see Figure 5). For example Kool
Mu (Magnetics from Magnetics) is suitable for such applications. Such materials are not specified by limitation. This material is 85% iron by weight,
Contains 6% aluminum and 9% silicon. Furthermore, the magnetic element is
(Including air magnetic element), molypermalloy powder, (MPP) magnetic element, high magnetic flux MP
It may be a P magnetic element, a powder magnetic element, a ferrite magnetic element with a gap, a tape winding magnetic element, a cut magnetic element, a laminated magnetic element, or an amorphous magnetic element. During operation, the temperature of the NSME rises and the permeability slowly falls, which raises the saturation point. The magnetic permeability differs from the prior art, which uses highly permeable materials above 2000u, which increases rapidly at high temperatures. See FIG. 11 showing permeability versus temperature. The prior art also suffers from reduced saturation levels of magnetic elements at high temperatures, making it difficult to operate at high power levels and high temperatures, and requiring the use of expensive oversized magnetic elements. (See Figure 12 showing bsat vs. temperature). The present invention takes advantage of desirable NSME properties. (See FIG. 17 showing permeability vs. temperature.) Operation at lower frequencies of 20-600 KHz reduces switching losses and magnetic element losses, allowing operation at higher temperatures. See FIG. 16, which shows loss density versus magnetic flux density. Unlike the prior art, the present invention
Use voltage mode control with overcurrent shutdown. Material selection is again based on mass and efficiency. By increasing the mass of the magnetic element, more energy is more efficiently coupled. The dissipation profile follows 12R / copper loss as the loss is reduced. The primary magnetic element is driven in a push-pull manner with a duty cycle of 48-49%, which results in an efficient use of the volume of the magnetic element.

FIG. 20 is a schematic diagram showing a filter and lightning input protection circuit according to the present invention for a converter connected to an AC line. The protection subcircuit LL includes a spark gap A1, diodes D20 and D21, a capacitor C1, and magnetic elements L1 and L2.

[0083]

[Table 17]

The AC line is connected to the node LL2. A typical DC to 440 Hz input frequency may be extended beyond such range by component selection. Node LL2 is connected to L1 of NSME, then node LL5, spark gap A
1, connected to the anode of the diode D22 and the cathode of the diode D20. The filter capacitor C60 is connected between the nodes LL0 and LL6. The filter capacitor C61 is connected between the nodes LL0 and LL5. The low side of the AC line is connected to node LL1 and then to magnetic element L2, and the other side of L2 is connected to spark gap A1, anode of diode D23 and cathode of diode D21 and node LL6. Capacitor C1 is connected to earth ground C1 and attenuates noise generated by the converter.
The use of unsaturated magnetic elements allows the input magnetic elements to absorb the extremely large voltages and currents normally generated by lightning, yet the spark gap A1 clamping does not occur in most cases. UL test (UL testi
ng), 60 16 ms, 2000 V pulses were applied between LL1 and LL2 without noticing the missing spark gap A1 and damaging it. During normal operation, the NSME L1 has a magnetic flux density of several hundred Gauss. From the graph of magnetic flux density vs. magnetomotive force (Fig. 15), 75u material is at least 50
It will accept more than double the magnetic flux density without restriction. This is an example of a magnetic element's ability to perform well with magnetic flux density many times higher than in the prior art. Elements L1 and L2 will prevent differential or common mode line transients. If the line-to-neutral transient is very large or has a long duration, the spark gap A1 will clamp the voltage to a safe level of about 400V. NSME L1 and L2
Is a conducted noise generated by the converter.
) Has the additional advantage of reducing

FIG. 20A is a schematic diagram showing another line filter. Filter sub-circuit L
F is capacitors C2 and C60-66, inductors L64 and L62,
It includes a magnetic element L63 and diodes D20 to D23.

[0086]

[Table 18]

The AC line is connected to the nodes LL2 and LL1. The node LL2 is connected to the y capacitor (y) via the upper leg of the inductor L64.
-Cap) Connect to the first leg of C64, then to capacitor C63, and then to the upper leg of bifilar wound inductor L62. Node LL1 is connected via the lower leg of inductor L64 to the second leg of y-capacitor C65 and then to capacitor C63, then bifilar wound inductor L6.
2 Connect to the lower leg. The capacitor C66 is connected between LL2 and LL1. The second upper leg of inductor L62 connects to the first leg of y-capacitor C61, then to capacitor C62, and then to the anode of D22 and D20.
Connect to the cathode of. The second lower leg of the inductor L62 has a y-capacitor C6.
0 to the second leg, then to capacitor C62, and then to the anode of D23 and the cathode of D21. Y capacitors C60, C61, C64
And the central leg of C65 is chassis return LL0
Connected to. Capacitor C69 connects node BR- to chassis ground LL0. The anodes of the diodes D20 and D21 are connected to the node BR-. The cathodes of diodes D22 and D23 are connected to MS63 L63 in parallel with C20 and node BR +. The capacitor C21 is connected to BR- and the node B.
It is connected to the other side of L63 in parallel with C20 forming +. Common mode inductors L64 and L62 are respectively from Butler, PA, USA
Highly permeable core material H41-406-TC, H manufactured by Magnetics inc.
Made on 42-109-TC. This material is provided as an example only and is not limiting. Capacitor C69 is connected to earth ground and attenuates noise generated by the converter. The present invention takes advantage of the high magnetic permeability properties of the ferrite used in inductors L64 and L62 (Fig. 1
5A). The core material is fully used in all four quadrants. Inductor L
64 and L62 are effective in removing the common mode EMI component. The differential mode noise generated by the main switch Q1 is C2
Effectively blocked by NSME's L63 in parallel with 0. Inductor L63 is operated in the first quadrant utilizing the inherent unsaturation properties of Kool Mu core material (manufactured by Magnetics Inc.). This material allows it to operate with large DC magnetizing currents without saturating. From the graph showing magnetic flux density vs. magnetomotive force (FIG. 15), 125 u of material was selected for this application. This material is provided as an example and is not limited to this material. This is an example of this magnetic element's ability to perform well at high magnetic flux densities many times greater than in the prior art. The NSME L63 in parallel with C20 forms a tuned tank that effectively blocks high frequencies from the AC line. Elements L64 and L62 will prevent common mode line transients. Line-
If the transient between neutrals is very large or has a long duration, the subcircuit TRN (FIG. 46) connected to BR + will transfer the transient again into the main storage capacitor C442. The present invention uses a ferrite type material on the AC side, and
Optimal use of the desired NSME on the C side enables low cost and high performance filtering.

FIG. 21 schematically shows another lightning protection sub-circuit LLA according to the invention for a converter connected to an AC line. The protection circuit comprises a fuse F1, a spark gap A1, capacitors C1, C60 and C61, and NSME L3.

[0089]

[Table 19]

The high side of the AC line is connected to the node LL2 and the fuse F1, and the load side of the fuse is connected to the NSME L3 and the capacitor C61. The load side of L3 is
It is connected to the spark gap A1, the cathode of the diode D20 and the anode of D22 forming the node LL5. The lower side of the AC line is connected to the node LL6, the capacitor C60, the spark gap A1, the cathode of the diode D21, and the anode of the diode D23. Diodes D20 and D2
The anode of No. 1 is connected to the capacitor C1. The capacitor C1 is connected to earth ground. C1 is radiation noise generated by the converter or EM
Attenuate I. The cathodes of the diodes D22 and D23 are connected to the capacitor C2. Capacitor C2 separates the high frequency harmonic current from the line. Capacitors C1, C61 and C60 are connected to earth ground node LL0. By using an unsaturated magnetic element, the input magnetic element is
It becomes possible to absorb an extremely large voltage and current generated in common in the line. Transients in the AC line will be limited by capacitors C60 and C61 and blocked by unsaturated magnetic element L3. If the line-neutral transient is very large or has a long duration, the magnetic element L3 allows the voltage across the spark gap A1 to rise, which protects the rectifier diodes D20-D23. Will clamp the voltage to a safe level. The NSME L3 has the additional advantage of reducing the conducted noise generated by the converter. C1 connected to the ground plane is effective in attenuating conducted and radiated EMI.

FIG. 22 schematically shows an AC line rectifier of the present invention. The rectification subcircuit BR1 includes diodes D20, D21, D22 and D23, and a capacitor C2.

[0092]

[Table 20]

The AC or DC signal from the input filter is connected to the bridge rectifier at nodes BR1 and BR2. Node BR1 connects the anode of diode D22 to the cathode of diode D20. Node BR2 connects the anode of diode D23 to the cathode of diode D21. Node BR + connects the cathode of diode D22 to the cathode of diode 23. Node BR- is diode D
The anode of 20 is connected to the anode of diode D21. Typical input frequencies from DC to 440 Hz may be extended beyond this range by component selection. Capacitor C2 is chosen to improve the power factor for a particular operating frequency and to isolate the switching current from the line. The diodes are selected to reliably block the desired line voltage and current to meet the requirements of the next converter stage.

FIG. 23 is a sub-circuit of an AC / DC controller according to the present invention. The sub-circuit PFA includes resistors R313 and R316 and capacitors C308 and C31.
3 and U1A of the PWM controller IC.

[0095]

[Table 21]

The control element U1A connects to a circuit with the following series connection: from pin 1 to the feedback node / pin PF1, to the capacitor C308, then to U1.
Connection of pin 2 of A to the node. Connect from pin 8 or node PFA2 of U1A with an internal 5.1 volt reference to pin 4 node through resistor R308. U1A
Pin 4 of is connected to the return node BR- via a capacitor C313. Such an arrangement allows the PFC output to be pulse width modulated with the application of a voltage to PF1. External feedback current is applied to pin 1 of U1A and node PF1. Node PFVC is connected from resistor R313 to pin 3 of U1A. Resistor R316 is connected to pin 3, then return node BR-
Connected to. Power pin 7 is connected to node PFA +. Pin 6 of the switch driver U1A of the control element is connected to the node PFCLK. The return ground node of U1A is connected to the return node BR-. Primary supply circuit (primary)
feed network), for example IPFFB (FIG. 40), FBA (FIG. 40)
A), IFB (FIG. 40B) and FB1 (FIG. 41) component failure can cause the output voltage of the boost stage to rapidly increase to breakdown levels. Fast overvoltage feedback circuit IOVFB (Fig. 40C) or OVP2 (Fig. 42B)
Increasing the current into PF1 limits the output voltage to a safe level. In addition, latch-type overvoltage protection circuits such as OVP (FIG. 42) and OVP1 (
42A) and OVP2 (FIG. 42B) can be used. The latch type stops the boost operation by cutting off the power to the control circuit. Latch-type circuits require power to be repeatedly applied to the converter to reset its latch. The input node PFVC of the IFB is connected to the resistor R313 and the internal zero-cross detector connected to pin 3, and is connected to the return node BR- via the resistor R316. The PFVC is connected to the BR-based magnetic element winding. Each time a bias in the magnetic element goes to zero, a new conduction cycle is started. The corrected power factor is chopping the input at high frequency.
) Is realized. The average pulse width decreases at higher line voltage and increases at lower voltage for a given load. The frequency is lower at the peak of the line and higher near the zero cross. The converter thus operates at a high input power factor.

FIG. 24 shows a sub-circuit of another power factor controller. The sub-circuit PFB includes resistors R313, R339, R314, R315, R328, R340, R341 and R346, a diode D308, and capacitors C310, C318, C3.
38, C340, C341 and C342, a transistor Q305, and a control element IC U1B.

[0098]

[Table 22]

The control element U1B connects to the circuit with the following series connection: from pin 1 to the node / pin PF1 and then to the capacitor C338 in series with the resistor R339.
Further connect to pin 2 node of U1B. Pin 1 is the input to the internal error amplifier and the connection to the external feedback circuit (FIGS. 40, 40A, 40B).
, 40C and 41). Increasing the voltage on Pin 1 causes PFCLK
The pulse width on pin 7 of the node is reduced. Resistor R328 is connected to the full-wave rectified AC line Haversine at node BR +, then to pin 3 of U1B, and to resistor R346 in parallel with capacitor C342 and to return node BR-. To be done. Node PFSC is a series resistor [R341 + R
340], these resistors are connected to pin 4 of U1B and also to diode D308 in parallel with capacitor C340 and to return node BR-. Power to the PFC controller is applied to node PFB + and pin 8 of U1B. The output clock node PFCLK is connected to the pin 7 of U1B and is connected to the sub-circuit AMP (FIG. 29) of the external buffer. Transistor Q
The collector of 305 is connected to the pin 2 node of U1B. Its base is connected in series with a capacitor C318 via a resistor R314 and then to pin 2 of U1B.
Connected to the node. Its base is also connected to [C310 || R315] and also to the return node BR-. The emitter of Q305 has a softstart compensation slope for the controller error amplifier.
Compensation ramp) to reduce stress and DC overshoot in the converter at power-up. The capacitor C341 is U
1 from pin 2 to the return node BR-. Pin 1 of U1B is pin PF
1 and also to capacitor C338 in series with resistor R339 to connect to the collector of transistor Q305 and pin 2 of U1. The current switched by PFC power switch Q1 (FIGS. 4 and 3) is sensed by R26 (see FIG. 4). The series resistor [R341 + R340] to pin 4 of U1B is R
Connect to the voltage developed across 26. This voltage is compared to an internal 1.5 volt reference voltage and the comparator output switches switch pin 7 of U1B during start-up or during periods of high current occurring during very heavy loads or low line conditions. Turn off. Capacitor C340 is connected to pin 4 of U1 and return node BR-
Is connected between to filter high frequency components. Pin 4 of U1 and return node P
The Schottky diode D308 connected between B- is connected to the controller (U
1 Pin 4) Protect the substrate from negative current injection. The maximum switch current value is set by R26 and the overcurrent is automatically limited within each cycle by the PFC controller. The full-wave rectified Haver sine at pin 3 of U1B is multiplied by the error voltage at pin 2. This product is compared to the magnetic element / switch current measured by R26 at pin 4. When the sensed magnetic element current increases to the current comparator level, the gate drive on pin 7 turns off. This behavior is
It has the effect of modulating the "on" time of switch Q1 to track the AC line voltage. The external feedback circuit is connected to the node PF1. Primary supply circuits such as IPFFB (FIG. 40), FBA (FIG. 40A), IFB (FIG. 40B) and FB
1 (FIG. 41), the output voltage of the boost stage can rapidly increase to a destructive level if a component failure occurs. Fast overvoltage feedback circuit IOV
FB (FIG. 40C) or OVP2 (FIG. 42B) increase the current into PF1 to limit the output voltage to a safe level. In addition, latch-type overvoltage protection circuits such as OVP (FIG. 42), OVP1 (FIG. 42A) and OVP2 (FIG. 4).
2B) can be used. The latch type stops the boost operation by removing power to the control circuit. Latch-type circuits require power to be repeatedly applied to the converter to reset the latch. Modulating the voltage at PF1 changes the PFC duty cycle and final output voltage. Thus, the PFC has a pre-conditioner (pre-) for the additional output stage.
It can be used as a regulator).

FIG. 25 schematically shows a full-wave rectified output stage and filter subcircuit OUTA. The rectifying stage consists of diodes D80 and D90. Filter is resistor R21
, Magnetic element L30, capacitors C26, C27, C28, C29, C30,
It consists of C31 and C32.

[0101]

[Table 23]

The input node / pin C7B is connected to the high side of the secondary winding of the external magnetic element with a center tap. Node C7B is connected to the anode of diode D8 and capacitors C26 and C27 in the following arrangement. The capacitor C27 is connected across the diode D80, and the capacitor C26 is connected in series with R21. The input node / pin C8B is connected to the low side of the secondary winding of the external center-tapped magnetic element. Pin C8B is connected to the anode of diode D9 and resistor R21, and capacitor C32 is connected across diode D90. Capacitors C27 and C32 are small values for reducing high frequency noise generated by rapidly switching high speed rectifiers D80 and D90, respectively. Capacitor C26 and resistor R21 are used to further dissipate high frequency energy. The anodes of diodes D80 and D90 are connected to a parallel capacitor C28 || C29 and NSME L30. Capacitor C28
And C31 are solid dielectric types, selected to have low impedance for high frequency signals.
Capacitors C29 and C30 are of low impedance at low frequency and of a larger polarized type selected for energy storage. The magnetic element L3 is connected to the cathode of the diode D8, and the second terminal of L30 is connected to the parallel capacitors C31 and C30 and the pin OUT +. The node OUT + is the positive side of the output and is connected to the external feedback sense line leading to the isolated feedback circuit. Parallel capacitor [C28 || C29 |
The other side of | C30 || C31] is connected to the pin OUT− and the secondary center tamp of the magnetic element forming the return node. Capacitor [C28 || C29]
, L30, and the combination of the capacitor [C30 || C31] are low-pass p
Form an i-type filter. The sub-circuit OUTA performs effective full-wave rectification and filtering.

FIG. 25A schematically shows a full wave rectified output stage. The rectification stage is a diode D8
0 and D90 and capacitors C931 and C928.

[0104]

[Table 24]

The input node / pin C7B is connected to the high side of the secondary winding of the external magnetic element with a center tap. Node C7B is connected to the anode of diode D80.
The input node / pin C8B is connected to the low side of the secondary winding of the external magnetic element with a center tap, and is connected to the anode of the diode D90. Node OUT- is the negative output and is the return line to the external isolated feedback circuit and the load (not shown). The cathodes of diodes D80 and D90 are connected to parallel capacitors C931 and C928. Capacitor C928 is a solid dielectric type, selected to have low impedance for high frequency signals. Capacitor C931 has a lower impedance for low frequency signals and is a larger polarization type selected to allow energy storage. Node OUT
+ Is the positive side of the output and is connected to the external feedback sense line leading to the isolated feedback circuit. The other side of parallel capacitor C928 || C931 is connected to the secondary center tamp of the magnetic element forming node OUT-.
The use of NSME for bush-pull magnetic elements requires minimal filtering after the rectifier.

FIG. 25B shows a schematic diagram of another final output rectifier and filter subcircuit OUTB. The rectifier subcircuit OUTB includes diodes D40, D41, D42 and D43, and capacitors C931 and C928.

[0107]

[Table 25]

An AC or DC signal is connected to the nodes C7B and C8B. Node C7
B connects the anode of diode D41 to the cathode of D40. Node C8
B connects the anode of diode D42 to the cathode of D43. Node OU
T + connects the cathode of the diode D42 to the cathode of the diode D43. The node OUT- connects the anode of the diode D40 to the anode of D43. The diode is selected to reliably block the desired line voltage and current to meet the load requirements. For low voltage outputs, Schottky type diodes are used because of their low forward voltage drop. Higher voltages will result in the use of fast silicon diodes because they can withstand high peak reverse voltage (PIV). NSM for push-pull magnetic element
The use of E requires minimal post-rectifier filtering. Capacitor C92
8 is shown diagrammatically as a single device. Capacitor C931 has a low impedance for low frequency signals and is of a larger polarization type selected for energy storage, and may have a typical value of 200 uF. Multiple capacitors can be used to increase capacitance or reduce output impedance. C931 is a solid dielectric type and is selected for its low impedance to high frequency signals. It is selected to reduce noise for a particular operating frequency and power level. Capacitor C92
8 is selected according to the operating frequency and power level. The sub circuit OUTB is
AC to D with slightly lower efficiency due to the extra junction
Rectify to C and filter.

FIG. 26 shows a sub-circuit CP of a floating 18 volt DC control power supply. Sub circuit C
P consists of diodes D501, D502 and D503, a resistor R507, a regulator Q504, and capacitors C503, C504, C505, C506 and C507.

[0110]

[Table 26]

The node CT1A is connected to the anode of the diode D503 and the upper secondary winding with a center tap. The node CT2A is connected to the anode of the diode D502 and the lower secondary winding with a center tap. The node CT0 is connected to the external winding center tap. Node CT0 is also the return line,
It is pin 2 of Q504 and capacitors C503, C504, C505, C50.
6 and C507. The cathode of each of the diodes D502 and D503 is connected to a resistor R507. R507 is a voltage regulator 50
4 pin 1 (input) node. Pin 3 of voltage regulator Q504 is a regulated DC output of 18vdc and is connected to the anode of block diode D501. The three pin voltage regulator Q504 is of the LM7818 type, which is a common device manufactured by many manufacturers.
Capacitors C503, C505, C506 are of 0.1 uF solid dielectric type and are used to filter high frequency ripple and prevent vibration of Q504. The connection of the cathodes of C503, C504 and D501 is the output node CP1 +. Isolated 18 volt DC is available between nodes CT0 and CP +. Used for driving regulator circuit and output switch during normal operation.

FIG. 26A shows another control power supply sub-circuit CP1. The sub-circuit CP1 includes a diode D260, a resistor R261, a transistor Q260, and a capacitor C.
261 to C265 and C260.

[0113]

[Table 27]

The node CT1A is connected to the anode of D261 and the upper secondary winding with a center tap. The node CT2A is connected to the anode of D262 and the lower secondary winding with a center tap. Node BR- connects to the external winding center tap. Node BR- is also the return line, which has a Q260 emitter,
Connected to capacitors C261 to C265 and R261. The cathodes of the diodes D261 and D262 are connected to the inductor L260 and the capacitor 266. The other side of capacitor C266 is connected to node FSC. Resistor R26
2 is further connected between the other side of inductor L260 and node VCC. The connection between R262 and L260 forms node TP15. Node VCC is connected to the positive terminals of capacitors C260-C265, the collector of Q260, and the cathode of D260. The anode of the Zener diode D260 with little leakage is Q
Connect to the base of 260, resistor R261 and capacitor C260. The Zener diode voltage is selected to start regulation at high boost levels. This allows VCC to follow the load level as shown by G260 (FIG. 26B). Voltage limiting begins at levels near full load (maximum boost). This is only an example and is not limiting. 1000
For wattage feeding, the VCC limitation is observed with increasing slope at segment 262 (FIG. 26B). This unique property has three advantages. First, as the boost (load) level increases, additional voltage is automatically provided to the main switch Q1 when maximum gate power is needed. Reducing the gate voltage at minimum boost reduces stress on the gate of the main switch Q1 and associated buffer components, which improves MBTF and efficiency. Second
In addition, VCC provides an internal load sense signal used to servo control the output voltage for load sbarring. The design of the load distribution aspect is as taught in FIG. 4A. Third, the signal used to convey the load magnitude without an additional current sensor becomes available. Diodes D262 and D261 provide rectified power supply capacitor C226, and capacitor C22
6 couples the AC voltage to node TP17 of subcircuit FS1 (FIG. 45). TP1
The AC voltage of 7 inhibits the operation of the fast start circuit when the converter is operating. The regulator CP1 is a shunt regulator.
or)). The component is chosen so that the limit begins near the maximum boost. In this way, power is not wasted at small load levels. further,
The gate voltage of the main switch Q1 is modulated to provide additional power with maximum boost to ensure maximum efficiency under changing load conditions.

FIG. 26B is a plot of VCC as a function of output power. Plot G26 shows ACDCPF1 (when load changes from 0 to 1000 watts.
It is generated by measuring VCC in FIG. 4A).

FIG. 27 shows the sub-circuit CP of the second floating 18 volt DC push-pull control power supply.
A is shown. The sub-circuit CPA includes diodes D601, D602 and D603, a resistor R607, a regulator Q604, capacitors C603, C604.
, C605, C606, C607 and C608.

[0117]

[Table 28]

The node CT1B is connected to the anode of D603 and the upper secondary winding with a center tap. The node CT2B is connected to the anode of D602 and the external center tapped secondary winding on the lower side. The node CT20 is connected to an external winding center tap. Node CT0 is also a return line, connecting to pin 2 of Q604 and capacitors C603, C604, C605, C606 and C607. The cathode of each of the diodes D602 and D603 is connected to the resistor R607. Resistor 607 is further connected to the node at pin 1 (input) of voltage regulator Q604. Pin 3 of voltage regulator Q604 is a regulated DC output of 18vdc and is connected to the anode of block diode D601. Capacitors C603, C605, C606 are solid dielectric types and are used to filter high frequency ripple and prevent vibration of Q604. The connection between the capacitors C603, C604 and the cathode of the diode D601 is the output node C.
It is P1 +. Isolated 18 volt DC is available between nodes CT20 and CP2 +. Used to drive the regulator circuit and output switch during normal operation.

FIG. 28 shows a sub-circuit OTP for overtemperature protection of the main switch. Sub circuit OTP
Includes a thermal switch and resistors R711 and R712.

[0120]

[Table 29]

Gate drive power is applied to the input node GAP and the thermal switch THS1. The maximum FET gate voltage required the input power supply voltage to be less than 20 volts and the voltage selected was 18 volts. The other side of THS1 is connected to a parallel resistor [R711 || R712]. A single resistor can represent multiple resistors. The drawing shows a surface mount arrangement. The other side of [R711 || R712] is connected to the output node TS +. Normally closed thermal switch T
S1 is in contact with the transistor Q1 of the main switch. If the temperature is higher than 105C, THS1 opens, thereby removing power to the buffer subcircuit AMP1 (FIG. 29), causing switch Q1 to become inactive and block, causing any cooling fan to fail. Or protect the boost switch if the circuit reaches high temperatures. In this embodiment of the invention, the speedup buffer A
The unsaturated magnetic elements (FIGS. 18, 18A and 19) of the MP (FIG. 29) allow the main switch to operate cooler than the prior art for a given power level. When the switch temperature returns to the normal range, THS1 closes, allowing the PFC to resume normal operation. Under normal load and ambient temperature, the thermal switch THS1 will never open.

FIG. 29 shows sub-circuits AMP, AMP1, A of the PFC buffer circuit for switching the drive command from PFCLK (FIGS. 23 and 24) or PWFM (FIG. 33).
MP2 and AMP3 are shown, and the control element is connected to the gate buffer circuit. The sub-circuit AMP includes a power FET Q702, a Darlington pair Q703, capacitors C709 and C715, and resistors R710 and R725.

[0123]

[Table 30]

DC power is applied to node GAT +, the drain of transistor Q702, and capacitor C709, which leads to ground. Maximum gate voltage required the input power supply voltage to be less than 20 volts, with 18 volts selected. The input node GA1 is connected to the gate of the FET Q702, and is connected to the base of BJT1 of the Darlington pair Q703 and the capacitor C715.
Capacitor C715 is the base of the Darlington pair, pin 1 to collector, pin 2
And the node of the collector of Q703 is also connected to ground. The emitter of BJT2 is connected to the gate of FET Q1. FET
The source of Q702 is connected to the gate of the output switch or node GA2 via a small optional series resistor R710. Power FE under a certain load
T tends to oscillate when driven from a low impedance source such as this buffer. Small resistances of about 2 ohms or less may be required so that there is no noticeable delay in the switch. In most cases R710 is replaced with a zero ohm jumper. Resistor R725 is connected from node GA0 and the source of Q702. The input switching signal to node GAP is in the range of 20 kHz to 600 kHz. By presenting a low impedance to quickly charge the gate of the output switch connected to node GA2, a very fast "on" time is achieved. When Q702 switches on, capacitor C709 provides additional current. Transistor Q703 provides a low impedance to rapidly remove charge from the gate, significantly reducing the "off" time. Such a particular topology provides an output switch rise time on the order of 10 ns, compared to the industry standard rise time of 250 ns. In addition, the corresponding fall time is <10 ns compared to the industry standard fall time of 200-300 ns (see Figures 13 and 14). If the converter operates at very high ambient temperatures, the thermal switch may be placed in series with the input power pin GA +. This allows the switch transistor to be successfully disabled. The sub-circuit AMP significantly reduces switching losses and possibly allows converter operation without forced air cooling, which was commonplace in the past.

FIG. 30 shows a schematic diagram of a snubber subcircuit of the present invention. Snubber subcircuit S
N is the diode D804 and D805 and the resistors R800, R817, R8.
18 and capacitors C814 and C819.

[0126]

[Table 31]

The node SNL2 is connected to the drain terminal of the external output switch and the flyback side of the inductive load. The input node SNL2 is connected from the node R800 connected in series with the capacitor C819 to the node SNOUT. The anode of the diode D805 is connected to the node S together with the resistor [R817 || R818] connected in parallel with D805.
Connected to NL2. Resistors R817 and R818 may be combined into a single resistor. The cathode of D805 is connected to capacitor C814 which connects to node / pin SNL1. The node SNL1 is connected to the power feeding side of the magnetic element of the external load. The other leg of the external magnetic element is connected to the anode of D805 and the anode side of the external flyback diode D4. The 1 MEG ohm resistors R817 and R818 draw charge from C814 and reset it for the next cycle. Capacitor C819 and resistor R800 capture the high frequency events from the external flyback diode D4 state transitions, and transfer some of the energy to an external holdup capacitor (hold) connected to node SNOUT.
up cap). The external flyback diodes D4 and D805 isolate the drain of the output switch so that the output switch does not have to escape the charge of the extra capacitance of a typical drain / source connected to the snubber circuit, which is faster. Switching takes place. It should be noted that such a circuit does not attempt to absorb the flyback in a large RC circuit that converts the available energy into losses. It does not try to pack the flyback into ground, nor does it add capacitance, slow the output switch, or increase switching loss. This subcircuit is used with its mirror SNB (FIG. 32) on both ends of an external push-pull switch. This design returns some of the flyback energy to the input power supply or output load. The "snubbing" effect slows the flyback rise and gives the external flyback diode time to start conducting. The circuit effectively manages high frequency flyback pulses.

FIG. 30A shows a schematic diagram of a sub-circuit of the diode snubber of the present invention. The snubber sub-circuit DSN comprises diodes D51, D52, D53, D54 and D55, and capacitors C51, C52, C53, C54 and D55.

[0129]

[Table 32]

The pin SNL2 is connected to the anode of D51, the cathode of D51 is connected to the anode of D52, the cathode of D52 is connected to the anode of D53, and D53.
Is connected to the anode of D54, the cathode of D54 is connected to the anode of D55, and the cathode of D55 is connected to pin SNOUT. The capacitors are a combination of series and parallel [D51 || C51] + [D52 || C52] + [D
53 || C53] + [D54 || C54] + [D55 || C55], which are connected across the respective diodes. The node SNL2 is connected to the drain terminal of the external output switch and the flyback side of the inductive load. The anode of the external flyback rectifier diode D4 (FIGS. 1, 3 and 4) is connected to the node SNL2.
Node SNOUT is a storage capacitor [C16 || C17] (FIGS. 1, 3 and 4).
And the cathode of the flyback diode D4. The external diode D4 in parallel with the DSN forms a hybrid diode. Schottky diodes have a fast recovery time (fast r
It has the desirable properties of an echo time (less than 6 nanoseconds (6 * 10 ⁻⁹ )) and a low forward voltage drop (0.4-0.9 volts) at high currents. Schottky diodes currently suffer from a limited reverse blocking voltage of up to 100V. Each diode will block 100V and the parallel capacitors will
The reverse voltage across the diode string is evenly distributed. The reverse junction capacitance of each diode is less than 10 pf, so it is much smaller than a parallel capacitor. Therefore, the reverse voltage is split approximately evenly across the diode. It is necessary to match the capacitors better than 5% to ensure a uniform voltage division. High precision is common and cheap for small capacitors. Different blocking voltages can be achieved by adjusting the number of diode / capacitor pairs. By way of example and not limitation, 500V was selected. The main flyback rectifier diode D4 blocks high voltages, but suffers from long reverse recovery times, with 50-500 nanoseconds being common in fast recovery diodes. What is needed is a diode with low voltage drop, high blocking voltage and extremely short recovery time. Snubber D in parallel with main flyback rectifier
SN is very close to such an ideal diode. The total blocking voltage is obtained by adding the blocking voltages of the individual diodes. The recovery time is determined by the slowest diode in the string and is often less than 5 nanoseconds. When the main rectifier starts conducting more slowly, a low forward voltage drop is achieved. A low capacitance is also realized as the capacitance is ⅕ of the individual capacitors. The hybrid diode begins commutation immediately after the main switch ceases to conduct and the unsaturated magnetic element begins to release its energy. This limits high voltage flyback overshoot to less than 40-70 volts. This keeps the switch well within its safe operating area (SOA), which provides higher output power and additional efficiency gain (effi).
), allowing it to operate at higher voltages due to
Alternatively, it allows the use of less expensive lower voltage switches while maintaining the same voltage margin. External flyback diodes D4 and D805
Isolates the drain of the output switch, resulting in faster switching because the output switch does not have to escape the charge of the extra capacitance of a typical snubber circuit. Note that this circuit does not attempt to absorb flyback in large RC networks that generate additional heat. Nor is it trying to pack a flyback into ground, nor adding capacitance, slowing down the output switch or increasing switching loss. It is possible to use the sub-circuit DSN in parallel with a slower rectifier, eg a flyback diode D4, to supplement the main rectifier. This provides additional protection to the switch and rectifies some of the flyback pulse before the main rectifier begins operation. Such high frequency energy ends up in heat or radiant noise.

FIG. 30B shows a schematic diagram of another snubber sub-circuit SNBB of the present invention. The snubber sub-circuit SNBB consists of a resistor R310 and a capacitor C821.

[0132]

[Table 33]

The node SNL2 is connected to the resistor R821 and the node S via the capacitor C821.
Connect to NOUT. The node SNOUT is connected to the cathode of the flyback diode. The node SNL2 is connected to the drain terminal of the external output switch and the flyback side of the inductive load. The "snubbing" effect delays the flyback rise to give the external rectifier diode time to start conducting.

FIG. 31 shows a schematic diagram of a sub-circuit of the snubber of the present invention. The snubber subcircuit SNA includes resistors R810 and R811 and capacitors C820 and C82.
It consists of 1.

[0135]

[Table 34]

The node SNA1 is connected from the series resistor R810, the capacitor C820 to the node SN.
A2 to the capacitor C821, the series resistor R811 to the node SNA.
Connect to 3. The node SNA1 is connected to the center tap of an external magnetic element.
The node SNA2 is connected to the drain terminal of the external output switch and the flyback side of the inductive load. The node SNA3 is connected to the source terminal of an external output switch. To reduce voltage transients across the switch, resistors R810 and C820 try to absorb a portion of the flyback. Part of the flyback is returned to ground by C821. This subcircuit is used with its mirror SNA (FIG. 31) on both ends of an external push-pull switch. The "snubbing" action slows the rise of the flyback and provides time for the external rectifying diodes D8 and D9 of Figure 25 or 25A to begin conducting. This circuit efficiently manages high frequency flyback pulses.

FIG. 32 is a schematic diagram of a snubber subcircuit of the present invention. Snubber subcircuit S
NB includes resistors R820 and R821 and capacitors C840 and C841.
including.

[0138]

[Table 35]

The node SNB1 has a series resistor R820, a capacitor C820, and a node SNA.
2 to capacitor C841, and series resistor R821 to node SNB3.
Connect to. The node SNB1 is connected to the center tap of an external magnetic element. The node SNB2 is connected to the drain terminal of the external output switch and the flyback side of the inductive load. The node SNB3 is connected to the source terminal of an external output switch. To reduce the voltage transients across this switch, resistors R820 and C840 try to absorb a portion of the high frequency flyback. C841 and R821 return part of the flyback to ground. The "snubbing" action is
The rise of the flyback is delayed to give the external rectifier diodes D8 and D9 of FIG. 25 or 25A time to start conducting. This circuit efficiently manages high frequency flyback pulses.

FIG. 33 shows the PWM (pulse width modulator) and FM (frequency modulator) sub-circuits of the present invention. The sub-circuit PWFM consists of resistors R401, R402, R403 and R404, capacitors C401, C402, C403, C404, C405 and C406, a controller IC U400 and a diode D401.

[0141]

[Table 36]

The control element U400 connects to the circuit with the following series connection: from pin 1 to the feedback pin PW1 and to the wiper terminal of the further adjustable resistor R404 (
Wiper) to the return node PWFM0. The resistor R404 may be replaced with two fixed resistors. Capacitor C403 is connected from pin 2 to pin 1. Capacitor C403 is used to filter the output of the error amplifier. The upper half of resistor R404 is connected to the 5.0 volt internal reference on pin 8 of node REF1. The internal 5.0 volt referenced U400 pin 8 or node REF1 is connected to the upper half of resistor R403 and the return node PWFM0 via capacitor C402. This reference provides the current to the external feedback circuit. The wiper terminal of R403 is connected to the node FM1 and pin 4, the pin 3 through R402, and the return node PWFM0 through C404. Resistor R403
May be replaced by two fixed resistors. Pulse width timing capacitor C4
04 connects pin 3 to the return node PWFMO. Low leakage diode (low
The anode of the leakage diode D401 is connected to the pin 3, and the cathode is connected to the node CLK of the output pin 6. Resistor R404 sets the nominal pulse width of node CLK on output pin 6. The pulse width can be adjusted from 0 (off) to 95%. Resistors R403 and C404 define the nominal operating frequency. By applying a 20 volt power supply between nodes PWFM + and PWFM0, controller U400 generates an internal 5.0 reference voltage at pin 7, node REF1. The node CLK of output pin 6 is set high about 20 volts (see segment 60 of trace G6 in the oscillograph of FIG. 34).
. By resetting pin 6 low (see trace G6 in the oscillograph of FIG. 34, segment 62), the voltage across C404 at pin 3 reaches the comparator level (trace of oscillograph of FIG. 34). G1 segment 6
1), C404 starts charging via R401. Capacitor C404 quickly discharges via D401 (see segment 63 of oscillograph trace G1 in FIG. 34). During the time that pin 6 is low (see segment 64 of trace G1 in the oscillograph of Figure 34), pin 3 remains 0.6 volts above the node of PWDM0. On the rising edge of pin 6, capacitor C405 begins to charge rapidly until the voltage on pin 4 reaches the internal comparator level (see segment 65 of trace G4 in the oscillograph of FIG. 34). The comparator triggers an internal transistor to rapidly discharge C404 (see segment 66 of trace G4 in the oscillograph of Figure 34). This cycle repeats with output pin 6 set high. The external feedback current applied to pin 1 of U400 and node PW1 (see trace G1 in the oscillograph of FIG. 34) follows the actual output voltage. Segment 67 of the oscillograph trace G1 (FIG. 34) is the period when the output switch is conducting and storing energy in NSME. Segment 68 of the oscillographic trace G1 (FIG. 34) is the period when the output signal is off and the stored energy in NSME can be transferred to the storage capacitor. Connect an external current source or feedback circuit to pin 1 or node P
By applying to W1, the pulse width can be modulated. Removing the current from PW1 lowers the comparator level, causing the comparator to trigger on the lower voltage across C404, reducing the pulse width. Current to node PW
Introduced within 1, the pulse width increases from nominal to 95% of maximum. Resistors R404 and C404 determine the nominal pulse width. This design allows the CLK output to be pulse width modulated. Applying an external feedback circuit to pin 4 or node FW1 allows the frequency to be modulated. Removing the current from FW1 slows the charging of C405. The longer the charging time, the lower the frequency from the nominal setting value. Such an arrangement allows the CLK output to be frequency modulated. Resonance controller (r
When used with an essonant controller), R403 and C405 determine a nominal frequency that is typically equal to the tank resonant frequency. External feedback is configured to lower the frequency from the nominal frequency (maximum output) to zero frequency “off”. When used as a pulse width controller, the nominal value is set to a maximum pulse width of about 90% and feedback reduces the pulse width. The sub-circuit PWFM can be frequency and pulse width modulated at the same time. Such a configuration and operation mode are unique to the present invention. Feedback of the output to the error amplifier is a unique mode of operation for control element U400. Subcircuit PWFM combines wide dynamic range, precise control, and fast response.

FIG. 34 shows an oscillographic trace of a PWFM (FIG. 33) controller in pulse width modulation mode.

FIG. 35 is an oscillographic trace of the primary voltage of the resonant converter of TCTP (FIG. 8). FIG. 35 is an oscillographic trace of the voltage developed across capacitor C10 (FIG. 8). In this example, the power supply VBAT was only 18 volts.

The inductance 203uH of the primary winding 100 (FIG. 18) is 26u 2.28.
oz. Achieved by winding 55 turns on (64.64 grams) Kool Mu magnetic element 101. The secondary winding 103 (FIG. 18) is wound on the core 101 for 15 turns. A load of 5.5 watts is connected to the winding 103. NSME
Primary winding 100 (FIG. 18) generated an excitation voltage with a peak of 229 volts greater than 10 times VBAT. Tank converters TCTP and TCSSC (FIG. 7) take advantage of the desirable properties of unsaturated magnetic elements to produce large flux biases. Effective large magnetic flux,
By adding a "flux nets" winding to the magnetic element,
It can be drawn into active power.

FIG. 36 shows a regulated 18 volt DC controlled power supply subcircuit REG. The sub circuit REG includes a resistor R517, a regulator Q514, and a capacitor C514.
, C515, C516, C518 and C517.

[0147]

[Table 37]

Pin REG0 connects to the return path of the external power supply. Node REG0 is also a return line, which connects to pin 2 of Q514 and capacitors C518, C514, C515 and C517. The resistor R517 is connected to the pin 1 (input) node of the voltage regulator Q514 and the input pin RIN +. Voltage regulator Q5
Pin 3 of 14 is the regulated DC output of 18vdc and capacitor C515
, C514 and the output pin 18V. Capacitors C515, C517
Is a solid dielectric type and is used to filter high frequency ripple and prevent vibration of Q514. The sub-circuit REG provides the regulated power supply for the control circuit and the output switch buffer AMP (FIG. 29).

FIG. 37 shows a non-isolated high-side switchback converter (switch).
1 schematically shows a sub-circuit HSBK of a back converter). FIG. 37 shows a sub-circuit HSBK of the non-insulated high-side switchback converter. The topology of this converter is a non-isolated high efficiency buck stage.
This back stage supplies regulated power to an efficient push-pull isolation stage. The sub circuit HSBK includes a diode D8, a capacitor C8, a FET transistor Q31, a sub circuit TCTP (FIG. 8), a sub circuit BL1 (FIG. 18B), a sub circuit IFB (FIG. 40B), and a sub circuit AMP (FIG. 29). ) And the sub-circuit PW
And FM (FIG. 33).

[0150]

[Table 38]

External power supply VBAT is connected to pins DCIN + and DCIN-. Pin DCI
N + is the source of the transistor Q31, the pin PWFFM0 of the sub circuit PWFM, the pin GA0 of the sub circuit AMP, the pin FBE of the sub circuit IFB, and the sub circuit T.
Connect to CTP pins DCIN + and B-. Sub circuit TCTP pin B +
The regulated 18 volt output from V.sub.2 connects to pin GA + of subcircuit AMP and pin PWFM + of subcircuit PWFM. This provides positive gate drive for the source of Q31. The return path of the power supply VBAT is the pin DCIN- and the sub circuit TC.
It is connected to the pin DCIN- of TP, the anode of the diode D68, the capacitor C68, RLOAD, the pin OUT- of the sub-circuit IFB, the output pin B- and the ground / return node GND. The sub-circuit PWFM is designed for 0-90% adjustable pulse width operation, with the maximum pulse width occurring in the absence of feedback current at pin PW1. As the feedback current increases, the pulse width and the output voltage from converter HSBK decrease. Sub circuit PWFM clock / PWM
The output pin CLK is connected to the input pin GA1 of the sub circuit AMP of the buffer.
The output of the pin GA2 of the sub circuit AMP is connected to the gate of Q31. The drain of Q31 is connected to the pin P1B of the sub-circuit BL1 and the cathode of D68.
The pin P1A of the sub circuit BL1 has a capacitor C8 and the pin OUT of the sub circuit IFB.
-And RLOAD. The pin CLK of the sub circuit PWFM is high (hi
gh), the output pin GA2 of the buffer AMP charges the gate of the transistor switch Q31. The switch Q31 becomes conductive, and the power source VBAT changes from NSME to BL.
The capacitor C68 is charged via 1 and energy is stored in BL1. The feedback output pin FBC from the sub circuit IFB is connected to the pulse width adjustment pin PW1 of the sub circuit PWFM. As the output voltage reaches the designed level,
Subcircuit IFB removes current from PW1 and directs PWFM to reduce the pulse width or the on-time of signal CLK. After the subcircuit PWFM reaches the commanded pulse width, the PWFM switches the output pin CLK low, turning off Q31 and stopping the current to BL1. The stored energy is NSME
BL1 is now discharged into diode D68, which is now forward biased, charging capacitor C68. By modulating the "on" time of switch Q31, the converter "backs" the applied voltage and effectively regulates it to a lower voltage. The regulated voltage is developed across nodes B- and B +. Subcircuit IFB provides an isolated feedback voltage to subcircuit PWFM. When the sub-circuit IFB detects that the converter outputs (nodes B + and B-) are at the designed voltage, more current is conducted by the phototransistor. When the current from PM1 drops, the PWFM is commanded to make the pulse width shorter. Therefore, the converter output voltage drops. In this case, the feedback signal from the IFB commands the PWFM to minimize the output. Switch Q3
The gate drive to 1 is eliminated, stopping all buck activity,
Capacitor C68 discharges via RLOAD. The input current from VBAT is sinusoidal, making the converter extremely quiet. In this way, the switch Q31 is
It is not exposed to the large current spikes typical of prior art saturated magnetic elements. Therefore, less stress is applied to the switch, which causes MTB
F increases. The sub-circuit HSBK has N in such a converter topology.
Take advantage of the desirable properties of SMEs.

FIG. 38 is an insulation type two-stage low-voltage side switch (low side switch).
2 schematically shows a sub-circuit LSBKPP of the buck converter of FIG. This converter topology is a low-stage switch back stage with high efficiency, which provides a regulated power supply for an efficient push-pull isolation stage. An efficient center tap full wave rectifier provides rectification. The sub circuit LSBKPP includes a diode D46,
The capacitor C46, the FET transistor Q141, and the sub circuit REG (see FIG. 36).
), A sub circuit OUTB (FIG. 25A), a sub circuit BL1 (FIG. 18B), a sub circuit TCTP (FIG. 8), a sub circuit IFB (FIG. 40B), a sub circuit AMP (FIG. 29), and a sub circuit. It consists of DCAC1 and a sub-circuit PWFM (FIG. 33).

[0153]

[Table 39]

External power supply VBAT is connected to pins DCIN + and DCIN-. From the pin DCIN +, the pins RIN +, D46 cathode of the sub circuit REG, the capacitor C46, the pin DCIN + of the sub circuit TCTP (FIG. 8), and the sub circuit DCA.
It is connected to pin DC + of Cl. Output pin +1 of voltage regulator subcircuit REG
8V corresponds to pin GA + of sub-circuit AMP and pin PWFM + of sub-circuit PWFM.
Connected to. The sub-circuit REG provides a regulated low voltage power supply to the controller and the buffer of the main switch. The negative side of VBAT is connected to pin DCIN- and ground return node GND. The node GND is a sub circuit PWF
M pin PWFFM0, sub circuit AMP pins GA0 and Q141 source, sub circuit IFB pin FBE, sub circuit REG pin REG0, and sub circuit TCTP
Is connected to the pin DCIN-. The sub-circuit PWFM (FIG. 33) is designed for variable pulse width operation. The nominal frequency is 20-600 kHz and the PWFM has a maximum pulse width of 9 without feedback current from the sub-circuit IFB.
It is configured to be 0% (maximum back voltage). Increasing the feedback current reduces the on-time of Q111, reducing the voltage to the push-pull stage and the output from converter LSBKPP. The clock output pin CLK of the sub-circuit PWFM is connected to the input pin GA1 of the sub-circuit AMP (FIG. 29) of the buffer. The output of GA2 of the sub-circuit AMP pin of the switch speed-up buffer is connected to the gate of Q141. The isolated 18 volt floating power supply from pin B + of subcircuit TCTP is connected to pin P18V of subcircuit DCACl. The drain of Q141 is connected to the anodes of pins P1A and D46 of subcircuit BL1. The return line of the pin DC- of the sub-circuit DCACl is connected to the pin P1B of the sub-circuit BL1 and the pins B- and C46 of the sub-circuit TCTP. The pin CLK of the sub-circuit PWFM is high and the buffer AMP output pin GA2 charges the gate of the transistor switch Q141. Switch Q141
Causes the reverse-biased diode D46 to conduct, that is, the capacitor C46 starts charging from the power supply VBAT through BL1 of NSME. Energy is stored in the NSME subcircuit BL1 during the time that the time Q141 is conducting. C46
To provide power to the final push-pull converter stage DCAC1. The output of the sub circuit OUTB of the output rectifier is the feedback sub circuit IFB.
And the output pin FBC from the sub-circuit IFB is connected to the PWFM of the sub-circuit.
Of the pulse width adjusting pin PW1. Subcircuit IFB removes current from PW1 and commands PWFM to shorten the on-time or pulse width of signal CLK. After the sub-circuit PWFM reaches the commanded pulse width, PFFM goes to CL.
Switch K low, turn off Q141 and stop current to BL1. Energy is released from the NSME BL1 to the now forward biased flyback diode D46, charging capacitor C46. Switch Q141
By modulating the on time of the converter voltage is adjusted. The regulated voltage is developed across the nodes DC + and GND of C46. Energy is provided to the isolated constant frequency push-pull DC / AC converter subcircuit DCAC1 (FIG. 2). The sub-circuit DCACI efficiently converts the regulated back voltage to a higher or lower voltage set by the turns ratio of the sub-circuit PPT1 (FIG. 19) of the magnetic element winding. The center tap of the magnetic element of the push-pull output is the pin OUT-, RLOAD of the sub-circuit OUTB, the pin OUT- of the sub-circuit IFB and the pin O which forms the return line for the load and feedback circuits.
It is connected to UT-. The output of the pin ACH of the sub circuit DCAC1 is connected to the pin C7B of the sub circuit OUTB. The output of the pin ACL of the sub-circuit DCACl is connected to the pin C8B of the sub-circuit OUTB. The sub circuit OUTB is
It rectifies the AC power generated by the sub-circuit DCAC1. Since the non-saturation magnetic converter is extremely quiet,
Only minimal filtering is required by OUTB. This will also reduce cost and increase efficiency as filter component losses are minimized. Subcircuit IFB provides the isolated feedback current to subcircuit PWFM. When the sub-circuit IFB senses a converter output (nodes OUT + and OUT−) higher than the design voltage / desired voltage, the current flows to node P.
Removed from M1. As the current from PMl decreases, the PWFM is commanded to reduce the pulse width, resulting in an enhanced buck action and a first
The converter output voltage of the stage is reduced. In this case, the feedback signal from the IFB commands the PWFM to minimize the output. The gate drive to switch Q141 is removed, all buck activity is stopped, and capacitor C46 is discharged. The input current to charge C46 from VBAT is sinusoidal, which makes the converter very quiet. In addition, switch Q141 is not exposed to potentially destructive current spikes. MTBF is increased because the stress on the switch is small. Subcircuit LSBKPP takes advantage of the desirable properties of NSME in this converter topology. BL of NSME
Adjusting 1 (FIG. 18B) sets the magnitude of the back voltage for use in the final push-pull isolation stage. Higher voltage achieves higher efficiency.
The final output voltage is set by the turns ratio of push-pull element PPT1 (FIG. 19). The converter LSBKPP enables a high voltage power supply to be efficiently converted into a high current isolated output.

FIG. 39 shows an insulated two-stage low voltage side switchback converter (low side switc).
FIG. 3 is a schematic diagram of a sub circuit LSBKPPBR of the h buck converter). This converter topology consists of a non-isolated high efficiency low voltage side switchback stage that
Provides regulated power to a high efficiency push-pull isolation stage. A full wave bridge rectifier provides rectification. The sub circuit LSBKPPBR includes a diode D6 and a capacitor C.
6, FET transistor Q111, sub circuit REG (FIG. 36), sub circuit OUT
BB (FIG. 25B), sub-circuit BL1 (FIG. 18B), sub-circuit TCTP (FIG. 8),
Sub circuit IFB (FIG. 40B), sub circuit AMP (FIG. 29), sub circuit DCAC1
(FIG. 2) and the sub-circuit PWFM (FIG. 33).

[0156]

[Table 40]

External power supply VBAT is connected to pins DCIN + and DCIN-. From the pin DCIN +, the pins RIN + of the sub-circuit REG, the cathode of D6, the capacitor C6, the pin DCIN + of the sub-circuit TCTP (FIG. 8), and the sub-circuit DCAC
It is connected to pin DC + of l. Output pin of voltage regulator subcircuit REG +18
V is connected to pin GA + of sub-circuit AMP and pin PWFM + of sub-circuit PWFM. The sub-circuit REG provides a regulated low voltage power supply to the controller and the buffer of the main switch. The negative side of VBAT is connected to the pin DCIN-, which is the pin PWFM0 of the sub circuit PWFM and the pin GA of the sub circuit AMP.
0, source of Q111, pin FBE of sub-circuit IFB, pin R of sub-circuit REG
EG0 is connected to the pin DCIN- of the sub circuit TCTP. Sub-circuit PWFM
(FIG. 33) is designed for variable pulse width operation. The nominal frequency is 20-600 KHz and the PWFM is configured to have a maximum pulse width of 90% (maximum back voltage) without feedback current from the sub-circuit IFB. Increasing the feedback current reduces the on-time of Q111, reducing the voltage to the push-pull stage and the output from converter LSBKPPBR. The clock output pin CLK of the sub circuit PWFM is connected to the sub circuit AMP (see FIG. 2) of the buffer.
It is connected to the input pin GA1 of 9). The output of pin GA2 of the sub-circuit AMP of the switch speedup buffer is connected to the gate of Q111. The isolated 18 volt floating power supply from pin B + of subcircuit TCTP is
It is connected to pin P18V of CACl. The drain of Q111 is the sub circuit BL
1 is connected to the anode of pins PA1 and D6. The return line of the pin DC- of the sub circuit DCACl is the pin P1B of the sub circuit BL1 and the pin B of the sub circuit TCTP.
-And connected to C6. The pin CLK of the sub-circuit PWFM is high, and the output pin GA2 of the buffer AMP charges the gate of the transistor switch Q111. The switch Q111 makes the reverse bias diode D6 conductive. That is, the capacitor C6 starts charging from the power supply VBAT through BL1 of NSME. During the time when Q111 is conducting, the sub circuit BL1 whose energy is NSME
Stored in. Power is provided to the final push-pull converter stage DCAC1 by charging C6. The output of the sub-circuit OUTBB of the output rectifier is connected to the feedback sub-circuit IPB, and the output pin FBC from the sub-circuit IFB.
Is connected to the pulse width adjusting pin PW1 of the sub-circuit PWFM. Sub circuit IF
B removes current from PW1 and commands PWFM to shorten the on-time or pulse width of signal CLK. After the sub-circuit PWFM reaches the commanded pulse width, the PFFM switches CLK low, turning off Q111, BL1
Current to is stopped. Energy is released from BL1 of NSME to the now forward biased flyback diode D6, charging capacitor C6. By modulating the on-time of switch Q111, the converter voltage is adjusted.
The regulated voltage is developed across the nodes DC + and DC- of C6. Energy-isolated constant frequency push-pull DC / AC converter subcircuit DCAC1
(Fig. 2). Allows the sub-circuit DCACI to efficiently convert the regulated back voltage to a higher or lower voltage set by the turns ratio of the magnetic element turns sub-circuit PPT1 (FIG. 19). The return node of the pin OUT- of the sub-circuit OUTBB is RLOAD, the pin AC0 of the sub-circuit DCAC1,
It is connected to the pin OUT− and the pin OUT− of the sub circuit IFB. Node O
UT- is the return line for the load and feedback circuits. Sub circuit DCAC
The output of the No. 1 pin ACH is connected to the pin C7B of the sub circuit OUTBB.
The output of the pin ACL of the sub circuit DCACl is connected to the pin C8B of the sub circuit OUTBB. Sub-circuit OUTBB rectifies the AC power generated by sub-circuit DCAC1. Since the disclosed unsaturated magnetic converter has a minimum output ripple, less filtering is required by OUTBB.
This will also reduce cost and increase efficiency as filter component losses are minimized. Subcircuit IFB provides the isolated feedback current to subcircuit PWFM. The open collector output of pin FBC of IFB is connected to pin PW1 of PWFM. Sub-circuit IFB is designed voltage /
Upon sensing a converter output (nodes OUT + and OUT-) that is higher than the desired voltage, current is removed from node PM1. When the current from PMl decreases, PW
The FM is commanded to reduce the pulse width, resulting in enhanced back action,
The output voltage of the first stage converter is reduced. In this case, the feedback signal from the IFB commands the PWFM to minimize the output. The gate drive to switch Q111 is removed, all back activity is stopped, and capacitor C6
Is discharged. Since NSMEs do not saturate, there are no destructive and noisy current spikes that are common in the prior art. The input current from VBAT to charge C6 is sinusoidal, which makes the converter very quiet. In addition, switch Q111 is not exposed to potentially destructive current spikes. MTBF is increased because the stress on the switch is small. Sub circuit LSBKPP
BR takes advantage of the desirable properties of NSME in this converter topology. Adjusting NSME BL1 (FIG. 18B) sets the back voltage to a level that can be used in the final push-pull isolation stage. The higher the voltage, the higher the efficiency achieved. The final output voltage is set by the turns ratio of push-pull element PPT1 (FIG. 19). The converter LSBKPPBR efficiently converts the high voltage power supply into a high power factor AC / DC converter such as the sub-circuit ACDCPF (FIG. 4).

FIG. 40 is a sub-circuit IP of an isolated overvoltage feedback circuit according to the present invention.
It is a schematic diagram of FFB. The sub-circuit IPFFB includes resistors R926, R927 and R.
928, R929 and R930, capacitor C927, Zener diode D
928 and D903, transistor Q915 and optoisolator U90
It consists of three.

[0159]

[Table 41]

The node PF + is connected to the cathode of D903 and the anode of the optoisolator U903 through the resistor R927. The cathode of diode D903 is connected to pin PF +. Resistor R928 goes from the anode of D928 to Q9
It is connected to 15 bases. Capacitor C927 is Zener diode D9
It is connected in parallel with 03. Resistor R928 limits the maximum base current. Resistor R929 is connected between the base and emitter of Q915. Resistor R9
29 is used in a high voltage diode to shunt excess Zener leakage current from a common base. The cathode of the 200V Zener diode D928 is connected to the pin PF +. The anode of D928 is R930 and R928.
It is connected to the. Resistor R930 provides a path for leakage current from 200V Zener diode D928. Resistor R926 limits the maximum current to the light emitting diode inside U903 to about 10 ma. Resistor R927 sets the maximum zener current at a maximum boost voltage of about 200V to 20 ma. Transistor Q915 is biased off when the voltage from nodes PF + and PF− is less than the 200V Zener voltage. The transistor is cut off, or non-conducting, and when no current is injected into the LED of U903, the internal phototransistor is also non-conducting. The external control subcircuit will not be commanded to change its output. When a voltage greater than 200V is applied to nodes PF + and PF-, reverse biased zener diode D928 injects current into the base of Q915. Resistor R927, capacitor C927 and diode D903 provide the 18V voltage to the collector of Q915. Transistor Q915 conducts current to the LED of U903 and base current is injected into the phototransistor of U903. Changing the LED current reflects this as a variable impedance between the FBC and FBE. The phototransistor may be connected as a variable current source or a variable impedance. This sub-circuit detects excessive boost voltage and rapidly feeds it back to the control sub-circuit (see PFA (Fig. 23), PFB (Fig. 24) or PWFM (Fig. 33)) and automatically lowers the boost voltage. .

FIG. 40A is a schematic diagram of a non-isolated boost output voltage feedback sub-circuit FBA. The sub-circuit FBA includes resistors R1120, R1121, R1122,
It consists of R1123 and R1124.

[0162]

[Table 42]

The input node PF + is connected to the series resistor [R1123 + R1124] and then to the parallel resistor [R20 || R21 || R22] and further to the return node BR-. The values of resistors R1120, R1121, R1122, R1123 and R1124 have a nominal input voltage of 385V and an output feedback voltage of 3.8.
Selected for 5V (see oscillograph G1 in FIG. 34). Resistor R1
Although 120, R1121, R1122, R1123 and R1124 are shown in surface mount configuration, they can be combined into two through hole resistors. The feedback output node PFL is a sub circuit PFA (FIG. 23) or PFB.
It is connected to the node PF1 of (FIG. 24). Return pin BR- is connected to BR- of PFA (FIG. 23) or PFB (FIG. 24). Nodes FBE and FBC may be connected between node FM1 and pin PWFM0 or between node PW1 and pin PWFM0 of control sub-circuit PWFM (FIG. 33).

FIG. 40B is a sub-circuit F of an isolated low voltage feedback circuit according to the present invention.
It is a schematic diagram of BA. Subcircuit IFB includes resistors R900, R901 and R9.
02, Zener diode D900, Darlington transistor Q900 and optoisolator U900.

[0165]

[Table 43]

The node OUT + connects the cathode of D900 to R901. The anode of diode D900 is connected to series resistor R900 and to the base of Darlington transistor Q900. A resistor R902 is connected from the base of Q900 to the emitter. Resistor R901 is opto-isolator U900
Is connected to the anode of the LED (light emitting diode) of which the cathode is Q9.
00 collector. The emitter of Q900 is the return current path,
It is connected to the pin / node OUT-. Resistor R901 limits the maximum current to the light emitting diode inside U900 to 20 ma. Resistor R902 diverts some of the zener leakage current from the base. Selection of the Zener diode voltage sets the converter output voltage to a typical value, eg 48V. The Zener voltage is a value obtained by subtracting two base-emitter junction voltage drops (1.4 V) from the final desired output. Once the OUT + node reaches the Zener diode voltage, a small base current biases Q900 into conduction,
The LED inside the optoisolator U900 is turned "on". The resistor R900 is
Limit the maximum base current to Q900. Resistors R900 and R901 connect the collector current of the Darlington transistor Q900 to the nodes OUT + and OUT-.
Is selected to be biased at the nominal voltage across. The voltage change between OUT + and OUT- changes the LED current in opto-isolator U900, which in turn
The base current of the phototransistor inside U900 is changed. The emitter of the phototransistor is the node FBE and the collector is the node FBC. Changing the LED current reflects this as a variable impedance between the FBC and FBE. The phototransistor may be connected as a variable current source or a variable impedance. Control subcircuit PFA (FIG. 23), PFB (FIG. 24) or PWFM (
When used with (Fig. 33), this phototransistor has a current shunt (cu
rrent shunt) is connected. Higher voltage is applied to nodes OUT + and OUT
When applied to −, the feedback shunt current increases, causing the control subcircuit (
See PFA (Figure 23), PFB (Figure 24) or PWFM (Figure 33))
Are commanded to reduce the pulse width or frequency. Due to the extremely high gain of the Darlington transistor and the fast response of the internal converter stage, the IFB provides fast feedback, active ripple reduction and effective load regulation.

FIG. 40C is a schematic diagram of an alternative PFC isolated overvoltage feedback circuit subcircuit IOVFB. The sub-circuit IOVFB has R917, R938, and R9.
39 and R940 resistors, diode D911, Darlington transistor Q914 and optoisolator U905.

[0168]

[Table 44]

The output of the PFC is connected to R917 at pin PF + and then to the collector of Q914. Resistor R917 sets the maximum current to the light emitting diode of U905. The resistor R938 is connected from the return node PF + towards the cathode of the Zener diode D911 and towards R938. The resistor R939 is connected from the return node PF- to the cathode of the Zener diode D911 and to R938. The anode of D911 is the wiper arm of the adjustable resistor R940 (
wiper arm). One leg of R940 is a transistor Q914
Of the LED's of R939 and U905 and R939. The emitter of Q914 is connected towards the anode of U904. Adjustable resistor R940 sets the maximum or trip voltage before transistor Q914 is biased on. Current is then provided to the U905 LED. The emitter of the phototransistor is the node FBE and the collector is the node FBC. Changing the LED current is reflected as a variable impedance between FBC and FBE. The phototransistor is usually connected as a shunt to force the control element to a minimum output. This subcircuit detects the boost voltage and feeds it back to the PFC. When an excessive boost voltage occurs, the PFC is forced to automatically lower the boost voltage.

FIG. 40D shows an alternative non-isolated boost output voltage feedback sub-circuit FB.
It is a schematic diagram of D. The sub-circuit FBD includes resistors R1120, R1121, and R11.
22, R1123 and R1124.

[0171]

[Table 45]

The input node PF + is connected to the series resistor [R1123 + R1124] and then to the parallel resistor [R1122 || R1121]. [R1122 || R11
21] is connected to the wiper arm of R1121 and [R1123 ||
R1120] to the return node BR-. The resistor value is selected for a nominal input voltage of 385V. Although resistors R1120 to R1124 are shown in a surface mount configuration, they can be combined in another series-parallel fashion to form another equivalent circuit. The feedback output node PFL is a sub circuit PFA.
(FIG. 23) or PFB (FIG. 24) connected to the node PF1. The return pin BR- is connected to the BR- of the PFA (Fig. 23) or PFB (Fig. 24). The nodes FBE and FBC are the nodes FM of the control sub-circuit PWFM (FIG. 33).
It may be connected between 1 and the pin PWFM0 or PW1 and the pin PWFM0. The component values have been selected to provide a 15V adjustment range.

FIG. 41 is a schematic diagram of an alternative low voltage feedback circuit sub-circuit FBI. The sub-circuit FBI is composed of resistors R81, R82 and R83, a Zener diode D80, an NPN transistor Q80 and a capacitor C80.

[0174]

[Table 46]

The node OUT + is connected to the cathode of D80. The anode of diode D80 is connected to OUT- through resistor R83, and resistor R82 is connected to the base of transistor Q80. Capacitor C80 is from base to pin OU
It is connected to T-. The capacitor C80 bypasses high frequency as noise to OUT-. The resistor R81 is connected from the emitter of Q80 to the node OUT-. Resistor R81 adds local negative feedback to reduce the effects of transistor gain changes. Q80 collector is pin FB
It is connected to C. The return current node is connected to pins FBE and OUT-. Resistor R82 limits the maximum base current to protect Q80. The resistor R83 shunts a portion of the Zener leakage current from the base. Zener diode voltage selection sets the converter output voltage, a typical value is 48V.
The Zener voltage is one base-emitter junction voltage drop (0.
65V). When the OUT + node reaches the nominal level, the reverse biased Zener diode conducts and begins injecting a small base current into Q80. This forward biases the transistor into conduction. OUT
The voltage change between + and OUT- changes the collector current of Q80. During normal operation, the Zener diode is biased at its bend, so small changes in voltage result in fairly large changes in collector current. When the subcircuit FBI is used with the control subcircuit PFA (FIG. 23), PFB (FIG. 24) or (FIG. 33), the transistors are connected as a current shunt. When a higher voltage is applied to the nodes OUT + and OUT-, the feedback shunt current increases and causes the control subcircuit (PFA (Figure 23) or PFB (Figure 24) or PWF.
M (see FIG. 33)) is commanded to reduce the pulse width or frequency. The sub-circuit FBI provides fast feedback and gain for the ripple component.
The rapid response of the internal converter stage achieves active ripple reduction and effective load regulation.

FIG. 41A is a schematic diagram of an alternative overvoltage feedback circuit subcircuit FB2. Subcircuit FB2 includes resistors R419, R418, R414 and R410,
Zener diode D410 and NPN transistors Q414 and Q41
It consists of three.

[0177]

[Table 47]

Node PF + is connected to a series resistor R410 + R419 + R418 and then to common or ground to form a voltage divider. The connecting portion of R418 and R419 is connected to the collector of Q414 and the cathode of the Zener diode D410. The anode of the diode D410 is connected to the base of the transistor Q414. The emitter of Q414 is connected to the base of Q413 and resistor R4
It is connected to the ground through 14. The emitter of Q413 is also connected to ground. The collector of Q413 is connected to node PF2 to connect to pin 2 of the regulator subcircuit PFB. Resistors R410, R419, R4
18 and D410 are selected to forward bias transistors Q413 and Q414 when node PF + exceeds DC450V with respect to common. This provides a boost activity (boos) until the fault condition subsides and a fast and reliable alternative adjustment is provided which results in the UL test requirements being met.
t activity) is adjusted.

FIG. 42 is a schematic diagram of a sub-circuit OVP1 of an embodiment of overvoltage protection according to the present invention. The sub-circuit OVPl includes an SCR (silicon controlled rectifier) SCR1200, a resistor R1200, a capacitor C1200 and a Zener diode D1200, D1.
202 and D1203.

[0180]

[Table 48]

The input pin PF + is connected to the cathode of the Zener diode D1203, and the anode of D1203 is a series Zener diode [D1202 + D1200].
, And then to the gate of the SCR 1200. [R1200 || C12
00] noise attenuator circuit from the gate of the SCR 1200 of the SCR to the return node B
It is connected to R-. Diodes D1102 and D1103 are both 20
It is 0V, and the D1101 is a 5.1V type, and the trip point of OVP is set at 405V by the total zener voltage. Other trip voltages may be implemented by choosing another combination of Zener diodes. Capacitor C
1200 and R1200 prevent the OVP from accidentally tripping due to leakage currents and transients. If the AC line voltage is very high, or if a component in the feedback loop (FIGS. 40A, 40B, 40C or 40) fails, the boost voltage will quickly rise to a level dangerous for the output switch or output storage capacitor. Can be. When the output boost voltage at node PF + rises above about 405V, Zener diodes D1203, D
1202 and D1200 conduct a small current to the gate of SCR1200
Turn on the R1200. When the SCR 1200 is turned on, a low impedance path is created between the AC lines through the rectifier subcircuit BR (FIG. 22).
The SCR 1200 and bridge rectifier diode must be selected to withstand short circuit currents that can exceed 100 amps before the input fuse opens. This quickly limits the boost output voltage to a safe level. This circuit should never operate under normal AC line voltage.
By varying the Zener voltage, this subcircuit is also suitable for use in protecting the load from overvoltage conditions across the rectifier output. Sub circuit O
VPl shuts off the converter without blowing the line fuse. Sub circuit O
The VP can be used as a failsafe backup for critical loads in combination with OVP1 (FIG. 42A).

FIG. 42A is a schematic diagram of a sub-circuit OVP2 of an embodiment of overvoltage protection according to the present invention. The sub-circuit OVP2 includes SCRs (silicon controlled rectifiers) SCR1101 and SCR1100, resistors R1101 and R1102 and SCR1100, capacitors C1100 and C1101 and Zener diodes D1100 and D1100.
1102 and D1103.

[0183]

[Table 49]

The anode of the SCR 1101 is a node / pin C connected to an externally controlled DC power supply.
It is P18V +. Return node BR- is connected to the cathode of SCR 1101 and capacitor C1100. The input node PF + is connected to the cathode of the Zener diode D1103 and the series resistor R1100, and then to the anode of the SCR 1102 of the SCR. The anode of D1103 is D110
It is connected to two cathodes. The anode of D1102 is connected to the cathode of D1100. The cathode of the SCR 1100 is connected to the gate of the SCR 1101. The anode of D1103 is a series Zener diode [D1102 +
D1100], then capacitor C1100, and then return node B
It is connected to R-. The capacitor [C1200 || R1200] prevents the OVPB from accidentally tripping due to leakage currents and transients. Very high AC line voltage or feedback loop (IPFFB in FIG. 40A)
, 40B FBA, 40C IFB or a component in FIG. 41 FBI), the boost voltage can rise rapidly to a level dangerous to the output switch or output storage capacitor. When the output boost voltage at node PF + rises above 405V, Zener diode D1103,
D1102 and D1100 conduct a small current to the gate of SCR1101,
The CR1101 is latched on. Resistor R1100 provides the holding current for SCR 1101. When the SCR1101 is turned on, the gate current becomes SCR1.
100, resistors R1100 and R1101 limit the gate current,
A holding current is given to the SCR 1100. The gate current to the SCR1100 causes S
CR is turned on, creating a low impedance path from node CP18V + to BR-. This action causes the buffer of the main switch and / or the PWM controller PFA (FIG. 23) or PWFM (FIG. 33) and / or buffer A.
The regulated power to MP (FIG. 29) is removed, so that the main switch is turned off. The converter is configured such that the boost voltage PF + is supplied to the SCR110 through the R1100.
It is held in the OFF state until the holding current of 1 cannot be maintained. Generally, SC
Power must be removed from the system to reset R1101. The minimum holding current of the SCR 1101 is typically 5-10 ma. The operation of OVP1 rapidly limits the boost output voltage to a safe level. This circuit should never operate under normal AC line voltage. By varying the Zener voltage, this subcircuit would also be suitable for use in protecting the load from overvoltage conditions across the output rectifier. Subcircuit OVPl shuts down the converter gently and requires manual intervention to reset the fault.

FIG. 42B is a schematic of the sub-circuit OVP2 of the isolated output overvoltage feedback circuit. Subcircuit OVP2 includes resistors R970, R971, and R972.
, Capacitor C970, Zener diode D970, SCR SCR970,
It consists of a Darlington transistor Q970 and an opto-isolator U970.

[0186]

[Table 50]

The pin OUT + side output of the converter is R972 and Zener diode D9.
It is connected to the cathode of 70. The anode of D970 is a series resistor R970.
Next to the base of Q970 is connected. Resistor R970 sets the maximum base current to Q970. A resistor R971 is connected between the anode of D970 and the return node OUT-. The anode of light emitting diode U970 is connected to resistor R972 and then to OUT +. The cathode of the U970 LED is Q
It is connected to the 980 collector. The emitter of Q980 is the return node OUT-
It is connected to the. Zener diode D960 sets the maximum or trip voltage before transistor Q970 is biased on to supply current to the LEDs of U970. When a voltage higher than the Zener voltage of D970 is applied, a small base current is injected into Q970. Transistor Q970 turns on and the LED inside U970 makes the phototransistor conductive, and pins OVC and OVC
Gives a low impedance to. An external push-pull driver sub-circuit PPG (see FIG. 43) is set by bringing the pin PGEN high and stopping the output stage.
) Is cut off immediately. The sub-circuit OVP2 detects the output voltage and push-pull P
Rapid feedback to FC. When excessive boost voltage occurs, PFC will
The boost voltage is forcibly and automatically lowered.

FIG. 42C is a schematic of a sub-circuit OVP3 of an isolated output overvoltage crowbar network. The sub-circuit OVP3 includes R980, R981, and R9.
82, R983, R984 and R985 resistors, capacitors C980, C9
81 and C982, Zener diode D980, SCR SCR980 and SCR981, Darlington transistor Q980 and optoisolator U980.

[0189]

[Table 51]

The converter output is sensed at pin OUT + with respect to pin OUT−. Pin OUT + is connected to the resistor R982 and the cathode of Zener diode D980. The anode of D980 is Q980 after the series resistor R980.
Connected to the base of. Resistor R980 limits the base current to Q980. A resistor R981 is connected between the anode of D980 and the return node OUT- to provide a diode leakage current path. Light emitting diode U980
Has its anode connected to OUT + through resistor R982. The cathode of the U980 LED is connected to the collector of Q980. The emitter of Q980 is connected to the return node OUT-. Zener diode D960 sets the maximum or trip voltage before transistor Q980 is biased on to supply current to the LEDs of U980. When a voltage higher than the Zener voltage of D980 is applied, a small base current is injected into Q980. The emitter of the opto-isolator U980 is connected to the gate of the SCR981 and [R984 ||
C982] and connected to the return line node BR-. Transistor Q980
Is turned on and the internal LED of the U980 puts the phototransistor in the conducting state, drawing gate current from an external 18V power supply connected to pin CP18V + to the SRC9 of the SRC.
Supply to 81. Circuit [R984 || C982] prevents false firing of SCR981 of SCR. The cathode of the SCR's SCR981 is connected to the gate of the SCR's SCR980 and is connected to the return line BR- through [R985 || C981]. When the SCR SCR981 is turned on and the gate current is a low voltage SCR SC.
Provided to R980. The high voltage boost output is connected to pin PF + and resistor R983 provides the holding current to SCR's SCR981 so that the SCR's SCR981
Hold CR980 on. The SCR's SCR980 has a low holding current,
And it is selected to block the maximum boost voltage across PF +. The anode of the SCR's SRC980 is connected to pin CP18V +. SC
The cathode of the R SRC980 is connected to the return pin BR-. SCR980
Clamps the low voltage power supply CP (FIG. 26) or CPA (FIG. 27). If the low voltage power supply goes down, the gate drive to the main switch is disabled and the converter is turned off. When the main switch Q1 (FIGS. 1, 3, and 4) is turned off, the hold-up capacitor C17 charges toward the peak of the applied AC line. When pin PF + is held near the peak of the line, SCR's SCR981
The SCR's SCR981 will be held on until the AC line power is transferred to the converter. The sub-circuit OVP3 detects the output voltage which is out of the specification,
It shuts down the converter, thereby protecting the load and the converter without creating the destructive currents that OVP (FIG. 42) creates.

FIG. 43 shows a sub circuit PPG of the push-pull oscillator, and FIG. 43 shows a sub circuit PPG of the push-pull oscillator according to the present invention. This example is based on Motorola MC3
A 3025 pulse width modulator IC is used to generate the clock signal that drives the push-pull output stage. The sub circuit PPG includes a two-phase oscillator U14 and a resistor R126.
, R130, R131, R132, R133, R134, R135, R136 and R137, capacitors C143, C136, C139, C140, C141.
And C142.

[0192]

[Table 52]

This implementation uses a Motorola MC33025 pulse width modulator IC to generate the clock signal that drives the push-pull output stage. However, any non-overlapping two-phase fixed frequency generator could be used. Pin 1 of U14 is [
Capacitor C143 || resistor R132] and then to pin 3.
Resistor R134 connects the internal 5.1V reference output of pin 16 of U14 to pin 1. Resistor R in series with R137 from 5.1V reference to retrace node PPG0
Reference numeral 135 forms a voltage divider whose center is connected to pin 2 of U14 to bring pin 2 to 2.55V. A resistor R126 is connected from pin 5 of U14 to the return node PPG0. A resistor R133 is connected from pin 1 of U14 to the return node PPG0. Timing capacitor C142 is connected from pins 6 and 7 of U14 to the return node PPG0. Resistor R126 and capacitor C142 set the operating frequency of the internal oscillator. The timing resistor could be replaced with a JFET, MOSFET, transistor, or similar switching device to provide variable frequency operation. The drain of the transistor will be connected to pin 5. The source is the return node P
It will be connected to PG0. The variable frequency command voltage / current is applied between the gate and the source. The capacitor C141 is connected to the return node PP from the pin 8 of U14.
It is connected to G0. The capacitor C136 is connected from the pin 16 of U14 to the return node PPG0. The capacitor C140 is connected from the pin 15 of U14 to the return node PPG0. The capacitor C139 is the pin 13 of U14.
To the return node PPG0. Resistor R136 is U14 pin 9
To the return node PPG0. Pins 10 and 12 of U14 are connected to the return node PPG0. The external power supply is connected to node / pin PPG + and PWM (pin 15) through resistor R130 connected to the 18V control power supply.
Pulse width modulator) IC is connected to U14. Resistor R131, connected to pin 13 and pin PPG + of U14, powers the totem-poll.
Provide to the output stage. The power return line is connected to the node PPG0. IC U14
About 20-600 KHz with a fixed duty cycle of 35-49.9%
Designed to operate at a constant frequency. Resistors R135, R137, R1
33 configures U14 to operate at maximum pulse width. A non-overlapping two-phase square wave is generated at node PH2 at pin 11 and node PH1 at pin 14 and sent to the speed-up buffer AMP depicted in FIG. The two-phase generator is configured to bring the core bias to zero and prevent the generation of overlapping drive signals that would provide excessive current to the switch. The sub circuit PPG is
It provides the drive for the push-pull switch and allows the NSME to be used efficiently.

FIG. 44 shows the in-rush limited sub-circuit SS1. The sub-circuit SSl includes a diode D447, resistors R441, R442, R443, R444, R445.
And R446, transistor Q446, and capacitors C449 and C442.
And C448.

[0195]

[Table 53]

Node PF + is connected to the positive input of storage capacitor C442 and series resistor R441.
It is connected to + R442. The series resistors R441 and R442 may be replaced by a single element. Series resistors R441 and R442 in parallel provide a safe discharge path for C442. The drain of the transistor Q446 is C442.
Is connected to the negative terminal of R442. The source of Q446 is connected to the return node BR-. The resistor [R443 || R445] is connected in parallel with the source terminal and the drain terminal of Q446. Resistors R443, R444 and R4
45 may be replaced by a single element. Resistor R446 is connected to the rectified line voltage node BR + and the gate of Q446. The cathode of the Zener diode D447 is connected to the gate of Q446. The anode of the Zener diode D447 is connected to the source of Q446. Diode D447
Limits the maximum gate voltage to about 16V. Parallel capacitors C448 and C4
49 is connected in parallel to D447. Resistor R446 and capacitor [C4
48 || C449] causes a delay of (0.05-0.2 seconds) at power-up. This delay range is only given as an example and is not limited to this. At power up, transistor Q446 is in a high impedance state. Therefore, the charging current of the capacitor C442 is [R443 || R444 || R445].
Limited by Referring to interval 441 of oscillograph G44 (FIG. 44A), this is when the transistor is not conducting, ie [R443
|| R444 || R445] provides the charging path and thus limits the inrush current. Significantly reduces stress on line filter and rectifier components during power-up. An exponential decrease in inrush current is observed during interval 441. The soft start interval 444 (FIG. 44A) of the oscillograph GPF + is also noted with a large AC ripple voltage due to series resistance. As the capacitor [C448 || C449] charges through R446, the gate voltage of Q446 increases, turning Q446 “on”. Transistor Q446 turns on during interval 442 (FIG. 44A). This behavior is noted by the increase in charging current 446 and the decrease in AC ripple during interval 445. Similarly, an exponential decrease in charging current is observed during charging of C442 during 442. Transistor Q446 keeps power until power is removed from the converter.
It is kept conductive. During interval 447, the boost converter starts operating. An additional inrush limit is provided by the subcircuit SST (FIG. 33B) so that the output voltage can be brought up smoothly during interval 448.
up). This is indicated by the line current increasing to full load during interval 443. According to the present invention, the inrush limit interval can be set by simply selecting the resistor / capacitor value. This realizes a new auxiliary soft start boost circuit SST. On the other hand, a high power factor is maintained during the start-up interval. A gentle start-up significantly reduces stress on components in high current paths and external fuses. MBTF is enhanced with the addition of minimal components. The invention also allows multiple units to be "hot" plugged in parallel for higher power and / or redundancy. The inrush limiter SSl simply separates the storage capacitor from the main DC bus. Now, "hot swapping" does not cause significant disturbance in the AC or main external DC bus. The unique master less load skaring method shown in Figure 4A allows any number of units to be connected in parallel for high power and high reliability.

FIG. 44A is an oscillograph of line current and output voltage during operation of sub-circuit SS1 (FIG. 44).

FIG. 45 is a schematic diagram of a fast start sub circuit FS1. The fast-start subcircuit FSl includes diodes D452 and D451,
It consists of resistors R451, R452, R453, R454, R455 and R456, transistors Q450 and Q451, and capacitors C452, C453 and C451.

[0199]

[Table 54]

Resistor R451 connects node VCC to the base of transistor Q450 and then to resistor R454 in parallel with capacitor C451 and then to ground or BR.
-Is connected. The anodes of the Zener diodes D451 and D452 are connected to the ground. The cathode of the Zener diode D451 is Q450.
Connected to the emitter. The cathode of the Zener diode D452 is Q4
It is connected to the collector of 50, the gate of Q451, and to node PF + through resistor R452 + R453. Resistor R455 connects from PF + to the drain of Q451. A resistor R456 connects from BR- (ground) to the source of Q451 to form node TP15, and also through a capacitor C452 to the gate of Q451. The capacitor C453 is connected to the nodes TP17 and T
It is connected between P45. When AC power is applied, the voltage at node PF + rises rapidly. Since VCC is zero (no boost), transistor Q450
Is not conducting. Resistor R452 + R453 charges C452, so Q
Forward bias 451. Oscillograph G45 (FIG. 45A) is a plot of the source-gate voltage of Q451. During interval G451, transistor Q451 provides power from PF + to VCC via R455. Interval G452 of oscillograph GVCC shows a rapid rise in VCC. Now all the power is immediately available to the switch buffer AMP (FIG. 29) of the main switch Q1 and the power factor controller PFA, PFB or PFB1. When VCC is 12.6V or higher, the boost converter gradually starts operating. This can be seen by the small AC voltage applied to TP45 during interval G454 (FIG. 45A). During the soft start interval G455, the transistor Q451 supplies power to VCC.
, While the boost operation proceeds rapidly. Once the soft start phase is complete, the rectified AC through D261 and D260 powers the VC
Provide to C. Capacitor C453 couples high frequency (HF) boost energy, thereby rapidly charging C451. When VCC rises above 5V, R451 provides a continuous bias current to C451, thus blocking activation of Q451. When Q450 is forward biased, the gate voltage on Q451 drops. After passing G456, the gate of transistor Q451 is reverse biased with respect to the source, which turns off fast start. If there is an overvoltage condition from a high line condition, or if there is a sudden unloading, the boost activity will cease, so that the AC voltage on TP45 will be removed. This removal of base drive reduces the current in the collector circuit of G450, which results in Q451 being forward biased if VCC falls below 5V. Whenever C451 falls below 5V, power will be provided to VCC. This novel circuit provides control power quickly before the boost operation begins and provides a unique way of maintaining control power during extended overvoltage or no-load periods. This ensures reliable fast start-up and fast recovery under the full range of load and fault conditions.

FIG. 45A is an oscillograph of the operating sub circuit FSl of the sub circuit SS1 (FIG. 45).

The transient protection subcircuit TRN shown in FIG. 46 includes diodes D460 to D462, a bridge rectifier 461, and capacitors C260 and C260.

[0203]

[Table 55]

The line voltage AC plus high-voltage power supply HV1 is connected to the AC voltage terminal of the bridge rectifier 461. The bridge DC + terminal is connected to the node BR +, the anode of the transient protection diodes D460 to D462, and the inductor L in parallel with the capacitor C20.
It is connected to 63. Inductor L63 and capacitor C20 have little to do with the operation of the transient protection circuit and are only shown for completeness. D46
The cathodes of 0-D462 have boost output and storage capacitors C2 and C2.
It is connected to 60. The boost circuit operation is shown in FIGS. 18A, 30, 29, and 2.
4 is shown. Three transient protection diodes are given as an example, but the number is not limited to this. The number of devices is a function of the forward current capacity of the selected device and the expected peak current. The capacitor C260 is a polar electrolytic element, and the one shown here is merely an example, and the present invention is not limited to this. A solid dielectric capacitor may be added in parallel with C260 for low impedance and high frequency performance. During normal operation, transient protection diodes D460-D462
Are reverse biased by the action of the boost. When a high voltage phenomenon HVl is applied to the AC line regardless of polarity, a rectified phenomenon appears at node BR +, which is also shown in oscillograph G463 (FIG. 46B). When the transient voltage exceeds the voltage on C2, D460-D462 are forward biased and energy is transferred to the storage capacitor C260. Conventional technology transient protection is a method of shunting energy into a spark gap or MOV type device. These devices have the disadvantages of limited lifetime, excessive leakage current, catastrophic failure and the like. Proper component selection ensures that extremely large transients are absorbed without exceeding device ratings. Therefore, high reliability is guaranteed with a minimum number of parts and a minimum cost. The invention is applicable to other off-line converters having a storage capacitor (boosted) maintained above the peak line voltage after rectification. This topology will work with either positive or negative reference converters.

The transient protection subcircuit TRNX of FIG. 46A consists of a resistor R468, a bridge rectifier BR468 and a capacitor C468.

[0206]

[Table 56]

The line voltage AC plus high voltage power supply HV1 is connected to the AC voltage terminal of the bridge rectifier BR468. Bridge output positive terminal connects to nodes BR + and C468
Is connected to a resistor R486 in parallel with. The bridge output negative terminal is the node BR-
And resistor R486 in parallel with C468. Sub-circuit TRNX
It may be connected in parallel with any AC or DC load that requires transient protection. When power is applied to the bridge, capacitor C468 charges to the peak voltage. Resistor R468 draws a small amount of charge from C468. Once charged, only a small amount of power is consumed by R468. Graph G462 (Fig. 46b)
During a transient of the type depicted in Figure 3, a high transient voltage is introduced inside capacitor C468, where C468 has a low internal impedance and a high forward current capacity BR.
468 is provided. By directing the transient energy into C468, the magnitude of the transient is limited. The voltage depicted in the oscillographic response G461 results. Auxiliary capacitors may be added to obtain higher voltage, current and / or lower impedance.

FIG. 46B is an oscillograph of converter operation during a high voltage transient. The oscillograph G461 is the output voltage PF +. The oscillograph G462 is the rectified AC line voltage BR +. Oscillograph G463 is the main boost switch Q1
Is the gate voltage to.

FIG. 47 is a signal diagram of power supply automatic load leveling. For clarity in teaching the present invention, FIG. 47 shows only the major elements. Four
The power supplied to 73 enters regulator stage 470. The regulator stage 470 includes a series pass, a variable reactance (AC), a boost, and a buck.
ck), shunt, etc. These are given as examples only and are not limiting. The regulator 470 has an output N47.
Only the control pin 479, which modulates 0 in proportion to the control signal, is required. A power or load sensing element 471 provides an output signal 472 to the load 476 that is proportional to the power provided by 470. The load sensing element is a Hall effect sensor (current)
, A resistor with a differential amplifier, a watt sensor or a current transformer. These are given as examples only and are not limiting. Requirements are signal 4
72 is proportional to the power supplied. Signal 47 for a particular sensor
A simple inverting amplifier (not shown) may be required to provide a level shift of 2, a buffer or a polarity reversal. For example, CP1 (Fig. 2
A VCC derived from the sampling of the boost magnetic element PFTIA (FIG. 4A) via 6A) provides such a signal. The signal 472 (VCC) is shown in FIG.
As shown in 6B, it varies as a function of load. Load leveling is done at node 472.
This is accomplished with the addition of a resistor R476 connected between and 477. Resistor R345 shown in FIG. 4A is the corresponding component of converter ACDCPF1. The power signal 472 is converted to a current through R476 and summing combiner 477.
Is injected into. Summing coupler 477 receives from sensor T473 a current proportional to converter temperature from R473. Thus, converter load distribution is based on power and / or temperature. The load distribution rate is pre-adjusted by a simple resistor ratio to maintain converter regulation. Resistor R479 produces a voltage proportional to the summing current, which is applied to the inverting terminal of comparator 478. Reference voltage V
470 is applied to the non-inverting input of comparator 478. The comparator produces a command signal 479 to modulate the regulator 470. The function of the comparator is to maintain a minimum voltage difference between the comparator input terminals. External power supplies 475 and 475N are connected to output node N474 and common load 476. This configuration allows many converters to be connected in parallel. Signal 472 (VCC) changes as a function of load, as shown in Figure 26B. Load leveling is accomplished with the addition of a resistor R476 connected between nodes 472 and 477. This adjusts the output voltage to decrease as the load increases. This unique feature allows N units to operate in parallel without the typical master-slave connection or master / slave circuitry. Thus, a lightly loaded converter will raise the output voltage, and thus will accept more load. Similarly, a heavily loaded converter will drop the voltage,
It will automatically reduce the load and put it on another converter or power supply. Thus, any number of converters can be connected in parallel for high power or high redundancy applications. In a normal master / slave configuration, loss of the master unit is extremely problematic. In the present invention, in the event of failure or removal of one or more units, the output of the remaining units will increase, thus absorbing the additional load. The optional temperature sensor T473 allows load distribution to be performed as a function of the temperature of the power supply in addition to the load. This minimizes the temperature gradient between multiple units. This automatic load leveling method is based on AC power or DC.
Applicable to power supply. The choice of components sets the nominal operating voltage and load share percentage. This method allows dynamic load distribution without the loss of general master / slave connections, expense and reliability. This method allows the mixing or automatic load balancing of different power supplies, for which it only requires their output voltages to be about the same. This ensures excellent alignment, easy setup, easy configuration, “hot-swap” possibilities and automatic recovery from fault conditions.

FIG. 47A is an alternative signal diagram for power supply automatic load leveling. For clarity to teach the present invention, FIG. 47A shows only major elements. The power supplied to 473 enters regulator stage 470. The regulator stage 471 can be any type of series path, variable reactance (AC), boost, buck, shunt, etc. These are given as examples only and are not limiting. The regulator 470 only needs the control pin 479 to modulate the output N470 proportionally to the control signal. A power or load sensing element 471 provides an output signal 472 to the load 476 that is proportional to the power provided by 470. The load sensing element may be a Hall effect sensor (current), a resistor with a differential amplifier, a watt sensor or a current transformer, these are by way of example only and not by way of limitation. The requirement is that the signal 472 be proportional to the power delivered. A simple inverting amplifier A470 may be required to level shift, buffer or reverse polarity signal 472 for a particular sensor. For example, CP
The VCC derived from the sampling of the boost magnetic element PFTIA (FIG. 4A) via 1 (FIG. 26A) provides such a signal. Signal 472 (VCC)
Varies as a function of load, as shown in FIG. 26B. Amplifier A470 and resistors R478 and R475 provide signal inversion to correct the signal polarity. Automatic load leveling is accomplished with a resistor R47 connected between the node outputs of A470 and 472.
It is carried out with 6 additions. The resistor R345 shown in FIG.
It is the corresponding component of DCPF1. The power signal 472 is converted to a current through R476 and injected into the reference connection N476. Reference voltage V470 is R
It is applied to the non-inverting input of comparator 478 through 470. This will effectively modulate the reference voltage and reduce the converter output voltage with higher power. Summing combiner 477 receives a current from R475 that is proportional to converter output N474. In this way, converter load distribution based on power is possible. A simple resistor ratio determines the proportion of load distribution and output voltage to maintain converter regulation. The resistor R479 generates a voltage proportional to the added current,
This is added to the inverting terminal of the comparator 478. The comparator is a regulator 470.
A command signal 479 is generated to modulate the. The function of this comparator is to maintain a minimum voltage difference between the comparator input terminals. One or more auxiliary external power supplies 475 and 475N are connected to the output node N474,
A common load 476 is directed. This configuration allows many converters to be connected in parallel. This regulates the output voltage to be lower as the load increases. This unique function allows N units to operate in parallel without the usual master / slave connections or master / slave circuits. Thus, a lightly loaded converter will raise the output voltage, and thus will accept more load. Similarly, a heavily loaded converter will drop the voltage, automatically unloading and transferring it to another converter or power supply. Thus, any number of converters can be connected in parallel for high power or high redundancy applications. In a normal master / slave configuration, loss of the master unit is extremely problematic. In the present invention, in case of failure or removal of one or more units,
Increase power to the remaining units to absorb additional load. This automatic load leveling method can be applied to AC or DC power supplies. The choice of components sets the nominal operating voltage and load share percentage. This method allows dynamic load distribution without the general master / slave connection, expense and reliability degradation. This method also allows mixing of different power sources, ie automatic load distribution, allowing different constant voltages. The only requirement is that for a given load, their stand-alone output voltages are about equal. This ensures excellent alignment, easy setup, easy configuration, “hot-swap” possibilities and automatic recovery from fault conditions.

Although the present invention has been described above with reference to the preferred embodiments, there are still many various embodiments that can be included in the scope of the present invention. It is to be inferred that no limitation is intended with respect to the particular embodiments disclosed herein and should not be limited.

[Brief description of drawings]

FIG. 1 is a schematic diagram (1) of an embodiment of a two-stage power factor correction AC / DC isolated output converter of the present invention.

FIG. 1A is a schematic diagram (part 2) of an embodiment of a two-stage power factor correction AC / DC isolated output converter of the present invention.

FIG. 2 is a schematic diagram of an embodiment of a single stage DC / AC converter with an isolated output subcircuit DCAC1.

FIG. 3 is a schematic view of an embodiment of a three-stage AC / DC isolated output converter of the present invention (No. 1).
Is.

FIG. 3A is a schematic diagram of an embodiment of a three-stage AC / DC isolated output converter of the present invention (No. 2).
Is.

FIG. 4 is a schematic diagram of a power factor corrected single stage AC / DC converter subcircuit ACDFPF.

FIG. 4A is a schematic diagram of an alternative power factor controller having a load sharing converter subcircuit ACDFPF1.

FIG. 5 is a graph comparing standard winding currents for saturated and unsaturated magnetic elements of equal inductance.

FIG. 6 is a schematic diagram of a sub-circuit NILBK of a non-isolated low-side switchback converter.

FIG. 7 is a schematic diagram of a preferred embodiment for a tank-coupled single-stage converter subcircuit TCSSC.

FIG. 8 is a schematic diagram of a tank-coupled totem pole converter subcircuit TCTP.

FIG. 9 is a block diagram of a single stage non-isolated DC / DC boost converter NILSBST.

FIG. 10 is a schematic diagram of a two-stage insulation type DC / DC boost control type push-pull converter BSTPP.

FIG. 11 is a graph of permeability as a function of temperature for typical prior art magnetic element materials.

FIG. 12 is a graph of magnetic flux density as a function of temperature for a typical prior art magnetic device material.

FIG. 12A is a graph of magnetic element loss for various magnetic flux densities and operating frequencies typical of prior art magnetic element materials.

[Fig. 13]   It is a graph which shows a standard switching loss.

FIG. 14   6 is a graph showing the lower switching loss of the present invention.

FIG. 15   3 is a graph showing a magnetization curve (BH) for NSME material.

FIG. 15A   3 is a graph of a magnetization curve for H material.

FIG. 16 is a graph of magnetic element loss for various magnetic flux densities and operating frequencies of NSME material.

FIG. 17   3 is a graph of permeability as a function of temperature for NSME.

FIG. 18   FIG. 7 is a schematic representation of a boost NSME subcircuit PFT1.

FIG. 18A   FIG. 9 is a schematic representation of an NSME sub-circuit PFTIA.

FIG. 18B   FIG. 6 is a schematic representation of an unsaturated 2-terminal NSME subcircuit BL1.

FIG. 18C   FIG. 6 is a schematic diagram of an NSME implemented as a distributed magnetic assembly PFT1D.

FIG. 19   It is a schematic diagram of a push-pull NSME sub-circuit PPT1.

FIG. 19A   FIG. 7 is a schematic representation of an alternative push-pull NSME subcircuit PPTIA.

FIG. 20 is a schematic diagram of NSME input transient protection and line filter subcircuit LL.

FIG. 20A   It is a schematic diagram showing an alternative line filter LF.

FIG. 21 is a schematic diagram of an alternative NSME input transient protection and line filter subcircuit LLA.

FIG. 22   It is a schematic diagram of an AC line rectifier subcircuit BR.

FIG. 23   It is a schematic diagram of subcircuit PFA of a power factor controller.

FIG. 24   FIG. 7 is a schematic diagram of an alternative power factor correction boost control element sub-circuit PFB.

FIG. 25   FIG. 6 is a schematic diagram of an output rectifier and filter subcircuit OUTA.

FIG. 25A   FIG. 7 is a schematic diagram of an alternative rectifier subcircuit OUTB.

FIG. 25B   FIG. 7 is a schematic diagram of an alternative final output rectifier and filter subcircuit OUTBB.

FIG. 26   FIG. 9 is a schematic diagram of a floating 18 volt DC control power subcircuit CP.

FIG. 26A   FIG. 7 is a schematic diagram of an alternative 18 volt DC control power subcircuit CP1.

FIG. 26B is a plot of VCC control voltage as a function of output power in watts of operating subcircuit ACDCPF1 (FIG. 4A).

FIG. 27 is a schematic diagram of an alternative floating 18 volt DC push-pull control power subcircuit CPA.

FIG. 28   It is the schematic of the over temperature protection subcircuit OTP.

FIG. 29: High-speed low-impedance buffer sub-circuits AMP, AMP1, AMP2 and A
It is a schematic diagram of MP3.

FIG. 30   It is a schematic diagram of the sub-circuit SN of the snubber of the main switch.

FIG. 30A   FIG. 6 is a schematic diagram of a snubber sub-circuit DSN of a rectifying diode of a main switch.

FIG. 30B   FIG. 9 is a schematic diagram of a sub-circuit SNBB of the snubber of the main switch.

FIG. 31   FIG. 7 is a schematic diagram of an alternative snubber sub-circuit SNA.

FIG. 32   It is a schematic diagram of a sub-circuit SNB of the mirror snubber.

FIG. 33   FIG. 7 is a schematic diagram of a pulse width / frequency modulator sub-circuit PWFM.

FIG. 34 is an oscillograph of node voltage measured during operation of subcircuit PWFM (FIG. 33).

FIG. 35 is an oscillograph of primary tank voltage measured during operation of subcircuit TCTP (FIG. 8).

FIG. 36   FIG. 6 is a schematic diagram of a non-isolated 18 volt DC control power subcircuit REG.

FIG. 37 is a schematic diagram of a sub-circuit HSBK of a non-isolated high side switchback converter.

FIG. 38 is a schematic diagram of an embodiment of a low side buck regulated two stage converter having an isolated push-pull output subcircuit LSBK PP.

FIG. 39. Alternative isolated two-stage low-side switchback converter subcircuit LSBKP
It is a schematic diagram about PBR.

FIG. 40   FIG. 7 is a schematic diagram of an overvoltage feedback sub-circuit IPFFB.

FIG. 40A   FIG. 6 is a schematic diagram of a non-isolated boost output voltage feedback sub-circuit FBA.

FIG. 40B   FIG. 6 is a schematic diagram of an isolated output voltage feedback sub-circuit IFB.

FIG. 40C   FIG. 7 is a schematic diagram of an alternative isolated overvoltage feedback sub-circuit IOVFB.

FIG. 40D is a schematic diagram of an alternative non-isolated boost output voltage feedback sub-circuit FBD.

FIG. 41   FIG. 7 is a schematic diagram of a non-isolated output voltage feedback sub-circuit FBI.

FIG. 41A   FIG. 9 is a schematic diagram of an alternative non-isolated feedback sub-circuit FB2.

FIG. 42   It is a schematic diagram of a sub-circuit OVP for overvoltage protection.

FIG. 42A   FIG. 7 is a schematic diagram of an isolated overvoltage feedback sub-circuit OVP1.

FIG. 42B   It is a schematic diagram of a sub-circuit OVP2 for overvoltage protection.

FIG. 42C   FIG. 9 is a schematic diagram of an isolated overvoltage feedback sub-circuit OVP3.

FIG. 43   FIG. 3 is a schematic diagram of a push-pull oscillator sub-circuit PPG.

FIG. 44 is a schematic diagram of a soft-start / inrush current limit sub-circuit SS1.

44A is an oscillograph of line current and output voltage during operation of subcircuit SS1 (FIG. 44).

FIG. 45   It is a schematic diagram of a sub-circuit FS1 for fast start.

FIG. 45A   FIG. 45 is an oscillograph of the sub circuit FS1 during operation of the sub circuit SS1 (FIG. 44).

FIG. 46   FIG. 7 is a schematic diagram of an alternative transient protection subcircuit TRN.

FIG. 46A is a schematic diagram of an alternative transient protection subcircuit TRNX for external applications.

FIG. 46B   3 is an oscillograph of converter operation during the occurrence of a high voltage transient.

FIG. 47   6 is a signal flow diagram that teaches a load distribution system.

FIG. 47A   7 is an alternative signal flow diagram that teaches a load distribution system.

─────────────────────────────────────────────────── ─── Continued front page    (81) Designated countries EP (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, I T, LU, MC, NL, PT, SE), OA (BF, BJ , CF, CG, CI, CM, GA, GN, GW, ML, MR, NE, SN, TD, TG), AP (GH, GM, K E, LS, MW, MZ, SD, SL, SZ, TZ, UG , ZW), EA (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM), AE, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, CA, CH, C N, CR, CU, CZ, DE, DK, DM, EE, ES , FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, K R, KZ, LC, LK, LR, LS, LT, LU, LV , MA, MD, MG, MK, MN, MW, MX, NO, NZ, PL, PT, RO, RU, SD, SE, SG, S I, SK, SL, TJ, TM, TR, TT, TZ, UA , UG, UZ, VN, YU, ZA, ZW (72) Inventor Woodland, Garth Blair             United States, Colorado 80122, Lito             Luton, South Fairfax strike             REIT 7017 F term (reference) 5H730 AA14 BB25 BB43 BB61 BB86                       CC01 DD04 DD41 EE02 EE03                       FD01 FG05 ZZ16 ZZ17 [Continued summary] A second novel generator implementation is the switching frequency / data Two-phase signal as a function of duty cycle and output voltage Supply and thereby bring about the adjustment. High slewley Drive with low source impedance and low attenuation By providing current to one or more main switches Switching bag that greatly reduces switching loss. By including the FA, higher efficiency can be realized. It

Claims (106)

[Claims] 1. A converter comprising a power factor corrected flyback converter having a feedback circuit, a push-pull converter having a duty cycle, and a full-wave rectification type output circuit, said power factor corrected fly. The buck converter supplies a variable signal to the push-pull converter, the push-pull converter supplies a signal having an operating frequency to the full-wave rectification type output circuit, and the push-pull converter further has an unsaturated region. Magnetic element (NS
ME) containing converter. 2. The converter of claim 1, wherein the NSME has a low magnetic permeability. 3. The NSME further comprises a mixture of 85% by weight of iron, 6% by weight of aluminum and 9% by weight of silicon, whereby a wide motion with respect to the magnetic element is obtained. The converter of claim 2 providing a temperature range. 4. The converter of claim 1, wherein the low magnetic permeability has a range of 1-500. 5. The converter of claim 4, wherein the NSME is an aeromagnetic element. 6. The converter of claim 1, wherein the NSME further has a BH curve characteristic ranging from B = 1 to 10,000 Gauss and H = 1 to 100 Oersted. 7. The converter according to claim 1, further comprising a frequency modulation circuit for optimizing an output signal from the NSME. 8. The converter of claim 7, wherein the push-pull converter further includes a double ended controller having a fixed pulse width. 9. The converter of claim 7, wherein the push-pull converter further includes a double ended controller having a variable frequency. 10. The push-pull converter further comprises a fixed pulse width of 40.
8. The converter of claim 7 including a double ended controller having a duty cycle in the range of% to 60%. 11. The converter of claim 7, wherein the push-pull converter further includes a double-ended controller having an optimization circuit that changes the relationship between pulse width and frequency. 12. The converter of claim 1, wherein the duty cycle is constant. 13. The converter of claim 1, wherein the duty cycle is variable. 14. The converter of claim 10, wherein the duty cycle is 50. 15. The converter of claim 1, further comprising a control circuit for monitoring the bias of the NSME, the control circuit controlling frequency and pulse width to optimize the efficiency of the NSME. 16. The NSME is   An air magnetic element,   Molypermalloy powder (MPP) magnetic element,   A high magnetic flux MPP magnetic element,   A powder magnetic element,   A ferrite magnetic element with a gap,   Tape wound magnetic element,   Cut magnetic element,   Laminated magnetic elements,   An amorphous magnetic element, The converter of claim 1 selected from the group consisting of: 17. A converter including a power factor corrected flyback converter having a feedback circuit, a push-pull converter having a duty cycle, and a full-wave rectification type output circuit, wherein the power factor corrected flyback converter is provided. A buck converter provides a variable signal to the push-pull converter, the push-pull converter provides a signal having an operating frequency to the full-wave rectification type output circuit, and the flyback converter is further provided in an unsaturated region. Operating magnetic element (NS
ME) containing converter. 18. The converter of claim 17, wherein the NSME has a lower magnetic permeability. 19. The NSME further comprises a mixture of 85% by weight of iron, 6% by weight of aluminum and 9% by weight of silicon, thereby providing a wide motion with respect to the magnetic element. 19. The converter of claim 18, which provides a temperature range. 20. The converter of claim 17, wherein the low permeability has a range of 1-500. 21. The converter of claim 20, wherein the NSME is an aeromagnetic element. 22. The converter of claim 17, wherein the NSME further has a B-H curve characteristic ranging from B = 1 to 10,000 Gauss and H = 1 to 100 Oersted. 23. The converter of claim 17, further comprising a frequency modulation circuit that optimizes the output signal from the NSME. 24. The converter of claim 17, wherein the push-pull converter further includes a double ended controller having a fixed pulse width. 25. The converter of claim 17, wherein the push-pull converter further includes a double-ended controller having a variable frequency. 26. The push-pull converter further comprises a fixed pulse width of 40.
18. The converter of claim 17 including a double ended controller having a duty cycle ranging from% to 60%. 27. The converter of claim 17, wherein the push-pull converter further includes a double-ended controller having an optimization circuit that changes the relationship between pulse width and frequency. 28. The converter of claim 17, wherein the duty cycle is constant. 29. The converter of claim 17, wherein the duty cycle is variable. 30. The converter of claim 17, wherein the duty cycle is 50. 31. The converter of claim 17, further comprising a control circuit for monitoring the bias of the NSME, the control circuit controlling frequency and pulse width to optimize the efficiency of the NSME. 32. The NSME is   An air magnetic element,   Molypermalloy powder (MPP) magnetic element,   A high magnetic flux MPP magnetic element,   A powder magnetic element,   A ferrite magnetic element with a gap,   Tape wound magnetic element,   Cut magnetic element,   Laminated magnetic elements,   An amorphous magnetic element, 18. The converter of claim 17, selected from the group consisting of: 33. A power factor corrected flyback converter having a feedback circuit; a push-pull converter having a duty cycle; and a full-wave rectifying output circuit, the power factor corrected flyback converter. The buck converter provides a variable signal to the push-pull converter, the push-pull converter provides a signal having an operating frequency to the full-wave rectification type output circuit, and the push-pull converter is further provided in an unsaturated region. Operating magnetic element (NS
ME) and the flyback converter further comprises a second magnetic element (NSME) operating in the unsaturated region. 34. The converter of claim 33, wherein the NSME has a lower magnetic permeability. 35. The NSME further comprises a mixture of 85% by weight of iron, 6% by weight of aluminum and 9% by weight of silicon, thereby providing a wide motion with respect to the magnetic element. 35. The converter of claim 34, which provides a temperature range. 36. The converter of claim 33, wherein the low magnetic permeability has a range of 1 to 500. 37. The converter of claim 34, wherein the NSME is an aeromagnetic element. 38. The converter of claim 33, wherein the NSME further has a BH curve characteristic ranging from B = 1 to 10,000 Gauss and H = 1 to 100 Oersted. 39. The converter of claim 33, further comprising a frequency modulation circuit that optimizes the output signal from the NSME. 40. The converter of claim 33, wherein the push-pull converter further comprises a double ended controller having a fixed pulse width. 41. The converter of claim 33, wherein the push-pull converter further includes a double-ended controller having a variable frequency. 42. The push-pull converter further comprises a fixed pulse width of 40.
34. The converter of claim 33 including a double ended controller having a duty cycle ranging from% to 60%. 43. The converter of claim 33, wherein the push-pull converter further includes a double-ended controller having an optimization circuit that changes the relationship between pulse width and frequency. 44. The converter of claim 33, wherein the duty cycle is constant. 45. The converter of claim 33, wherein the duty cycle is variable. 46. The converter of claim 33, wherein the duty cycle is 50. 47. The converter of claim 33, further comprising a control circuit for monitoring the bias of the NSME, the control circuit controlling frequency and pulse width to optimize the efficiency of the NSME. 48. The NSME is   An air magnetic element,   Molypermalloy powder (MPP) magnetic element,   A high magnetic flux MPP magnetic element,   A powder magnetic element,   A ferrite magnetic element with a gap,   Tape wound magnetic element,   Cut magnetic element,   A laminated magnetic element,   An amorphous magnetic element, 34. The converter of claim 33 selected from the group consisting of: 49. A voltage regulator having a capacitor, the capacitor comprising a voltage regulator having a voltage derived from a pulse width from the flyback converter, the capacitor boosting across the magnetic element. A converter according to claim 1, wherein the reference is a voltage, the capacitor has a reference voltage for the primary side of the push-pull converter, and the voltage follows a load. 50. Further comprising a power factor control (PFC) circuit, said PFC circuit further comprising a first FET having a switching mode and a buffer, said buffer comprising a second FET and a Darlington transistor. By pair,
A voltage is applied to the gate of the first FET in a first cycle and a voltage is removed from the gate of the first FET in a second cycle, including a pair of the second FET and a Darlington transistor; The converter according to claim 1. 51. A transformer used in a converter of a power supply, comprising: a core; a primary winding wound around the core; and at least one secondary winding wound around the core. And the core includes at least one magnetic element (NSME) operating in an unsaturated region. 52. An input for receiving a variable DC voltage, a sub-circuit of a magnetic element electrically connected to the input, and at least one push-pull output electrically connected to the sub-circuit of the magnetic element. An AC-DC converter including a switch, the sub-circuit of the magnetic element including at least one magnetic element (NSME) operating in an unsaturated region. 53. A power factor corrected flyback converter having a feedback circuit; a forward buck converter; and a push-pull converter having a duty cycle, the power factor corrected flyback converter comprising: Providing an output signal to the forward buck converter, the forward buck converter providing a regulated voltage to the push-pull converter and a full-wave rectifying output circuit, the push-pull converter providing a signal having an operating frequency to the full-wave. A converter for providing a rectified output circuit, wherein each of the flyback converter, the forward buck converter, and the push-pull converter includes at least one magnetic element (NSME) operating in an unsaturated region. . 54. A flyback management circuit combined with a switch for generating a high transient voltage (flyback), comprising a power supply form, a rectifier connected to the switch, and a resistor connected in parallel with the rectifier. A first resistor / capacitor circuit having a capacitor in series with both the rectifier and the switch; a second resistor / capacitor circuit connected between the switch and the output configuration;
And wherein the flyback management circuit returns the high transient voltage to both the output configuration and the power supply configuration. 55. A high voltage protection circuit for a switch in combination with a switch, a power supply, an output configuration and an inductive energy storage element, the flyback rectifier diode being in parallel with a capacitor subcircuit. A fast rectifier and the sub-circuit connected in parallel with the flyback rectifier diode, and wherein a closed switch high voltage spike is first transferred through the sub-circuit and then to the flyback rectifier diode. High voltage protection circuit transferred through. 56. A transient voltage protection circuit comprising a power supply input, an output, first and second input nodes, at least one of said input nodes operating in series in a unsaturated region. An input node having (NSME), a shunt capacitor connected in parallel with the ground, a shunt spark gap connected in parallel with the shunt capacitor, a rectifier connected in parallel with the shunt spark gap in a bridge topology, and the output And a capacitor connected in parallel with the capacitor, and a capacitor connected between the negative side of the output and the ground, a transient voltage protection circuit. 57. The circuit of claim 56, wherein the NSME further has a low magnetic permeability having a range of 1 to 550u. 58. The circuit of claim 57, wherein the NSME further has the characteristic of a substantially vertical BH curve. 59. An improved device of a switch driven gate buffer having an amplifier function, including a high speed N-channel FET, a DC power supply to the drain terminal of the FET, and an input signal to the gate of the FET. The input signal is in turn connected to the base of a fast PNP transistor connected between the source of the FET and ground, the PNP transistor having a base connected to the gate of the FET, the base of the PNP transistor being And a capacitor connected between the PNP transistor collector and the PNP transistor collector, wherein the PNP transistor emitter is connected to the FET source. 60. The improved device of claim 59, further comprising a resistor connected between the source of the FET and the switch gate. 61. The improved device of claim 59, further comprising a shunt resistor connecting the source of the FET to ground. 62. The improved device of claim 59, further comprising a temperature activated switch in series with said DC power source. 63. At least two magnetic elements (NS) operating in an unsaturated region.
ME)), wherein the elements are connected in series with each other. 64. At least two magnetic elements (NS) operating in an unsaturated region.
ME), wherein the elements are connected in parallel with each other. 65. A converter feedback circuit, comprising: a positive input terminal and a negative input terminal connected to the output of the converter; and a circuit output terminal connected to the control circuit of the converter, wherein the positive input A terminal connected in series with the regulating diode and in series with a resistor, further connected to the base of the transistor, the negative input terminal connected to the emitter of the transistor and in turn connected to the base of the transistor Connected to a parallel resistor / capacitor parallel sub-circuit, the transistor having a collector connected to the cathode of an optical isolator, the optical isolator having an anode connected to a series resistor to the positive input terminal. A converter feedback circuit having an output connected to the circuit output terminal. 66. An overvoltage protection sub-circuit comprising: a positive input terminal connected to the output of the converter; a negative input terminal; and at least one Zener diode connected to the positive input terminal. A gate diode having an anode connected to the gate of a first silicon controlled rectifier (SCR) and a further connector to a resistor / capacitor parallel subcircuit connected to the negative input terminal; An SCR of 1 has an anode connected in series with a resistor to the positive input terminal, the negative input terminal has a connection to a second resistor / capacitor sub-circuit, and A resistor / capacitor subcircuit of the second SCR gate and the second SCR gate circuit.
Of the SCR in parallel with the cathode of the second SCR, wherein the gate of the second SCR is connected to the cathode of the first SCR and the cathode of the second SCR is connected to the negative output terminal. An overvoltage protection subcircuit having an anode of the second SCR having a connection to a positive output terminal. 67. A converter including a power factor corrected resonance mode controller, a resonance mode converter having a feedback circuit, a switch drive gate buffer, and a full-wave rectification type output circuit, wherein the power factor controller is Providing a variable frequency signal to the resonant mode converter, the resonant mode converter further comprising a magnetic element (NSME) operating in an unsaturated region, and a positive input terminal and a negative input terminal connected to a power supply, The positive input terminal is connected to the collector of the NPN transistor, the positive input terminal is further connected to the resonant capacitor and the resistor, and further connected to the collector of the optical isolator, and the emitter of the optical isolator is connected to the NPN transistor. Is connected to the base of the It is connected to a first terminal of NSME, the emitter of the NPN transistor and the drain of N-channel FET the NS
A converter connected to the second terminal of ME, the negative input terminal connected to the source of the N-channel FET and the return node of the switch buffer. 68. The converter of claim 67, wherein the NSME further has a low magnetic permeability. 69. The NSME further comprises a mixture of 85% by weight of iron, 6% by weight of aluminum and 9% by weight of silicon to provide a wide operating temperature range for the NSME. The converter of claim 67. 70. The converter of claim 68, wherein the low permeability has a range of 1 to 550u. 71. The converter of claim 67, wherein the NSME is an aeromagnetic element. 72. The converter of claim 67, wherein the NSME further has a B-H curve characteristic ranging from B = 1 to 10,000 Gauss and H = 1 to 100 Oersted. 73. The converter of claim 67, further including a frequency modulation circuit to condition the output signal from the NSME. 74. The resonant mode converter is driven by the power factor corrected resonant mode controller via a variable frequency controller.
7. The converter according to 7. 75. The converter of claim 67, wherein the NSME further comprises distributed magnetic elements. 76. The NSME is   An air magnetic element,   Molypermalloy powder (MPP) magnetic element,   A high magnetic flux MPP magnetic element,   A powder magnetic element,   A ferrite magnetic element with a gap,   Tape wound magnetic element,   Cut magnetic element,   Laminated magnetic elements,   An amorphous magnetic element, 68. The converter of claim 67 selected from the group consisting of: 77. A resonance converter including a power factor corrected resonance mode controller, a resonance mode converter having a feedback circuit, and a full-wave rectification type output circuit, wherein the power factor corrected resonance mode controller is Providing a variable frequency signal to the resonant mode converter, the resonant mode converter further comprising a magnetic element (NSME) operating in an unsaturated region, and a positive input terminal and a negative input terminal connected to a power supply. The positive input terminal is connected to the collector of an NPN transistor, the NPN transistor has an emitter connected to the emitter of the PNP transistor and the first terminal of the NSME, and the negative input terminal is a resonance capacitor. The base of the PNP transistor is connected to the collector of the PNP transistor, A resonance converter in which the base of the NPN transistor and the output of the power factor corrected resonance mode controller are connected, and the resonance capacitor is further connected to a second terminal of the NSME. 78. The converter of claim 77, wherein the NSME further has a low magnetic permeability. 79. The NSME further comprises a mixture of 85% by weight of iron, 6% by weight of aluminum and 9% by weight of silicon to provide a wide operating temperature range for the magnetic element. 79. The converter of claim 77. 80. The converter of claim 78, wherein the low permeability has a range of 1 to 550. 81. The converter of claim 77, wherein the NSME is an aeromagnetic element. 82. The converter of claim 77, wherein the NSME further has a BH curve characteristic ranging from B = 1 to 10,000 Gauss and H = 1 to 100 Oersted. 83. The converter of claim 77, further comprising a frequency modulation circuit to condition the output signal from the NSME. 84. The converter of claim 77, wherein the resonant mode converter is driven by a power factor corrected resonant mode controller via a variable frequency controller. 85. The converter of claim 77, wherein the NSME further comprises distributed magnetic elements. 86. The NSME is   An air magnetic element,   Molypermalloy powder (MPP) magnetic element,   A high magnetic flux MPP magnetic element,   A powder magnetic element,   A ferrite magnetic element with a gap,   Tape wound magnetic element,   Cut magnetic element,   Laminated magnetic elements,   An amorphous magnetic element, 78. The converter of claim 77 selected from the group consisting of: 87. A resonant sub-circuit in which a resonant relationship is formed between the magnetic element and the capacitor by including a capacitor having a connection to the magnetic element, the magnetic element further being unsaturated. A resonant subcircuit including a magnetic element (NSME) operating in a region. 88. The sub-circuit of claim 87, further connecting to a filter circuit reduces the mass, complexity and cost of the filter circuit for a given filter characteristic. 89. The converter of claim 88, wherein the NSME further has a low magnetic permeability. 90. The NSME further comprises a mixture of 85% by weight of iron, 6% by weight of aluminum and 9% by weight of silicon to provide a wide operating temperature range for the magnetic element. 90. The converter of claim 89 provided. 91. The converter of claim 89, wherein said low magnetic permeability has a range of 1 to 500. 92. The converter of claim 89, wherein the NSME is an aeromagnetic element. 93. The converter of claim 89, wherein the NSME further has a B-H curve characteristic ranging from B = 1 to 10,000 Gauss and H = 1 to 400 Oersted. 94. The sub-circuit of claim 88, wherein the connections are parallel connections. 95. The sub-circuit of claim 88, wherein the connection is a series connection. 96. In a power conversion circuit having an energized magnetic element, an improvement of the circuit is that the magnetic element is a magnetic element operating in an unsaturated region (NSME), and the magnetic element has a natural frequency. And that the energizing power is substantially matched to the natural frequency, thereby providing higher power density, improved thermal stability, and higher conversion efficiency. Is a power conversion circuit. 97. The converter of claim 96, wherein the NSME further has a low magnetic permeability. 98. The NSME further comprises a mixture of 85% by weight of iron, 6% by weight of aluminum and 9% by weight of silicon, thereby providing a wide operating temperature range for the magnetic element. 98. The converter of claim 97, wherein a range is provided. 99. The converter of claim 97, wherein said low magnetic permeability has a range of 1 to 500. 100. The converter of claim 97, wherein the NSME is an aeromagnetic element. 101. The converter of claim 97, wherein the NSME further has a BH curve characteristic ranging from B = 1 to 10,000 Gauss and H = 1 to 400 Oersted. 102. A transient voltage protection circuit comprising a rectifier sub-circuit and a capacitor / resistor parallel circuit having a path to ground, resulting in a capacitor passive mode when the line voltage is normal. And a transient voltage protection circuit in which the current flows through the capacitor due to the low impedance mode in the rectifier when the line voltage is slightly exceeded. 103. A method of preventing an excessive inrush current from flowing into a capacitor at a DC output of a power converter, wherein a series resistor is provided for the output capacitor, and a switch is provided at both ends of the series resistor. And providing a control signal on the operation of the power converter to close the switch and shunt the series resistor to ground to cause controlled charging of the output capacitor. How to include. 104. An apparatus for maintaining approximately equal load levels among N power supply units in a parallel multiple power supply topology for load distribution, redundancy and hot swap power supplies, said power supply units. For each (N ₁ , N ₂ , N _X ) of the above, a part of the output voltage is supplied to a comparison circuit having a comparator for comparing a part of the output voltage with a reference voltage, An output signal current load measuring circuit is provided for each, and the output from the measuring circuit forms an addition signal together with a part of the output voltage, so that the N power supply units have substantially the same power. A device for which distribution is provided. 105. An apparatus for maintaining approximately equal load levels among N power supply units in a parallel multiple power supply topology for load distribution, redundancy and hot swap power supplies, said power supply units. For each (N ₁ , N ₂ , N _X ) of the above, a part of the output voltage is supplied to a comparison circuit having a comparator for comparing a part of the output voltage with a reference voltage, An output signal current load measuring circuit is provided for each of them, and an output from the measuring circuit forms a bias current with respect to the reference voltage, so that a substantially equal power distribution is achieved among the N power supply units. Will be provided with the device. 106. An apparatus for speeding up start-up of a power supply control circuit in a power converter in a voltage reduction and high temperature circuit start-up environment, the apparatus having the same ground potential as the ground potential for the control circuit, A rectification voltage source that is independent of the control circuit and has a function of starting up the power supply control circuit first, a switch that connects a part of the rectification voltage source to the power supply control circuit, and a function of turning off the switch. An apparatus for providing a fast start circuit with little energy dissipation under normal operating conditions by including a detection circuit that determines an operating mode of the power converter.