JP2003347711A - Printed circuit board - Google Patents
Printed circuit boardInfo
- Publication number
- JP2003347711A JP2003347711A JP2002221338A JP2002221338A JP2003347711A JP 2003347711 A JP2003347711 A JP 2003347711A JP 2002221338 A JP2002221338 A JP 2002221338A JP 2002221338 A JP2002221338 A JP 2002221338A JP 2003347711 A JP2003347711 A JP 2003347711A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- resin
- printed circuit
- substrate
- solder mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明はプリント回路板の構
造に係り、特に固定ソルダーマスク(solder mask)を
備えるプリント回路板(printed circuit board)に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a printed circuit board, and more particularly, to a printed circuit board having a fixed solder mask.
【0002】[0002]
【従来の技術】プリント回路板上に固定ソルダーマスク
を配設する技術に関しては、現在比較的先進的なものと
して、米国特許第5,626,774号が開示してい
る、プリント印刷回路板に含まれた樹脂に適合する樹脂
をソルダーマスクの材質に使用し、および材質をいかに
してプリント回路版に配設し固定ソルダーマスクとする
かの技術がある。技術によって作製したソルダーマスク
は、従来のソルダーマスクにおける厚さが不均一でガラ
ス転移温度(Tg)が低く、プリント回路版上に溶接す
る回路部分が精確に表されないといった問題を解決した
が、ソルダーマスクの厚さをどのように選択するか、ソ
ルダーマスク全層が備えるべき厚さの均一性はどれくら
いが適当かといった点には触れていない。2. Description of the Related Art As a technique for disposing a fixed solder mask on a printed circuit board, US Pat. No. 5,626,774 discloses a relatively advanced technique. There is a technique in which a resin compatible with the contained resin is used for the material of the solder mask, and how the material is disposed on the printed circuit board to form a fixed solder mask. Solder masks manufactured by the technology have solved the problem that the thickness of the conventional solder mask is not uniform, the glass transition temperature (Tg) is low, and the circuit portion to be welded on the printed circuit board is not accurately represented. It does not mention how to select the thickness of the mask or how much the thickness uniformity of all layers of the solder mask should be.
【0003】[0003]
【発明が解決しようとする課題】ソルダーマスクの厚さ
が不均一であると、プリント回路版は後続のパッキング
過程において、ソルダーマスク表面とパッケージダイと
の間に間隙が発生し、樹脂のはみ出しが生じるほか、前
記従来のプリント回路版ではソルダーマスク表面の粗さ
が足りないため、後続のパッキング過程でソルダーマス
ク表面とダイ材料との間がしっかりと結合されず、ダイ
材料が剥離する現象が生じがちであった。If the thickness of the solder mask is not uniform, the printed circuit board will have a gap between the surface of the solder mask and the package die during the subsequent packing process, and the resin will protrude. In addition, in the conventional printed circuit board, since the surface of the solder mask is insufficient in roughness, the solder mask surface and the die material are not firmly connected in the subsequent packing process, and a phenomenon that the die material is peeled off occurs. I tended to.
【0004】さらに、従来のプリント回路版において、
ソルダーマスクで被覆されていない回路は、配線が密に
なりすぎるとイオン移動(ion migration)が往々にし
て発生し、換言すれば、これにより回路版の配線密度が
低減されていた。また従来プリント回路版の上下層回路
を接続する中空のめっきスルーホールには空気が充填す
るため、後続のパッケージ過程、特に加熱過程において
パッケージの全体構造に好ましくない影響をもたらして
いた。Further, in a conventional printed circuit board,
In circuits not covered with a solder mask, ion migration often occurs when the wiring is too dense, in other words, this has reduced the wiring density of the circuit board. In addition, since the hollow plating through holes connecting the upper and lower layer circuits of the printed circuit board are filled with air, the subsequent package process, particularly the heating process, has an unfavorable effect on the overall structure of the package.
【0005】本発明の主な目的は、様々な方式の半導体
チップのパッキングに適合可能な厚さの固定ソルダーマ
スクを備えるプリント回路板を提供することにある。本
発明の次なる目的は、回路板を半導体チップパッケージ
の基材とする際に、パッケージ全体を被覆するためのダ
イ材料と緊密に結合し、ダイ過程で樹脂のはみ出しが発
生しないプリント回路板を提供することにある。本発明
のさらなる目的は、導電回路の配設密度を高めるプリン
ト回路板を提供することにある。SUMMARY OF THE INVENTION It is a primary object of the present invention to provide a printed circuit board having a fixed solder mask having a thickness suitable for packing various types of semiconductor chips. The next object of the present invention is to provide a printed circuit board that is tightly bonded to a die material for covering the entire package when the circuit board is used as a base material of a semiconductor chip package, and that does not cause resin to protrude during the die process. To provide. It is a further object of the present invention to provide a printed circuit board that increases the density of conductive circuits.
【0006】[0006]
【課題を解決するための手段】上記目的を達成するため
に、本発明の請求項記載のプリント回路板は、第1の樹
脂材料から作製され、天井部表面および底部表面を有
し、天井部表面には第1の導電回路が配設され、回路に
は被遮蔽部分と露出部分とがある基板と、第2の樹脂か
ら作製され、第2の樹脂の熱膨張係数が実質的に第1の
樹脂と同じで、ソルダーマスクが第1の導電回路の被遮
蔽部分を被覆しおよび平らな外表面を形成する方式で基
板の天井部表面上に配設されている第1のソルダーマス
クとを備え、ソルダーマスクの厚さの均一度は毎500
mmを一つの長さの測量単位としたとき、単位内におい
てソルダーマスクの最大厚さと最小厚さの差は10μm
以下となる。In order to achieve the above object, a printed circuit board according to the present invention is made of a first resin material, has a ceiling surface and a bottom surface, and has a ceiling portion. A first conductive circuit is provided on the surface, and the circuit is made of a substrate having a shielded portion and an exposed portion, and a second resin, and the thermal expansion coefficient of the second resin is substantially the first. And a first solder mask disposed on the ceiling surface of the substrate in such a manner that the solder mask covers the shielded portion of the first conductive circuit and forms a flat outer surface. The thickness uniformity of the solder mask is 500
When mm is a unit of measurement for one length, the difference between the maximum thickness and the minimum thickness of the solder mask in the unit is 10 μm
It is as follows.
【0007】本発明の請求項記載のプリント回路板のも
う一つの特徴は、第1の導電回路には被遮蔽部分と露出
部分とがあって、露出部分の回路が底部と天井部を備え
ていることである。第1のソルダーマスクには、第1の
領域と第2の領域があり、第1の領域が第1の導電回路
の被遮蔽部分を被覆しおよび平らな外表面を形成する方
式で基板の天井部表面上に配設され、第2の領域が導電
回路の露出部分の回路底部を完全に被覆している。Another feature of the printed circuit board according to the present invention is that the first conductive circuit has a shielded portion and an exposed portion, and the exposed portion circuit has a bottom portion and a ceiling portion. It is that you are. The first solder mask has a first region and a second region, the first region covering the shielded portion of the first conductive circuit and forming a flat outer surface. The second region is disposed on the outer surface, and the second region completely covers the circuit bottom of the exposed portion of the conductive circuit.
【0008】[0008]
【発明の実施の形態】本発明の詳細な構造と効果を明確
にするため、次に実施例にもとづき図面を参照して説明
する。まず、図1および図2を参照すると、本発明の第
1実施例におけるプリント回路版10には、基板20お
よび2つのソルダーマスク40が備わっている。BEST MODE FOR CARRYING OUT THE INVENTION In order to clarify the detailed structure and effects of the present invention, a description will be given of an embodiment with reference to the drawings. First, referring to FIGS. 1 and 2, a printed circuit board 10 according to a first embodiment of the present invention includes a substrate 20 and two solder masks 40.
【0009】基板20は繊維材料および含浸樹脂から作
製されており、繊維材料はガラス繊維でよく、樹脂材料
はエポキシ樹脂(epoxy resin)、ポリアミド樹脂(pol
yamide resin)、シアン化樹脂(cyanoester resin)な
どの樹脂から選択する。基板20には天井面22および
底面24があって、天井面と底面上にはそれぞれ所定の
パターンを呈する導電回路26が配設され、導電回路2
6には被遮蔽部分261と露出部分263が備わってい
る。各導電回路には複数の基板20を貫通するめっきス
ルーホール28が連通している。The substrate 20 is made of a fiber material and an impregnated resin, the fiber material may be glass fiber, and the resin material is an epoxy resin, a polyamide resin (pol
Select from resins such as yamide resin) and cyanoester resin. The substrate 20 has a ceiling surface 22 and a bottom surface 24, and a conductive circuit 26 having a predetermined pattern is disposed on each of the ceiling surface and the bottom surface.
6 has a shielded portion 261 and an exposed portion 263. A plated through hole 28 penetrating the plurality of substrates 20 communicates with each conductive circuit.
【0010】各ソルダーマスク40は、熱膨張係数が基
板20に含まれる樹脂の熱膨張係数と接近しているかま
たは同じである樹脂材料から作製され、基板20の天井
面22と底面24に貼付され、各導電回路26の被遮蔽
部分261を完全に被覆するとともに、各めっきスルー
ホール28の中空部分を充填しており、即ち、各めっき
スルーホール28中心の充填物281は、2つのソルダ
ーマスク40と同じ材質であるとともに一体に形成され
ている。Each solder mask 40 is made of a resin material whose coefficient of thermal expansion is close to or equal to the coefficient of thermal expansion of the resin contained in the substrate 20, and is attached to the ceiling surface 22 and the bottom surface 24 of the substrate 20. The shielded portion 261 of each conductive circuit 26 is completely covered, and the hollow portion of each plated through hole 28 is filled. That is, the filler 281 at the center of each plated through hole 28 has two solder masks 40. And are integrally formed.
【0011】ソルダーマスク40を基板の表面に貼付す
るときには、まずアルミ箔401を用意して、その一つ
の面上に半固化(B-staged)のエポキシ樹脂層402を
塗布してから、アルミ箔を基板の表面上に貼付し、エポ
キシ樹脂層402がアルミ箔401と基板20の表面と
を介するようにし、10〜40kgw/cm2の圧力お
よび140〜185℃の温度で前記の組成物を1.5〜
3時間圧し、エポキシ樹脂層402を固化させて、各め
っきスルーホール28を塞いでおよび基板20の表面に
密着させる(図2A参照)。When the solder mask 40 is to be adhered to the surface of the substrate, an aluminum foil 401 is first prepared, and a semi-solidified (B-staged) epoxy resin layer 402 is applied on one surface thereof. the attached on the surface of the substrate, the epoxy resin layer 402 so as to through the surface of the aluminum foil 401 and the substrate 20, the above composition at a temperature of 10~40kgw / cm 2 pressure and one hundred and forty to one hundred and eighty-five ° C. 1 .5-
Pressure is applied for 3 hours to solidify the epoxy resin layer 402, close each plating through hole 28, and make close contact with the surface of the substrate 20 (see FIG. 2A).
【0012】次いで、アルミ箔表面にフォトレジスト
(photo-resist)層403を塗布し(図2B参照)、フ
ィルム(図には未表示)を配してフォトレジスト層40
3を露光し、フォトレジスト層403を導電回路26の
遮蔽部分に対応する位置で現像させ、続けて適当な溶剤
で未現像部分のフォトレジスト層およびアルミ箔をそれ
ぞれ除去し、導電回路の露出部分に対応するソルダーマ
スクを外に露出させる(図2C参照)。さらに適当な化
学溶剤で残りのフォトレジスト層を除去する(図2D参
照)。Next, a photoresist (photo-resist) layer 403 is applied to the surface of the aluminum foil (see FIG. 2B), and a film (not shown in the figure) is disposed to form a photoresist layer 40.
3 is exposed, and the photoresist layer 403 is developed at a position corresponding to the shielded portion of the conductive circuit 26. Subsequently, the undeveloped portion of the photoresist layer and the aluminum foil are respectively removed with an appropriate solvent, and the exposed portion of the conductive circuit Is exposed outside (see FIG. 2C). Further, the remaining photoresist layer is removed with an appropriate chemical solvent (see FIG. 2D).
【0013】続けて、プラズマエッチング法またはレー
ザーによって、導電回路の露出部分上方に対応するソル
ダーマスクを除去し、基板20上の導電回路26の露出
部分263を外に露出させる(図2E参照)。最後に、
適当な溶剤で残りのアルミ箔を除去して、ソルダーマス
ク40の製造工程を完了する(図2F参照)。Subsequently, the corresponding solder mask above the exposed portion of the conductive circuit is removed by a plasma etching method or a laser to expose the exposed portion 263 of the conductive circuit 26 on the substrate 20 (see FIG. 2E). Finally,
The remaining aluminum foil is removed with an appropriate solvent to complete the manufacturing process of the solder mask 40 (see FIG. 2F).
【0014】ソルダーマスク40の厚さは2〜200μ
mの間とすることができ、極めて優れた平坦度を備えさ
せ、詳しくは、毎500mmを一つの長さの測量単位と
したときに、ソルダーマスク40の最大厚さtmaxと最
小厚さtminの差が10μm以下になるように制御し
(図3参照)、さらに、ソルダーマスクは極めて優れた
マイクロラフネス(micro-roughness)を備えており、
通常はそのRz値が0.5〜10μmの間となる。The thickness of the solder mask 40 is 2 to 200 μm.
m, and has a very good flatness. More specifically, when 500 mm is taken as one length measurement unit, the maximum thickness t max and the minimum thickness t max of the solder mask 40 are set. The difference in min is controlled so as to be 10 μm or less (see FIG. 3), and the solder mask has extremely excellent micro-roughness.
Usually, the Rz value is between 0.5 and 10 μm.
【0015】従って、プリント回路版にフリップチップ
パッケージを配する際には、厚さが大きいソルダーマス
クを使用すると、チップ60をソルダーマスク40の表
面に密着させることが可能であり、両者間に何らかの物
質を充填させる必要はなくなる(図4参照)。また本発
明の第2実施例として、プリント回路版にワイアボンデ
ィング式パッケージを配する際には、薄いソルダーマス
クを用いると同時に、極めて少量の接着剤70でチップ
をしっかりとプリント回路板上に貼付し、こうすること
によりパッケージ全体の厚さを大幅に減少させることが
可能になる(図5参照)。Therefore, when a flip-chip package is arranged on a printed circuit board, if a solder mask having a large thickness is used, the chip 60 can be brought into close contact with the surface of the solder mask 40, and somehow can be provided between the two. There is no need to fill material (see FIG. 4). As a second embodiment of the present invention, when arranging a wire bonding type package on a printed circuit board, a thin solder mask is used, and at the same time, a chip is firmly attached to the printed circuit board with a very small amount of adhesive 70. However, this makes it possible to greatly reduce the thickness of the entire package (see FIG. 5).
【0016】また、図6に示す本発明の第3実施例のよ
うに、ソルダーマスク40を配設するときには、ソルダ
ーマスクに導電回路の被遮蔽部分261を完全に被覆す
るための第1の領域401および導電回路の露出部分2
63の底部265だけを被覆するための第2の領域40
2の2つの領域を備えさせ、これによって導電回路の露
出部分と基板20との結合力を向上させる。このほか、
露出部分66の底部661周縁が絶縁のソルダーマスク
402によって包囲されているため、露出した隣接する
回路間でイオン移動が発生しにくい。従って、各回路の
ピッチ(pitch)をさらに縮小し、換言すれば、プリン
ト回路板の配線密度をさらに高めることが可能になる。When the solder mask 40 is provided as in the third embodiment of the present invention shown in FIG. 6, a first region for completely covering the shielded portion 261 of the conductive circuit on the solder mask is provided. 401 and exposed part 2 of conductive circuit
A second region 40 for covering only the bottom 265 of 63
2 to improve the bonding strength between the exposed portion of the conductive circuit and the substrate 20. other than this,
Since the periphery of the bottom portion 661 of the exposed portion 66 is surrounded by the insulating solder mask 402, ion migration hardly occurs between exposed adjacent circuits. Therefore, the pitch of each circuit can be further reduced, in other words, the wiring density of the printed circuit board can be further increased.
【図1】本発明の第1実施例によるプリント回路板を示
す断面図である。FIG. 1 is a sectional view showing a printed circuit board according to a first embodiment of the present invention.
【図2】本発明の第1実施例によるプリント回路板のソ
ルダーマスクを基板上に配設する製造過程を示した断面
図A〜Fである。FIGS. 2A to 2F are cross-sectional views illustrating a manufacturing process of disposing a solder mask of a printed circuit board on a substrate according to a first embodiment of the present invention;
【図3】図1におけるA部分の拡大図である。FIG. 3 is an enlarged view of a portion A in FIG.
【図4】本発明の第1実施例によるプリント回路板にお
いて、フリップチップパッケージを用いた状態を示す断
面図である。FIG. 4 is a cross-sectional view illustrating a state in which a flip-chip package is used in the printed circuit board according to the first embodiment of the present invention.
【図5】本発明の第2実施例によるプリント回路板にお
いて、ワイアボンディング式チップパッケージを用いた
状態を示す断面図である。FIG. 5 is a cross-sectional view showing a printed circuit board according to a second embodiment of the present invention using a wire bonding type chip package.
【図6】本発明の第3実施例におけるプリント回路板に
おいて、導電回路の露出部分とソルダーマスクとの関係
を示す断面図である。FIG. 6 is a sectional view showing a relationship between an exposed portion of a conductive circuit and a solder mask in a printed circuit board according to a third embodiment of the present invention.
10 プリント回路板 20 基板 22 天井面 24 底面 26 導電回路 40 ソルダーマスク 261 遮蔽部分 263 露出部分 10. Printed circuit board 20 substrates 22 Ceiling surface 24 bottom 26 Conductive circuit 40 Solder mask 261 Shielding part 263 Exposed part
フロントページの続き Fターム(参考) 5E314 AA32 AA36 BB06 BB12 CC15 DD07 FF05 FF17 GG05 GG11 GG17 GG24 5E317 AA24 BB02 BB03 CC31 CD23 CD27 GG14 GG16 Continuation of front page F term (reference) 5E314 AA32 AA36 BB06 BB12 CC15 DD07 FF05 FF17 GG05 GG11 GG17 GG24 5E317 AA24 BB02 BB03 CC31 CD23 CD27 GG14 GG16
Claims (18)
面および底部表面を有し、天井部表面には第1の導電回
路が配設され、回路には被遮蔽部分と露出部分とがある
基板と、 第2の樹脂から作製され、第2の樹脂の熱膨張係数は実
質的に第1の樹脂と同じであり、第1の導電回路の被遮
蔽部分を被覆しおよび平らな外表面を形成する方式で基
板の天井部表面上に配設される第1のソルダーマスクと
を備えるプリント回路板であって、 ソルダーマスクが毎500mmを一つの長さの測量単位
としたとき、その最大厚さと最小厚さとの差が10μm
以下であることを特徴とするプリント回路板。1. A first resin material, having a ceiling surface and a bottom surface, a first conductive circuit disposed on the ceiling surface, and the circuit includes a shielded portion and an exposed portion. A substrate, made of a second resin, having a coefficient of thermal expansion substantially the same as that of the first resin, covering the shielded portion of the first conductive circuit and having a flat outer surface And a first solder mask disposed on the ceiling surface of the substrate in a method of forming a printed circuit board. 10μm difference between thickness and minimum thickness
A printed circuit board characterized by the following.
回路に被遮蔽部分と露出部分とが備わっているプリント
回路板であって、 前記第2の樹脂から作製され、同様に前記第2の導電回
路の被遮蔽部分を被覆しおよび平らな外表面を形成する
方式で前記基板の底面上に配設される第2のソルダーマ
スクを備えることを特徴とする請求項1記載のプリント
回路板。2. A second conductive circuit is provided on a bottom surface of the substrate,
A printed circuit board having a shielded portion and an exposed portion in a circuit, the printed circuit board being made of the second resin, also covering the shielded portion of the second conductive circuit and providing a flat outer surface. The printed circuit board according to claim 1, further comprising a second solder mask disposed on a bottom surface of the substrate in a forming manner.
有し、前記基板の天井部表面と底表面とを貫通し、前記
第1の導電回路と前記第2の導電回路とを電気的に接続
し、各めっきスルーホール内にそれぞれ充填物を備え、
各充填物の材質が各ソルダーマスクの材質と同じである
ことを特徴とする請求項2記載のプリント回路板。3. The substrate has a plurality of plated-through holes, penetrates a ceiling surface and a bottom surface of the substrate, and electrically connects the first conductive circuit and the second conductive circuit. And, each with a filler in each plating through hole,
3. The printed circuit board according to claim 2, wherein the material of each filler is the same as the material of each solder mask.
μmであることを特徴とする請求項1記載のプリント回
路板。4. The solder mask has a thickness of 2 to 200.
The printed circuit board according to claim 1, wherein the thickness is μm.
るRz値が0.5〜10μmであることを特徴とする請
求項1記載のプリント回路板。5. The printed circuit board according to claim 1, wherein an Rz value, which is a roughness of an outer surface of the solder mask, is 0.5 to 10 μm.
脂であることを特徴とする請求項1記載のプリント回路
板。6. The printed circuit board according to claim 1, wherein said first and second resins are epoxy resins.
樹脂であることを特徴とする請求項1記載のプリント回
路板。7. The printed circuit board according to claim 1, wherein said first and second resins are polyamide resins.
化樹脂であることを特徴とする請求項1記載のプリント
回路板。8. The printed circuit board according to claim 1, wherein said first and second resin materials are cyanide resins.
面および底部表面を備え、天井部表面には第1の導電回
路が配設され、回路には被遮蔽部分と露出部分とがあ
り、露出部分の回路には底部と天井部とが備わっている
基板と、 第2の樹脂から作製され、第2の樹脂の熱膨張係数が実
質的に第1の樹脂と同じであり、第1の領域と第2の領
域とを有し、第1の領域は第1の導電回路の被遮蔽部分
を被覆しおよび平らな外表面を形成する方式で前記基板
の天井部表面上に配設されており、第2の領域が導電回
路の露出部分の回路底部を完全に被覆している第1のソ
ルダーマスクと、 を備えることを特徴とするプリント回路板。9. A first resin material, having a ceiling surface and a bottom surface, a first conductive circuit disposed on the ceiling surface, and the circuit having a shielded portion and an exposed portion. A substrate having a bottom and a ceiling in the circuit of the exposed portion; and a second resin, wherein the second resin has substantially the same thermal expansion coefficient as the first resin. And a second region, the first region being disposed on the ceiling surface of the substrate in a manner to cover the shielded portion of the first conductive circuit and form a flat outer surface. A first solder mask, wherein the second region completely covers the circuit bottom of the exposed portion of the conductive circuit.
域が毎500mmを一つの長さの測量単位とするとき、
その最大厚さと最小厚さとの差が10μm以下であるこ
とを特徴とする請求項9記載のプリント回路板。10. When the first region of the first solder mask has a length of 500 mm as a unit of measurement,
10. The printed circuit board according to claim 9, wherein a difference between the maximum thickness and the minimum thickness is 10 μm or less.
配設され、回路に被遮蔽部分と露出部分とがあり、露出
部分の回路には底部と天井部とがあるプリント回路板で
あって、前記第2の樹脂から作製され、第1の領域と第
2の領域があり、第1の領域は第2の導電回路の被遮蔽
部分を被覆しおよび平らな外表面を形成する方式で前記
基板の底部表面上に配設され、第2の領域が導電回路露
出部分の回路底部を完全に被覆していることを特徴とす
る請求項9記載のプリント回路板。11. A printed circuit board having a second conductive circuit disposed on a bottom surface of the substrate, the circuit having a shielded portion and an exposed portion, and the exposed portion of the circuit having a bottom portion and a ceiling portion. There is a first region and a second region made of the second resin, wherein the first region covers a shielded portion of the second conductive circuit and forms a flat outer surface. 10. The printed circuit board according to claim 9, wherein the second region is disposed on a bottom surface of the substrate, and the second region completely covers a circuit bottom of the exposed portion of the conductive circuit.
ルーホールがあって、前記基板の天井部表面と底部表面
とを貫通しており、前記第1の導電回路と前記第2の導
電回路とを電気的に接続し、各めっきスルーホール内に
はそれぞれ充填物があり、各充填物の材質が前記ソルダ
ーマスクの材質と同じであることを特徴とする請求項1
1記載のプリント回路板。12. The substrate further includes a plurality of plated through holes, which penetrate through a ceiling surface and a bottom surface of the substrate, wherein the first conductive circuit and the second conductive circuit 2. A material is electrically connected to each of the plated through holes, and a filler is provided in each of the plated through holes, and a material of each of the fillers is the same as a material of the solder mask.
The printed circuit board according to claim 1.
さが2〜200μmの間であることを特徴とする請求項
9記載のプリント回路板。13. The printed circuit board according to claim 9, wherein the thickness of the first region of the solder mask is between 2 and 200 μm.
表面の粗さであるRz値が0.5〜10μmの間である
ことを特徴とする請求項9記載のプリント回路板。14. The printed circuit board according to claim 9, wherein an Rz value, which is a roughness of an outer surface of the first region of the solder mask, is between 0.5 and 10 μm.
ポキシ樹脂であることを特徴とする請求項9記載のプリ
ント回路板。15. The printed circuit board according to claim 9, wherein the first resin and the second resin are epoxy resins.
リアミド樹脂であることを特徴とする請求項9記載のプ
リント回路板。16. The printed circuit board according to claim 9, wherein said first resin and said second resin are polyamide resins.
材料がシアン化樹脂であることを特徴とする請求項9記
載のプリント回路板。17. The printed circuit board according to claim 9, wherein said first resin material and said second resin material are cyanide resins.
表面および底部表面を有し、天井部表面には第1の導電
回路が配設され、前記第1の導電回路には被遮蔽部分と
露出部分とがあり、底部表面に第2の導電回路が配設さ
れ、前記第2の導電回路には被遮蔽部分と露出部分とが
ある基板と、 第2の樹脂から作製され、第2の樹脂の熱膨張係数が実
質的に第1の樹脂と同じであり、第1の導電回路の被遮
蔽部分を被覆しおよび平らな外表面を形成する方式で基
板の天井部表面上に配設される第1のソルダーマスク
と、 第2の樹脂から作製され、第2の導電回路の被遮蔽部分
を被覆しおよび平らに外表面を形成する方式で基板の底
部表面上に配設される第2のソルダーマスクと、 基板の天井部表面と底部表面を貫通し、第1の導電回路
と第2の導電回路を電気的に接続し、内部にそれぞれ充
填物を備え、各充填物の材質が各ソルダーマスクの材質
と同じである複数のめっきスルーホールと、 を備えることを特徴とするプリント回路板。18. A first resin material, having a ceiling surface and a bottom surface, wherein a first conductive circuit is disposed on the ceiling surface, and the first conductive circuit has a shielded portion. A second conductive circuit is disposed on the bottom surface, and the second conductive circuit is formed of a substrate having a shielded portion and an exposed portion; and a second resin. Resin having substantially the same coefficient of thermal expansion as the first resin, and disposed on the ceiling surface of the substrate in such a manner as to cover the shielded portion of the first conductive circuit and form a flat outer surface. A first solder mask, which is made of a second resin, and is disposed on the bottom surface of the substrate in a manner to cover the shielded portion of the second conductive circuit and form the outer surface flat. And a second conductive mask and a second conductive mask and a second conductive mask. A printed circuit board, comprising: a plurality of plated through holes electrically connected to a conductive circuit, each including a filler therein, and a material of each filler being the same as a material of each solder mask.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW091110994 | 2002-05-24 | ||
TW91110994 | 2002-05-24 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2003347711A true JP2003347711A (en) | 2003-12-05 |
Family
ID=29778224
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2002221338A Pending JP2003347711A (en) | 2002-05-24 | 2002-07-30 | Printed circuit board |
Country Status (2)
Country | Link |
---|---|
JP (1) | JP2003347711A (en) |
KR (1) | KR20030091393A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009253261A (en) * | 2008-04-07 | 2009-10-29 | Samsung Electro Mech Co Ltd | High density circuit board and manufacturing method thereof |
-
2002
- 2002-05-27 KR KR1020020029372A patent/KR20030091393A/en not_active Application Discontinuation
- 2002-07-30 JP JP2002221338A patent/JP2003347711A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009253261A (en) * | 2008-04-07 | 2009-10-29 | Samsung Electro Mech Co Ltd | High density circuit board and manufacturing method thereof |
Also Published As
Publication number | Publication date |
---|---|
KR20030091393A (en) | 2003-12-03 |
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