JP2003347562A - Sub carrier of optical semiconductor device and optical semiconductor device - Google Patents

Sub carrier of optical semiconductor device and optical semiconductor device

Info

Publication number
JP2003347562A
JP2003347562A JP2002154409A JP2002154409A JP2003347562A JP 2003347562 A JP2003347562 A JP 2003347562A JP 2002154409 A JP2002154409 A JP 2002154409A JP 2002154409 A JP2002154409 A JP 2002154409A JP 2003347562 A JP2003347562 A JP 2003347562A
Authority
JP
Japan
Prior art keywords
optical semiconductor
semiconductor device
insulating base
base
conductor layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2002154409A
Other languages
Japanese (ja)
Other versions
JP3987765B2 (en
Inventor
Naohito Ide
尚人 井手
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2002154409A priority Critical patent/JP3987765B2/en
Publication of JP2003347562A publication Critical patent/JP2003347562A/en
Application granted granted Critical
Publication of JP3987765B2 publication Critical patent/JP3987765B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01046Palladium [Pd]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance

Landscapes

  • Optical Couplings Of Light Guides (AREA)
  • Wire Bonding (AREA)
  • Semiconductor Lasers (AREA)
  • Light Receiving Elements (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a sub carrier of an optical semiconductor device whereby a wiring conductor layer is formed from the top to the side of an insulation pedestal with enhanced reliability of electrical connection. <P>SOLUTION: The sub carrier comprises an insulation pedestal 1 having a first step 15a and a second step 15b formed by notching a part between the top and the side of an insulation base 13 shaped almost like rectangular parallelepiped, a PD mounting part 14a which is formed on one side of the insulation pedestal 1 and has an optical semiconductor device (PD) 2 joined thereon, a first wiring pattern 14b which is formed from the top of the insulation pedestal 1 via the first step 15a or the second step 15b to one side of the insulation pedestal 1 and is connected to the PD mounting part 14a, and a second wiring pattern 14c which is electrically connected to the optical semiconductor device 2. <P>COPYRIGHT: (C)2004,JPO

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、光通信分野等で用
いられ、フォトダイオード(PD),半導体レーザ(P
D)等の光半導体素子を搭載するためのサブキャリアお
よび光半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in the field of optical communication and the like, and includes a photodiode (PD) and a semiconductor laser (P).
The present invention relates to a subcarrier for mounting an optical semiconductor element such as D) and an optical semiconductor device.

【0002】[0002]

【従来の技術】従来、光通信分野においては、光半導体
装置が高周波信号を電気−光変換し光ファイバ等へ光信
号として伝送するために用いられており、10G(ギガ)
ビット/秒(bps)を超えるデータ通信のビットレー
トを持つものが広く用いられるようになってきている。
2. Description of the Related Art Conventionally, in the field of optical communication, an optical semiconductor device has been used for converting an RF signal into an optical signal and transmitting the signal as an optical signal to an optical fiber or the like.
Devices having a data communication bit rate exceeding bits per second (bps) have been widely used.

【0003】従来のPD,LD等の光半導体素子を具備
した光半導体装置を図5に示す。図5に示すように、10
1は光半導体素子を搭載するための絶縁基台(サブキャ
リア)、102はPD、103aはPD102の上部電極と絶縁
基台101表面の配線パターンとを電気的に接続する第一
のボンディングワイヤ、103bは絶縁基台101表面の配線
パターンと回路基板120の回路配線とを電気的に接続す
るための第二のボンディングワイヤである。また、104
はLD、105はLD搭載用のサブマウント、106は測温素
子、107はペルチェ素子、108はセラミックス等から成る
基体、108aは基体108の平板状の底板部、108bは基体1
08の側壁部である。また、109は金属等から成る蓋体、1
10は金属等から成る筒状の光ファイバ固定部材(以下、
固定部材ともいう)、111は光ファイバ、112は外部リー
ド端子、120はPD102を制御するための制御回路やイン
ピーダンス整合用の線路導体等が形成された回路基板で
ある。
FIG. 5 shows a conventional optical semiconductor device having an optical semiconductor element such as a PD or LD. As shown in FIG.
1 is an insulating base (subcarrier) for mounting an optical semiconductor element, 102 is a PD, 103a is a first bonding wire for electrically connecting an upper electrode of the PD 102 and a wiring pattern on the surface of the insulating base 101, 103b is a second bonding wire for electrically connecting the wiring pattern on the surface of the insulating base 101 and the circuit wiring on the circuit board 120. Also, 104
Is an LD, 105 is a submount for mounting the LD, 106 is a temperature measuring element, 107 is a Peltier element, 108 is a base made of ceramics or the like, 108a is a flat bottom plate of the base 108, 108b is a base 1
08 side wall. 109 is a lid made of metal or the like, 1
10 is a cylindrical optical fiber fixing member made of metal or the like (hereinafter, referred to as
Reference numeral 111 denotes an optical fiber; 112, an external lead terminal; and 120, a circuit board on which a control circuit for controlling the PD 102, a line conductor for impedance matching, and the like are formed.

【0004】絶縁基台101は、図6に示すように、セラ
ミックス等から成る略直方体の絶縁基材113の表面に導
体層から成る各種機能部が形成されており、絶縁基材11
3の一側面にPDが搭載される導体層から成るPD搭載
部114aが形成され、絶縁基材113の上面に第一の配線パ
ターン114bおよび第二の配線パターン114cが形成され
ている。また、絶縁基材113の一側面には、PD搭載部1
14aと第一の配線パターン114bを電気的に接続する接
続部114d、および第二の配線パターン114cと電気的に
接続され、第一のボンディングワイヤ103aがボンディ
ングされるボンディング部114eが形成されている。さ
らに、絶縁基材113の下面には、基体108の底板部108a
の上面にAu−Snロウ材等を介して接着固定される下
部導体層114fが形成されている。
As shown in FIG. 6, the insulating base 101 has a substantially rectangular parallelepiped insulating base material 113 made of ceramics or the like, on which various functional parts made of a conductor layer are formed.
A PD mounting portion 114a made of a conductor layer on which a PD is mounted is formed on one side surface of the third substrate 3, and a first wiring pattern 114b and a second wiring pattern 114c are formed on the upper surface of the insulating base 113. Also, on one side surface of the insulating base material 113, the PD mounting portion 1 is provided.
A connecting portion 114d electrically connecting the first wiring pattern 114b to the first wiring pattern 114b and a bonding portion 114e electrically connected to the second wiring pattern 114c and bonding the first bonding wire 103a are formed. . Further, on the lower surface of the insulating base 113, a bottom plate 108a of the base 108 is provided.
Is formed on the upper surface of the lower conductor layer 114f which is bonded and fixed via an Au-Sn brazing material or the like.

【0005】PD102は、絶縁基台101のPD搭載部114
aにAu−Snロウ材等を介して接着固定される。PD
102が搭載された絶縁基台101は、基体108の底板部108a
の上面にPD102の受光面がLD104や光ファイバ111と
光学的に結合するように接着固定されている。また、基
体108の底板部108aの上面には、LD104および測温素
子106が搭載されたサブマウント105がペルチェ素子107
を介して載置されている。
[0005] The PD 102 is a PD mounting portion 114 of the insulating base 101.
a, which is bonded and fixed via an Au-Sn brazing material or the like. PD
The insulating base 101 on which the base 102 is mounted is a bottom plate portion 108a of the base 108.
The light receiving surface of the PD 102 is adhesively fixed to the upper surface of the optical disk so as to be optically coupled to the LD 104 and the optical fiber 111. A submount 105 on which an LD 104 and a temperature measuring element 106 are mounted is provided with a Peltier element
Is placed via.

【0006】光ファイバ111はLD104から発光される光
を外部に伝送するとともに、光ファイバ111から伝送さ
れた光をPD102に受光させて光信号を電気信号に変換
させる。または、PD102はLD104から後方へ出射され
た光をモニタするためのものである。
The optical fiber 111 transmits the light emitted from the LD 104 to the outside and causes the PD 102 to receive the light transmitted from the optical fiber 111 to convert an optical signal into an electric signal. Alternatively, the PD 102 is for monitoring the light emitted backward from the LD 104.

【0007】基体108の下面には、外部リード端子112が
固定されており、PD102、LD104、測温素子106、ペ
ルチェ素子107が電気的に接続されている。また、基体1
08の上面に蓋体109がシーム溶接法等により接合される
ことにより、光半導体装置を気密に封止する。
An external lead terminal 112 is fixed to the lower surface of the base 108, and the PD 102, LD 104, temperature measuring element 106, and Peltier element 107 are electrically connected. Also, the base 1
The optical semiconductor device is hermetically sealed by joining the lid body 109 to the upper surface of 08 by a seam welding method or the like.

【0008】この光半導体装置は、PD102が絶縁基台1
01のPD搭載部114aにAu−Sn合金等から成る低融
点ろう材を介して接着固定される。その後、PD102の
上部電極とボンディング部114eとを、AuやAl等か
らなる第一のボンディングワイヤ103aを介して電気的
に接続する。そして、PD102が搭載された絶縁基台101
は、その下部導体層114fが基体108の底板部108aの上
面に、Au−Sn合金やPb−Sn合金等から成るろう
材を介して接着固定される。その後、絶縁基台101の第
一の配線パターン114bおよび第二の配線パターン114c
を、回路基板120の回路配線や線路導体に、AuやAl
等からなる第二のボンディングワイヤ103bにより電気
的に接続する。同様に、LD104と測温素子106をサブマ
ウント105の上面にろう材を介して接着固定した後、予
めろう材を介して基体108の底板部108aの上面に接着固
定されたペルチェ素子107の上面にサブマウント105をろ
う材を介して接着固定する。
In this optical semiconductor device, the PD 102 is an insulating base 1
01 is mounted and fixed to the PD mounting portion 114a via a low melting point brazing material made of an Au-Sn alloy or the like. Thereafter, the upper electrode of the PD 102 and the bonding portion 114e are electrically connected via a first bonding wire 103a made of Au, Al, or the like. Then, the insulating base 101 on which the PD 102 is mounted
The lower conductor layer 114f is bonded and fixed to the upper surface of the bottom plate portion 108a of the base 108 via a brazing material made of an Au-Sn alloy, a Pb-Sn alloy, or the like. Thereafter, the first wiring pattern 114b and the second wiring pattern 114c of the insulating base 101 are formed.
To the circuit wiring and the line conductor of the circuit board 120 by using Au or Al
Are electrically connected by a second bonding wire 103b. Similarly, after the LD 104 and the temperature measuring element 106 are bonded and fixed to the upper surface of the submount 105 via a brazing material, the upper surface of the Peltier element 107 is bonded and fixed in advance to the upper surface of the bottom plate 108a of the base 108 via the brazing material. The submount 105 is bonded and fixed via a brazing material.

【0009】[0009]

【発明が解決しようとする課題】しかしながら、上記従
来の光半導体装置においては、PD102が搭載された絶
縁基台101は、組立工程において、コレット等の搬送治
具により挟まれた状態で移動して、基体108の底板部108
aの上面に載置されるが、その際、第一の配線パターン
114bと接続部114dおよび第二の配線パターン114cと
ボンディング部114eが電気的に接続される絶縁基材113
の稜部が搬送治具と接触し、稜部で導体層が傷付いたり
削り取られて、第一の配線パターン114bと接続部114d
および第二の配線パターン114cとボンディング部114e
が断線したり、導通抵抗が増大してしまうという問題点
があった。
However, in the above-described conventional optical semiconductor device, the insulating base 101 on which the PD 102 is mounted moves while being sandwiched by a transfer jig such as a collet in an assembling process. , Bottom plate 108 of base 108
a, the first wiring pattern
Insulating base material 113 for electrically connecting 114b to connecting portion 114d and second wiring pattern 114c to bonding portion 114e.
Of the first wiring pattern 114b and the connecting portion 114d.
And the second wiring pattern 114c and the bonding portion 114e.
However, there is a problem that the wire breaks or the conduction resistance increases.

【0010】また、絶縁基台101は、PD搭載部114a、
接続部114dおよびボンディング部114eが絶縁基材113
の同じ一側面に形成されているため、スパッタリング
法、真空蒸着法、フォトリソグラフィ法、エッチング法
等を用いて同時に形成される。その後、第一の配線パタ
ーン114b、第二の配線パターン114cが形成されるが、
これら配線パターンの形成がPD搭載部114a、接続部1
14dおよびボンディング部114eの形成と別々となるた
め、それらが電気的に接続される稜部において、断線が
発生し易いという問題点があった。
The insulating base 101 includes a PD mounting portion 114a,
The connecting portion 114d and the bonding portion 114e are
Are formed at the same time by using a sputtering method, a vacuum evaporation method, a photolithography method, an etching method, or the like. After that, a first wiring pattern 114b and a second wiring pattern 114c are formed,
The formation of these wiring patterns is performed by the PD mounting portion 114a, the connection portion 1
Since this is separate from the formation of the bonding portion 114d and the bonding portion 114e, there is a problem that disconnection easily occurs at a ridge portion where they are electrically connected.

【0011】従って、本発明は上記問題点に鑑みて完成
されたものであり、その目的は、電気的接続の信頼性を
高くして絶縁基材の上面から側面にわたって配線導体層
(配線パターン)を形成した絶縁基台を具備した光半導
体装置を提供することにある。
Accordingly, the present invention has been completed in view of the above problems, and an object of the present invention is to provide a wiring conductor layer (wiring pattern) extending from the upper surface to the side surface of an insulating base material by increasing the reliability of electrical connection. It is an object of the present invention to provide an optical semiconductor device provided with an insulating base on which is formed.

【0012】[0012]

【課題を解決するための手段】本発明の光半導体素子の
サブキャリアは、略直方体の絶縁基材の上面と一側面と
の間に一部を切り欠いた第一および第二の段差が形成さ
れた絶縁基台と、該絶縁基台の前記一側面に形成され
た、光半導体素子が接合される導体層と、前記絶縁基台
の前記上面から前記第一の段差または前記第二の段差を
経て前記一側面にかけて形成された、前記導体層に接続
される第一の配線導体層および前記光半導体素子に電気
的に接続される第二の配線導体層とを具備したことを特
徴とする。
The subcarrier of the optical semiconductor device of the present invention has first and second steps, each of which is partially cut away, between the upper surface and one side surface of a substantially rectangular insulating base material. An insulating base, a conductor layer formed on the one side surface of the insulating base, to which an optical semiconductor element is bonded, and the first step or the second step from the upper surface of the insulating base. A first wiring conductor layer connected to the conductor layer and a second wiring conductor layer electrically connected to the optical semiconductor element. .

【0013】本発明のサブキャリアは、絶縁基台の上面
から第一の段差または第二の段差を経て側面にかけて形
成された、導体層に接続される第一の配線導体層および
光半導体素子に電気的に接続される第二の配線導体層が
設けられていることから、光半導体装置の組立工程でサ
ブキャリアをコレット等の搬送治具で挟んで移動させた
際に、搬送治具の接触等によって第一および第二の配線
導体層に断線不良や導通抵抗の増大等が発生するのを防
止することができる。また、絶縁基台の上面と側面に別
々に第一,第二の配線導体層を形成すると、上面と側面
との間の稜部が一つの稜線(角部)ではなく第一および
第二の段差が形成されているため、上面に第一および第
二の配線導体層を形成する際に上面に直交する第一およ
び第二の段差の内面にも導体が廻り込んで形成され、ま
た側面に第一および第二の配線導体層を形成する際に側
面に直交する第一および第二の段差の内面にも導体が廻
り込んで形成されるため、第一および第二の段差の内面
に重複して導体が形成されることとなり、第一および第
二の段差において電気的接続の信頼性が向上する。
[0013] The subcarrier of the present invention includes a first wiring conductor layer connected to a conductor layer and an optical semiconductor element formed from the upper surface of the insulating base to the side surface via the first step or the second step. Since the second wiring conductor layer that is electrically connected is provided, when the subcarrier is sandwiched and moved by a transport jig such as a collet in an assembling process of the optical semiconductor device, the contact of the transport jig is caused. By doing so, it is possible to prevent the first and second wiring conductor layers from suffering from a disconnection defect, an increase in conduction resistance, and the like. In addition, when the first and second wiring conductor layers are separately formed on the upper surface and the side surface of the insulating base, the ridge between the upper surface and the side surface is not one ridge line (corner) but the first and second wiring conductor layers. Since the steps are formed, the conductor is also formed around the inner surfaces of the first and second steps orthogonal to the upper surface when forming the first and second wiring conductor layers on the upper surface, and on the side surfaces. When the first and second wiring conductor layers are formed, the conductor also extends around the inner surfaces of the first and second steps which are orthogonal to the side surfaces, and thus overlaps the inner surfaces of the first and second steps. As a result, the conductor is formed, and the reliability of the electrical connection is improved at the first and second steps.

【0014】本発明の光半導体装置は、上面に凹部が形
成されているとともに該凹部から外側面にかけて形成さ
れた貫通孔を有する基体と、前記貫通孔に嵌着された筒
状の光ファイバ固定部材と、前記凹部の底面に載置され
た本発明のサブキャリアと、該サブキャリアの前記導体
層に接合されるとともに前記第一および第二の配線導体
層に電気的に接続された光半導体素子と、前記基体の上
面の前記凹部の周囲に接合された蓋体とを具備したこと
を特徴とする。
An optical semiconductor device according to the present invention comprises: a base having a concave portion formed on the upper surface and having a through hole formed from the concave portion to the outer surface; and a cylindrical optical fiber fixed to the through hole. A member, a subcarrier of the present invention mounted on the bottom surface of the concave portion, and an optical semiconductor bonded to the conductor layer of the subcarrier and electrically connected to the first and second wiring conductor layers An element and a lid joined to the periphery of the concave portion on the upper surface of the base are provided.

【0015】本発明の光半導体装置は、電気的接続の信
頼性の高い光半導体素子搭載用のサブキャリアを用いた
高信頼性のものとなる。
The optical semiconductor device of the present invention has high reliability using a subcarrier for mounting an optical semiconductor element having high electrical connection reliability.

【0016】[0016]

【発明の実施の形態】本発明のサブキャリアおよび光半
導体装置について以下に詳細に説明する。図1は本発明
の光半導体装置について実施の形態の一例を示す断面
図、図2は本発明の光半導体装置に搭載される光半導体
素子のサブキャリアについて実施の形態の一例を示す斜
視図、図3,図4は本発明の光半導体装置に搭載される
サブキャリアについて実施の形態の他の例をそれぞれ示
す斜視図である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A subcarrier and an optical semiconductor device according to the present invention will be described in detail below. FIG. 1 is a cross-sectional view showing an example of an embodiment of an optical semiconductor device of the present invention, FIG. 2 is a perspective view showing an example of an embodiment of a subcarrier of an optical semiconductor element mounted on the optical semiconductor device of the present invention, 3 and 4 are perspective views showing other examples of the embodiment of the subcarrier mounted on the optical semiconductor device of the present invention.

【0017】これらの図において、1はサブキャリアを
成す絶縁基台、2は光半導体素子としてのPD、3aは
PD2の上部電極と絶縁基台1表面の配線パターンとを
電気的に接続する第一のボンディングワイヤ、3bは絶
縁基台1表面の配線パターンと回路基板20の回路配線と
を電気的に接続するための第二のボンディングワイヤ、
4はLD、5はサブマウント、6は測温素子、7はペル
チェ素子、8は基体、8aは基体8の底板部、8bは基
体8の側壁部、9は蓋体、10は固定部材、11は光ファイ
バ、12は外部リード端子である。
In these figures, reference numeral 1 denotes an insulating base forming a subcarrier, 2 denotes a PD as an optical semiconductor element, and 3a denotes an upper electrode for electrically connecting an upper electrode of the PD 2 and a wiring pattern on the surface of the insulating base 1. One bonding wire 3b is a second bonding wire for electrically connecting the wiring pattern on the surface of the insulating base 1 and the circuit wiring on the circuit board 20;
4 is an LD, 5 is a submount, 6 is a temperature measuring element, 7 is a Peltier element, 8 is a base, 8a is a bottom plate of the base 8, 8b is a side wall of the base 8, 9 is a lid, 10 is a fixing member, 11 is an optical fiber and 12 is an external lead terminal.

【0018】また、13は絶縁基台1を構成する略直方体
の絶縁基材、14aは絶縁基台1の一側面に形成された導
体層としてのPD搭載部、14bは絶縁基台1の上面に形
成された第一の配線導体層としての第一の配線パター
ン、14cは絶縁基台1の上面に形成された第二の配線導
体層としての第二の配線パターン、14dはPD搭載部14
aと第一の配線パターン14bとを電気的に接続する接続
部、14eは第二の配線パターン14cと電気的に接続さ
れ、第一のボンディングワイヤ3aがボンディングされ
るボンディング部、14fは基体8の底板部8aの上面に
Au−Snロウ材等を介して接着固定される下部導体
層、15a,15bは第一,第二の配線パターン14b,14c
が形成された、稜部の一部が切り欠かれた第一および第
二の段差である。
Reference numeral 13 denotes a substantially rectangular parallelepiped insulating base constituting the insulating base 1, 14a denotes a PD mounting portion as a conductor layer formed on one side surface of the insulating base 1, and 14b denotes an upper surface of the insulating base 1. A first wiring pattern as a first wiring conductor layer formed on the insulating base 1; a second wiring pattern as a second wiring conductor layer formed on the upper surface of the insulating base 1;
a, a connecting portion that electrically connects the first wiring pattern 14b to the first wiring pattern 14b; 14e, a bonding portion that is electrically connected to the second wiring pattern 14c, to which the first bonding wire 3a is bonded; The lower conductor layer 15a, 15b is bonded and fixed to the upper surface of the bottom plate portion 8a via an Au-Sn brazing material, etc., and the first and second wiring patterns 14b, 14c
Are formed, and the first and second steps are partially cut away.

【0019】なお、第一の配線パターン14bはPD搭載
部14aに直接的に接続されるようにPD搭載部14aと一
体的に形成されているが、第二の配線パターン14cと同
様にPD搭載部14aとは別々に形成してボンディングワ
イヤで電気的に接続してもよい。また、第二の配線パタ
ーン14cは第一のボンディングワイヤ3aを介してPD
2の露出した主面や受光面等に形成された電極等に電気
的に接続される。
The first wiring pattern 14b is formed integrally with the PD mounting portion 14a so as to be directly connected to the PD mounting portion 14a. It may be formed separately from the portion 14a and electrically connected by a bonding wire. The second wiring pattern 14c is connected to the PD via the first bonding wire 3a.
2 are electrically connected to electrodes and the like formed on the exposed main surface and light receiving surface.

【0020】さらに、20は、第二のボンディングワイヤ
3bを介して絶縁基台1の配線パターンと電気的に接続
される回路基板である。この回路基板20は、PD2を制
御するための制御回路やインピーダンス整合用の線路導
体等が形成されたものであり、その上面には回路配線や
線路導体が形成されており、第一の配線パターン4bお
よび第二の配線パターン4cを、回路基板20の回路配線
や線路導体に、AuやAl等からなる第二のボンディン
グワイヤ3bにより電気的に接続する。
Reference numeral 20 denotes a circuit board which is electrically connected to the wiring pattern of the insulating base 1 via the second bonding wires 3b. The circuit board 20 has a control circuit for controlling the PD 2 and a line conductor for impedance matching formed thereon, and a circuit wiring and a line conductor are formed on an upper surface thereof. 4b and the second wiring pattern 4c are electrically connected to the circuit wiring and the line conductor of the circuit board 20 by the second bonding wire 3b made of Au, Al or the like.

【0021】本発明のサブキャリアは、略直方体の絶縁
基材13の上面と一側面との間に一部を切り欠いた第一の
段差15aおよび第二の段差15bが形成された絶縁基台1
と、絶縁基台1の一側面に形成された、光半導体素子
(PD2)が接合される導体層(PD搭載部14a)と、
絶縁基台1の上面から第一の段差15aまたは第二の段差
15bを経て一側面にかけて形成された、導体層に接続さ
れる第一の配線導体層(第一の配線パターン14b)およ
び光半導体素子に電気的に接続される第二の配線導体層
(第二の配線パターン14c)とを具備した構成である。
The subcarrier according to the present invention comprises an insulating base in which a first step 15a and a second step 15b, each of which is partially cut away, are formed between the upper surface and one side surface of a substantially rectangular insulating base material 13. 1
And a conductor layer (PD mounting portion 14a) formed on one side surface of the insulating base 1 and joined to the optical semiconductor element (PD2);
The first step 15a or the second step from the upper surface of the insulating base 1.
A first wiring conductor layer (first wiring pattern 14b) connected to the conductor layer and a second wiring conductor layer (second Wiring pattern 14c).

【0022】また、本発明の光半導体装置は、上面に凹
部が形成されているとともに凹部から外側面にかけて形
成された貫通孔を有する基体8と、貫通孔に嵌着された
筒状の光ファイバ固定部材10と、凹部の底面に載置され
た本発明のサブキャリアと、サブキャリアの導体層に接
合されるとともに第一および第二の配線導体層に電気的
に接続された光半導体素子と、基体の上面の凹部の周囲
に接合された蓋体9とを具備した構成である。
Further, the optical semiconductor device of the present invention has a base 8 having a concave portion formed on the upper surface and having a through hole formed from the concave portion to the outer surface, and a cylindrical optical fiber fitted into the through hole. The fixing member 10, the subcarrier of the present invention mounted on the bottom surface of the concave portion, and an optical semiconductor element which is bonded to the conductor layer of the subcarrier and electrically connected to the first and second wiring conductor layers. , And a lid 9 joined to the periphery of the concave portion on the upper surface of the base.

【0023】本発明の光半導体装置は、基体8の底板部
8aの上面に載置された光半導体素子としてのPD2が
搭載された絶縁基台1と、ペルチェ素子7を介して載置
されたLD4および測温素子6が搭載されたサブマウン
ト5とを具備しており、基体8の側壁部8bの上面に蓋
体9を取着することにより気密封止されている。
In the optical semiconductor device of the present invention, the insulating base 1 on which the PD 2 as an optical semiconductor element is mounted on the upper surface of the bottom plate 8a of the base 8 and the Peltier element 7 are mounted. It has a submount 5 on which the LD 4 and the temperature measuring element 6 are mounted, and is hermetically sealed by attaching a lid 9 to the upper surface of the side wall 8 b of the base 8.

【0024】基体8は、底板部8aと側壁部8bとから
成り、上面に各種部品を収容するための凹部が形成され
ている。この基体8は、底板部8aと側壁部8bとが一
体的に形成されたものであってもよい。基体8の側壁部
8bには凹部から外側面にかけて貫通孔が形成され、そ
の貫通孔には光ファイバ11を固定するための筒状の固定
部材10が嵌着接合されている。
The base 8 comprises a bottom plate 8a and a side wall 8b, and has a recess formed on its upper surface for accommodating various components. The base body 8 may be one in which the bottom plate portion 8a and the side wall portion 8b are integrally formed. A through hole is formed in the side wall portion 8b of the base 8 from the concave portion to the outer surface, and a cylindrical fixing member 10 for fixing the optical fiber 11 is fitted and joined to the through hole.

【0025】本発明のサブキャリアにおいて、絶縁基台
1の本体部分である絶縁基材13は、セラミックス(焼結
体)等の絶縁材料から成り、例えばAl23質焼結体、
窒化アルミニウム(AlN)質焼結体、炭化珪素(Si
C)質焼結体、窒化珪素(Si34)質焼結体、ガラス
セラミックス焼結体等から成る。
[0025] In the sub-carrier of the present invention, the insulating substrate 13 is a main portion of the insulating base 1 is made of an insulating material such as ceramics (sintered body), for example, Al 2 O 3 sintered material,
Aluminum nitride (AlN) sintered body, silicon carbide (Si
C) Sintered body, silicon nitride (Si 3 N 4 ) -based sintered body, glass ceramic sintered body, and the like.

【0026】絶縁基台1の第一,第二の配線パターン14
b,14cを含む各導体層は、例えば密着金属層、拡散防
止層、主導体層が順次積層された3層構造の導体層から
成る。そして、密着金属層は絶縁基材13との密着性の点
で、Ti,Cr,Ta,Nb,Ni−Cr合金,Ta2
N等の少なくとも1種より成るのが良い。密着金属層の
厚さは0.01〜0.2μm程度が良い。0.01μm未満では強
固に密着することが困難となり、0.2μmを超えると成
膜時の内部応力によって剥離が生じ易くなる。
The first and second wiring patterns 14 of the insulating base 1
Each of the conductor layers including b and 14c is formed of, for example, a conductor layer having a three-layer structure in which an adhesion metal layer, a diffusion prevention layer, and a main conductor layer are sequentially laminated. The adhesion metal layer is made of Ti, Cr, Ta, Nb, Ni—Cr alloy, Ta 2
It is preferable to be made of at least one of N and the like. The thickness of the adhesion metal layer is preferably about 0.01 to 0.2 μm. If it is less than 0.01 μm, it will be difficult to firmly adhere, and if it exceeds 0.2 μm, peeling will easily occur due to internal stress during film formation.

【0027】拡散防止層は、密着金属層と主導体層との
相互拡散を防ぐうえで、Pt,Pd,Rh,Ni,Ni
−Cr合金,Ti−W合金等の少なくとも1種より成る
のが良い。拡散防止層の厚さは0.05〜1μm程度が良
く、0.05μm未満では、ピンホール等の欠陥が発生して
拡散防止層としての機能を果たしにくくなる。1μmを
超えると、成膜時の内部応力により剥離が生じ易くな
る。拡散防止層にNi−Cr合金を用いる場合は、密着
性も確保できるため、密着金属層を省くことも可能であ
る。
The diffusion preventing layer is formed of Pt, Pd, Rh, Ni, Ni to prevent mutual diffusion between the adhesion metal layer and the main conductor layer.
-It is preferable to be made of at least one of a Cr alloy, a Ti-W alloy and the like. The thickness of the diffusion prevention layer is preferably about 0.05 to 1 μm. If the thickness is less than 0.05 μm, defects such as pinholes are generated and the function as the diffusion prevention layer is hardly achieved. If it exceeds 1 μm, peeling is likely to occur due to internal stress during film formation. When a Ni—Cr alloy is used for the diffusion prevention layer, the adhesion can be ensured, so that the adhesion metal layer can be omitted.

【0028】さらに主導体層は電気抵抗の小さいAu,
Cu,Ni,Ag等より成るのが良く、その厚さは0.1
〜5μm程度が良い。0.1μm未満では、電気抵抗が大
きくなる傾向があり、5μmを超えると、成膜時の内部
応力により剥離を生じ易くなる。また、Auは貴金属で
高価であることから、低コスト化の点でなるべく薄く形
成することが好ましい。Cuは酸化し易いので、その上
にNiおよびAuから成る保護層をメッキ法等で被着す
るのが良い。
Further, the main conductor layer is made of Au having a small electric resistance,
It is preferably made of Cu, Ni, Ag, etc., and has a thickness of 0.1
About 5 μm is good. If it is less than 0.1 μm, the electrical resistance tends to increase, and if it exceeds 5 μm, peeling is likely to occur due to internal stress during film formation. Further, since Au is a noble metal and expensive, it is preferable to form it as thin as possible from the viewpoint of cost reduction. Since Cu is easily oxidized, a protective layer made of Ni and Au is preferably applied thereon by plating or the like.

【0029】絶縁基台1のPD搭載部14aにはPD2を
固定するための低融点ろう材をスパッタリング法等によ
り所定の厚みに被着させても良い。これにより、PD2
を接着固定する際にろう材のプリフォームを配置する手
間を省くことができる。低融点ろう材としては、Au−
Ge合金(融点約356℃)、Au−Si合金(融点約370
℃)、Au−Sn合金(融点約183℃)、In−Pb合
金(融点約172℃)、In(融点約157℃)等が好まし
い。これらは融点が400℃以下であるため、接着温度を
低くすることができる。その結果、光半導体素子が熱衝
撃破壊されることがないという利点がある。また、組立
工程において、低温接着ができることにより、昇温時間
および冷却時間を短くすることができる。その結果、生
産コストを低くすることができる。
A low melting point brazing material for fixing the PD 2 may be applied to the PD mounting portion 14a of the insulating base 1 to a predetermined thickness by a sputtering method or the like. Thereby, PD2
This eliminates the need for arranging a brazing material preform when bonding and fixing the preform. As a low melting point brazing material, Au-
Ge alloy (melting point about 356 ° C), Au-Si alloy (melting point about 370 ° C)
° C), an Au-Sn alloy (melting point of about 183 ° C), an In-Pb alloy (melting point of about 172 ° C), In (melting point of about 157 ° C) and the like are preferable. Since these have a melting point of 400 ° C. or less, the bonding temperature can be lowered. As a result, there is an advantage that the optical semiconductor element is not destroyed by thermal shock. Further, in the assembling process, the low-temperature bonding can be performed, so that the time for raising the temperature and the time for cooling can be shortened. As a result, production costs can be reduced.

【0030】絶縁基台1の第一,第二の段差15a,15b
は、ダイシング法、スライシング法または平面研削法あ
るいはサンドブラスト法等により形成される。
The first and second steps 15a, 15b of the insulating base 1
Are formed by a dicing method, a slicing method, a surface grinding method, a sand blast method, or the like.

【0031】第一,第二の段差15a,15bは、第一,第
二の配線パターン14a,14bが形成される稜部の一部を
切り欠いて形成されており、第一,第二の段差15a,15
bの上面における長さ(第一,第二の配線パターン14
a,14bの長手方向の長さ)L 1(図2)および幅(第
一,第二の配線パターン14a,14bの幅方向の幅)L2
(図2)は、0.03mm以上が良い。0.03mm未満だと、
第一,第二の段差15a,15bの内面に第一,第二の配線
パターン14a,14bを形成するのが困難となり、その結
果、電気的接続の信頼性が低下する。また、第一,第二
の段差15a,15bの幅L2は、第一,第二の配線パター
ン14b,14cのそれぞれの幅の1/2以上が好ましい。
1/2より小さくなると、第一,第二の段差15a,15b
が小さくなる代わりに稜部に形成された配線導体層の幅
が大きくなるため、組立工程において断線不良や導通抵
抗の増大が発生し易くなる。
The first and second steps 15a and 15b correspond to the first and second steps, respectively.
Part of the ridge where the second wiring patterns 14a and 14b are formed
The first and second steps 15a, 15
b on the top surface (the first and second wiring patterns 14
a, the length of 14b in the longitudinal direction) L 1(FIG. 2) and width (No.
The width in the width direction of the first and second wiring patterns 14a and 14b) LTwo
(FIG. 2) is preferably 0.03 mm or more. If it is less than 0.03 mm,
First and second wirings are provided on the inner surfaces of the first and second steps 15a and 15b.
It becomes difficult to form the patterns 14a and 14b,
As a result, the reliability of the electrical connection decreases. The first and second
Width L of steps 15a and 15bTwoAre the first and second wiring patterns
It is preferable that the width is equal to or more than の of each width of the pins 14b and 14c.
If it is smaller than 1/2, the first and second steps 15a, 15b
Width of the wiring conductor layer formed on the ridge instead of
The disconnection failure and conduction resistance during the assembly process.
An increase in resistance is likely to occur.

【0032】第一,第二の段差15a,15bは、図2に示
すように底面が互いに直交する2面(側方からみた断面
形状がL字状の面)から成るものであってもよいし、図
3,図4に示すように底面が一つの斜面から成っていて
もよい。
As shown in FIG. 2, the first and second steps 15a and 15b may be composed of two surfaces whose bottom surfaces are orthogonal to each other (surfaces having an L-shaped cross section as viewed from the side). Alternatively, as shown in FIGS. 3 and 4, the bottom surface may be formed of one slope.

【0033】また、図2,図3に示すように、第一の配
線パターン14bおよび第二の配線パターン14cの幅はそ
れぞれ第一,第二の段差15a,15bよりも幅広であって
もよいし、図4に示すように、第一,第二の段差15a,
15bの幅がそれぞれ第一の配線パターン14bおよび第二
の配線パターン14cよりも幅広であってもよい。図2,
図3の場合、第一,第二の段差15a,15bの内面には絶
縁基台1の上面と側面に別々に導体層を成膜することに
より配線導体層が重複して形成されるため、電気的接続
の信頼性が向上する。図4の場合、絶縁基台1の上面と
側面との間の稜部に搬送治具等が接触して稜部に欠け等
が発生しても配線導体層には全く欠け等が発生しないた
め、電気的接続の信頼性が向上する。また図4の場合に
も、絶縁基台1の上面と側面に別々に導体層を成膜する
ことにより配線導体層を重複して形成することもでき、
電気的接続の信頼性がさらに向上し好ましいものとな
る。
As shown in FIGS. 2 and 3, the widths of the first wiring pattern 14b and the second wiring pattern 14c may be wider than the first and second steps 15a and 15b, respectively. Then, as shown in FIG. 4, the first and second steps 15a,
The width of 15b may be wider than the first wiring pattern 14b and the second wiring pattern 14c, respectively. Figure 2
In the case of FIG. 3, the wiring conductor layers are formed on the inner surfaces of the first and second steps 15a and 15b separately by forming conductor layers on the upper surface and the side surfaces of the insulating base 1 separately. The reliability of the electrical connection is improved. In the case of FIG. 4, even if the carrier jig or the like contacts the ridge between the upper surface and the side surface of the insulating base 1 and the ridge is chipped or the like, the wiring conductor layer is not chipped at all. And the reliability of the electrical connection is improved. Also in the case of FIG. 4, the wiring conductor layers can be formed overlapping by separately forming the conductor layers on the upper surface and the side surfaces of the insulating base 1,
This is preferable because the reliability of the electrical connection is further improved.

【0034】本発明の配線導体層である第一の配線パタ
ーン14bおよび第二の配線パターン14cは、スパッタリ
ング法や真空蒸着法等の薄膜形成法により成膜される
が、絶縁基台1の上面と側面に別々に配線導体層を形成
することが好ましい。この場合、絶縁基台1の上面と側
面との間の稜部が一つの稜線(角部)ではなく第一,第
二の段差15a,15bが形成されているため、上面に配線
導体層を形成する際に上面に直交する第一,第二の段差
15a,15bの内面にも導体が廻り込んで形成され、また
側面に配線導体層を形成する際に側面に直交する第一,
第二の段差15a,15bの内面にも導体が廻り込んで形成
されるため、第一,第二の段差15a,15bの内面に重複
して導体が形成されることとなり、第一,第二の段差15
a,15bにおいて電気的接続の信頼性が向上する。
The first wiring pattern 14b and the second wiring pattern 14c, which are the wiring conductor layers of the present invention, are formed by a thin film forming method such as a sputtering method or a vacuum evaporation method. It is preferable to form wiring conductor layers separately on the side surfaces. In this case, since the ridge between the upper surface and the side surface of the insulating base 1 is not one ridge line (corner) but the first and second steps 15a and 15b are formed, the wiring conductor layer is formed on the upper surface. First and second steps perpendicular to the top surface when forming
The conductors are also formed around the inner surfaces of 15a and 15b, and when forming the wiring conductor layer on the side surfaces, the first and the right sides are orthogonal to the side surfaces.
Since the conductor also extends around the inner surfaces of the second steps 15a and 15b, the conductors are formed overlapping the inner surfaces of the first and second steps 15a and 15b. Step 15
In a and 15b, the reliability of the electrical connection is improved.

【0035】本発明の基体8は、Al23質焼結体、A
lN質焼結体、ムライト質焼結体、SiC炭化珪素質焼
結体、Si34質焼結体、ガラスセラミックス等のセラ
ミックス、またはCuを含浸させたタングステン多孔質
体、Fe−Ni合金、Fe−Ni−Co合金等の金属か
ら成る。基体8を構成する底板部8aと側壁部8bとは
同じ材料から形成されていても良いし、互いに異なる材
料から形成されていても良い。ただし、底板部8aと側
壁部8bとを異なる材料で形成する場合、両者の熱膨張
係数差ができるだけ小さいものとなる組合せを選択する
ことが好ましい。また、底板部8aと側壁部8bとは一
体的に形成されていてもよい。
The substrate 8 of the present invention is made of an Al 2 O 3 sintered body,
Ceramics such as 1N sintered body, mullite sintered body, SiC silicon carbide sintered body, Si 3 N 4 sintered body, glass ceramic, or porous tungsten impregnated with Cu, Fe—Ni alloy , Fe-Ni-Co alloy and the like. The bottom plate portion 8a and the side wall portion 8b constituting the base 8 may be formed of the same material or may be formed of different materials. However, when the bottom plate portion 8a and the side wall portion 8b are formed of different materials, it is preferable to select a combination that minimizes the difference in thermal expansion coefficient between the two. Further, the bottom plate portion 8a and the side wall portion 8b may be formed integrally.

【0036】基体8の底板部8aの上面には、回路基板
20と、ペルチェ素子7が接着固定されている。ペルチェ
素子7は、LD4を所定の温度に冷却または加熱するた
めの熱ポンプとして機能し、測温素子6により測定した
LD4の温度を検知し、LD4が所定の温度となるよう
に冷却または加熱する。そして、このペルチェ素子7の
上面には、サブマウント5が搭載されており、サブマウ
ント5上にLD4および測温素子6が隣接して設置され
る。
A circuit board is provided on the upper surface of the bottom plate 8a of the base 8.
20 and the Peltier element 7 are adhesively fixed. The Peltier element 7 functions as a heat pump for cooling or heating the LD 4 to a predetermined temperature, detects the temperature of the LD 4 measured by the temperature measuring element 6, and cools or heats the LD 4 to a predetermined temperature. . The submount 5 is mounted on the upper surface of the Peltier element 7, and the LD 4 and the temperature measuring element 6 are installed adjacent to the submount 5.

【0037】さらに、基体8の底板部8aまたは側壁部
8bには、Fe−Ni合金やFe−Ni−Co合金等の
金属から成る外部リード端子12が容器の外部に突出する
ようにして設けられている。この外部リード端子12は、
基体8の底板部8aまたは側壁部8bを貫通するように
して設けられるかまたは基体8の内部から外部に導出さ
れたメタライズ層等の配線導体に接合されることによ
り、容器の内部と外部とを電気的に接続している。そし
て、この外部リード端子12には、容器内部の回路基板2
0、LD4、測温素子6、ペルチェ素子7が電気的に接
続される。
Further, an external lead terminal 12 made of a metal such as an Fe-Ni alloy or an Fe-Ni-Co alloy is provided on the bottom plate 8a or the side wall 8b of the base 8 so as to protrude outside the container. ing. This external lead terminal 12
The inside and outside of the container are separated from each other by being provided so as to penetrate the bottom plate portion 8a or the side wall portion 8b of the base 8 or being joined to a wiring conductor such as a metallized layer led out from the inside of the base 8 to the outside. Electrically connected. The external lead terminals 12 are connected to the circuit board 2 inside the container.
0, the LD 4, the temperature measuring element 6, and the Peltier element 7 are electrically connected.

【0038】なお、本発明は上記実施の形態に限定され
るものではなく、本発明の要旨を逸脱しない範囲内にお
いて種々の変更を施すことは何等差し支えない。
It should be noted that the present invention is not limited to the above-described embodiment, and that various changes can be made without departing from the scope of the present invention.

【0039】[0039]

【発明の効果】本発明の光半導体素子のサブキャリア
は、略直方体の絶縁基材の上面と一側面との間に一部を
切り欠いた第一および第二の段差が形成された絶縁基台
と、絶縁基台の一側面に形成された、光半導体素子が接
合される導体層と、絶縁基台の上面から第一の段差また
は第二の段差を経て一側面にかけて形成された、導体層
に接続される第一の配線導体層および光半導体素子に電
気的に接続される第二の配線導体層とを具備したことに
より、光半導体装置の組立工程でサブキャリアをコレッ
ト等の搬送治具で挟んで移動させた際に、搬送治具の接
触等によって第一および第二の配線導体層に断線不良や
導通抵抗の増大等が発生するのを防止することができ
る。また、絶縁基台の上面と側面に別々に第一,第二の
配線導体層を形成すると、上面と側面との間の稜部が一
つの稜線(角部)ではなく第一および第二の段差が形成
されているため、上面に第一および第二の配線導体層を
形成する際に上面に直交する第一および第二の段差の内
面にも導体が廻り込んで形成され、また側面に第一およ
び第二の配線導体層を形成する際に側面に直交する第一
および第二の段差の内面にも導体が廻り込んで形成され
るため、第一および第二の段差の内面に重複して導体が
形成されることとなり、第一および第二の段差において
電気的接続の信頼性が向上する。
The subcarrier of the optical semiconductor device according to the present invention is an insulating substrate in which first and second steps are formed by partially cutting out between the upper surface and one side surface of a substantially rectangular insulating substrate. The base, a conductor layer formed on one side of the insulating base, to which the optical semiconductor element is bonded, and a conductor formed from the upper surface of the insulating base to one side via the first step or the second step. By providing a first wiring conductor layer connected to the layer and a second wiring conductor layer electrically connected to the optical semiconductor element, the subcarrier can be transported by collet or the like in the assembly process of the optical semiconductor device. It is possible to prevent the first and second wiring conductor layers from suffering from a disconnection failure, an increase in conduction resistance, and the like due to contact of the transport jig and the like when being moved by being held by the tool. In addition, when the first and second wiring conductor layers are separately formed on the upper surface and the side surface of the insulating base, the ridge between the upper surface and the side surface is not one ridge line (corner) but the first and second wiring conductor layers. Since the steps are formed, the conductor is also formed around the inner surfaces of the first and second steps orthogonal to the upper surface when forming the first and second wiring conductor layers on the upper surface, and on the side surfaces. When the first and second wiring conductor layers are formed, the conductor also extends around the inner surfaces of the first and second steps which are orthogonal to the side surfaces, and thus overlaps the inner surfaces of the first and second steps. As a result, the conductor is formed, and the reliability of the electrical connection is improved at the first and second steps.

【0040】本発明の光半導体装置は、上面に凹部が形
成されているとともに凹部から外側面にかけて形成され
た貫通孔を有する基体と、貫通孔に嵌着された筒状の光
ファイバ固定部材と、凹部の底面に載置された本発明の
サブキャリアと、サブキャリアの導体層に接合されると
ともに第一および第二の配線導体層に電気的に接続され
た光半導体素子と、基体の上面の凹部の周囲に接合され
た蓋体とを具備したことにより、電気的接続の信頼性の
高い光半導体素子搭載用のサブキャリアを用いた高信頼
性のものとなる。
The optical semiconductor device of the present invention comprises a base having a concave portion formed on the upper surface and having a through hole formed from the concave portion to the outer surface, a cylindrical optical fiber fixing member fitted into the through hole. A subcarrier of the present invention mounted on the bottom surface of the concave portion, an optical semiconductor element joined to the conductor layer of the subcarrier and electrically connected to the first and second wiring conductor layers, and an upper surface of the base And a lid joined to the periphery of the concave portion described above, thereby achieving high reliability using a subcarrier for mounting an optical semiconductor element having high electrical connection reliability.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の光半導体装置について実施の形態の一
例を示す断面図である。
FIG. 1 is a cross-sectional view illustrating an example of an embodiment of an optical semiconductor device of the present invention.

【図2】本発明のサブキャリアについて実施の形態の一
例を示す斜視図である。
FIG. 2 is a perspective view showing an example of an embodiment of a subcarrier of the present invention.

【図3】本発明のサブキャリアについて実施の形態の他
の例を示す斜視図である。
FIG. 3 is a perspective view showing another example of the embodiment of the subcarrier of the present invention.

【図4】本発明のサブキャリアについて実施の形態の他
の例を示す斜視図である。
FIG. 4 is a perspective view showing another example of the embodiment of the subcarrier of the present invention.

【図5】従来の光半導体装置を示す断面図である。FIG. 5 is a sectional view showing a conventional optical semiconductor device.

【図6】従来のサブキャリアを示す斜視図である。FIG. 6 is a perspective view showing a conventional subcarrier.

【符号の説明】[Explanation of symbols]

1:絶縁基台 2:PD 4:LD 8:基体 9:蓋体 10:光ファイバ固定部材 13:絶縁基材 14b:第一の配線パターン 14c:第二の配線パターン 15:段差 1: Insulation base 2: PD 4: LD 8: Substrate 9: Lid 10: Optical fiber fixing member 13: Insulating base material 14b: First wiring pattern 14c: Second wiring pattern 15: Step

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 略直方体の絶縁基材の上面と一側面との
間に一部を切り欠いた第一および第二の段差が形成され
た絶縁基台と、該絶縁基台の前記一側面に形成された、
光半導体素子が接合される導体層と、前記絶縁基台の前
記上面から前記第一の段差または前記第二の段差を経て
前記一側面にかけて形成された、前記導体層に接続され
る第一の配線導体層および前記光半導体素子に電気的に
接続される第二の配線導体層とを具備したことを特徴と
する光半導体素子のサブキャリア。
1. An insulating base in which first and second steps having a part cut away between an upper surface and a side surface of a substantially rectangular parallelepiped insulating base are formed, and the one side surface of the insulating base. Formed in the
A conductor layer to which an optical semiconductor element is joined, and a first layer connected to the conductor layer formed from the upper surface of the insulating base to the one side surface via the first step or the second step. A subcarrier for an optical semiconductor device, comprising: a wiring conductor layer; and a second wiring conductor layer electrically connected to the optical semiconductor device.
【請求項2】 上面に凹部が形成されているとともに該
凹部から外側面にかけて形成された貫通孔を有する基体
と、前記貫通孔に嵌着された筒状の光ファイバ固定部材
と、前記凹部の底面に載置された請求項1記載のサブキ
ャリアと、該サブキャリアの前記導体層に接合されると
ともに前記第一および第二の配線導体層に電気的に接続
された光半導体素子と、前記基体の上面の前記凹部の周
囲に接合された蓋体とを具備したことを特徴とする光半
導体装置。
2. A base having a concave portion formed on the upper surface and having a through hole formed from the concave portion to the outer surface, a cylindrical optical fiber fixing member fitted into the through hole, The subcarrier according to claim 1 mounted on a bottom surface, and an optical semiconductor element bonded to the conductor layer of the subcarrier and electrically connected to the first and second wiring conductor layers, An optical semiconductor device, comprising: a lid joined to the periphery of the concave portion on the upper surface of the base.
JP2002154409A 2002-05-28 2002-05-28 Subcarrier of optical semiconductor element and optical semiconductor device Expired - Fee Related JP3987765B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002154409A JP3987765B2 (en) 2002-05-28 2002-05-28 Subcarrier of optical semiconductor element and optical semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002154409A JP3987765B2 (en) 2002-05-28 2002-05-28 Subcarrier of optical semiconductor element and optical semiconductor device

Publications (2)

Publication Number Publication Date
JP2003347562A true JP2003347562A (en) 2003-12-05
JP3987765B2 JP3987765B2 (en) 2007-10-10

Family

ID=29771222

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002154409A Expired - Fee Related JP3987765B2 (en) 2002-05-28 2002-05-28 Subcarrier of optical semiconductor element and optical semiconductor device

Country Status (1)

Country Link
JP (1) JP3987765B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006040987A (en) * 2004-07-23 2006-02-09 Nichia Chem Ind Ltd Semiconductor laser package
JP2007123464A (en) * 2005-10-27 2007-05-17 Kyocera Corp Subcarrier and semiconductor device
CN115004070A (en) * 2020-01-22 2022-09-02 古河电气工业株式会社 Semiconductor device with a plurality of transistors
CN115004070B (en) * 2020-01-22 2024-05-10 古河电气工业株式会社 Semiconductor device with a semiconductor element having a plurality of electrodes

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006040987A (en) * 2004-07-23 2006-02-09 Nichia Chem Ind Ltd Semiconductor laser package
JP4635501B2 (en) * 2004-07-23 2011-02-23 パナソニック株式会社 Laser diode package
JP2007123464A (en) * 2005-10-27 2007-05-17 Kyocera Corp Subcarrier and semiconductor device
JP4688632B2 (en) * 2005-10-27 2011-05-25 京セラ株式会社 Subcarrier and semiconductor device
CN115004070A (en) * 2020-01-22 2022-09-02 古河电气工业株式会社 Semiconductor device with a plurality of transistors
CN115004070B (en) * 2020-01-22 2024-05-10 古河电气工业株式会社 Semiconductor device with a semiconductor element having a plurality of electrodes

Also Published As

Publication number Publication date
JP3987765B2 (en) 2007-10-10

Similar Documents

Publication Publication Date Title
JP3500304B2 (en) Semiconductor element support member and semiconductor element storage package using the same
JP2003347562A (en) Sub carrier of optical semiconductor device and optical semiconductor device
JP4035028B2 (en) Subcarrier of optical semiconductor element and optical semiconductor device
JP2004296948A (en) Subcarrier for optical semiconductor element and optical semiconductor device
JP4688632B2 (en) Subcarrier and semiconductor device
JP2004282027A (en) Submount
JP4404649B2 (en) Subcarrier of optical semiconductor element and optical semiconductor device
JP2003273372A (en) Optical semiconductor device
JP3623179B2 (en) Semiconductor element storage package and semiconductor device
JP2002314186A (en) Package for storing optical semiconductor element and optical semiconductor device
JP2006310378A (en) Submount and mounting method of electronic element
JP4726457B2 (en) Submount
JP4160888B2 (en) I / O terminal and semiconductor element storage package and semiconductor device
JP2006156585A (en) Sub mount and electronic device using it
JP2005244543A (en) Package for accommodating piezoelectric vibrator and piezoelectric device
JP2007095930A (en) Submount and semiconductor device
JP4467320B2 (en) Subcarrier of optical semiconductor element and optical semiconductor device
JP3628187B2 (en) Semiconductor element support member and semiconductor element storage package using the same
JP2004087683A (en) Packaging for housing i/o terminal and semiconductor element and semiconductor device
JP2002246494A (en) Package for accommodating semiconductor device
JP2008034580A (en) Submount, electronic apparatus, and mounting method of electronic element
JP2003068929A (en) Substrate for loading semiconductor element and semiconductor device
JP4018964B2 (en) I / O terminal and semiconductor element storage package
JP2001036185A (en) Ceramic terminal and package for optical semiconductor element
JP2012227482A (en) Electronic component mounting package and electronic device using the same

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20041018

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20070314

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070320

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070521

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20070619

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20070713

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100720

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100720

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110720

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120720

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120720

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130720

Year of fee payment: 6

LAPS Cancellation because of no payment of annual fees