JP2002246494A - Package for accommodating semiconductor device - Google Patents

Package for accommodating semiconductor device

Info

Publication number
JP2002246494A
JP2002246494A JP2001044033A JP2001044033A JP2002246494A JP 2002246494 A JP2002246494 A JP 2002246494A JP 2001044033 A JP2001044033 A JP 2001044033A JP 2001044033 A JP2001044033 A JP 2001044033A JP 2002246494 A JP2002246494 A JP 2002246494A
Authority
JP
Japan
Prior art keywords
hole
lead wire
frame
input
thermoelectric cooling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001044033A
Other languages
Japanese (ja)
Other versions
JP3642739B2 (en
Inventor
Emi Koiso
絵美 小磯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2001044033A priority Critical patent/JP3642739B2/en
Publication of JP2002246494A publication Critical patent/JP2002246494A/en
Application granted granted Critical
Publication of JP3642739B2 publication Critical patent/JP3642739B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

PROBLEM TO BE SOLVED: To normally and safely operate a semiconductor device for a long time by improving strength against pull in the lead wire of a thermoelectric cooling element, by firmly jointing the lead wire of the thermoelectric cooling element to the metallized wiring layer of an I/O terminal, and by securing continuity. SOLUTION: The connection section in the I/O terminal 3 is provided at a flat section in the formation section of the metallized wiring layer 11 inside a frame body 2 through the upper and lower surfaces; at the same time, a through-hole 3d and a metallized layer are formed; and in the through-hole 3d, a step section is formed. At the step section, inside diameters become small from the upper-surface-side opening to the inside. On the inner surface of the through-hole 3d, the metallized layer is formed, and a lead wire 13 is inserted into the through-hole 3d for brazing.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体素子を収納
するための半導体素子収納用パッケージに関し、特に半
導体素子収納用パッケージに設けられる入出力端子にお
ける熱電冷却素子のリード線の接続部を改善したものに
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device housing package for housing a semiconductor device, and more particularly to an improved connection portion of a lead wire of a thermoelectric cooling element at an input / output terminal provided in the semiconductor device housing package. About things.

【０００２】[0002]

【従来の技術】従来、マイクロ波帯やミリ波帯等の高周
波信号を用いる半導体素子を収納するための半導体素子
収納用パッケージ（以下、半導体パッケージという）を
図４〜図７に示す。これらの図において、１０１は基
体、１０２は枠体、１０３は入出力端子、１０５は蓋
体、１０６は半導体素子を示す。これら基体１０１、枠
体１０２、入出力端子１０３、蓋体１０５とで、半導体
素子１０６を半導体パッケージ内に収容する。2. Description of the Related Art Conventionally, semiconductor device housing packages (hereinafter, referred to as semiconductor packages) for housing a semiconductor device using a high frequency signal such as a microwave band or a millimeter wave band are shown in FIGS. In these figures, 101 is a base, 102 is a frame, 103 is an input / output terminal, 105 is a lid, and 106 is a semiconductor element. The base 101, the frame 102, the input / output terminals 103, and the lid 105 accommodate the semiconductor element 106 in a semiconductor package.

【０００３】基体１０１は、半導体素子１０６を載置す
る載置部１０１ａを有し、載置部１０１ａには半導体素
子１０６が熱電冷却素子１０８を間に介して金（Ａｕ）
−シリコン（Ｓｉ）ロウ材等の接着剤により接着固定さ
れるものであり、鉄（Ｆｅ）−ニッケル（Ｎｉ）−コバ
ルト（Ｃｏ）合金や銅（Ｃｕ）−タングステン（Ｗ）合
金等の金属材料から成る。The base 101 has a mounting portion 101a on which a semiconductor element 106 is mounted. The semiconductor element 106 is mounted on the mounting portion 101a with a thermoelectric cooling element 108 interposed therebetween.
A metal material such as an iron (Fe) -nickel (Ni) -cobalt (Co) alloy or a copper (Cu) -tungsten (W) alloy, which is bonded and fixed by an adhesive such as silicon (Si) brazing material; Consists of

【０００４】枠体１０２は、基体１０１の上面に載置部
１０１ａを囲繞するように銀ロウ等のロウ材で接合さ
れ、側部に入出力端子１０３を嵌着する取付部１０２ａ
が形成されたものであり、Ｆｅ−Ｎｉ−Ｃｏ合金やＦｅ
−Ｎｉ合金等の金属材料から成る。The frame body 102 is joined to the upper surface of the base body 101 with a brazing material such as silver brazing so as to surround the mounting portion 101a, and a mounting portion 102a to which the input / output terminal 103 is fitted on the side.
Are formed, and an Fe—Ni—Co alloy or Fe
-It is made of a metal material such as a Ni alloy.

【０００５】入出力端子１０３は、アルミナ（Ａｌ
2Ｏ3），窒化アルミニウム（ＡｌＮ），ムライト（３Ａ
ｌ2Ｏ3・２ＳｉＯ2）等のセラミックスから成り、枠体
１０２の内外に突出する平板部の突出部１０３ａ，１０
３ｂと枠体１０２に嵌着される立壁部１０３ｃとを有し
ており、半導体パッケージの内外を導出するようにモリ
ブデン（Ｍｏ）−マンガン（Ｍｎ），タングステン
（Ｗ）等から成る金属ペーストを焼結したメタライズ配
線層１１１が平板部の上面に被着されて半導体素子１０
６と外部電気回路基板とを電気的に接続する。[0005] The input / output terminal 103 is made of alumina (Al).
2 O 3 ), aluminum nitride (AlN), mullite (3A
l 2 O 3 · 2SiO 2) made of ceramics or the like, the protruding portion 103a of the plate portion which projects into and out of the frame 102, 10
3b and a vertical wall portion 103c fitted to the frame 102. A metal paste made of molybdenum (Mo) -manganese (Mn), tungsten (W), or the like is fired so as to lead the inside and outside of the semiconductor package. The connected metallized wiring layer 111 is attached on the upper surface of
6 and an external electric circuit board.

【０００６】また、入出力端子１０３は、枠体１０２を
貫通してまたは切り欠いて形成された取付部１０２ａに
銀ロウ等のロウ材で嵌着される。The input / output terminal 103 is fitted to a mounting portion 102a formed through or cut out of the frame 102 with a brazing material such as silver brazing.

【０００７】その入出力端子１０３の熱電冷却素子１０
８のリード線１１３の接続部は、図４，図５，図６のよ
うに、入出力端子１０３のメタライズ配線層１１１形成
部内に設けられ、平板部の上面から下面にかけて同一の
大きさに切り欠かれた貫通孔１０３ｊ、切欠部１０３ｋ
が形成されていることから、リード線１１３を正確かつ
容易に所定の位置に位置決めすることができ、その結
果、リード線１１３をメタライズ配線層１１１に正確か
つ容易に電気的に接続させることができるものが提案さ
れている（特開平８−３７２４７号公報参照）。The thermoelectric cooling element 10 of the input / output terminal 103
8, the connection part of the lead wire 113 is provided in the metallized wiring layer 111 forming part of the input / output terminal 103 as shown in FIGS. 4, 5, and 6, and is cut into the same size from the upper surface to the lower surface of the flat plate part. Chipped through hole 103j, notch 103k
Is formed, lead wire 113 can be accurately and easily positioned at a predetermined position, and as a result, lead wire 113 can be accurately and easily electrically connected to metallized wiring layer 111. One has been proposed (see JP-A-8-37247).

【０００８】リード端子１１４は、入出力端子１０３の
メタライズ配線層１１１に銀ロウ等のロウ材を介して接
合され、外部電気回路と入出力端子１０３との高周波信
号の入出力を行うものであり、Ｆｅ−Ｎｉ−Ｃｏ合金等
の金属材料から成る。The lead terminal 114 is connected to the metallized wiring layer 111 of the input / output terminal 103 via a brazing material such as silver brazing, and inputs and outputs a high-frequency signal between the external electric circuit and the input / output terminal 103. , Fe-Ni-Co alloy and the like.

【０００９】シールリング１０４は、枠体１０２の上面
に銀ロウ等のロウ材で接合され入出力端子１０３を上方
より挟持するとともに、上面に蓋体１０５をシーム溶接
等により接合するための接合媒体として機能する。The seal ring 104 is joined to the upper surface of the frame 102 with a brazing material such as silver brazing, and holds the input / output terminal 103 from above, and also joins the lid 105 to the upper surface by seam welding or the like. Function as

【００１０】また、メタライズ配線層１１１の枠体１０
２外側には、外部電気回路との高周波信号の入出力を行
うために、導電性を有するＦｅ−Ｎｉ−Ｃｏ合金等の金
属材料から成るリード端子１１４が銀ロウ等のロウ材で
接合されるとともに、半導体素子１０６と電気的に接続
するためのボンディングワイヤー１１２が接合される。The frame 10 of the metallized wiring layer 111
On the outside, a lead terminal 114 made of a metal material such as a conductive Fe-Ni-Co alloy is joined with a brazing material such as silver brazing to input and output a high-frequency signal to and from an external electric circuit. At the same time, a bonding wire 112 for electrically connecting to the semiconductor element 106 is joined.

【００１１】そして、図７に示すように、基体１０１の
載置部１０１ａに半導体素子１０６を熱電冷却素子１０
８を間に介して接着固定し、半導体素子１０６の各電極
をボンディングワイヤー１１２を介してメタライズ配線
層１１１に接続するとともに、熱電冷却素子１０８の電
極に接続されたリード線１１３をメタライズ配線層１１
１に半田を介して電気的に接続する。次に、枠体１０２
の上面に蓋体１０５を接合し、基体１０１と枠体１０２
と入出力端子１０３とシールリング１０４と蓋体１０５
とから成る容器１０７の内部に、半導体素子１０６及び
熱電冷却素子１０８を気密に収容する。最後に、枠体１
０２の光ファイバ固定部材１１０に光ファイバ１０９の
一端を挿通させるとともに、これを半田等の接着剤やレ
ーザ溶接によって接合させ、光ファイバ１０９を枠体１
０２に固定することによって最終製品としての半導体装
置となる。そして、この半導体装置において、光ファイ
バ１０９を介して内部に収容する半導体素子１０６と外
部との光信号の授受が可能となる。Then, as shown in FIG. 7, the semiconductor element 106 is mounted on the mounting portion 101a of the
8, the electrodes of the semiconductor element 106 are connected to the metallized wiring layer 111 via bonding wires 112, and the lead wires 113 connected to the electrodes of the thermoelectric cooling element 108 are connected to the metallized wiring layer 11
1 is electrically connected via solder. Next, the frame 102
The lid 105 is joined to the upper surface of the
, Input / output terminal 103, seal ring 104, lid 105
The semiconductor element 106 and the thermoelectric cooling element 108 are hermetically accommodated in a container 107 composed of Finally, frame 1
The optical fiber 109 is inserted through one end of the optical fiber 109 through the optical fiber fixing member 110, and the optical fiber 109 is bonded by an adhesive such as solder or laser welding.
By fixing to 02, a semiconductor device as a final product is obtained. In this semiconductor device, an optical signal can be exchanged between the semiconductor element 106 housed therein and the outside via the optical fiber 109.

【００１２】[0012]

【発明が解決しようとする課題】しかしながら、上記の
特開平８−３７２４７号公報に提案された半導体パッケ
ージでは、熱電冷却素子１０８のリード線１１３を半田
付けするとき、半田が溜まる範囲は入出力端子１０３の
平板部の上面に施したメタライズ配線層１１１のみであ
り、その結果リード線１１３が線方向の引っ張りに対す
る強度が不十分となり、リード線１１３が外れ易くなっ
て半導体素子１０６の冷却が不能になったり冷却効率が
大きく低下する場合があった。また、線方向の引っ張り
に対する強度を上げようとして、半田の体積を増やした
としても、隣接するメタライズ配線層１１１に半田が流
れてしまい、メタライズ配線層１１１間に半田ブリッジ
が発生し短絡する場合があった。However, in the semiconductor package proposed in the above-mentioned Japanese Patent Application Laid-Open No. 8-37247, when the lead wire 113 of the thermoelectric cooling element 108 is soldered, the area where the solder accumulates is limited to the input / output terminals. Only the metallized wiring layer 111 provided on the upper surface of the flat plate portion 103 is formed. As a result, the strength of the lead wire 113 against pulling in the linear direction becomes insufficient, and the lead wire 113 is easily detached, so that the semiconductor element 106 cannot be cooled. In some cases, the cooling efficiency was greatly reduced. Further, even if the volume of the solder is increased in order to increase the strength against the pull in the line direction, the solder flows to the adjacent metallized wiring layer 111, and a solder bridge may be generated between the metallized wiring layers 111 to cause a short circuit. there were.

【００１３】また、図６のように、入出力端子１０３の
平板部に切欠部１０３ｋを形成すると、半田の冷熱収縮
の際に接合部分の半田にクラックや割れ等が発生した場
合、熱電冷却素子１０８のリード線１１３が切欠部１０
３ｋから外れて、平板部の端面から枠体１０２の内側へ
移動し、他の配線等と接触し電気的に短絡するという問
題点があった。Further, as shown in FIG. 6, when a notch 103k is formed in a flat plate portion of the input / output terminal 103, when a crack or a crack is generated in the solder at the joint portion during the thermal shrinkage of the solder, the thermoelectric cooling element 108 lead wire 113 is notch 10
3k, there is a problem that it moves from the end face of the flat plate portion to the inside of the frame body 102 and comes into contact with other wirings and the like to cause an electrical short circuit.

【００１４】従って、本発明は上記問題点に鑑み完成さ
れたものであり、その目的は、熱電冷却素子のリード線
の線方向への引っ張りに対する強度を向上させ、さらに
そのリード線と入出力端子のメタライズ配線層との接合
を強固なものとし、導通を確実なものとすることによ
り、半導体素子を長期間にわたり正常かつ安定に作動さ
せることである。SUMMARY OF THE INVENTION Accordingly, the present invention has been completed in view of the above problems, and an object of the present invention is to improve the strength of a thermoelectric cooling element in pulling a lead wire in a line direction, and further improve the lead wire and input / output terminals. The purpose of the present invention is to make the semiconductor element operate normally and stably for a long period of time by strengthening the bonding with the metallized wiring layer and ensuring the conduction.

【００１５】[0015]

【課題を解決するための手段】本発明の半導体パッケー
ジは、上面に半導体素子が熱電冷却素子を介して載置さ
れる載置部を有する基体と、該基体の上面に前記載置部
を囲繞するように取着された金属製の枠体と、該枠体を
貫通してまたは切り欠いて形成された入出力端子の取付
部と、上面の一辺側から対向する他辺側にかけて形成さ
れた複数のメタライズ配線層を有する誘電体から成る平
板部および該平板部の上面に前記複数のメタライズ配線
層を間に挟んで接合された誘電体から成る立壁部から構
成されるとともに前記枠体内側の前記メタライズ配線層
に前記熱電冷却素子のリード線の接続部を有して前記取
付部に嵌着された前記入出力端子とを具備して成り、前
記枠体の上面に蓋体が接合される半導体素子収納用パッ
ケージにおいて、前記入出力端子の前記接続部は、前記
枠体内側の前記メタライズ配線層の形成部内の前記平板
部に上下面を貫通して設けられ、かつ上面側開口から内
側にかけて内寸法が小となる段差部が形成された貫通孔
と、該貫通孔の内面に形成されたメタライズ層とから成
り、前記貫通孔に前記リード線が挿入されろう付けされ
ていることを特徴とする。According to the present invention, there is provided a semiconductor package including a base having a mounting portion on which a semiconductor element is mounted via a thermoelectric cooling element, and surrounding the mounting portion on the upper surface of the base. A metal frame attached so as to be attached, an input / output terminal mounting portion formed through or cut out of the frame, and formed from one side of the upper surface to the other side facing the same. A flat plate portion made of a dielectric having a plurality of metallized wiring layers, and an upright wall portion made of a dielectric joined to the upper surface of the flat plate portion with the plurality of metallized wiring layers interposed therebetween, The metallized wiring layer includes a connection portion for a lead wire of the thermoelectric cooling element, and the input / output terminal fitted to the attachment portion, and a lid is joined to an upper surface of the frame. In semiconductor device storage packages, The connection portion of the writing output terminal is provided on the flat plate portion in the formation portion of the metallized wiring layer inside the frame body so as to penetrate the upper and lower surfaces, and the step portion whose inner dimension becomes smaller from the upper surface side opening to the inner side. And a metallized layer formed on the inner surface of the through hole, wherein the lead wire is inserted into the through hole and brazed.

【００１６】本発明は、上記の構成により、入出力端子
の接続部は、枠体内側のメタライズ配線層の形成部内の
平板部に上下面を貫通して設けられ、かつ上面側開口か
ら内側にかけて内寸法が小となる段差部が形成された貫
通孔と、貫通孔の内面に形成されたメタライズ層とから
成り、貫通孔にリード線が挿入されろう付け接続されて
いることから、貫通孔の内部に半田溜まりを設けること
ができ、半田の体積を増やして接続強度を向上させ得
る。また、組み立て作業中やろう付け後の熱収縮によ
り、リード線を下方に引っ張るような外力が加わること
が多いが、この外力に対する強度がきわめて向上し、リ
ード線の外れを解消することができる。また、ろう材の
断面積が大きくなるため、接合部の電気抵抗値を下げる
ことができ、熱電冷却素子を駆動するための電力を十分
に供給し得、熱電冷却素子及び半導体素子の動作が安定
化する。According to the present invention, with the above structure, the connection portion of the input / output terminal is provided through the upper and lower surfaces of the flat plate portion in the formation portion of the metallized wiring layer inside the frame, and extends from the upper side opening to the inside. The through hole is formed with a step portion having a small internal dimension, and a metallized layer formed on the inner surface of the through hole, and since a lead wire is inserted into the through hole and brazed, the A solder pool can be provided inside, and the volume of the solder can be increased to improve the connection strength. In addition, an external force that pulls the lead wire downward is often applied due to heat shrinkage during the assembling work or after brazing. However, the strength against this external force is extremely improved, and the lead wire can be prevented from coming off. In addition, since the cross-sectional area of the brazing filler metal is increased, the electric resistance value of the joint can be reduced, sufficient power for driving the thermoelectric cooling element can be supplied, and the operation of the thermoelectric cooling element and the semiconductor element can be stabilized. Become

【００１７】本発明において、好ましくは、前記貫通孔
の上面側開口の幅に対する下面側開口の幅の比が０．４
〜０．９であることを特徴とする。In the present invention, preferably, the ratio of the width of the lower surface side opening to the width of the upper surface side opening of the through hole is 0.4.
０．９0.9.

【００１８】本発明は、上記の構成により、半田溜まり
を設け、半田の体積を増やして接続強度を大きくできる
ととともに、リード線を下方に引っ張るような外力に対
する強度がさらに高くなる。また、ろう材とメタライズ
層との接合面積がさらに増えるため、強固に熱電冷却素
子のリード線とメタライズ配線層を半田付けでき、その
結果熱電冷却素子の接続信頼性が向上し、外部からの衝
撃等で接合部が外れることがなくなる。According to the present invention, with the above structure, the solder pool is provided, the volume of the solder can be increased, the connection strength can be increased, and the strength against external force such as pulling the lead wire downward is further increased. In addition, the joint area between the brazing material and the metallized layer is further increased, so that the lead wires of the thermoelectric cooling element and the metallized wiring layer can be firmly soldered. As a result, the connection reliability of the thermoelectric cooling element is improved, and external shocks Thus, the joint portion does not come off.

【００１９】[0019]

【発明の実施の形態】本発明の半導体パッケージについ
て以下に詳細に説明する。図１は本発明の半導体パッケ
ージの実施の形態を示す斜視図であり、図２，図８は図
１の入出力端子を示し、図２，図８において、（ａ）は
入出力端子の斜視図、（ｂ）は貫通孔の拡大断面図、
（ｃ）は貫通孔の他の例を示す拡大断面図である。ま
た、図３は図１に示す半導体パッケージに半導体素子を
収容したものの断面図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS The semiconductor package of the present invention will be described in detail below. FIG. 1 is a perspective view showing an embodiment of a semiconductor package according to the present invention. FIGS. 2 and 8 show the input / output terminals of FIG. 1, and FIG. 2 and FIG. FIG. 3B is an enlarged sectional view of the through hole.
(C) is an enlarged sectional view showing another example of the through hole. FIG. 3 is a sectional view of a semiconductor package housed in the semiconductor package shown in FIG.

【００２０】図１において、１は基体、２は枠体、３は
入出力端子、４はシールリング、５は蓋体であり、これ
らで半導体素子６を内部に収容するための容器７（図
３）が主に構成される。In FIG. 1, 1 is a base, 2 is a frame, 3 is an input / output terminal, 4 is a seal ring, and 5 is a lid. These are containers 7 (see FIG. 1) for accommodating a semiconductor element 6 therein. 3) is mainly configured.

【００２１】図１において、１は基体であり、その上面
にはＩＣ，ＬＳＩ，半導体レーザ（ＬＤ），フォトダイ
オード（ＰＤ）等の半導体素子６が熱電冷却素子８を間
に介して載置するための載置部１ａを有している。In FIG. 1, reference numeral 1 denotes a base, on which a semiconductor element 6 such as an IC, an LSI, a semiconductor laser (LD), a photodiode (PD) is mounted with a thermoelectric cooling element 8 interposed therebetween. Mounting section 1a for mounting.

【００２２】この基体１は、Ｆｅ−Ｎｉ−Ｃｏ合金やＣ
ｕ−Ｗ等の金属材料や、アルミナ，窒化アルミニウム，
ムライト等のセラミックスから成り、金属材料から成る
場合、例えば、Ｆｅ−Ｎｉ−Ｃｏ合金のインゴット
（塊）に圧延加工や打ち抜き加工等の従来周知の金属加
工法を施すことによって所定の形状に製作される。一
方、セラミックスから成る場合、その原料粉末に適当な
有機バインダや溶剤等を添加混合しペースト状と成すと
ともに、このペーストをドクターブレード法やカレンダ
ーロール法によってセラミックグリーンシートと成し、
しかる後セラミックグリーンシートに適当な打ち抜き加
工を施し、これを複数枚積層し焼成することによって作
製される。The substrate 1 is made of an Fe—Ni—Co alloy or C
metal materials such as u-W, alumina, aluminum nitride,
When made of a ceramic material such as mullite and made of a metal material, for example, it is manufactured into a predetermined shape by applying a conventionally known metal working method such as rolling or punching to an ingot of an Fe-Ni-Co alloy. You. On the other hand, in the case of ceramics, a suitable organic binder and a solvent are added to the raw material powder and mixed to form a paste.At the same time, the paste is formed into a ceramic green sheet by a doctor blade method or a calender roll method.
Thereafter, the ceramic green sheet is appropriately punched, and a plurality of the green sheets are laminated and fired.

【００２３】なお、基体１が金属材料からなる場合、そ
の表面に耐蝕性に優れかつロウ材との濡れ性に優れる金
属、具体的には厚さ０．５〜９μｍのＮｉ層と、厚さ
０．５〜５μｍのＡｕ層を順次メッキ法により被着させ
ておくのがよく、基体１が酸化腐蝕するのを有効に防止
できるとともに、基体１の上面の載置部１ａに半導体素
子６を熱電冷却素子８を間に介して強固に接着固定させ
ることができる。When the substrate 1 is made of a metal material, a metal having excellent corrosion resistance and excellent wettability with a brazing material, specifically, a Ni layer having a thickness of 0.5 to 9 μm, It is preferable that an Au layer having a thickness of 0.5 to 5 μm is sequentially applied by a plating method, so that the base 1 can be effectively prevented from being oxidized and corroded, and the semiconductor element 6 is mounted on the mounting portion 1 a on the upper surface of the base 1. The thermoelectric cooling element 8 can be firmly adhered and fixed with the interposition.

【００２４】一方、基体１がセラミックスから成る場
合、半導体素子６を熱電冷却素子８を間に介して載置す
る載置部１ａに耐蝕性に優れかつロウ材との濡れ性に優
れる金属、具体的には厚さ０．５〜９μｍのＮｉ層と、
厚さ０．５〜５μｍのＡｕ層を順次メッキ法により被着
させておくのがよく、基体１の上面の載置部１ａに半導
体素子６を熱電冷却素子８を間に介して強固に接着固定
させることができる。On the other hand, when the substrate 1 is made of ceramics, a metal having excellent corrosion resistance and excellent wettability with the brazing material is provided on the mounting portion 1a on which the semiconductor element 6 is mounted with the thermoelectric cooling element 8 interposed therebetween. Specifically, a Ni layer having a thickness of 0.5 to 9 μm,
It is preferable that an Au layer having a thickness of 0.5 to 5 μm is sequentially applied by plating, and the semiconductor element 6 is firmly adhered to the mounting portion 1 a on the upper surface of the base 1 with the thermoelectric cooling element 8 interposed therebetween. Can be fixed.

【００２５】枠体２は、基体１上に載置部１ａを囲繞す
るように取着され、Ｆｅ−Ｎｉ−Ｃｏ合金やＦｅ−Ｎｉ
合金等の金属材料から成る。例えば、Ｆｅ−Ｎｉ−Ｃｏ
合金のインゴットをプレス加工により所定の枠状となす
ことによって製作される。The frame 2 is mounted on the base 1 so as to surround the mounting portion 1a, and is made of an Fe--Ni--Co alloy or an Fe--Ni alloy.
It is made of a metal material such as an alloy. For example, Fe-Ni-Co
It is manufactured by forming an ingot of an alloy into a predetermined frame shape by press working.

【００２６】また、枠体２には、内部に収容する半導体
素子６との間で光信号を授受するための光ファイバ９が
挿通固定される光ファイバ固定部材１０が枠体２を貫通
して銀ロウ等のロウ材を介して接合される。この光ファ
イバ固定部材１０は、Ｆｅ−Ｎｉ−Ｃｏ合金やＦｅ−Ｎ
ｉ合金等の金属から成り、例えば、Ｆｅ−Ｎｉ合金のイ
ンゴットをプレス加工することにより所定の筒状に製作
される。The frame 2 has an optical fiber fixing member 10 through which an optical fiber 9 for transmitting and receiving an optical signal to and from the semiconductor element 6 housed therein is inserted and fixed. It is joined via a brazing material such as silver brazing. The optical fiber fixing member 10 is made of a Fe—Ni—Co alloy or a Fe—N
It is made of a metal such as an i-alloy, and is manufactured into a predetermined cylindrical shape by, for example, pressing an ingot of an Fe-Ni alloy.

【００２７】また、光ファイバ固定部材１０は、光ファ
イバ９を挿通可能な軸方向の貫通孔１０ａを有する筒体
であり、貫通孔１０ａに光ファイバ９の一端を挿通させ
るとともにこれを半田等の接着剤やレーザ溶接により固
定し、これにより光ファイバ９を介して内部に収容する
半導体素子６と外部との光信号の授受が可能となる。The optical fiber fixing member 10 is a cylindrical body having an axial through hole 10a through which the optical fiber 9 can be inserted. One end of the optical fiber 9 is inserted into the through hole 10a and the It is fixed by an adhesive or laser welding, so that an optical signal can be exchanged between the semiconductor element 6 housed inside and the outside via the optical fiber 9.

【００２８】入出力端子３は、基体１，枠体２に熱膨張
係数が近似するアルミナセラミックス等のセラミックス
から成り、枠体２の内外に突出する突出部３ａ，３ｂを
有する平板部と枠体２に嵌着される立壁部３ｃとから構
成され、半導体パッケージの内外を導出するようにＭｏ
−Ｍｎ等から成る金属ペーストを焼結したメタライズ配
線層１１が平板部上面に被着されて、半導体素子６と外
部電気回路基板とを電気的に接続する。The input / output terminal 3 is made of ceramics such as alumina ceramics having a thermal expansion coefficient similar to that of the base 1 and the frame 2, and has a flat plate having projections 3a and 3b projecting in and out of the frame 2, and a frame. And an upright wall 3c fitted to the semiconductor package 2 so that the inside and outside of the semiconductor package can be led out.
A metallized wiring layer 11 obtained by sintering a metal paste made of Mn or the like is attached to the upper surface of the flat plate portion, and electrically connects the semiconductor element 6 to an external electric circuit board.

【００２９】本発明の熱電冷却素子８のリード線１３を
接続するための入出力端子３の平板部に設けた貫通孔３
ｄについて、実施の形態を図２，図８に示す。これら
は、平板部を２層構造とし、貫通孔３ｄの内部の内寸法
が上層側が下層側よりも大きくなるように構成したもの
である。The through-hole 3 formed in the flat plate portion of the input / output terminal 3 for connecting the lead wire 13 of the thermoelectric cooling element 8 of the present invention
An embodiment of d is shown in FIGS. These are configured such that the flat plate portion has a two-layer structure, and the inner size inside the through hole 3d is larger on the upper layer side than on the lower layer side.

【００３０】図２（ｂ）において、３ｆは、熱電冷却素
子８のリード線１３を接続するための入出力端子３の平
板部の上層部であり、３ｇは下層部を示す。貫通孔３ｄ
は、内側の幅が上層部３ｆより下層部３ｇの方で小さい
階段状である。即ち、枠体２内側のメタライズ配線層１
１の形成部内の平板部に上下面を貫通して設けられ、か
つ上面側開口から内側にかけて内寸法が小となる段差部
が形成された貫通孔３ｄである。また、貫通孔３ｄの内
面にはメタライズ層を施している。この構成により、貫
通孔３ｄの内面に半田溜まりを容易に設けることがで
き、半田の体積を増やして接合強度を上げることができ
る。In FIG. 2B, reference numeral 3f denotes an upper layer portion of the flat plate portion of the input / output terminal 3 for connecting the lead wire 13 of the thermoelectric cooling element 8, and 3g denotes a lower layer portion. 3d through hole
Has a stepped shape in which the inner width is smaller in the lower layer portion 3g than in the upper layer portion 3f. That is, the metallized wiring layer 1 inside the frame 2
A through-hole 3d is formed in the flat portion in the formation portion of No. 1 so as to penetrate the upper and lower surfaces, and is formed with a step portion whose inner dimension becomes smaller from the upper surface side opening to the inside. A metallized layer is provided on the inner surface of the through hole 3d. With this configuration, a solder pool can be easily provided on the inner surface of the through hole 3d, and the solder strength can be increased by increasing the volume of the solder.

【００３１】なお、貫通孔３ｄの内側の幅は最大幅を示
すものであり、貫通孔３ｄの断面が円形の場合内側の直
径に相当する。The width inside the through hole 3d indicates the maximum width, and when the cross section of the through hole 3d is circular, it corresponds to the inside diameter.

【００３２】本発明では、貫通孔３ｄの上面側開口の幅
Ｗ１に対する下面側開口の幅Ｗ２の比が０．４〜０．９
であることが好ましい。０．４未満になると、貫通孔３
ｄの下面側開口の幅Ｗ２が小さくなることにより、リー
ド線１３を貫通孔３ｄ内に挿入させるのが困難になった
り、また下層部３ｇの半田溜まり量が少なくなることか
らリード線１３を上方に突き上げるような外力に対する
強度が低下し易くなる。さらに、上層部３ｆと下層部３
ｇとの半田の体積比が大きく異なることにより、半田の
冷熱収縮の際に段差部の角部を起点としてクラックや割
れ等が発生し、リード線１３の接合強度が低下し外れ易
くなる。また０．９を超えると、貫通孔３ｄの内部の段
差部に半田溜まりを設ける部分が少なくなり、半田の体
積を増やすことができず、接続強度を向上させることが
困難となる。In the present invention, the ratio of the width W2 of the lower surface side opening to the width W1 of the upper surface side opening of the through hole 3d is 0.4 to 0.9.
It is preferred that If it is less than 0.4, the through hole 3
Since the width W2 of the lower opening on the lower surface side of d becomes small, it becomes difficult to insert the lead wire 13 into the through hole 3d, and the amount of solder pool in the lower layer portion 3g becomes small, so that the lead wire 13 The strength against an external force such as thrusting is easily reduced. Further, the upper layer 3f and the lower layer 3
When the volume ratio of the solder to g is largely different, cracks and cracks are generated starting from the corners of the step portion during the thermal shrinkage of the solder, and the bonding strength of the lead wire 13 is reduced and easily detached. On the other hand, if it exceeds 0.9, the portion where the solder pool is provided in the step portion inside the through hole 3d is reduced, so that the volume of the solder cannot be increased, and it is difficult to improve the connection strength.

【００３３】貫通孔３ｄの内部の上層部３ｆの深さは、
貫通孔３ｄの全体の深さの１／３以上がよく、この場合
半田溜りを大きくして接合強度を大きくすることができ
る。より好ましくは、上層部３ｆの深さは貫通孔３ｄの
全体の深さの１／２以下がよい。The depth of the upper layer 3f inside the through hole 3d is:
The depth is preferably equal to or more than 1/3 of the entire depth of the through hole 3d. In this case, the solder pool can be increased to increase the bonding strength. More preferably, the depth of the upper layer portion 3f is not more than の of the entire depth of the through hole 3d.

【００３４】さらに、図２（ｃ）に示す構成とすること
もできる。同図において、３ｆ′はリード線１３を接続
するための入出力端子３の平板部の上層部、３ｇ′は下
層部を示し、上層部３ｆ′より下層部３ｇ′の方が小さ
い階段状であり、上層部３ｆ′がさらに２段以上の階段
状になっており、貫通孔３ｄ′の内面にはメタライズ層
を施した構成である。これにより、貫通孔３ｄ′の内面
に半田溜まりをより多く設けることができ、半田の体積
を増やして強度を上げることができる。また、リード線
１３をメタライズ配線層１１にロウ付け接合する際に発
生する応力は、上層部３ｆ′の２段以上の階段状の貫通
孔部分で分散されて小さいものとなり、割れやクラック
を大幅に減少できる。Further, a configuration shown in FIG. 2C can be adopted. In the figure, 3f 'denotes an upper layer portion of the flat plate portion of the input / output terminal 3 for connecting the lead wire 13, 3g' denotes a lower layer portion, and the lower layer portion 3g 'is smaller than the upper layer portion 3f' in a stepped shape. The upper layer portion 3f 'has a stepped shape of two or more steps, and the inner surface of the through hole 3d' is provided with a metallized layer. Thereby, more solder pools can be provided on the inner surface of the through hole 3d ', and the volume of the solder can be increased to increase the strength. Further, the stress generated when the lead wire 13 is joined to the metallized wiring layer 11 by brazing is dispersed in the stepped through-holes of two or more steps in the upper layer portion 3f 'and becomes small, and cracks and cracks are greatly reduced. Can be reduced.

【００３５】また、図８（ｂ）に示す構成とすることも
できる。同図において、３ｈはリード線１３を接続する
ための入出力端子３の平板部の上層部、３ｉは下層部で
あり、上層部３ｈとその上層部３ｈより内寸法が小さい
直線状の下層部３ｉとから成り、上層部３ｈの幅は上面
側開口の幅Ｗ３よりも下端側の幅Ｗ４が大きいこと、例
えば上層部３ｈの側断面形状が上方から下方に向かって
広がる台形になっているのが好ましい。この場合、上層
部３ｈの側面で囲まれる立体形状は半円錐台、角錐台等
の錐台状となる。また、貫通孔３ｅの内面にはメタライ
ズ層を施している。これにより、リード線１３に上方向
の引っ張り力または押し上げ力が加わった場合にも、上
層部３ｈの傾斜した側面が引っ掛かりの機能を発揮し、
引っ張り力または押し上げ力に対する強度を上げること
ができる。Further, the configuration shown in FIG. 8B can be adopted. 3, 3h is an upper layer portion of the flat plate portion of the input / output terminal 3 for connecting the lead wire 13, 3i is a lower layer portion, and an upper layer portion 3h and a linear lower layer portion having an inner dimension smaller than that of the upper layer portion 3h. 3i, the width of the upper layer portion 3h is such that the width W4 at the lower end side is larger than the width W3 of the upper surface side opening, for example, the side section shape of the upper layer portion 3h has a trapezoidal shape that spreads downward from above. Is preferred. In this case, the three-dimensional shape surrounded by the side surface of the upper layer portion 3h is a truncated cone such as a truncated half cone or a truncated pyramid. Further, a metallized layer is formed on the inner surface of the through hole 3e. Thereby, even when an upward pulling force or a pushing-up force is applied to the lead wire 13, the inclined side surface of the upper layer portion 3h exhibits a function of catching,
Strength against pulling force or pushing force can be increased.

【００３６】さらに、図８（ｃ）の構成とすることもで
きる。同図において、３ｈ′はリード線１３を接続する
ための入出力端子３の平板部の上層部、３ｉ′は下層部
であり、上層部３ｈ′の側断面形状が上層から下層に向
かって広がる台形等の錐台状になっていて、さらに上層
部３ｈ′の側断面形状が２段以上の台形になっているこ
とが好ましく、それらの台形の側辺の傾斜角θは同じ角
度であることが好ましい。そして、貫通孔３ｅ′の内面
にはメタライズ層を施している。これにより、リード線
１３に上方向の引っ張り力または押し上げ力が加わった
場合に、上層部３ｈ′の側面が引っ掛かりの機能を発揮
し、引っ張り力または押し上げ力に対する強度をさらに
上げることができる。また、リード線１３をメタライズ
配線層１１にロウ付けする際に発生する応力は、上層部
３ｈ′の２段以上の台形の貫通孔部分で分散されて小さ
いものとなり、割れやクラックを大幅に減少できる。Further, the configuration shown in FIG. 8C can be adopted. In the figure, reference numeral 3h 'denotes an upper layer portion of the flat plate portion of the input / output terminal 3 for connecting the lead wire 13, 3i' denotes a lower layer portion, and a side sectional shape of the upper layer portion 3h 'spreads from the upper layer to the lower layer. It is preferable that the upper layer portion 3h 'is formed in a trapezoidal shape such as a trapezoid, and that the side cross-sectional shape of the upper layer portion 3h' is a trapezoid having two or more steps. Is preferred. A metallized layer is formed on the inner surface of the through hole 3e '. Thereby, when an upward pulling force or a pushing up force is applied to the lead wire 13, the side surface of the upper layer portion 3h 'exerts the function of catching, and the strength against the pulling force or the pushing up force can be further increased. Further, the stress generated when the lead wire 13 is brazed to the metallized wiring layer 11 is dispersed and reduced in the trapezoidal through-holes of two or more steps in the upper layer portion 3h ', thereby greatly reducing cracks and cracks. it can.

【００３７】さらに、台形の側辺の傾斜角θ、即ち段差
部の上部の側面と平板部の上面とのなす角度θは、４５
〜８０°の範囲とすることが好ましく、４５°未満の場
合、上層部３ｈ′の側面が入出力端子３を製造する際の
セラミック積層工程にて撓んで変形して作製が困難とな
り、また８０°を超える場合、リード線１３を上方向に
引っ張る力または押し上げ力に対して、上層部３ｈ′の
側面での引っ掛かりの機能を十分に発揮しないという不
具合が生じ易くなる。Further, the inclination angle θ of the side of the trapezoid, that is, the angle θ formed between the upper side surface of the step portion and the upper surface of the flat plate portion is 45
If the angle is less than 45 °, the side surface of the upper layer portion 3h ′ is bent and deformed in the ceramic laminating step in manufacturing the input / output terminal 3 and becomes difficult to manufacture. When the angle exceeds °, a problem that the function of hooking on the side surface of the upper layer portion 3h 'is not sufficiently exhibited with respect to the force of pulling or pushing up the lead wire 13 easily occurs.

【００３８】メタライズ層の被覆面積は、図２，図８の
貫通孔３ｄ，３ｅの内面に対して２０％以上が好まし
い。メタライズ層の被覆範囲としては、貫通孔３ｄ，３
ｅの内面全体に対して、一部分に偏って被覆されている
のではなく、全体的に均一に被覆されている方がリード
線１３の引っ張り力または押し上げ力に対する強度は向
上する。また、２０％未満になると、半田溜まりの形成
が困難になり、リード線１３の引っ張り強度が低下する
不具合を生じ易い。The coverage area of the metallized layer is preferably 20% or more with respect to the inner surfaces of the through holes 3d and 3e in FIGS. As the coverage of the metallized layer, the through holes 3d, 3
If the entire inner surface of e is not partially covered, but is evenly covered as a whole, the strength of the lead wire 13 against the pulling force or the pushing force is improved. On the other hand, if it is less than 20%, it becomes difficult to form a solder pool, and it tends to cause a problem that the tensile strength of the lead wire 13 is reduced.

【００３９】なお、貫通孔３ｄ，３ｅは、入出力端子３
の平板部となるセラミックグリーンシートに予め所定形
状に打ち抜き加工を施すことによって、熱電冷却素子６
の電極と接続されたリード線１３が半田付けされる入出
力端子３の部位に形成される。The through holes 3d and 3e are connected to the input / output terminals 3
The ceramic green sheet serving as the flat plate portion is punched into a predetermined shape in advance, so that the thermoelectric cooling element 6
The lead wire 13 connected to the electrode is formed at the portion of the input / output terminal 3 to be soldered.

【００４０】また、入出力端子３は、枠体２を貫通して
または切り欠いて形成された取付部２ａに銀ロウ等のロ
ウ材で嵌着される。The input / output terminal 3 is fitted to a mounting portion 2a formed through or notched through the frame 2 with a brazing material such as silver brazing.

【００４１】リード端子１４は、入出力端子３のメタラ
イズ配線層１１の枠体２外側に銀ロウ等のロウ材を介し
て接合され、外部電気回路と入出力端子３との高周波信
号の入出力を行うものであり、Ｆｅ−Ｎｉ−Ｃｏ合金等
の金属材料から成る。その金属のインゴットを従来周知
の圧延加工法や打ち抜き加工法、エッチング加工法等の
金属加工法を採用することによって、所定の棒状となす
ように製作される。The lead terminal 14 is joined to the outside of the frame 2 of the metallized wiring layer 11 of the input / output terminal 3 via a brazing material such as silver brazing, and the input / output of high-frequency signals between the external electric circuit and the input / output terminal 3 is performed. And made of a metal material such as an Fe—Ni—Co alloy. The metal ingot is manufactured to have a predetermined rod shape by employing a metal processing method such as a rolling method, a punching method, and an etching method that are well known in the art.

【００４２】シールリング４は、枠体２の上面に銀ロウ
等のロウ材で接合され入出力端子３を上方より挟持する
とともに、上面に蓋体５をシーム溶接等により接合する
ための接合媒体として機能し、Ｆｅ−Ｎｉ−Ｃｏ合金等
の金属から成る。The sealing ring 4 is joined to the upper surface of the frame 2 with a brazing material such as silver brazing, and holds the input / output terminal 3 from above, and a joining medium for joining the lid 5 to the upper surface by seam welding or the like. And made of a metal such as an Fe-Ni-Co alloy.

【００４３】また、メタライズ配線層１１には、外部電
気回路との高周波信号の入出力を行うために、導電性を
有するＦｅ−Ｎｉ−Ｃｏ合金等の金属材料から成るリー
ド端子１４が銀ロウ等のロウ材で接合されるとともに、
枠体２内側において半導体素子６と電気的に接続するた
めのボンディングワイヤー１２が接合される。The metallized wiring layer 11 has a lead terminal 14 made of a conductive metal material such as a Fe-Ni-Co alloy for inputting and outputting a high-frequency signal to and from an external electric circuit. With the brazing material,
A bonding wire 12 for electrically connecting to the semiconductor element 6 is joined inside the frame 2.

【００４４】そして、図３に示すように、基体１の載置
部１ａに半導体素子６を熱電冷却素子８を間に介して接
着固定させ、半導体素子６の各電極をボンディングワイ
ヤー１２を介してメタライズ配線層１１に接続させると
ともに、熱電冷却素子８の電極に接続されたリード線１
３をメタライズ配線層１１に半田を介して電気的に接続
し、次に枠体２の上面に蓋体５を接合させ、基体１と枠
体２と入出力端子３とシールリング４と蓋体５とから成
る容器７内部に半導体素子６及び熱電冷却素子８を気密
に収容し、最後に枠体２の光ファイバ固定部材１０に光
ファイバ９の一端を挿通させるとともにこれを半田等の
接着剤やレーザ溶接によって接合させ、光ファイバ９を
枠体２に固定することによって、最終製品としての半導
体装置となる。そして、光ファイバ９を介して内部に収
容する半導体素子６と外部との光信号の授受、送受が可
能となる。Then, as shown in FIG. 3, the semiconductor element 6 is bonded and fixed to the mounting portion 1 a of the base 1 with a thermoelectric cooling element 8 interposed therebetween, and each electrode of the semiconductor element 6 is bonded via a bonding wire 12. The lead wire 1 connected to the metallized wiring layer 11 and connected to the electrode of the thermoelectric cooling element 8
3 is electrically connected to the metallized wiring layer 11 via solder, and then a lid 5 is joined to the upper surface of the frame 2, the base 1, the frame 2, the input / output terminals 3, the seal ring 4, the lid The semiconductor element 6 and the thermoelectric cooling element 8 are hermetically accommodated in a container 7 composed of the optical fiber 5 and one end of the optical fiber 9 is inserted through the optical fiber fixing member 10 of the frame 2 and an adhesive such as solder. Or by laser welding and fixing the optical fiber 9 to the frame 2 to obtain a semiconductor device as a final product. Then, transmission and reception of optical signals between the semiconductor element 6 housed therein and the outside via the optical fiber 9 become possible.

【００４５】かくして、本発明は、入出力端子のリード
線の接続部が、枠体内側のメタライズ配線層の形成部内
の平板部に上下面を貫通して設けられ、かつ上面側開口
から内側にかけて内寸法が小となる段差部が形成された
貫通孔と、この貫通孔の内面に形成されたメタライズ層
とから成り、貫通孔にリード線が挿入されろう付け接続
されていることから、貫通孔の内部に半田溜まりを設け
ることができ、半田の体積を増やして接続強度を向上さ
せ得る。また、組み立て作業中やろう付け後の熱収縮に
より、リード線を下方に引っ張るような外力が加わるこ
とが多いが、この外力に対する強度がきわめて向上し、
リード線の外れを解消することができる。また、ろう材
の断面積が大きくなるため、接合部の電気抵抗値を下げ
ることができ、熱電冷却素子を駆動するための電力を十
分に供給し得、熱電冷却素子及び半導体素子の動作が安
定化する。Thus, according to the present invention, the connection portion of the lead wire of the input / output terminal is provided on the flat plate portion in the formation portion of the metallized wiring layer inside the frame so as to penetrate the upper and lower surfaces, and extends from the upper surface side opening to the inside. A through hole having a step portion having a small inner dimension is formed, and a metallized layer formed on the inner surface of the through hole. Since the lead wire is inserted into the through hole and brazed, the through hole is formed. , A solder pool can be provided inside, and the connection strength can be improved by increasing the volume of the solder. In addition, due to thermal contraction during the assembly work or after brazing, an external force that pulls the lead wire downward is often applied, but the strength against this external force has been extremely improved,
The detachment of the lead wire can be eliminated. In addition, since the cross-sectional area of the brazing filler metal is increased, the electric resistance value of the joint can be reduced, sufficient power for driving the thermoelectric cooling element can be supplied, and the operation of the thermoelectric cooling element and the semiconductor element can be stabilized. Become

【００４６】また、本発明によれば、半田溜まりを設
け、半田の体積を増やして接続強度を大きくできるとと
ともに、リード線を下方に引っ張るような外力に対する
強度がさらに高くなる。また、ろう材とメタライズ層と
の接合面積がさらに増えるため、強固に熱電冷却素子の
リード線とメタライズ配線層を半田付けでき、その結果
熱電冷却素子の接続信頼性が向上し、外部からの衝撃等
で接合部が外れることがなくなる。Further, according to the present invention, the solder pool is provided, the volume of the solder is increased, the connection strength can be increased, and the strength against an external force such as pulling the lead wire downward is further increased. In addition, the joint area between the brazing material and the metallized layer is further increased, so that the lead wires of the thermoelectric cooling element and the metallized wiring layer can be firmly soldered. As a result, the connection reliability of the thermoelectric cooling element is improved, and external shocks Thus, the joint portion does not come off.

【００４７】なお、本発明は上述の実施の形態に限定さ
れるものではなく、本発明の要旨を逸脱しない範囲内で
あれば種々の変更は可能である。例えば、下層部３ｇ
｛図２（ｂ）｝がさらに２段以上の階段状であってもよ
く、貫通孔３ｄの内面にはメタライズ層が施されている
構成であってもよい。この構成により、貫通孔３ｄの内
面に半田溜まりをより多く設けることができるため、半
田の体積を増やして強度を上げることができる。また、
熱電冷却素子８のリード線１３をメタライズ配線層１１
にロウ付け接合する際に発生する応力は、下層部３ｇの
２段以上の階段状の貫通孔分で分散されてさらに小さい
ものとなり、割れやクラックを大幅に減少できる。The present invention is not limited to the above-described embodiment, and various changes can be made without departing from the scope of the present invention. For example, lower layer 3g
{FIG. 2 (b)} may have two or more steps, and the inner surface of the through hole 3d may be provided with a metallized layer. With this configuration, more solder pools can be provided on the inner surface of the through hole 3d, so that the volume of the solder can be increased and the strength can be increased. Also,
The lead wire 13 of the thermoelectric cooling element 8 is
The stress generated at the time of brazing and joining is reduced by two or more steps of through-holes in the lower layer portion 3g and becomes smaller, so that cracks and cracks can be greatly reduced.

【００４８】また、上記実施の形態においては、リード
線を貫通孔に挿入しろう付けする構成について説明した
が、リード線の代わりにピン等の棒状の接続端子を用い
ても本発明と同様の作用効果が得られる。従って、本発
明においては、棒状または線状の接続端子を用いた構成
であれば本発明の作用効果を奏することとなる。In the above-described embodiment, the structure in which the lead wire is inserted into the through-hole and brazed is described. However, the present invention can be applied to a case where a bar-shaped connection terminal such as a pin is used instead of the lead wire. An effect can be obtained. Therefore, in the present invention, the effects of the present invention can be obtained as long as the configuration uses the rod-shaped or linear connection terminals.

【００４９】[0049]

【発明の効果】本発明は、入出力端子の接続部が、枠体
内側のメタライズ配線層の形成部内の平板部に上下面を
貫通して設けられ、かつ上面側開口から内側にかけて内
寸法が小となる段差部が形成された貫通孔と、貫通孔の
内面に形成されたメタライズ層とから成り、貫通孔にリ
ード線が挿入されろう付けされていることにより、貫通
孔の内部に半田溜まりを設けることができ、半田の体積
を増やして接続強度を向上させ得る。また、組み立て作
業中やろう付け後の熱収縮により、リード線を下方に引
っ張るような外力が加わることが多いが、この外力に対
する強度がきわめて向上し、リード線の外れを解消する
ことができる。また、ろう材の断面積が大きくなるた
め、接合部の電気抵抗値を下げることができ、熱電冷却
素子を駆動するための電力を十分に供給し得、熱電冷却
素子及び半導体素子の動作が安定化する。According to the present invention, the connection portion of the input / output terminal is provided through the upper and lower surfaces of the flat portion in the formation portion of the metallized wiring layer inside the frame, and the inner dimension is increased from the upper opening to the inner side. It consists of a through hole with a small step, and a metallized layer formed on the inner surface of the through hole. A lead wire is inserted into the through hole and brazed, so that the solder pools inside the through hole Can be provided, and the connection strength can be improved by increasing the volume of the solder. In addition, an external force that pulls the lead wire downward is often applied due to heat shrinkage during the assembling work or after brazing. However, the strength against this external force is extremely improved, and the lead wire can be prevented from coming off. In addition, since the cross-sectional area of the brazing material is increased, the electric resistance value of the joint can be reduced, sufficient power for driving the thermoelectric cooling element can be supplied, and the operation of the thermoelectric cooling element and the semiconductor element can be stabilized. Become

【００５０】また本発明は、好ましくは貫通孔の上面側
開口の幅に対する下面側開口の幅の比が０．４〜０．９
であることにより、半田溜まりを設け、半田の体積を増
やして接続強度を大きくできるととともに、リード線を
下方に引っ張るような外力に対する強度がさらに高くな
る。また、ろう材とメタライズ層との接合面積がさらに
増えるため、強固に熱電冷却素子のリード線とメタライ
ズ配線層を半田付けでき、その結果熱電冷却素子の接続
信頼性が向上し、外部からの衝撃等で接合部が外れるこ
とがなくなる。Preferably, the ratio of the width of the lower surface side opening to the width of the upper surface side opening of the through hole is 0.4 to 0.9.
Accordingly, the solder pool is provided, the volume of the solder is increased, the connection strength can be increased, and the strength against an external force such as pulling the lead wire downward is further increased. In addition, the joint area between the brazing material and the metallized layer is further increased, so that the lead wires of the thermoelectric cooling element and the metallized wiring layer can be firmly soldered. As a result, the connection reliability of the thermoelectric cooling element is improved, and external shocks Thus, the joint portion does not come off.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の半導体パッケージについて実施の形態
の例を示す斜視図である。FIG. 1 is a perspective view showing an example of an embodiment of a semiconductor package of the present invention.

【図２】図１の半導体パッケージにおける入出力端子の
実施の形態の例を示し、（ａ）は入出力端子の斜視図、
（ｂ）は入出力端子の貫通孔の拡大断面図、（ｃ）は貫
通孔の他の例を示す拡大断面図である。FIGS. 2A and 2B show an example of an embodiment of input / output terminals in the semiconductor package of FIG. 1; FIG.
(B) is an enlarged sectional view of a through hole of the input / output terminal, and (c) is an enlarged sectional view showing another example of the through hole.

【図３】図１の半導体パッケージに半導体素子を収容し
た構成を示す断面図である。FIG. 3 is a sectional view showing a configuration in which a semiconductor element is housed in the semiconductor package of FIG. 1;

【図４】従来の半導体パッケージの斜視図である。FIG. 4 is a perspective view of a conventional semiconductor package.

【図５】図４の半導体パッケージにおける入出力端子を
示し、（ａ）は入出力端子の斜視図、（ｂ）は入出力端
子の貫通孔の拡大断面図である。5A and 5B show input / output terminals in the semiconductor package of FIG. 4, wherein FIG. 5A is a perspective view of the input / output terminals, and FIG. 5B is an enlarged sectional view of a through hole of the input / output terminals.

【図６】従来の半導体パッケージの他の例を示す斜視図
である。FIG. 6 is a perspective view showing another example of a conventional semiconductor package.

【図７】図４の半導体パッケージに半導体素子を収容し
た構成を示す断面図である。FIG. 7 is a cross-sectional view showing a configuration in which a semiconductor element is housed in the semiconductor package of FIG. 4;

【図８】図１の半導体パッケージにおける入出力端子の
実施の形態の他の例を示し、（ａ）は入出力端子の斜視
図、（ｂ）は入出力端子の貫通孔の拡大断面図、（ｃ）
は貫通孔の他の例を示す拡大断面図である。8A and 8B show another example of the embodiment of the input / output terminals in the semiconductor package of FIG. 1; FIG. 8A is a perspective view of the input / output terminals; FIG. 8B is an enlarged sectional view of a through hole of the input / output terminals; (C)
FIG. 4 is an enlarged sectional view showing another example of the through hole.

【符号の説明】[Explanation of symbols]

１：基体 １ａ：載置部 ２：枠体 ２ａ：取付部 ３：入出力端子 ３ｄ：貫通孔 ３ｆ：上層部 ３ｇ：下層部 ５：蓋体 ６：半導体素子 ８：熱電冷却素子 １１：メタライズ配線層 １３：リード線 1: Base 1a: Placement section 2: Frame 2a: Mounting section 3: Input / output terminal 3d: Through hole 3f: Upper layer section 3g: Lower layer section 5: Lid 6: Semiconductor element 8: Thermoelectric cooling element 11: Metallized wiring Layer 13: Lead wire

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 上面に半導体素子が熱電冷却素子を介し
て載置される載置部を有する基体と、該基体の上面に前
記載置部を囲繞するように取着された金属製の枠体と、
該枠体を貫通してまたは切り欠いて形成された入出力端
子の取付部と、上面の一辺側から対向する他辺側にかけ
て形成された複数のメタライズ配線層を有する誘電体か
ら成る平板部および該平板部の上面に前記複数のメタラ
イズ配線層を間に挟んで接合された誘電体から成る立壁
部から構成されるとともに前記枠体内側の前記メタライ
ズ配線層に前記熱電冷却素子のリード線の接続部を有し
て前記取付部に嵌着された前記入出力端子とを具備して
成り、前記枠体の上面に蓋体が接合される半導体素子収
納用パッケージにおいて、前記入出力端子の前記接続部
は、前記枠体内側の前記メタライズ配線層の形成部内の
前記平板部に上下面を貫通して設けられ、かつ上面側開
口から内側にかけて内寸法が小となる段差部が形成され
た貫通孔と、該貫通孔の内面に形成されたメタライズ層
とから成り、前記貫通孔に前記リード線が挿入されろう
付けされていることを特徴とする半導体素子収納用パッ
ケージ。1. A base having a mounting portion on which a semiconductor element is mounted via a thermoelectric cooling element on an upper surface, and a metal frame mounted on the upper surface of the base so as to surround the mounting portion. Body and
A flat portion made of a dielectric having a plurality of metallized wiring layers formed from one side of the upper surface to the other side facing the mounting portion of the input / output terminal formed by penetrating or notching the frame; A lead wall of the thermoelectric cooling element is connected to the metallized wiring layer inside the frame, comprising a standing wall made of a dielectric bonded to the upper surface of the flat plate portion with the plurality of metallized wiring layers interposed therebetween. The input / output terminal fitted to the mounting portion, the semiconductor device housing package having a lid joined to the upper surface of the frame. The portion is provided through the upper and lower surfaces of the flat plate portion in the formation portion of the metallized wiring layer inside the frame body, and a through hole in which a step portion having an inner size smaller from the upper surface side opening to the inner side is formed. And the uki Consists of a formed on an inner surface of the hole metallization layer, a semiconductor device package for housing and said lead wire in the through hole is brazed is inserted. 【請求項２】 前記貫通孔の上面側開口の幅に対する下
面側開口の幅の比が０．４〜０．９であることを特徴と
する請求項１記載の半導体素子収納用パッケージ。2. The package according to claim 1, wherein a ratio of a width of the lower surface side opening to a width of the upper surface side opening of the through hole is 0.4 to 0.9.
JP2001044033A 2001-02-20 2001-02-20 Package for storing semiconductor elements Expired - Fee Related JP3642739B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001044033A JP3642739B2 (en) 2001-02-20 2001-02-20 Package for storing semiconductor elements

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001044033A JP3642739B2 (en) 2001-02-20 2001-02-20 Package for storing semiconductor elements

Publications (2)

Publication Number Publication Date
JP2002246494A true JP2002246494A (en) 2002-08-30
JP3642739B2 JP3642739B2 (en) 2005-04-27

Family

ID=18906095

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Link
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011517763A (en) * 2008-04-04 2011-06-16 アルファ ラヴァル コーポレイト アクチボラゲット Plate heat exchanger
CN103329260A (en) * 2011-07-26 2013-09-25 京瓷株式会社 Package for accommodating semiconductor element, semiconductor device provided with same, and electronic device
JP2013213666A (en) * 2013-07-11 2013-10-17 Alfa Laval Corporate Ab Plate heat exchanger

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011517763A (en) * 2008-04-04 2011-06-16 アルファ ラヴァル コーポレイト アクチボラゲット Plate heat exchanger
US9103597B2 (en) 2008-04-04 2015-08-11 Alfa Laval Corporate Ab Plate heat exchanger
CN103329260A (en) * 2011-07-26 2013-09-25 京瓷株式会社 Package for accommodating semiconductor element, semiconductor device provided with same, and electronic device
JP2013213666A (en) * 2013-07-11 2013-10-17 Alfa Laval Corporate Ab Plate heat exchanger

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