JP4160888B2

JP4160888B2 - Input/output terminal, semiconductor element storage package, and semiconductor device

Info

Publication number: JP4160888B2
Application number: JP2003332018A
Authority: JP
Inventors: 信幸田中
Original assignee: Kyocera Corp
Current assignee: Kyocera Corp
Priority date: 2003-09-24
Filing date: 2003-09-24
Publication date: 2008-10-08
Anticipated expiration: 2023-09-24
Also published as: JP2005101205A

Description

本発明は、ＩＣ，ＬＳＩ等の半導体集積回路素子や光通信用の光半導体素子などを収納するための半導体素子収納用パッケージに用いられる入出力端子および半導体素子収納用パッケージならびに半導体装置に関する。 The present invention relates to input/output terminals used in semiconductor element storage packages for storing semiconductor integrated circuit elements such as ICs and LSIs, and optical semiconductor elements for optical communications, as well as semiconductor devices.

従来、ＩＣ，ＬＳＩ等の半導体集積回路素子や光通信分野で用いられる光半導体素子などの半導体素子を収納する半導体素子収納用パッケージ（以下、パッケージともいう）は、半導体素子から発生する熱を強制的に基体へ移動させ、半導体素子を安定して作動させるためのペルチェ素子等の熱電冷却素子を具備している。例えば、半導体レーザ（ＬＤ）、フォトダイオード（ＰＤ）等の光半導体素子を用い、熱電冷却素子としてペルチェ素子を設置したパッケージを図６に断面図で、図７に斜視図で示す。これらの図において、21は基体、23は枠体、24は入出力端子、31は熱電冷却素子、34はリード線である。 Conventionally, semiconductor element storage packages (hereinafter also referred to as packages) that store semiconductor elements such as semiconductor integrated circuit elements such as ICs and LSIs, and optical semiconductor elements used in the optical communications field, are equipped with thermoelectric cooling elements such as Peltier elements to forcibly transfer heat generated from the semiconductor elements to a base and ensure stable operation of the semiconductor elements. For example, a package using an optical semiconductor element such as a semiconductor laser (LD) or photodiode (PD) and equipped with a Peltier element as a thermoelectric cooling element is shown in a cross-sectional view in Figure 6 and in a perspective view in Figure 7. In these figures, 21 is the base, 23 is the frame, 24 is the input/output terminal, 31 is the thermoelectric cooling element, and 34 is the lead wire.

基体21は鉄（Ｆｅ）−ニッケル（Ｎｉ）−コバルト（Ｃｏ）合金等の金属や銅（Ｃｕ）−タングステン（Ｗ）等の焼結材から成り、その上側主面の中央部に、ＬＤ，ＰＤ等の光半導体素子30を搭載した熱電冷却素子31を載置するための載置部21ａを有している。 The base 21 is made of a metal such as an iron (Fe)-nickel (Ni)-cobalt (Co) alloy or a sintered material such as copper (Cu)-tungsten (W), and has a mounting section 21a in the center of its upper main surface for mounting a thermoelectric cooling element 31 equipped with an optical semiconductor element 30 such as an LD or PD.

また、基体21の上側主面の外周部には、側部に光ファイバ32を固定するための光ファイバ固定部材22の取付部23ｂおよび入出力端子24の取付部23ａを有する枠体23が載置部21ａを囲繞するように立設されており、枠体23は基体21とともにその内側に半導体素子30を収容する空所を形成する。 A frame 23 having an attachment portion 23b of an optical fiber fixing member 22 for fixing an optical fiber 32 to the side and an attachment portion 23a of an input/output terminal 24 is erected on the outer periphery of the upper main surface of the base 21 so as to surround the mounting portion 21a, and the frame 23, together with the base 21, forms a cavity inside for accommodating the semiconductor element 30.

光ファイバ固定部材22は枠体23の内側の端部がサファイアやガラス等の透光性材料から成る窓部材22ａで塞がれており、枠体23の外側の端部から光ファイバ32が挿通固定される。 The inner end of the optical fiber fixing member 22 is covered by a window member 22a made of a light-transmitting material such as sapphire or glass, and the optical fiber 32 is inserted and fixed from the outer end of the frame 23.

枠体23は基体21と同様にＦｅ−Ｎｉ−Ｃｏ合金やＣｕ−Ｗの焼結材等から成り、基体21と一体成形される、または基体21に銀（Ａｇ）ろう等のろう材を介してろう付けされる、またはシーム溶接法等の溶接法により接合されることによって、基体21の上側主面の外周部に立設される。 The frame 23 is made of a sintered material such as an Fe-Ni-Co alloy or Cu-W, just like the base 21, and is either molded integrally with the base 21, or brazed to the base 21 using a brazing material such as silver (Ag) solder, or joined by a welding method such as seam welding, and is erected on the outer periphery of the upper main surface of the base 21.

また、入出力端子24は、アルミナ（Ａｌ_２Ｏ_３）質焼結体、窒化アルミニウム（ＡｌＮ）質焼結体、ムライト（３Ａｌ_２Ｏ_３・２ＳｉＯ_２）質焼結体等のセラミックスから成り、平板部24ｂと立壁部24ｃとから構成される。平板部24ｂの上面には、一辺から対向する他辺にかけて形成され、タングステン（Ｗ），モリブデン（Ｍｏ）等のメタライズ層から成る線路導体24ａを有するとともに、線路導体24ａの一部を狭持して接合される立壁部24ｃが設置される。この入出力端子24は、枠体23の取付部23ａにろう材を介して嵌着接合され、線路導体24ａが枠体23の内外を導通することとなる。 The input/output terminal 24 is made of ceramics such as alumina ( _Al2O3 ) sintered body, _aluminum nitride (AlN) sintered body, or _mullite ( _3Al2O3.2SiO2 ) sintered body, and is composed of a flat plate portion 24b and a vertical wall portion 24c. The flat plate portion 24b has a line conductor 24a formed from one side to the opposite side and made _of a metallized layer of tungsten (W), molybdenum (Mo), or the like, on its upper surface, and is provided with a vertical wall portion 24c which is joined by sandwiching a part of the line conductor 24a. The input/output terminal 24 is fitted and joined to the mounting portion 23a of the frame 23 via a brazing material, and the line conductor 24a is electrically connected between the inside and outside of the frame 23.

線路導体24ａの枠体23外側の部位には、Ｆｅ−Ｎｉ−Ｃｏ合金等の金属から成る外部リード端子27がＡｇろう等のろう材を介して取着される。一方、線路導体24ａの枠体23内側の部位には、半導体素子30の各電極がボンディングワイヤ33を介して電気的に接続されるとともに、熱電冷却素子31のリード線34の先端部が半田付けされ電気的に接続される。 External lead terminals 27 made of a metal such as an Fe-Ni-Co alloy are attached to the outside of the frame 23 of the line conductor 24a via a solder material such as Ag solder. On the other hand, the electrodes of the semiconductor element 30 are electrically connected to the inside of the frame 23 of the line conductor 24a via bonding wires 33, and the tips of the lead wires 34 of the thermoelectric cooling element 31 are soldered and electrically connected.

この線路導体24ａのリード線34との接続部は、枠体23内側に位置する平板部24ｂの線路導体24ａの線路方向に直交する側面に設けられた、横断面形状がＵ字状の切欠き部24ｄの内面に、線路導体24ａが延設されて成る。これにより、切欠き部24ｄの内面とリード線34との間の半田の接合面積が拡大し、入出力端子24とリード線34との接続が強固なものになる。 The connection between the line conductor 24a and the lead wire 34 is formed by extending the line conductor 24a onto the inner surface of a cutout 24d having a U-shaped cross section, which is provided on the side of the flat plate portion 24b located inside the frame body 23, perpendicular to the line direction of the line conductor 24a. This increases the solder joint area between the inner surface of the cutout 24d and the lead wire 34, making the connection between the input/output terminal 24 and the lead wire 34 stronger.

また、枠体23および入出力端子24の上面には、Ｆｅ−Ｎｉ−Ｃｏ合金等の金属から成るシールリング25がＡｇろう等のろう材を介して接合され、シールリング25の上面には、Ｆｅ−Ｎｉ−Ｃｏ合金等の金属から成る蓋体26がろう付け法やシームウエルド法等の溶接法で接合される。そして、基体21、枠体23、シールリング25および蓋体26から成る容器内部に光半導体素子30が収容され気密に封止される。 A seal ring 25 made of a metal such as an Fe-Ni-Co alloy is joined to the upper surfaces of the frame 23 and the input/output terminals 24 via a brazing material such as Ag brazing, and a lid 26 made of a metal such as an Fe-Ni-Co alloy is joined to the upper surface of the seal ring 25 by a welding method such as brazing or seam welding. The optical semiconductor element 30 is then housed and hermetically sealed inside the container made up of the base 21, frame 23, seal ring 25, and lid 26.

最後に、枠体23に設けた光ファイバ固定部材22に光ファイバ32を溶接等によって接合させ、光ファイバ32を枠体23に固定することによって製品としての光半導体装置となる。この場合、光ファイバ32は、その端部に金属製フランジ32ａを予め取着させておき、金属製フランジ32ａを例えばレーザ溶接法によって光ファイバ固定部材22に溶接することにより光ファイバ固定部材22に取着される。 Finally, the optical fiber 32 is joined to the optical fiber fixing member 22 provided on the frame 23 by welding or the like, and the optical fiber 32 is fixed to the frame 23 to form a finished optical semiconductor device. In this case, the optical fiber 32 has a metal flange 32a attached to its end in advance, and is attached to the optical fiber fixing member 22 by welding the metal flange 32a to the optical fiber fixing member 22 by, for example, laser welding.

この光半導体装置は、外部電気回路（図示せず）から供給される電気信号によって光半導体素子30に光を励起させ、この光を光ファイバ32を介して外部に伝送することによって、高速光通信等に使用される光半導体装置として機能する。または、外部から光ファイバ32を介して伝送してくる光信号を、透光性部材22ａを透過させ、光半導体素子30に受光させて光信号を電気信号に変換することによって、高速光通信等に使用される光半導体装置として機能する。 This optical semiconductor device functions as an optical semiconductor device used for high-speed optical communications, etc., by exciting light in the optical semiconductor element 30 with an electrical signal supplied from an external electrical circuit (not shown) and transmitting this light to the outside via the optical fiber 32. Alternatively, it functions as an optical semiconductor device used for high-speed optical communications, etc., by transmitting an optical signal transmitted from the outside via the optical fiber 32 through the light-transmitting member 22a, receiving it in the optical semiconductor element 30, and converting the optical signal into an electrical signal.

なお、この光半導体装置には、半導体素子30が作動中に発生する熱を外部に良好に放熱するために、光半導体素子30と基体21との間に熱電冷却素子31が配設されている。熱電冷却素子31には、セラミック基板が、基体21に接合される面と光半導体素子30が搭載される面にそれぞれ設けてあり、熱電冷却素子31の基体21に接合される面のセラミック基板の上面に電極が形成されている。この電極にはリード線34の一端部が接続されている（例えば、下記の特許文献１参照）。 In addition, in this optical semiconductor device, a thermoelectric cooling element 31 is disposed between the optical semiconductor element 30 and the base 21 in order to efficiently dissipate heat generated by the semiconductor element 30 during operation to the outside. The thermoelectric cooling element 31 has a ceramic substrate provided on both the surface bonded to the base 21 and the surface on which the optical semiconductor element 30 is mounted, and an electrode is formed on the upper surface of the ceramic substrate on the surface of the thermoelectric cooling element 31 bonded to the base 21. One end of a lead wire 34 is connected to this electrode (see, for example, Patent Document 1 below).

そして、リード線34の他端部が入出力端子24の線路導体24ａに半田付けにより電気的に接続され、外部リード端子27、線路導体24ａおよびリード線34を介して外部より熱電冷却素子31に電力が供給される。即ち、リード線34は、熱電冷却素子31に駆動電圧を供給することによって、熱電冷却素子31を光半導体素子30から基体21に熱を移動させる熱ポンプとして作動させる。従って、光半導体素子30の熱は熱電冷却素子31を介して基体21に強制的に伝達され、基体21から大気中に放散され、その結果光半導体素子30が常に定温で安定して作動することとなる。
特開2000−183254号公報特開2002−324868号公報 The other end of the lead wire 34 is electrically connected by soldering to the line conductor 24a of the input/output terminal 24, and power is supplied from the outside to the thermoelectric cooling element 31 via the external lead terminal 27, the line conductor 24a, and the lead wire 34. That is, the lead wire 34 supplies a driving voltage to the thermoelectric cooling element 31, thereby causing the thermoelectric cooling element 31 to function as a heat pump that transfers heat from the optical semiconductor element 30 to the base 21. Therefore, the heat of the optical semiconductor element 30 is forcibly transferred to the base 21 via the thermoelectric cooling element 31 and dissipated from the base 21 into the atmosphere, with the result that the optical semiconductor element 30 always operates stably at a constant temperature.
JP 2000-183254 A JP 2002-324868 A

しかしながら、図６のような従来の入出力端子24においては、大きな直流電流を流すために線路導体24ａの抵抗を小さくすることが望まれるが、線路導体24ａの厚さは５〜20μｍ程度と非常に薄いため、その抵抗を小さくすることがきわめて困難である。従って、熱電冷却素子31の作動に必要な数Ａ〜十数Ａ程度の大きな直流電流を入出力端子24に流すと、大きなジュール熱が発生し、この熱により、線路導体24ａが断線したり、また枠体23内部の温度が上昇して内部の光半導体素子30に誤作動を発生させ、最終的に光半導体素子30を熱破壊させるという問題があった。 However, in the conventional input/output terminal 24 shown in Figure 6, it is desirable to reduce the resistance of the line conductor 24a in order to pass a large DC current, but since the thickness of the line conductor 24a is very thin, about 5 to 20 μm, it is extremely difficult to reduce its resistance. Therefore, when a large DC current of about several A to several tens of A required to operate the thermoelectric cooling element 31 is passed through the input/output terminal 24, a large amount of Joule heat is generated, which can cause the line conductor 24a to break or the temperature inside the frame 23 to rise, causing the internal optical semiconductor element 30 to malfunction and ultimately destroying the optical semiconductor element 30.

そこで、線路導体24ａの抵抗を小さくする構成として、線路導体24ａの幅を広げることが考えられるが、線路導体24ａの幅を十分に抵抗が低下するような幅にまで広げると、必然的に入出力端子24の大きさを従来の数倍以上に大きくしなければならない。そのため、枠体23の取付部23ａに入出力端子24を嵌着できなくなるという問題点があった。 In order to reduce the resistance of the line conductor 24a, it is possible to consider widening the line conductor 24a. However, if the line conductor 24a is widened to a width that sufficiently reduces the resistance, the size of the input/output terminal 24 must be increased by several times or more compared to the conventional size. This creates the problem that the input/output terminal 24 cannot be fitted into the mounting portion 23a of the frame body 23.

また、線路導体24ａを厚くすることにより抵抗を小さくすることができるが、その場合例えば厚さが従来の数倍〜十数倍程度の線路導体24ａを形成する必要があり、そのような厚い線路導体24ａを適用すると、入出力端子24の平板部24ｂと立壁部24ｃとの接合部において、線路導体24ａの周囲のセラミックグリーンシート間に積層のための圧力がかかり難くなってセラミックグリーンシート同士の良好な接合状態が得られなくなる。そのため、入出力端子24の平板部24ｂと立壁部24ｃとの間に剥れ（デラミネーション）が生じ易くなり、枠体23内部の気密性が損なわれ易いという問題点があった。 Although the resistance can be reduced by thickening the line conductor 24a, it is necessary to form the line conductor 24a several times to a dozen times thicker than before. If such a thick line conductor 24a is used, it becomes difficult to apply pressure for stacking between the ceramic green sheets around the line conductor 24a at the joint between the flat plate portion 24b and the vertical wall portion 24c of the input/output terminal 24, and good bonding between the ceramic green sheets cannot be obtained. This makes it easy for delamination to occur between the flat plate portion 24b and the vertical wall portion 24c of the input/output terminal 24, which causes the problem that the airtightness inside the frame 23 is easily compromised.

また、抵抗の小さい銅（Ｃｕ）から成る線路導体24ａを用いることも考えられるが、Ｃｕの融点が約1083℃と低いため、一般的に用いられている1500〜1600℃で焼成されるアルミナ（Ａｌ_２Ｏ_３）質焼結体から成る入出力端子24に、同時焼成によって線路導体24ａを形成しようとすると、Ｃｕが融解し流れて所望の形状の線路導体24ａを形成できないという問題点があった。 It is also possible to use the line conductor 24a made of copper (Cu), which has low resistance. However, because the melting point of Cu is low at approximately 1083°C, if an attempt is made to form the line conductor 24a by co-firing with the input/output terminal 24 made of alumina ₍ _Al2O3 ) sintered body, which is commonly used and fired at 1500-1600°C, the Cu will melt and flow, making it impossible to form the line conductor 24a in the desired shape.

また、特許文献２に示されるように、平板部24ｂとなる複数のセラミックグリーンシート間に内層導体層を形成するとともに平板部24ｂの上面に線路導体24ａを形成し、平板部24ｂの端で内層導体層と線路導体24ａとを並列接続することによって線路導体24ａの抵抗を下げるという方法もある。 Also, as shown in Patent Document 2, there is a method in which an inner conductor layer is formed between multiple ceramic green sheets that form the flat plate portion 24b, a line conductor 24a is formed on the upper surface of the flat plate portion 24b, and the resistance of the line conductor 24a is reduced by connecting the inner conductor layer and the line conductor 24a in parallel at the end of the flat plate portion 24b.

しかしながら、この特許文献２に示される構成では、平板部24ｂの端部に線路導体24ａとリード線34の先端部とを接合するための切欠き部24ｄを設けると、切欠き部24ｄの周囲の平板部24ｂとなるセラミックグリーンシート間に内層導体層が介在することによって密着強度が低下し、セラミックグリーンシート間で剥れが生じ易くなり、枠体23内部の気密性が損なわれ易くなるという問題点があった。 However, in the configuration shown in Patent Document 2, when a notch 24d is provided at the end of the flat portion 24b to join the line conductor 24a and the tip of the lead wire 34, an inner conductor layer is interposed between the ceramic green sheets that form the flat portion 24b around the notch 24d, which reduces the adhesive strength, making it easier for peeling to occur between the ceramic green sheets and making it easier for the airtightness inside the frame 23 to be compromised.

従って、本発明は上記問題点に鑑み完成されたものであり、その目的は、入出力端子の線路導体の抵抗を小さくすることにより、大きな直流電力を半導体素子冷却用の熱電冷却素子に供給して半導体素子の作動性を良好にするとともに、パッケージの気密性を損なうことのない入出力端子、およびこの入出力端子を用いたパッケージ、ならびに半導体装置を提供することにある。 The present invention was completed in consideration of the above problems, and its purpose is to provide an input/output terminal that reduces the resistance of the line conductors of the input/output terminals, thereby supplying a large amount of DC power to a thermoelectric cooling element for cooling a semiconductor element, improving the operability of the semiconductor element, and does not impair the airtightness of the package, as well as a package and semiconductor device that use this input/output terminal.

本発明の入出力端子は、上面の一辺側から対向する他辺側にかけて形成された線路導体を有するセラミックスから成る直方体状の平板部および該平板部の上面に前記線路導体の一部を間に挟んで接合されたセラミックスから成る立壁部から構成され、前記平板部の下面と前記立壁部の上面と前記線路導体の線路方向に平行な両側面とに接地導体層がそれぞれ形成されている入出力端子において、前記平板部は、複数のセラミック層が積層されて成るとともに前記一辺側の端面から前記他辺側の端面にわたる内層導体層が設けられ、さらにこれら両端面に上下方向に切欠き部がそれぞれ設けられているとともに該切欠き部の内面に前記線路導体の端および前記内層導体層の端を電気的に接続する導体層がそれぞれ形成されており、前記切欠き部は前記内層導体層の中央部よりも幅が狭く、前記内層導体層は端部が前記切欠き部に向かって漸次幅が狭くなっているとともに先端の幅が前記切欠き部と同じであり、さらに、前記切欠き部の一方は平面視における最奥部の形状が半円状であるとともに前記線路導体の線路方向における長さが前記内層導体層の端部よりも長いことを特徴とする。 The input/output terminal of the present invention is composed of a rectangular parallelepiped flat plate portion made of ceramics having a line conductor formed from one side of the upper surface to the opposing other side, and a vertical wall portion made of ceramics joined to the upper surface of the flat plate portion with a part of the line conductor sandwiched therebetween, and in the input/output terminal in which ground conductor layers are formed on the lower surface of the flat plate portion, the upper surface of the vertical wall portion, and both side surfaces parallel to the line direction of the line conductor, the flat plate portion is formed by laminating a plurality of ceramic layers, and an inner layer conductor layer is provided from the end surface of the one side to the end surface of the other side, and these A notch is provided in the vertical direction on each end surface, and a conductor layer that electrically connects the end of the line conductor and the end of the inner conductor layer is formed on the inner surface of the notch, the notch is narrower than the center of the inner conductor layer, the end of the inner conductor layer gradually narrows toward the notch and has the same width as the notch, and one of the notches has a semicircular shape at its innermost part in a plan view and the length of the line conductor in the line direction is longer than the end of the inner conductor layer.

本発明の半導体素子収納用パッケージは、上面に熱電冷却素子を介して半導体素子が載置される載置部を有する基体と、該基体の上面に前記載置部を囲繞するように取着され、側部に貫通孔または切欠きから成る入出力端子の取付部が形成された枠体と、前記入出力端子の取付部に嵌着された請求項１記載の入出力端子とを具備し、前記熱電冷却素子のリード線は前記入出力端子の前記一方の切欠き部に半田付けされて前記線路導体に電気的に接続されることを特徴とする。 The package for housing a semiconductor element of the present invention comprises a base having a mounting portion on the upper surface of which a semiconductor element is mounted via a thermoelectric cooling element, a frame body attached to the upper surface of the base so as to surround the mounting portion and having an input/output terminal mounting portion formed of a through hole or a notch on the side, and the input/output terminal according to claim 1 fitted into the mounting portion of the input/output terminal, and the lead wire of the thermoelectric cooling element is soldered to one of the notches of the input/output terminal and electrically connected to the line conductor.

本発明の半導体装置は、上記構成の半導体素子収納用パッケージと、前記載置部にロウ付け固定されるとともに前記リード線が前記入出力端子の前記一方の切欠き部に半田付けされて前記線路導体に電気的に接続された前記熱電冷却素子と、該熱電冷却素子の上面に載置固定され前記入出力端子に電気的に接続された半導体素子と、前記枠体の上面に取着された蓋体とを具備していることを特徴とする。 The semiconductor device of the present invention is characterized by comprising a package for housing a semiconductor element as described above, the thermoelectric cooling element that is brazed to the mounting portion and the lead wire is soldered to one of the notches of the input/output terminal and electrically connected to the line conductor, a semiconductor element that is mounted and fixed on the upper surface of the thermoelectric cooling element and electrically connected to the input/output terminal, and a lid attached to the upper surface of the frame.

本発明の入出力端子は、平板部は、複数のセラミック層が積層されて成るとともに一辺側の端面から他辺側の端面にわたる内層導体層が設けられ、さらにこれら両端面に上下方向に切欠き部がそれぞれ設けられているとともに切欠き部の内面に線路導体の端および内層導体層の端を電気的に接続する導体層がそれぞれ形成されていることから、内層導体層が線路導体に並列に接続して線路導体の両端間の抵抗を数分の１程度以下に小さくすることができる。その結果、大きな直流電流を流すことが可能な入出力端子が得られる。また、内層導体層の層数、幅、長さを調整することにより、線路導体の両端間の抵抗を容易に制御することができ、所望の設計値の入出力端子を非常に容易に製造することが可能となる。 The input/output terminal of the present invention has a flat plate portion formed by laminating a plurality of ceramic layers and an inner conductor layer extending from the end face of one side to the end face of the other side. Furthermore, notches are provided in the vertical direction on both end faces, and conductor layers that electrically connect the ends of the line conductor and the ends of the inner conductor layer are formed on the inner surfaces of the notches. Therefore, the inner conductor layer is connected in parallel to the line conductor, and the resistance between both ends of the line conductor can be reduced to a fraction or less. As a result, an input/output terminal capable of passing a large direct current is obtained. Furthermore, by adjusting the number of layers, width, and length of the inner conductor layer, the resistance between both ends of the line conductor can be easily controlled, making it possible to very easily manufacture an input/output terminal with the desired design value.

また、切欠き部は内層導体層の中央部よりもよりも幅が狭く、内層導体層は切欠き部に向かって漸次幅が狭くなっているとともに先端の幅が切欠き部と同じであることから、セラミックグリーンシートを積層して平板部を形成する際、切欠き部を有するセラミックグリーンシートを内層導体層を挟み込むように積層しても、内層導体層の端部の両側における上下のセラミックグリーンシート同士の密着面積を大きくすることができ、セラミックグリーンシート間に剥がれが生じるのを有効に抑制することができる。その結果、入出力端子の気密性および導通信頼性を向上させ、半導体素子の作動性を向上させることができる。 In addition, the cutout portion is narrower than the center of the inner conductor layer, and the width of the inner conductor layer gradually narrows toward the cutout portion with the tip having the same width as the cutout portion. Therefore, when the ceramic green sheets are stacked to form the flat portion, even if the ceramic green sheets having the cutout portion are stacked so as to sandwich the inner conductor layer, the contact area between the upper and lower ceramic green sheets on both sides of the end of the inner conductor layer can be increased, and peeling between the ceramic green sheets can be effectively suppressed. As a result, the airtightness and conductivity reliability of the input/output terminals can be improved, and the operability of the semiconductor element can be improved.

さらに、内層導体層の先端の幅は切欠き部と同じであることから、内層導体層が切欠き部を全周にわたって覆うことができ、内層導体層と切欠き部の内面の導体層との接触面積を大きくすることができる。特に、切欠き部の内面の全面に導体層を形成すれば、切欠き部の内面の導体層と内層導体層との接触面積を非常に大きくすることができ、上下の内層導体層同士を低抵抗で接続することができる。その結果、入出力端子の電気的特性を良好にすることができる。 Furthermore, because the width of the tip of the inner conductor layer is the same as the notch, the inner conductor layer can cover the entire circumference of the notch, making it possible to increase the contact area between the inner conductor layer and the conductor layer on the inner surface of the notch. In particular, by forming a conductor layer on the entire inner surface of the notch, the contact area between the conductor layer on the inner surface of the notch and the inner conductor layer can be made very large, making it possible to connect the upper and lower inner conductor layers with low resistance. As a result, the electrical characteristics of the input/output terminals can be improved.

また、切欠き部の一方は平面視における最奥部の形状が半円状であるとともに線路導体の線路方向における長さが内層導体層の端部よりも長いことから、切欠き部の最奥部の導体層に熱電冷却素子のリード線を接続した際、リード線の周囲を大面積の内層導体層で覆うことができるため、リード線の周囲の内層導体層の抵抗を小さくして内層導体層からリード線へ電流を非常に流し易くすることができる。さらに、大電流が流れることによってリード線と切欠き部内面の導体層との接続部付近が発熱し、リード線と平板部との間に熱膨張係数差が生じたとしても、リード線周囲に内層導体層が大きな面積で配設されているのでリード線周囲の平板部を内層導体層で有効に補強することができるとともに、切欠き部の最奥部を半円状として応力を集中し難くすることにより、リード線周囲の平板部にクラックが生じるのを有効に防止することができる。 In addition, since the innermost part of one of the notches is semicircular in plan view and the length of the line conductor in the line direction is longer than the end of the inner conductor layer, when the lead wire of the thermoelectric cooling element is connected to the conductor layer at the innermost part of the notch, the lead wire can be covered with a large inner conductor layer, which reduces the resistance of the inner conductor layer around the lead wire and makes it very easy to pass a current from the inner conductor layer to the lead wire. Furthermore, even if a large current flows and heats up the connection between the lead wire and the conductor layer on the inner surface of the notch, causing a difference in thermal expansion coefficient between the lead wire and the flat plate part, the inner conductor layer is arranged with a large area around the lead wire, so the flat plate part around the lead wire can be effectively reinforced with the inner conductor layer, and by making the innermost part of the notch semicircular and making it difficult for stress to concentrate, it is possible to effectively prevent cracks from occurring in the flat plate part around the lead wire.

本発明の半導体素子収納用パッケージは、上面に熱電冷却素子を介して半導体素子が載置される載置部を有する基体と、基体の上面に載置部を囲繞するように取着され、側部に貫通孔または切欠きから成る入出力端子の取付部が形成された枠体と、入出力端子の取付部に嵌着された上記本発明の入出力端子とを具備し、熱電冷却素子のリード線は入出力端子の一方の切欠き部に半田付けされて線路導体に電気的に接続されることにより、半導体素子の作動性が良好となり、また半導体素子収納用パッケージの気密性を損なうことのない信頼性の高いものとなる。 The semiconductor device storage package of the present invention comprises a base having a mounting portion on the upper surface of which a semiconductor device is placed via a thermoelectric cooling element, a frame body attached to the upper surface of the base so as to surround the mounting portion and having an input/output terminal mounting portion formed of a through hole or notch on the side, and the input/output terminal of the present invention fitted into the input/output terminal mounting portion, and the lead wire of the thermoelectric cooling element is soldered to one of the notches of the input/output terminal and electrically connected to the line conductor, thereby improving the operability of the semiconductor device and providing a highly reliable package that does not impair the airtightness of the semiconductor device storage package.

本発明の半導体装置は、上記本発明の半導体素子収納用パッケージと、載置部にロウ付け固定されるとともにリード線が入出力端子の一方の切欠き部に半田付けされて線路導体に電気的に接続された熱電冷却素子と、熱電冷却素子の上面に載置固定され入出力端子に電気的に接続された半導体素子と、枠体の上面に取着された蓋体とを具備していることにより、上記本発明の半導体素子収納用パッケージの特徴を有する作動性が良好で信頼性の高いものとなる。 The semiconductor device of the present invention comprises the semiconductor element storage package of the present invention, a thermoelectric cooling element that is brazed to the mounting portion and has a lead wire soldered to one of the notches of the input/output terminals and electrically connected to the line conductor, a semiconductor element that is mounted and fixed on the upper surface of the thermoelectric cooling element and electrically connected to the input/output terminals, and a lid attached to the upper surface of the frame, thereby achieving good operability and high reliability that are characteristic of the semiconductor element storage package of the present invention.

本発明の入出力端子および半導体素子収納用パッケージを以下に詳細に説明する。図１（ａ）は、枠体３に設けられた本発明の入出力端子４について実施の形態の例を示す断面図、図１（ｂ）は図１（ａ）の入出力端子４の要部上面図、図１（ｃ）は図１（ａ）の入出力端子４の要部斜視図である。また、図２（ａ）は図１の入出力端子４におけるリード線が接続される一方側の内層導体層の要部平面図、図２（ｂ）は図１の入出力端子４における他方側の内層導体層の要部平面図である。さらに、図３は本発明の入出力端子４における内層導体層について実施の形態の他の例を示す要部平面図である。また、半導体素子として、半導体レーザ（ＬＤ）、フォトダイオード（ＰＤ）等の光半導体素子を用い、熱電冷却素子としてペルチェ素子を設置した本発明の半導体素子収納用パッケージを図４に断面図で、図５に斜視図で示す。以下、本発明の半導体素子収納用パッケージの一例である光半導体素子収納用パッケージ、および光半導体装置について説明する。 The input/output terminal and the semiconductor element storage package of the present invention will be described in detail below. FIG. 1(a) is a cross-sectional view showing an example of an embodiment of the input/output terminal 4 of the present invention provided on the frame 3, FIG. 1(b) is a top view of the main part of the input/output terminal 4 of FIG. 1(a), and FIG. 1(c) is a perspective view of the main part of the input/output terminal 4 of FIG. 1(a). FIG. 2(a) is a plan view of the main part of the inner layer conductor layer on one side to which the lead wire is connected in the input/output terminal 4 of FIG. 1, and FIG. 2(b) is a plan view of the main part of the inner layer conductor layer on the other side of the input/output terminal 4 of FIG. 1. FIG. 3 is a plan view of the main part showing another example of an embodiment of the inner layer conductor layer in the input/output terminal 4 of the present invention. FIG. 4 is a cross-sectional view of the semiconductor element storage package of the present invention, in which an optical semiconductor element such as a semiconductor laser (LD) or a photodiode (PD) is used as the semiconductor element, and a Peltier element is installed as the thermoelectric cooling element, and FIG. 5 is a perspective view. Below, the optical semiconductor element storage package, which is an example of the semiconductor element storage package of the present invention, and the optical semiconductor device will be described.

図１〜図５において、４ｂは複数のセラミック層４ｂ−１を積層して成る直方体状の平板部、４ｃは平板部４ｂ上に接合された立壁部、４ａは平板部４ｂの上面に形成された線路導体、４ａ−２および４ａ−３は、立壁部４ｃの線路方向の両側に露出した線路導体４ａの一方側および他方側である。４ｄは平板部４ｂの下面に形成された下部接地導体層、４ｅは平板部４ｂの側面から立壁部４ｃの側面にかけて形成された側部接地導体層、４ｆは立壁部４ｃの上面に形成された上部接地導体層である。 In Figures 1 to 5, 4b is a rectangular parallelepiped flat plate portion formed by stacking multiple ceramic layers 4b-1, 4c is a vertical wall portion joined onto the flat plate portion 4b, 4a is a line conductor formed on the upper surface of the flat plate portion 4b, 4a-2 and 4a-3 are one side and the other side of the line conductor 4a exposed on both sides of the vertical wall portion 4c in the line direction. 4d is a lower ground conductor layer formed on the lower surface of the flat plate portion 4b, 4e is a side ground conductor layer formed from the side of the flat plate portion 4b to the side of the vertical wall portion 4c, and 4f is an upper ground conductor layer formed on the upper surface of the vertical wall portion 4c.

また、４ａ−１は平板部４ｂ内部の複数のセラミック層４ｂ−１の層間に形成されるとともに線路導体４ａに並列接続された内層導体層である。４ａ−11は、内層導体層４ａ−１の他の形態であって、両端間を並列接続するように形成された複数の配線導体から成る。４ｂ−２は線路導体４ａの一方側の端と内層導体層４ａ−１の一方側の端とを電気的に接続するキャスタレーション導体等から成る一方側の導体層、４ｂ−３は線路導体４ａの他方側の端と内層導体層４ａ−１の他方側の端とを電気的に接続するキャスタレーション導体等から成る他方側の導体層である。 4a-1 is an inner conductor layer formed between the multiple ceramic layers 4b-1 inside the flat plate portion 4b and connected in parallel to the line conductor 4a. 4a-11 is another form of the inner conductor layer 4a-1, and is made up of multiple wiring conductors formed to connect both ends in parallel. 4b-2 is a one-side conductor layer made of a castellation conductor or the like that electrically connects one end of the line conductor 4a and one end of the inner conductor layer 4a-1, and 4b-3 is the other-side conductor layer made of a castellation conductor or the like that electrically connects the other end of the line conductor 4a and the other end of the inner conductor layer 4a-1.

さらに、４ｇ−２は内面に導体層４ｂ−２が形成される切欠き部、４ｇ−３は内面に導体層４ｂ−３が形成される切欠き部であり、内層導体層４ａ−１は端部が切欠き部４ｇ−２，４ｇ−３に向かって漸次幅が狭くなっているとともに先端の幅が切欠き部４ｇ−２，４ｇ−３と同じである。 4g-2 is a notch on whose inner surface the conductor layer 4b-2 is formed, and 4g-3 is a notch on whose inner surface the conductor layer 4b-3 is formed. The width of the inner conductor layer 4a-1 gradually narrows toward the notches 4g-2 and 4g-3 at its ends, and the width of its tip is the same as that of the notches 4g-2 and 4g-3.

また、図４，図５において、１は基体、３は枠体、４は入出力端子、５はシールリング、６は蓋体であり、これらで半導体素子10を内部に収容するためのパッケージが構成される。 In addition, in Figures 4 and 5, 1 is a base body, 3 is a frame body, 4 is an input/output terminal, 5 is a seal ring, and 6 is a lid body, which together form a package for housing a semiconductor element 10 inside.

本発明の入出力端子４は、上面の一辺側から対向する他辺側にかけて形成された線路導体４ａを有するセラミックスから成る直方体の平板部４ｂおよび平板部４ｂの上面に線路導体４ａの一部を間に挟んで接合されたセラミックスから成る立壁部４ｃから構成され、平板部４ｂの下面と立壁部４ｃの上面と線路導体４ａの線路方向に平行な両側面とに接地導体層がそれぞれ形成されている。そして、平板部４ｂは、複数のセラミック層４ｂ−１が積層されて成るとともに一辺側の端面から他辺側の端面にわたる内層導体層４ａ−１が積層されて成り、さらにこれら両端面に上下方向に切欠き部４ｇ−２，４ｇ−３がそれぞれ設けられているとともに切欠き部４ｇ−２，４ｇ−３の内面に線路導体４ａの端および内層導体層４ａ−１の端を電気的に接続する導体層４ｂ−２，４ｂ−３がそれぞれ形成されている。 The input/output terminal 4 of the present invention is composed of a rectangular parallelepiped flat plate portion 4b made of ceramics having a line conductor 4a formed from one side of the upper surface to the opposing other side, and a vertical wall portion 4c made of ceramics joined to the upper surface of the flat plate portion 4b with a part of the line conductor 4a sandwiched between them, and a ground conductor layer is formed on the lower surface of the flat plate portion 4b, the upper surface of the vertical wall portion 4c, and both side surfaces parallel to the line direction of the line conductor 4a. The flat plate portion 4b is formed by laminating multiple ceramic layers 4b-1 and an inner layer conductor layer 4a-1 extending from the end surface of one side to the end surface of the other side, and further, notches 4g-2 and 4g-3 are provided in the vertical direction on both end surfaces, and conductor layers 4b-2 and 4b-3 that electrically connect the end of the line conductor 4a and the end of the inner layer conductor layer 4a-1 are formed on the inner surface of the notches 4g-2 and 4g-3, respectively.

本発明の入出力端子４は、図１，図２に示すように下部接地導体層４ｄ、側部接地導体層４ｅおよび上部接地導体層４ｆが設けられており、図３，図４に示すように、枠体３の側部に設けた貫通孔または切欠き部から成る取付部３ａに嵌着されろう付けされる。これにより、入出力端子４は、枠体３を取付部３ａにおいて気密に封止するとともに、外部電気回路装置からの大きな直流電流を枠体３の内部に収容されている熱電冷却素子11にボンディングワイヤやリード線14を介して伝達する。 The input/output terminal 4 of the present invention is provided with a lower ground conductor layer 4d, a side ground conductor layer 4e, and an upper ground conductor layer 4f as shown in Figures 1 and 2, and is fitted and brazed to a mounting portion 3a consisting of a through hole or a notch provided on the side of the frame body 3 as shown in Figures 3 and 4. As a result, the input/output terminal 4 hermetically seals the frame body 3 at the mounting portion 3a, and transmits a large direct current from an external electric circuit device to the thermoelectric cooling element 11 housed inside the frame body 3 via a bonding wire or lead wire 14.

また、入出力端子４の平板部４ｂおよび立壁部４ｃは電気的な絶縁体であるセラミックスから成り、立壁部４ｃによって線路導体４ａが中央部で区分され、一方側４ａ−２と他方側４ａ−３が露出するように構成されている。 The flat plate portion 4b and the vertical wall portion 4c of the input/output terminal 4 are made of ceramics, which is an electrical insulator, and the vertical wall portion 4c divides the line conductor 4a in the center, so that one side 4a-2 and the other side 4a-3 are exposed.

入出力端子４は、例えばセラミック母基板を多数個に分割する作製法、いわゆる従来公知の多数個取りによる作製法によって作製され、平板部４ｂおよび立壁部４ｃはアルミナ（Ａｌ_２Ｏ_３）質焼結体、窒化アルミニウム（ＡｌＮ）質焼結体、ムライト（３Ａｌ_２Ｏ_３・２ＳｉＯ_２）質焼結体等の焼結体（セラミックス）から成る。 The input/output terminals 4 are fabricated, for example, by a method of dividing a ceramic mother board into many pieces, i.e., a conventionally known method of fabricating many pieces, and the flat plate portion 4b and the vertical wall portion _4c are made of a sintered body (ceramics) such as an alumina ( _Al2O3 ) sintered body, an _aluminum _nitride (AlN) sintered body, or a mullite ( _3Al2O3.2SiO2 ) sintered body.

入出力端子４が例えばＡｌ_２Ｏ_３質焼結体から成る場合、例えば以下のようにして作製される。まずＡｌ_２Ｏ_３の粉末と、焼結助材としての酸化カルシウム（ＳｉＯ_２）、酸化カルシウム（ＣａＯ）、酸化マグネシウム（ＭｇＯ）などの粉末と、適当なバインダーおよび溶剤とを混合してスラリーとなし、これを従来周知のドクターブレード法などのテープ成形法によって所定厚さのセラミックグリーンシートに成形する。次に、焼成後にセラミック層４ｂ−１となる厚さ0.15ｍｍのセラミックグリーンシートを例えば４枚準備し、最下層となるセラミックグリーンシートを除くセラミックグリーンシートに、導体層４ｂ−２、導体層４ｂ−３が形成される貫通孔を周知の金型打抜き法で形成する。それらの貫通孔の内部に、例えばタングステン（Ｗ）を主成分としバインダーおよび有機溶剤が添加混合されて成る導体ペーストが周知のスクリーン印刷法などで埋め込まれるか、または貫通孔の内面に上記導体ペーストが被着されて電気的な導電路が形成される。 When the input/output terminal 4 is made of, for example, an _Al2O3 sintered body, it is manufactured _, for example, as follows. First, _Al2O3 powder, powder of calcium _oxide ( _SiO2 ), calcium oxide (CaO), magnesium oxide (MgO), etc. as a sintering aid, a suitable binder and a solvent are mixed to form a slurry, which is then molded into a ceramic green sheet of a predetermined thickness by a tape molding method such as a doctor blade method known in the art. Next, for example, four ceramic green sheets with a thickness of 0.15 mm that will become the ceramic layer 4b-1 after firing are prepared, and through holes in which the conductor layers 4b-2 and 4b-3 will be formed are formed in the ceramic green sheets except for the ceramic green sheet that will be the bottom layer by a known die punching method. A conductor paste made of, for example, tungsten (W) as the main component with the addition of a binder and an organic solvent is filled into the inside of the through holes by a known screen printing method, or the conductor paste is applied to the inner surface of the through holes to form an electrical conductive path.

これらの貫通孔は、セラミックグリーンシートを積層後に切断分割することによって、縦方向（上下方向）に二分されるように切断されて切欠き部４ｇ−２，４ｇ−３となり、この内面に被着された導体ペーストがキャスタレーション導体等から成る導体層４ｂ−２，４ｂ−３となる。導体層４ｂ−２，４ｂ−３となる貫通孔の幅は0.3〜１ｍｍが好適であり、0.3ｍｍ未満では、大電流を流すことで発生するジュール熱により断線し易くなる。１ｍｍを超える場合、貫通孔の内面に被着した導体層により導通路が形成されるが、その際貫通孔の内面に導体ペーストを被着形成することが困難になる。 These through holes are cut in half vertically (up and down) by cutting and dividing the ceramic green sheets after lamination to form notches 4g-2, 4g-3, and the conductive paste applied to the inner surface becomes conductive layers 4b-2, 4b-3 made of castellation conductors or the like. The width of the through holes that become conductive layers 4b-2, 4b-3 is preferably 0.3 to 1 mm; if it is less than 0.3 mm, it is prone to breakage due to Joule heat generated by passing a large current. If it exceeds 1 mm, a conductive path is formed by the conductive layer applied to the inner surface of the through hole, but it becomes difficult to apply and form the conductive paste on the inner surface of the through hole.

次に、導体ペーストを、焼成後の幅が例えば0.2〜１ｍｍ程度、厚さが５〜20μｍ程度の線路導体４ａとなるように、最上層のセラミックグリーンシート上に印刷塗布する。また、導体ペーストを、焼成後の厚さが５〜20μｍ程度、幅が0.2〜１ｍｍ程度の内層導体層４ａ−１となるように、セラミック層４ｂ−１となるセラミックグリーンシートの上面に印刷塗布する。このとき、図１に示すように導体層４ｂ−２，４ｂ−３が形成される切欠き部４ｇ−２，４ｇ−３にかけて導体ペーストを印刷塗布する。さらに、導体ペーストを、焼成後の厚さが５〜20μｍ程度の下部接地導体層４ｄとなるように、最下層のセラミックグリーンシートの下面に印刷塗布する。 Next, the conductor paste is printed onto the top ceramic green sheet so that it becomes the line conductor 4a with a width of, for example, about 0.2 to 1 mm and a thickness of about 5 to 20 μm after firing. The conductor paste is also printed onto the top surface of the ceramic green sheet that will become the ceramic layer 4b-1 so that it becomes the inner conductor layer 4a-1 with a thickness of about 5 to 20 μm and a width of about 0.2 to 1 mm after firing. At this time, the conductor paste is printed onto the notches 4g-2 and 4g-3 where the conductor layers 4b-2 and 4b-3 will be formed, as shown in FIG. 1. The conductor paste is also printed onto the bottom surface of the bottom ceramic green sheet so that it becomes the lower ground conductor layer 4d with a thickness of about 5 to 20 μm after firing.

これらのセラミックグリーンシートを所定の順序で積層し、平板部４ｂとなる多層構造のセラミックグリーンシート積層体を得る。 These ceramic green sheets are stacked in a predetermined order to obtain a multi-layered ceramic green sheet laminate that will become the flat plate portion 4b.

さらに、焼成後に立壁部４ｃとなる厚さ１ｍｍ程度のセラミックグリーンシートを準備する。このセラミックグリーンシートにおいて、平面視形状が細長い長方形状の貫通孔が複数平行に形成されるように打ち抜くことにより、幅が１ｍｍ、長さが数十ｍｍの複数の細長い帯状部を平行に形成する。その帯状部の上面に上部接地導体層４ｆとなる導体ペーストを、焼成後に５〜20μｍの厚さとなるように印刷塗布する。 Furthermore, a ceramic green sheet with a thickness of about 1 mm is prepared, which will become the vertical wall portion 4c after firing. This ceramic green sheet is punched out so that multiple parallel through holes having an elongated rectangular shape in a plan view are formed, thereby forming multiple parallel elongated strip-shaped portions with a width of 1 mm and a length of several tens of mm. A conductor paste that will become the upper ground conductor layer 4f is printed and applied to the upper surface of the strip-shaped portions so that the thickness after firing is 5 to 20 μm.

次に、上記セラミックグリーンシート積層体上に、上記帯状部を有するセラミックグリーンシートを積層圧着し、帯状部の両側にある長方形状の貫通孔を長手方向に平行な中心線において切断することにより、断面が凸型状のセラミックグリーンシートの積層体を得る。さらに、この積層体を長手方向に対して垂直方向に複数個に切断して入出力端子４となる個片の積層体を得、得られた個片の積層体の側面に側部接地導体層４ｅとなるメタライズ層を焼成後に５〜20μｍ程度の厚さになるように印刷塗布し、最後に1500〜1600℃程度の高温で焼成することにより、入出力端子４が得られる。 Next, a ceramic green sheet having the above-mentioned band-shaped portion is laminated and pressed onto the above-mentioned ceramic green sheet laminate, and the rectangular through holes on both sides of the band-shaped portion are cut along a center line parallel to the longitudinal direction to obtain a ceramic green sheet laminate having a convex cross section. Furthermore, this laminate is cut into multiple pieces perpendicular to the longitudinal direction to obtain individual laminate pieces that will become the input/output terminals 4, and a metallized layer that will become the side ground conductor layer 4e is printed and applied to the side surfaces of the obtained individual laminate pieces so that it will be about 5 to 20 μm thick after firing, and finally, the input/output terminals 4 are obtained by firing at a high temperature of about 1500 to 1600°C.

こうして得られた入出力端子４は、図４，５に示すように枠体３の側部に形成された貫通孔または切欠き部から成る取付部３ａに嵌着され、枠体３に収納される熱電冷却素子11に対する直流電流の入力用端子として機能する。また、入出力端子４において、高周波信号の入出力用として形成される線路導体４ａは、その直下の平板部４ｂ内部には内層導体層４ａ−１が形成されないのがよい。これは、高周波信号の入出力用の線路導体４ａの場合、その特性インピーダンスを所定の値に整合する必要があり、線路導体４ａの直下の平板部４ｂ内部に内層導体層４ａ−１があると特性インピーダンスの整合が困難になるからである。 The input/output terminal 4 thus obtained is fitted into the mounting portion 3a consisting of a through hole or a notch formed on the side of the frame body 3 as shown in Figures 4 and 5, and functions as a terminal for inputting a direct current to the thermoelectric cooling element 11 housed in the frame body 3. In addition, in the input/output terminal 4, it is preferable that the line conductor 4a formed for inputting and outputting high-frequency signals does not have an inner layer conductor layer 4a-1 formed inside the flat plate portion 4b directly below it. This is because, in the case of the line conductor 4a for inputting and outputting high-frequency signals, it is necessary to match its characteristic impedance to a predetermined value, and if there is an inner layer conductor layer 4a-1 inside the flat plate portion 4b directly below the line conductor 4a, it becomes difficult to match the characteristic impedance.

本発明の入出力端子４は、線路導体４ａと内層導体層４ａ−１とで並列回路が構成されていること、また好ましくは内層導体層４ａ−１が並列接続されるように形成された配線導体４ａ−11で構成されていることから、線路導体４ａの一方側４ａ−３に入力された大きな直流電流は、導体層４ｂ−３を介して線路導体４ａと内層導体層４ａ−１とに分かれて伝達され、内層導体層４ａ−１を流れる直流電流は導体層４ｂ−２によって線路導体４ａの他方側４ａ−２に至り、線路導体４ａを流れる直流電流と合流して基体１の載置部１ａに載置されている熱電冷却素子11に送られる。その結果、熱電冷却素子11で光半導体素子10が良好に冷却され、安定した信号を光半導体素子10より出力することができる。 The input/output terminal 4 of the present invention is configured such that a parallel circuit is formed by the line conductor 4a and the inner conductor layer 4a-1, and preferably is configured by the wiring conductor 4a-11 formed so that the inner conductor layer 4a-1 is connected in parallel. Therefore, a large DC current input to one side 4a-3 of the line conductor 4a is divided and transmitted to the line conductor 4a and the inner conductor layer 4a-1 via the conductor layer 4b-3, and the DC current flowing through the inner conductor layer 4a-1 reaches the other side 4a-2 of the line conductor 4a by the conductor layer 4b-2, where it is merged with the DC current flowing through the line conductor 4a and sent to the thermoelectric cooling element 11 mounted on the mounting portion 1a of the base 1. As a result, the optical semiconductor element 10 is well cooled by the thermoelectric cooling element 11, and a stable signal can be output from the optical semiconductor element 10.

このように、本発明の入出力端子４によれば、外部電気回路装置からの大きな直流電流が、平板部４ｂに形成された、線路導体４ａおよび内層導体層４ａ−１により構成された並列回路を流れることにより、線路導体４ａを流れる電流が小さくなるため抵抗も小さくなり、大きな熱が発生することがなくなる。また、従来の入出力端子24では、線路導体４ａの幅を広げようとすると入出力端子24の大きさが数倍程度に大きくなり、枠体３の側部に嵌着できなくなるという問題があり、また線路導体４ａを厚くしようとするとセラミックグリーンシート同士に接合不良が生じることから、線路導体４ａの抵抗を小さくすることが困難であったものが、本発明の入出力端子４により、線路導体４ａの幅や厚さを大きくせずに入出力端子４の大きさを従来通りとすることができる。また、平板部４ｂと立壁部４ｃとの接合部に接合不良が発生することがないものとなる。 In this way, according to the input/output terminal 4 of the present invention, a large DC current from an external electric circuit device flows through a parallel circuit formed on the flat plate portion 4b and composed of the line conductor 4a and the inner conductor layer 4a-1, so that the current flowing through the line conductor 4a becomes small, and the resistance also becomes small, and no large heat is generated. In addition, with the conventional input/output terminal 24, if the width of the line conductor 4a is increased, the size of the input/output terminal 24 becomes several times larger, and there is a problem that it cannot be fitted to the side of the frame body 3, and if the line conductor 4a is made thicker, poor bonding occurs between the ceramic green sheets, making it difficult to reduce the resistance of the line conductor 4a. However, with the input/output terminal 4 of the present invention, the size of the input/output terminal 4 can be kept the same as before without increasing the width or thickness of the line conductor 4a. In addition, poor bonding does not occur at the joint between the flat plate portion 4b and the vertical wall portion 4c.

本発明の入出力端子４において、内層導体層４ａ−１は単層または複数層設けることができるが、複数層設ける場合10層以下がよい。10層を超えると、抵抗が減少しにくくなる。また、内層導体層４ａ−１の厚さは５〜25μｍがよく、５μｍ未満では、抵抗を下げることが困難になる。25μｍを超えると、層間に剥離が発生し易くなる。 In the input/output terminal 4 of the present invention, the inner conductor layer 4a-1 can be a single layer or multiple layers, but if multiple layers are provided, it is preferable to provide 10 layers or less. If there are more than 10 layers, it becomes difficult to reduce the resistance. In addition, the thickness of the inner conductor layer 4a-1 is preferably 5 to 25 μm, and if it is less than 5 μm, it becomes difficult to reduce the resistance. If it exceeds 25 μm, peeling between the layers is likely to occur.

さらに、セラミック層４ｂ−１の厚さは100〜635μｍ程度がよく、100μｍ未満では、位置合せしたり積層することが困難となる。635μｍを超えると、貫通孔への導体ペーストの充填や被着が困難となる。 Furthermore, the thickness of the ceramic layer 4b-1 is preferably about 100 to 635 μm. If it is less than 100 μm, it becomes difficult to align and stack. If it exceeds 635 μm, it becomes difficult to fill and apply the conductive paste to the through holes.

また、図２に平板部４ｂのセラミック層４ｂ−１に形成された内層導体層４ａ−１の平面図を示すように、切欠き部４ｇ−２，４ｇ−３は内層導体層４ａ−１の中央部よりも幅が狭く、かつ内層導体層４ａ−１は端部が切欠き部４ｇ−２，４ｇ−３に向かって漸次幅が狭くなっているとともに先端の幅が切欠き部４ｇ−２，４ｇ−３と同じであることにより、内層導体層４ａ−１の先端にセラミックグリーンシートの密着面４ａ−４が形成され、セラミックグリーンシートを積層して平板部４ｂを形成する際、切欠き部を有するセラミックグリーンシートを内層導体層４ａ−１を挟み込むように積層しても、内層導体層４ａ−１の端部の両側における上下のセラミックグリーンシート同士の密着面積を大きくすることができ、セラミックグリーンシート間に剥がれが生じるのを有効に抑制することができる。その結果、入出力端子４の気密性および導通信頼性を向上させ、半導体素子の作動性を向上させることができる。 As shown in FIG. 2, the plan view of the inner conductor layer 4a-1 formed on the ceramic layer 4b-1 of the flat plate portion 4b, the notches 4g-2 and 4g-3 are narrower than the center of the inner conductor layer 4a-1, and the end of the inner conductor layer 4a-1 gradually narrows toward the notches 4g-2 and 4g-3, and the width of the tip is the same as that of the notches 4g-2 and 4g-3. This allows the adhesion surface 4a-4 of the ceramic green sheet to be formed at the tip of the inner conductor layer 4a-1, and when the ceramic green sheets are laminated to form the flat plate portion 4b, even if the ceramic green sheets having the notches are laminated so as to sandwich the inner conductor layer 4a-1, the adhesion area between the upper and lower ceramic green sheets on both sides of the end of the inner conductor layer 4a-1 can be increased, and peeling between the ceramic green sheets can be effectively suppressed. As a result, the airtightness and conduction reliability of the input/output terminal 4 can be improved, and the operability of the semiconductor element can be improved.

また、内層導体層４ａ−１の先端の幅は切欠き部４ｇ−２，４ｇ−３と同じであることから、内層導体層４ａ−１が切欠き部４ｇ−２，４ｇ−３を全周にわたって覆うことができ、内層導体層４ａ−１と切欠き部４ｇ−２，４ｇ−３の内面の導体層４ｂ−２，４ｂ−３との接触面積を大きくすることができる。特に、切欠き部４ｇ−２，４ｇ−３の内面の全面に導体層４ｂ−２，４ｂ−３を形成すれば、切欠き部４ｇ−２，４ｇ−３の内面の導体層と内層導体層４ｂ−２，４ｂ−３との接触面積を非常に大きくすることができ、上下の内層導体層４ａ−１同士を低抵抗で接続することができる。その結果、入出力端子４の電気的特性を良好にすることができる。 In addition, since the width of the tip of the inner conductor layer 4a-1 is the same as that of the notches 4g-2 and 4g-3, the inner conductor layer 4a-1 can cover the entire circumference of the notches 4g-2 and 4g-3, and the contact area between the inner conductor layer 4a-1 and the conductor layers 4b-2 and 4b-3 on the inner surfaces of the notches 4g-2 and 4g-3 can be increased. In particular, if the conductor layers 4b-2 and 4b-3 are formed on the entire inner surfaces of the notches 4g-2 and 4g-3, the contact area between the conductor layers on the inner surfaces of the notches 4g-2 and 4g-3 and the inner conductor layers 4b-2 and 4b-3 can be greatly increased, and the upper and lower inner conductor layers 4a-1 can be connected with low resistance. As a result, the electrical characteristics of the input/output terminal 4 can be improved.

さらに、切欠き部の一方４ｇ−２は平面視における最奥部の形状が半円状であるとともに線路導体４ａの線路方向における長さＡが内層導体層４ａ−１の端部の長さＢよりも長いことから、切欠き部４ｇ−２の最奥部の導体層４ｂ−２に熱電冷却素子のリード線14を接続した際、リード線14の周囲を大面積の内層導体層４ａ−１で覆うことができるため、リード線14の周囲の内層導体層４ａ−１の抵抗を小さくして内層導体層４ａ−１からリード線14へ電流を非常に流し易くすることができる。さらに、大電流が流れることによってリード線14と切欠き部４ｇ−２内面の導体層４ｂ−２との接続部付近が発熱し、リード線14と平板部４ｂとの間に熱膨張係数差が生じたとしても、リード線14周囲に内層導体層４ａ−１が大きな面積で配設されているのでリード線14周囲の平板部４ｂを内層導体層４ａ−１で有効に補強することができるとともに、切欠き部４ｇ−２の最奥部を半円状として応力を集中し難くすることにより、リード線14周囲の平板部４ｂにクラックが生じるのを有効に防止することができる。 Furthermore, one of the cutouts 4g-2 has a semicircular shape at its innermost part in a plan view, and the length A of the line conductor 4a in the line direction is longer than the length B of the end of the inner conductor layer 4a-1. Therefore, when the lead wire 14 of the thermoelectric cooling element is connected to the innermost conductor layer 4b-2 of the cutout 4g-2, the lead wire 14 can be covered with a large area of the inner conductor layer 4a-1. This reduces the resistance of the inner conductor layer 4a-1 around the lead wire 14, making it very easy to pass a current from the inner conductor layer 4a-1 to the lead wire 14. Furthermore, even if a large current flows and heat is generated near the connection between the lead wire 14 and the conductor layer 4b-2 on the inner surface of the notch 4g-2, causing a difference in thermal expansion coefficient between the lead wire 14 and the flat plate portion 4b, the inner conductor layer 4a-1 is arranged over a large area around the lead wire 14, so the flat plate portion 4b around the lead wire 14 can be effectively reinforced by the inner conductor layer 4a-1, and the innermost part of the notch 4g-2 is semicircular, making it difficult for stress to concentrate, effectively preventing cracks from occurring in the flat plate portion 4b around the lead wire 14.

また本発明において、図３に示すように、内層導体層４ａ−１は、線路導体４ａの両端にそれぞれ接続される導体層４ｂ−２，４ｂ−３との接続部間を並列接続するように形成された複数の配線導体４ａ−11から成っていることが好ましい。これにより、さらに線路導体４ａの両端間の抵抗を小さくすることができ、よってさらに大きな直流電流を流すことができる。この場合、複数の配線導体４ａ−11の本数は２〜10本がよく、２本未満では、導体層４ｂ−２，４ｂ−３間の抵抗の減少が小さくジュール熱の発生が大きくなり易い。10本を超えると、抵抗減少効果が小さくなっていく。 In the present invention, as shown in FIG. 3, it is preferable that the inner conductor layer 4a-1 is composed of a plurality of wiring conductors 4a-11 formed so as to connect in parallel between the connection parts with the conductor layers 4b-2 and 4b-3, which are respectively connected to both ends of the line conductor 4a. This further reduces the resistance between both ends of the line conductor 4a, and therefore allows a larger DC current to flow. In this case, the number of the plurality of wiring conductors 4a-11 is preferably 2 to 10. If there are fewer than two, the reduction in resistance between the conductor layers 4b-2 and 4b-3 is small, and Joule heat is likely to be generated. If there are more than 10, the effect of reducing resistance becomes smaller.

また、複数の配線導体４ａ−11は、導体層４ｂ−２，４ｂ−３との接続部より離れたものほど配線長が長くなり抵抗が増大するので、導体層４ｂ−２，４ｂ−３との接続部から離れるに従って幅広に形成し抵抗を小さくするのがよく、全体として同程度の抵抗の配線導体４ａ−11とすることができる。 In addition, the multiple wiring conductors 4a-11 have a longer wiring length and higher resistance the further they are from the connection parts with the conductor layers 4b-2 and 4b-3. Therefore, it is preferable to make the wiring conductors 4a-11 wider and reduce resistance the further they are from the connection parts with the conductor layers 4b-2 and 4b-3, and it is possible to make the wiring conductors 4a-11 have the same resistance overall.

そして、本発明の光半導体装置は、入出力端子４を枠体３の側部の取付部３ａにＡｇロウなどのロウ材で嵌着するとともに円筒状等の筒状の光ファイバ固定部材２を枠体３の他の側部の取付部３ｂにＡｇロウなどのロウ材で嵌着し、さらに熱電冷却素子11を載置部１ａに載置して熱電冷却素子11上に光半導体素子10を半田材等で搭載固定し、枠体３の上面にＦｅ−Ｎｉ−Ｃｏ合金等から成る蓋体（図示せず）を接合することにより作製される。 The optical semiconductor device of the present invention is fabricated by fitting the input/output terminals 4 to the mounting portion 3a on the side of the frame 3 with a brazing material such as Ag brazing, fitting the cylindrical optical fiber fixing member 2 to the mounting portion 3b on the other side of the frame 3 with a brazing material such as Ag brazing, placing the thermoelectric cooling element 11 on the mounting portion 1a, mounting and fixing the optical semiconductor element 10 on the thermoelectric cooling element 11 with a solder material or the like, and joining a lid (not shown) made of an Fe-Ni-Co alloy or the like to the top surface of the frame 3.

かくして、本発明の入出力端子４を有する枠体３は、大きな直流電流で作動させる熱電冷却素子11を収納し得るものとなる。 Thus, the frame 3 having the input/output terminals 4 of the present invention can house a thermoelectric cooling element 11 that operates with a large DC current.

なお、本発明は上記実施の形態に限定されるものではなく、本発明の要旨を逸脱しない範囲内であれば種々の変更を施すことは可能である。例えば、上記実施の形態では、本発明の入出力端子４を光半導体素子収納用パッケージに適用した場合について説明したが、混成集積回路基板等の入出力端子として本発明の入出力端子４を適用してもよい。また、半導体素子として光半導体素子10ではなくＩＣ，ＬＳＩ等の半導体集積回路素子を用いる場合、光ファイバ固定部材２およびその取付部３ｂは不要である。 The present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the present invention. For example, in the above embodiment, the input/output terminal 4 of the present invention is applied to a package for housing an optical semiconductor element, but the input/output terminal 4 of the present invention may also be applied as an input/output terminal of a hybrid integrated circuit board or the like. Furthermore, if a semiconductor integrated circuit element such as an IC or LSI is used as the semiconductor element instead of an optical semiconductor element 10, the optical fiber fixing member 2 and its mounting portion 3b are not necessary.

本発明はＩＣ，ＬＳＩ等の半導体集積回路素子や光通信用の光半導体素子などを収納するための半導体素子収納用パッケージに用いられる入出力端子、およびそれを用いた半導体素子収納用パッケージならびに半導体装置において、大きな直流電力を内部に供給するものに好適に利用できる。 The present invention can be suitably used for input/output terminals used in semiconductor element storage packages for storing semiconductor integrated circuit elements such as ICs and LSIs, and optical semiconductor elements for optical communications, as well as for semiconductor element storage packages and semiconductor devices using the same that supply large DC power to the inside.

本発明の入出力端子について実施の形態の例を示すものであり、（ａ）は入出力端子の断面図、（ｂ）は入出力端子の要部上面図、（ｃ）は入出力端子の要部斜視図である。1A is a cross-sectional view of the input/output terminal according to an embodiment of the present invention, FIG. 1B is a top view of the main part of the input/output terminal, and FIG. 1C is a perspective view of the main part of the input/output terminal. （ａ）は図１の入出力端子におけるリード線が接続される一方側の内層導体層の要部平面図、（ｂ）は図１の入出力端子における他方側の内層導体層の要部平面図である。2A is a plan view of a main portion of an inner conductor layer on one side to which a lead wire is connected in the input/output terminal of FIG. 1, and FIG. 2B is a plan view of a main portion of an inner conductor layer on the other side in the input/output terminal of FIG. 本発明の入出力端子における内層導体層について実施の形態の他の例を示す平面図である。11 is a plan view showing another example of an inner conductor layer in an input/output terminal according to the present invention; FIG. 本発明の半導体素子収納用パッケージについて実施の形態の例を示す断面図である。1 is a cross-sectional view showing an example of an embodiment of a package for housing a semiconductor element according to the present invention; 図４の半導体素子収納用パッケージの斜視図である。FIG. 5 is a perspective view of the semiconductor device housing package of FIG. 4. 従来の半導体素子収納用パッケージの断面図である。FIG. 1 is a cross-sectional view of a conventional package for housing a semiconductor element. 図６の半導体素子収納用パッケージの斜視図である。FIG. 7 is a perspective view of the semiconductor element housing package of FIG. 6.

Explanation of symbols

１：基体
１ａ：載置部
３：枠体
４：入出力端子
４ａ：線路導体
４ａ−１：内層導体層
４ｂ：平板部
４ｂ−１：セラミック層
４ｂ−２，４ｂ−３：導体層
４ｃ：立壁部
４ｄ：下部接地導体層
４ｅ：側部接地導体層
４ｆ：上部接地導体層
４ｇ−２，４ｇ−３：切欠き部
10：半導体素子
11：熱電冷却素子 1: Base body 1a: Mounting portion 3: Frame body 4: Input/output terminal 4a: Line conductor 4a-1: Inner conductor layer 4b: Flat plate portion 4b-1: Ceramic layers 4b-2, 4b-3: Conductor layer 4c: Standing wall portion 4d: Lower ground conductor layer 4e: Side ground conductor layer 4f: Upper ground conductor layer 4g-2, 4g-3: Notch portion
10. Semiconductor elements
11: Thermoelectric cooling element

Claims

In an input/output terminal that is composed of a rectangular parallelepiped flat plate portion made of ceramics having a line conductor formed from one side of the upper surface to the opposing other side, and a vertical wall portion made of ceramics joined to the upper surface of the flat plate portion with a portion of the line conductor sandwiched therebetween, and in which ground conductor layers are formed on the lower surface of the flat plate portion, the upper surface of the vertical wall portion, and both side surfaces parallel to the line direction of the line conductor, the flat plate portion is composed of a plurality of laminated ceramic layers, and an inner layer conductor layer is provided from the end surface of the one side to the end surface of the other side, and further, both end surfaces are formed with a vertical conductor layer. An input/output terminal in which a notch is provided in each of the terminals, and a conductor layer that electrically connects the end of the line conductor and the end of the inner conductor layer is formed on the inner surface of the notch, the notch is narrower than the center of the inner conductor layer, the end of the inner conductor layer gradually narrows toward the notch and has the same width as the notch, and further, one of the notches has a semicircular shape at its innermost part in a plan view, and the length of the line conductor in the line direction is longer than the end of the inner conductor layer.

A package for housing semiconductor elements, comprising: a base having a mounting portion on the upper surface of which a semiconductor element is mounted via a thermoelectric cooling element; a frame body attached to the upper surface of the base so as to surround the mounting portion and having an input/output terminal mounting portion formed of a through hole or a notch on the side; and the input/output terminal according to claim 1 fitted into the mounting portion of the input/output terminal, wherein the lead wire of the thermoelectric cooling element is soldered to one of the notches of the input/output terminal and electrically connected to the line conductor.

A semiconductor device comprising the package for housing a semiconductor element according to claim 2, the thermoelectric cooling element brazed to the mounting portion and electrically connected to the line conductor with the lead wire soldered to one of the notches of the input/output terminal, a semiconductor element mounted and fixed on the upper surface of the thermoelectric cooling element and electrically connected to the input/output terminal, and a lid attached to the upper surface of the frame.