JP2003338627A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To attain a semiconductor device which can be formed without being affected by a step of an under layer pattern. <P>SOLUTION: A smooth inclined plane is formed on a cap (dielectric layer) 30 which is formed over a groove 13 and covers a doped polysilicon 5. Y/X≤5 is met, where X is the in-plane length of the surface of the body 50 of the inclined plane 26, and Y is the height of the body 50 of the inclined plane 26 from its surface. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as an IGBT (insulated gate bipolar transistor) and a manufacturing method thereof.

[0002]

2. Description of the Related Art Miniaturization is indispensable for improving the performance of semiconductor devices, and power semiconductors are no exception. However, as miniaturization progresses, the unevenness of the shape per unit area on the surface of the semiconductor device becomes more severe, which adversely affects the device performance, manufacturing process, and reliability. In particular, power transistors, power MOS-FETs, IGBTs, thyristors, G having current densities ranging from several A / cm ² to several hundred A / cm ^2.
In power semiconductor devices such as TO and MOS gate thyristors, (1) thickening of the aluminum electrode wiring on the surface (2) thickness uniformity (3) flatness is an important issue.

By carrying out (1), it is possible to lower the power loss by lowering the resistance value of the aluminum electrode wiring and raise the operating frequency of the device. By carrying out (2),
By making the resistance value in the aluminum electrode wiring uniform,
It is possible to expand the safe operation of the entire device and the safe operation area (SOA), and by carrying out (3), it is possible to reduce the contact resistance in wire bonding and press contact when assembling a semiconductor chip package.

In recent years, with the increase in integration and performance of general semiconductor devices, the circuit patterns formed therein are becoming finer and more precise, and it is necessary to form them with high precision.

On the other hand, the circuit pattern of the power semiconductor device is not so fine as that of the other semiconductor devices. However, in recent years, there is an increasing tendency for power semiconductor devices to have finer circuit patterns for higher integration and higher performance, as in general semiconductor devices.

In the process step of forming the electrode wiring connected between the electrodes or to the external terminal in the power semiconductor device, many steps have been performed before. Therefore, the step difference of the surface shape before the electrode wiring is formed. Is often getting bigger.

Although aluminum or an Al alloy such as AlSi is generally used for the electrode wiring, it is technically difficult to form the Al or Al alloy flat, and improvement thereof is desired.

FIG. 28 shows a trench gate type I which is a conventional power semiconductor device in which a high step pattern is formed in electrode wiring.
It is a cross-sectional schematic diagram which showed the structure of GBT (IGBT: Insulated gate Bipolar Transistor).

28, an electrode wiring formation in a conventional trench gate type IGBT will be described as an example with reference to FIG.

As shown in the figure, an n ⁻ semiconductor layer 2 is formed on one main surface of a p ⁺ semiconductor substrate 1 having one main surface and the other main surface.
Is formed, the p semiconductor layer 3 is formed on the n ⁻ semiconductor layer, and the n ⁺ semiconductor layer 4 is formed on the p semiconductor layer 3. Then, n ⁺ penetrates from the surface of the semiconductor layer 4 the n ⁺ semiconductor layer 4 and the p semiconductor layer 3 n ^- a plurality of grooves 13 over the portion of the semiconductor layer 2 of the surface (two in FIG. 28) is formed . Groove 1
The sectional shape of 3 is Y-shaped and the bottom is rounded.

A silicon oxide film 14 is formed on the inner wall of each groove 13, and a doped polysilicon 5 which is a low resistance conductive filler is formed in most of the inside of each groove 13 through the silicon oxide film 14. Is filled. Examples of the doped polysilicon 5 include phosphorus-doped n-type doped polysilicon. The doped polysilicon 5 functions as a control electrode, and regions near both outer wall surfaces of the groove 13 in the p semiconductor layer 3 serve as channel regions.

A silicon oxide film 2 is formed on each polysilicon 5.
7 is formed. The silicon oxide film 7 is formed, for example, as follows. After the doped polysilicon 5 filling the whole of the groove 13 is etched to some extent in the depth direction of the groove 13, a silicon oxide film 7 is formed on the doped polysilicon 5 for the purpose of covering the opening of the groove 13. It is formed by using the CVD method or the like. The silicon oxide film 7 caps the opening of the groove 13.

A refractory metal film 8 serving as a silicide layer or a barrier metal for realizing a low ohmic resistance is deposited on the silicon oxide film 7, and a refractory metal film 8 is deposited on the refractory metal film 8.
The electrode wiring layer 6 made of an l-alloy film is formed. In addition,
In this case, the refractory metal film 8 is an alloy film.

[0014]

Since the electrode wiring layer 6 of the conventional trench gate type IGBT is constructed as described above, the silicon oxide film 7 formed on the doped polysilicon 5 in the groove 13 is formed. A “void” or a cavity 9 is formed inside, reflecting the sharp shape of the tip. When a “void” or a cavity is formed in the electrode wiring layer 6, the electric resistance of the electrode wiring layer 6 becomes high and desired electric characteristics cannot be obtained.

Further, in an extreme case, there is a problem that the electrode wiring layer 6 is disconnected due to a "void" or a cavity at a high step portion, which causes a fatal defect in electrical resistance and reliability. It was

The present invention has been made to solve the above problems, and it is an object of the present invention to obtain a semiconductor device in which a layer can be formed without any defect without being affected by the step of the underlying pattern and a manufacturing method thereof. To aim.

[0017]

A semiconductor device according to a first aspect of the present invention has one main surface and the other main surface,
A base including a first semiconductor region of a predetermined conductivity type in one main surface and a second semiconductor region of the predetermined conductivity type in the other main surface, each having a predetermined depth from one main surface of the base. A plurality of groove portions selectively formed, a plurality of insulating films formed on the inner walls of the plurality of groove portions, and a plurality of controls filled in the plurality of groove portions via the plurality of insulating films. An electrode layer, a plurality of insulating layers formed on the plurality of control electrode layers so as to project from the surface of the base body, and the first base layer of the base body.
A first main electrode formed on at least half the formation area of the semiconductor region and a second main electrode formed on the second semiconductor region of the base, and the plurality of control electrodes are provided. A control voltage commonly applied to the layers controls a current flowing between the first and second main electrodes through the first and second semiconductor regions, and the plurality of insulating layers are respectively arranged from top to bottom. It has a gently sloping surface over
Conditional expression: Y / X ≦ 5, where X is the length of the inclined surface in the in-plane direction of the one main surface of the base body, and Y is the formation height of the inclined surface from the one main surface of the base body. To be satisfied.

A semiconductor device according to a second aspect of the present invention has one main surface and the other main surface, the first semiconductor region of a predetermined conductivity type is provided in the one main surface, and the other main surface is provided in the first semiconductor region. A base body including a second semiconductor region of a predetermined conductivity type, a plurality of groove portions each selectively formed at a predetermined depth from one main surface of the base body, and the base body from an inner wall of the plurality of groove portions. A plurality of insulating films formed to extend over a part of one main surface of the base and the inside of the plurality of trenches filled with the plurality of insulating films; On the plurality of control electrode layers formed to extend on the part of the one main surface and on the plurality of control electrode layers in the plurality of groove portions, a plurality of the control electrode layers formed to project from one main surface of the base body. The insulating layer and the formation area of at least half or more of the first semiconductor region of the base A first main electrode formed on the first semiconductor electrode and a second main electrode formed on the second semiconductor region of the base, and the first main electrode is formed by a control voltage commonly applied to the plurality of control electrode layers. And a current flowing between the second main electrodes via the first and second semiconductor regions is controlled,
Each of the plurality of insulating layers on each of the plurality of grooves has a gentle slope from the upper side to the lower side, and X is the length of the slope in the direction of the one main surface of the base, and Y is the base of the slope. Forming height from one main surface of the base, H1: forming height from one main surface of the base of each of the plurality of control electrode layers formed on the part of the one main surface of the base, H2: When the formation height of each of the plurality of insulating layers from the one main surface of the base on the plurality of grooves is defined, the conditional expression: H2 ≧ H1 and the conditional expression: Y / X ≦ 5 are both satisfied.

According to a third aspect of the present invention, the plurality of groove portions are formed at a predetermined distance from each other,
If W: the predetermined distance, H: height of each of the plurality of insulating layers from one main surface of the substrate, the conditional expression: (W / H) ≦ 8 may be satisfied. Good.

Further, according to a fourth aspect of the present invention, the plurality of insulating layers are respectively a base insulating layer formed on the control electrode layer and a main insulating layer formed on the base insulating layer. You may comprise so that it may consist of.

Further, according to a fifth aspect of the present invention, each of the plurality of insulating layers is a base insulating layer formed on the control electrode layer and a main insulating layer formed on the base insulating layer. And an auxiliary insulating layer formed on the main insulating layer.

A semiconductor device according to a sixth aspect of the present invention has one main surface and the other main surface, and is composed of at least one upper surface side upper layer portion and the other main surface side lower layer portion. Of the first conductive type semiconductor, a plurality of second conductive type first semiconductor regions selectively formed in the upper layer portion of the base, and a plurality of the first semiconductor regions. A plurality of second conductivity types of the first conductivity type selectively formed on the surface;
Semiconductor regions, a plurality of insulating films formed on one region of each of the first semiconductor regions between the upper layer portion of the base and each of the second semiconductor regions, and the plurality of insulating films. A plurality of control electrodes formed thereon, a plurality of insulating layers formed over the plurality of insulating films and the plurality of control electrodes, and a first main electrode formed on one main surface of the base body And a second main electrode formed on the other main surface of the base body, and controlling a current flowing between the first and second main electrodes by a control voltage commonly applied to the plurality of control electrodes. The plurality of insulating layers each have a gentle inclined surface from the upper portion to the lower portion, X: the length of the inclined surface in the in-plane direction of the one main surface of the base body, Y: the inclined surface Conditional expression: Y / X ≦ 5 To.

According to a seventh aspect of the present invention, the plurality of control electrodes are formed at a predetermined distance from each other, and W: the predetermined distance, H: one main surface of the base of the insulating layer. When the formation height of is, the conditional expression: (W
/ H) ≦ 8 may be satisfied.

According to the eighth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: (a) a main surface on one side and a main surface on the other side. A base body configured to have the upper layer portion made of a semiconductor of a first conductivity type is prepared, and the upper layer portion of the base body is selectively formed;
A plurality of first semiconductor regions of conductivity type, and the plurality of first semiconductor regions
Selectively formed on the surface of each semiconductor region of the first
A plurality of second semiconductor regions of conductivity type, and a plurality of second semiconductor regions formed on one region of each of the first semiconductor regions between the upper layer portion of the base and each of the second semiconductor regions. A step of forming a MOS structure comprising an insulating film and a plurality of control electrodes respectively formed on the plurality of insulating films; and (b) an insulating layer on one main surface of the base body including the plurality of control electrodes. And (c) patterning the insulating layer to form an opening at a predetermined location, and (d) heat treating the patterned insulating layer to form the opening in the insulating layer. Forming a sloping surface in the region near the portion, (e) forming a first main electrode on one main surface of the base, and (f) forming a second main surface on the other main surface of the base. After forming the device, In the method of manufacturing a semiconductor device in which a current flowing between the first and second main electrodes is controlled by a control voltage commonly applied to a plurality of control electrodes, the heat treatment in the step (d) is carried out when the insulating layer is It is performed at a temperature of softening or higher, and the sloped surface of the insulating layer has X: the length of the sloped surface in the direction of the one main surface of the base body, Y: the formation height of the sloped surface from the one main surface of the base body. , The conditional expression: Y / X ≦ 5 is satisfied.

According to a ninth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein the plurality of control electrodes are formed at a predetermined distance, and W: the predetermined distance, H: one of the bases of the insulating layer. The conditional expression: (W / H) ≦ 8 may be satisfied when the formation height from the main surface is defined.

[0026]

In the semiconductor device according to claim 1 of the present invention, the plurality of insulating layers respectively formed on the plurality of grooves have an inclined surface, and the inclined surface is X: one of the bases of the inclined surface. When the length of the main surface in the in-plane direction is Y, and the height of the inclined surface is formed from one main surface of the substrate, the conditional expression: Y / X ≦ 5 is satisfied. The step formed from the one main surface of the substrate due to the formation of the above does not adversely affect the overlying layer.

In the semiconductor device according to the second aspect of the present invention, the plurality of insulating layers formed on the plurality of grooves have an inclined surface, and the inclined surface has the above-mentioned conditional expression: Y / X.
Since ≦ 5 is satisfied, the step from the one main surface of the substrate caused by the formation of the plurality of insulating layers does not adversely affect the layer to be stacked.

Further, since the plurality of insulating layers satisfy the above conditional expression: H2 ≧ H1, the plurality of insulating layers are formed so as to cover the control electrode layer formed on the one main surface of the base. It is possible to obtain a plurality of insulating layers having a relatively flat surface.

Further, in the semiconductor device according to the present invention, further, the plurality of grooves are formed at a predetermined distance, and W: the predetermined distance, H: one main body of each of the plurality of insulating layers. In the case of the formation height from the surface, since the conditional expression: (W / H) ≦ 8 is satisfied, the integration degree can be maintained at a relatively high level.

According to the semiconductor device of claim 4,
Since each of the plurality of insulating layers is composed of a base insulating layer formed on the control electrode layer and a main insulating layer formed on the base insulating layer, interference between the main insulating layer and the control electrode layer is prevented. It can be prevented by an insulating layer.

In addition, in the semiconductor device according to the present invention, by forming the auxiliary insulating layer on the main insulating layer, the height of the insulating layer can be relatively easily formed to a desired height. Therefore, it becomes easy to achieve the conditional expression H2 ≧ H1.

In the semiconductor device according to claim 6 of the present invention, the plurality of insulating layers formed on the plurality of grooves have an inclined surface, and the inclined surface is X: one main part of the base of the inclined surface. Where Y is the in-plane length of the surface, and Y is the height of the inclined surface formed from one main surface of the substrate, the conditional expression:
Since Y / X ≦ 5 is satisfied, the step difference from the one main surface of the substrate caused by the formation of the plurality of insulating layers does not have a bad influence on the overlying layer.

Further, in the semiconductor device according to the present invention, further, a plurality of control electrodes are formed with a predetermined distance therebetween, and W: the predetermined distance, H: one of the bases of each of the plurality of insulating layers. When forming height from the main surface, the conditional expression: (W / H) ≦ 8 is satisfied, so that the degree of integration can be maintained at a relatively high level.

Further, in the method of manufacturing a semiconductor device according to claim 8, the inclined surface of the insulating layer is X: the length of the inclined surface in the direction of the one main surface of the substrate, and Y: the inclined surface. When the formation height from one main surface of the substrate is satisfied, the conditional expression: Y / X ≦ 5 is satisfied, so that the step from the one main surface of the substrate caused by the formation of this insulating layer is It does not have a bad influence.

Further, in the method of manufacturing a semiconductor device according to claim 9, the plurality of control electrodes are formed at a predetermined distance, and W: the predetermined distance, H: one of the bases of each of the plurality of insulating layers. When forming height from the main surface,
Since the conditional expression: (W / H) ≦ 8 is satisfied, the degree of integration can be maintained at a relatively high level.

[0036]

BEST MODE FOR CARRYING OUT THE INVENTION << First Embodiment >><Structure> FIG. 1 is a sectional view showing the structure of a trench gate type IGBT according to a first embodiment of the present invention. As shown in the figure, an n ⁻ semiconductor layer 2 is formed on one main surface of a p ⁺ semiconductor substrate 1 having one main surface and the other main surface,
The p semiconductor layer 3 is formed on the n ⁻ semiconductor layer, and the n ⁺ semiconductor layer 4 is formed on the p semiconductor layer 3. Then, n ⁺ penetrates from the surface of the semiconductor layer 4 the n ⁺ semiconductor layer 4 and the p semiconductor layer 3 n ^- a plurality of grooves over the part of the semiconductor layer 2 of the surface 13
(Two in FIG. 1) are formed. The cross-sectional shape of the groove 13 is Y
The shape is round and the bottom is rounded.

A silicon oxide film 14 is formed on the inner wall of each groove 13, and a doped polysilicon 5 which is a low resistance conductive filler is formed in most of the inside of each groove 13 through the silicon oxide film 14. Is filled. Examples of the doped polysilicon 5 include phosphorus-doped n-type doped polysilicon. The doped polysilicon 5 functions as an insulated gate type control electrode via the silicon oxide film 14, and the regions in the p semiconductor layer 3 near both outer wall surfaces of the trench 13 serve as channel regions.

Then, a thin CVD oxide film 12 is formed on the doped polysilicon 5, and a plurality of BPSGs (Borophosph) are formed so as to cover each groove 13 including the CVD oxide film 12.
o silicate glass) films 10 are formed respectively. Then, a silicon oxide film 7 is further formed on the top of the BPSG film 10, and the BPSG film 10 and the silicon oxide film 7 cap a plurality of cap portions 3 for capping the opening of the groove 13.
Forming 0.

A refractory metal film 8 is formed on the surface of the n ⁺ semiconductor layer 4 including a plurality of cap portions 30, and an electrode wiring layer 6 serving as an emitter electrode is formed on the refractory metal film 8.

<Trench Gate Structure> FIG. 12 is a plan view showing a planar shape of the trench gate type IGBT shown in FIG. As shown in the figure, the grooves 13 are formed adjacent to each other with a width Wc.

12 to 17, the p ⁺ semiconductor substrate 1, the n ⁻ semiconductor layer 2, the p semiconductor layer 3 and the n ⁺ semiconductor layer 4 are collectively shown as one base body 50 made of a semiconductor. Further, illustration of the silicon oxide film 7 is omitted.

FIG. 13 is a cross-sectional view showing the AA cross section of FIG. As shown in the figure, a groove 13 is formed from the front surface to the back surface of the base body 50, and the silicon oxide film 14 is formed from the inner wall surface of the groove 13 to the front surface of the base body 50.
Is formed, the doped polysilicon 5 is filled in the groove 13 through the silicon oxide film 14, and is formed so as to extend over a part of the surface of the substrate 50. Then, a CVD oxide film 12 is formed on the doped polysilicon 5,
The BPSG film 10 is formed on the CVD oxide film 12. B
The PSG film 10 is formed at a height tcap from the surface of the base body 50, and the doped polysilicon 5 is formed at a height tgate from the surface of the base body 50.

FIG. 14 is a cross-sectional view showing a BB cross section of FIG. This cross section corresponds to the cross sectional view of FIG. 1, and it can be seen that the BPSG film 10 is formed on the groove 13 at a height tcap from the surface of the base body 50.

FIG. 15 is a cross-sectional view showing the C-C cross section of FIG. As shown in the figure, the doped polysilicon 5 is filled in the groove 13 through the silicon oxide film 14 and is formed so as to extend also on the surface of the base body 50.
It has a thickness of the formation height tgate from the surface of.
On the other hand, a CVD oxide film 1 is formed on the doped polysilicon 5.
2 and the BPSG film 10 are formed.

FIG. 16 is a sectional view showing a DD section in FIG. As shown in the figure, the doped polysilicon 5 is formed on the surface of the substrate 50 through the silicon oxide film 14, and the CVD oxide film 12 and the BPSG film 10 are formed on the doped polysilicon 5. It has a height tgate from the surface of the base body 50 of the doped polysilicon 5.

FIG. 17 is a sectional view showing a section taken along line EE in FIG. As shown in the figure, the silicon oxide film 14 is formed on the surface of the base body 50, and a height t from the surface of the base body 50 is formed on a part of the surface of the base body 50 through the silicon oxide film 14.
A gate doped polysilicon 5 is formed, and a CVD oxide film 12 is formed so as to cover the doped polysilicon 5.
A BPSG film 10 is formed covering the doped polysilicon 5 via the CVD oxide film 12.

Thus, the doped polysilicon 5 is
In order to make contact with the outside, it is formed on a part of the surface of the base 50 and has a height tgate from the surface of the base 50. On the other hand, the BPSG film 10 (cap portion 30) is formed on the groove 13 at a height tcap from the surface of the base body 50.

At this time, for example, as shown in FIG. Conditional expression: tcap ≧ tgate Are satisfied.

<Manufacturing Method> FIGS. 2 to 10 show the cap portion 3.
It is sectional drawing which shows the formation method of 0. Hereinafter, with reference to these drawings, a method of forming the cap portion 30 above each groove 13 will be described.

First, an existing manufacturing technique is used to obtain the structure shown in FIG. That is, the n ⁻ semiconductor layer 2 is formed on one main surface of the p ⁺ semiconductor substrate 1, the p semiconductor layer 3 is formed on the n ⁻ semiconductor layer 2, and the n ⁺ semiconductor layer 4 is formed on the p semiconductor layer 3. rounded bottom with a plurality of grooves 13 to reach the surface of the semiconductor layer 2 Y-shaped ^- to obtain a substrate 50, through the n ⁺ n ⁺ semiconductor layer 4 and the p semiconductor layer 3 from the surface of the semiconductor layer 4 n A groove is formed by a reactive ion etching (hereinafter referred to as RIE) technique, and a silicon oxide film 14 is formed on the surface of the base body 50 including the inner wall of each groove 13 by a thermal oxidation method.

Then, the doped polysilicon 5 is formed in each groove 1.
While filling the inside of the substrate 3, as shown in FIGS. 13 and 15, the silicon oxide film 14 is formed so as to extend over a part of the surface of the substrate 50. Then, after the doped polysilicon 5 filled in the groove 13 is etched to some extent in the depth direction of the groove 13, the surface of the doped polysilicon 5 is oxidized by the CVD method or the like, as shown in FIG. like,
A silicon oxide film 12 is formed.

Next, as shown in FIG. 3, the BPSG film 10 which is an interlayer insulating film is formed by CVD (Chemiccul Vapor Deposit).
The ion) method is used to deposit a large thickness of 1 to 2 μm.

Then, the BPSG film 10 is subjected to a heat treatment at 800 to 1000 ° C. for several minutes to several hours in an oxidizing atmosphere containing oxygen or steam (mixed combustion of oxygen and hydrogen). At this time, since the softening point of the BPSG film 10 is near 800 ° C., the BPSG film 10 is softened by the above heat treatment, causing a so-called reflow phenomenon, and in FIG.
Since the other part of the BPSG film 10 flows in, the surface of the BPSG film 10 can be flattened as shown in FIG. At this time, the silicon oxide film 12 can reliably prevent the adverse effect that phosphorus or boron from the BPSG film 10 diffuses into the doped polysilicon 5 inside the trench.

Further, as shown in FIG. 5, the flattened BPSG film 10 is etched down to a film thickness that facilitates contact hole formation by exposing the substrate 50 by anisotropic etching described later. . When etching down, for example, an aqueous solution containing HF is used to form the BPSG film 1.
The film thickness d of 0 is set to about 3000 to 8000 angstroms.

Subsequently, as shown in FIG. 6, a silicon oxide film 7 having better adhesion to the positive photoresist than the BPSG film 10 is deposited on the BPSG film 10, and the positive photoresist is formed on the silicon oxide film 7. 11 which is the photoresist of
To form. Since the silicon oxide film 7 has excellent adhesion to the resist 11, the patterning process of the resist 11 described later and the etching process using the patterned resist 11 as a mask can be accurately performed.

Then, as shown in FIG. 7, the resist 11 is patterned by using the photolithography technique. Next, as shown in FIG. 8, an etching process for causing side etching is performed by using an aqueous solution containing HF and the like by using the patterned resist 11 as a mask.
The taper portion TP is formed by performing an undercut in the silicon oxide film 7 and the BPSG film 10 for the G film 10.

After that, anisotropic etching is performed according to the mask size of the resist 11 to form the silicon oxide film 7 and the BPSG film 10 which will be the cap portion of the contact hole 25 and the groove 13, as shown in FIG. Here, the silicon oxide films 7 and B located above the cap portion 30
Since the taper portion TP is formed on the PSG film 10,
The BPSG film 10 and the silicon oxide film 7 having the shape shown in FIG.
Electrode wiring layer 6 made of Al alloy on the cap portion made of
Even when the above is formed, the coverage of the electrode wiring layer 6 can be improved as compared with the conventional case.

Next, the silicon oxide film 7 and the BPSG film 1
0 or oxygen or steam (mixed combustion of oxygen and hydrogen)
Heat treatment at 800 to 1000 ° C. for several minutes to several hours in an oxidizing atmosphere containing. At this time, since the BPSG film 10 has a softening point near 800 ° C., it is softened by the heat treatment,
Due to the reflow phenomenon, the cross-sectional shape of the BPSG film 10 is rounded, and as shown in FIG. 10, the contact hole, that is, the high step with the surface of the base body 50 is in a gentle state. In this way, the cap portion 30 including the BPSG film 10 and the silicon oxide film 7 is completed on each groove 13.

Thereafter, after forming a silicide layer (not shown) on the surface of the substrate 50, a refractory metal film 8 is deposited by the sputter method, and an electrode wiring layer 6 made of AlSi or the like is further formed by the sputter method. For example, since the smooth inclined surface 26 is formed in the cross-sectional shape of the cap portion 30, even if the electrode wiring layer 6 serving as an emitter electrode is formed so as to cover the cap portion 30 that forms a step with the base body 50. Therefore, it is possible to reliably prevent the occurrence of voids and cavities 9 in the electrode wiring layer 6 that have conventionally occurred, and to significantly improve the coverage of the electrode wiring layer 6.

Hereinafter, this point will be described in detail. In order to improve the coverage of the electrode wiring layer 6, the cap portion 30 is provided with a smooth inclined surface 26 by the heat treatment. Here, as shown in FIG. 10, X: length of the inclined surface 26 in the in-plane direction of the surface of the base body 50, Y: height of the electrode wiring layer 6 when the inclined surface 26 is formed from the surface of the base body 50 Parameter ratio Dmin expressing the coating property (the substrate 5 on which the cap portion 30 is not formed)
11 shows the relationship between the thickness of the electrode wiring layer 6 on 0) / Dmax (the thickness of the electrode wiring layer 6 on the cap portion 30). It can be said that as the parameter Dmin / Dmax approaches 1, the coverage of the electrode wiring layer 6 is better.

As is apparent from FIG. 11, if Y / X ≦ 5 is satisfied, the parameter Dmin / Dmax can be maintained at 0.5 or more, and relatively good coverage of the electrode wiring layer 6 can be maintained. it can. Furthermore, if Y / X ≦ 2 is satisfied,
The parameter Dmin / Dmax can be maintained at 0.8 or more, and the fairly good coverage of the electrode wiring layer 6 can be maintained.

That is, if the shape of the inclined surface 26 of the cap portion 30 is formed so as to satisfy Y / X ≦ 5, it is possible to maintain relatively good coverage of the electrode wiring layer 6. Furthermore, if it is formed so as to satisfy Y / X ≦ 2, it is possible to maintain a fairly good coverage of the electrode wiring layer 6 (first characteristic).

As a result, according to the first feature, since the electrode wiring layer 6 can be formed with good coverage on the cap portion 30 which is the base pattern forming the step on the base body 50, the electrode wiring to be the emitter electrode is formed. An IGBT can be obtained without any defect in the layer 6 without being affected by the underlying pattern.

When the height of the cap portion 30 from the surface of the n ⁺ semiconductor layer 4 is H and the formation interval of the grooves 13 is Wc, the cap should be formed so as to satisfy the conditional expression: (Wc / H) ≦ 8. For example, good coverage of the electrode wiring layer can be maintained while maintaining the integration degree at a relatively high level (second characteristic).

Furthermore, the height tgate of the doped polysilicon 5 of the substrate 50 on the groove 13 from the surface of the substrate 50, and B
The height tcap from the surface of the cap portion 30 of the PSG film 10
By satisfying the conditional expression: tcap ≧ tgate between and, the BPSG film having a flat surface, as shown in FIG. 13, regardless of whether or not the doped polysilicon 5 is formed on the surface of the substrate 50. Since 10 (cap portion 30) can be formed on the base body 50, the electrode wiring layer 6 formed on the cap portion 30 can maintain good coverage (third feature).

As a result, according to the third feature, the electrode wiring layer 6 can be formed on the cap portion 30 with good coverage, so that the electrode wiring layer 6 serving as the emitter electrode is not affected by the underlying pattern. An IGBT formed without any defect can be obtained.

<< Second Embodiment >> FIG. 18 is a sectional view showing a structure of an IGBT having a surface gate type MOS gate structure according to a second embodiment of the present invention. FIG. 19 is a sectional view showing the surface gate structure. As shown in these figures, a P ⁺ substrate 41 having one main surface and the other main surface
An n semiconductor layer 21 is formed on one of the upper main surfaces, a plurality of p diffusion regions 22 are selectively formed on the surface of the n semiconductor layer 21, and an n ⁺ diffusion region 23 is selected on the plurality of p diffusion regions 22. Formed.

Then, from a part of the surface of the n ⁺ diffusion region 23, the surface of the p diffusion region 22, the surface of the n semiconductor layer 21,
A plurality of gate oxide films 16 are formed on the surface of the other p diffusion region 22 and a part of the surface of the other n ⁺ diffusion region 23, and a gate electrode 17 is formed on the plurality of gate oxide films 16.
A plurality of insulating layers 18 are formed so as to cover each gate electrode 17.

Also, the insulating layer 18, the p diffusion region 22 and the n
^An emitter electrode 42 is formed on ⁺ diffusion region 23, and a collector electrode 43 is formed on the other main surface of the P ⁺ substrate.

FIG. 20 is a plan view showing a first example of the planar structure of the IGBT of the second embodiment. As shown in the figure, the strip-shaped insulating layer 18 is formed at intervals of the distance D3.
Note that D1 to D3 in FIG. 20 are respectively D1 to D in FIG.
Corresponds to 3.

FIG. 21 is a plan view showing a second example of the planar structure of the IGBT of the second embodiment. As shown in the figure, the rectangular insulating layer 18 has a distance D31 in the horizontal direction of FIG.
Spaces are formed at intervals of a distance D32 in the vertical direction of FIG. Note that D11, D21, and D31 in FIG. 21 correspond to D1, D2, and D3 in FIG. 19 when the cross section is taken along the line FF ′, and D12, D22, and D32 in FIG. This corresponds to D1, D2 and D3 in FIG. At this time, D11, D12, D21,
The size of each of D22, D31, and D33 is arbitrary.

As a third example of the planar structure of the IGBT of the second embodiment, the rectangular portion of FIG. 21 is the drain / source region, and the other regions are the gate region (insulating layer 18).
It is also conceivable that it is a region for forming).

The method of manufacturing the IGBT according to the second embodiment will be described below. First, the n semiconductor layer 21 is formed on one main surface of the P ⁺ substrate 41, and as shown in FIG. 19, the p diffusion region 22 and the n ⁺ diffusion region 23 and the gate are formed on the surface of the n semiconductor layer 21. A MOS gate structure composed of the oxide film 16 and the gate electrode 17 is formed by a known method.

After that, the insulating layer 18 is formed on the entire surface, and the insulating layer 18 such as a BPSG film is patterned by photolithography or the like so as to cover the gate oxide film 16 and the gate electrode 17.

Next, the insulating layer 18 is subjected to a heat treatment for several minutes to several hours at a temperature not lower than the temperature at which the insulating layer 18 is softened in an oxidizing atmosphere containing oxygen or water vapor (mixed combustion of oxygen and hydrogen). Then, the insulating layer 18 is softened by the above heat treatment, a reflow phenomenon occurs, and the cross-sectional shape of the insulating layer 18 becomes round. As shown in FIG. 22, the insulating layer 1 having the inclined surface 26 is formed.
8 is completed.

After that, the emitter electrode 42 is formed on the insulating layer 18, the p diffusion region 22 and the n ⁺ diffusion region 23, and the collector electrode 43 is formed on the other main surface of the P ⁺ substrate 41. The IGBT of the embodiment is completed. The step of forming the electrodes 42 and 43 is not necessarily the last step.

Here, in the smooth inclined surface 26 formed on the insulating layer 18 by the heat treatment, X: length of the inclined surface 26 in the in-plane direction of the surface of the n semiconductor layer 21 Y: n semiconductor layer of the inclined surface 26 If the formation height from the surface of 21 is set so as to satisfy Y / X ≦ 5 as in the first embodiment, a relatively good coverage of the emitter electrode 42 can be maintained. Further, if it is formed so as to satisfy Y / X ≦ 2, a considerably good emitter electrode 42
The coating property of can be maintained (first feature).

As a result, according to the first characteristic, the insulating layer 18 which is a base pattern forming a step on the n semiconductor layer 21.
Since the emitter electrode 42 can be formed thereon with good coverage, an IGBT having no defect can be obtained without the emitter electrode 42 being affected by the underlying pattern.

When the height of the insulating layer 18 from the surface of the n-semiconductor layer 21 is H and the formation interval of the gate electrodes 17 is W, the condition formula: (W / H) ≦ 8 should be satisfied. For example, good coverage of the electrode wiring layer can be maintained while maintaining the integration degree at a relatively high level (second characteristic).

<< Third Embodiment >> In the first embodiment, the case of the trench gate type IGBT using the P type substrate 1 as the power semiconductor device is shown. As shown, an N type substrate 51 is used
Even if a trench gate type MOSFET using a groove as a gate is formed with the same configuration as that of the first embodiment, the same effect as that of the first embodiment can be obtained.

<< Fourth Embodiment >> Furthermore, FIG.
As shown in, the MCT (MOS C
Even if an ontrolled thyristar is formed, the same effect as that of the first embodiment can be obtained. 1A is a p ⁺ semiconductor substrate having an anode short structure partially having an N ⁺ region, and 19 is a P ⁺ diffusion region formed in the upper layer portion of the n ⁺ semiconductor layer 4 near the groove 13, Other configurations are the same as those of the IGBT of the first embodiment.

<< Others >> In the IGBT of the first embodiment, the Al alloy is used as the electrode wiring layer 6 which becomes the emitter electrode, but Al may be used. Also, although a high step difference is smoothed by using a BPSG film as the cap portion 30 formed on the groove 13, PSG (Phosphosilicate glass) which is a silicate glass that can be easily flattened.
A film, an oxide film using TEOS [Si (OC ₂ H ₅ ) ₄ ] as a raw material, or the like may be used.

When the PSG film is used as the interlayer insulating layer for forming the cap portion 30, as in the case of using the BPSG film, the heat treatment used for flattening the PSG film or the like is performed from the PSG film. Since there is a risk that phosphorus will diffuse into the doped polysilicon 5 inside the groove, the surface of the doped polysilicon 5 as the filling material is oxidized by thermal oxidation or the CVD method as in the first embodiment. Membrane 1
2 need to be formed.

As a first modification of the first embodiment, as shown in FIG. 25, the p ⁺ semiconductor substrate 1 and the n ⁻ semiconductor layer 2 of the first embodiment shown in FIG. The structure may be such that an n ⁺ buffer layer 31 is interposed between them. As a second modification, as shown in FIG. 26, the p ⁺ semiconductor substrate 1 is a p ^{+ type} anode short structure having an N ⁺ region as a part thereof. The structure may be replaced with the semiconductor substrate 1A, and as a third modification,
As shown in FIG. 27, p ⁺ p ⁺ semiconductor substrate 1A is replaced with the p ⁺ semiconductor substrate 1A of the anode short structure having a portion in the N ⁺ region of the semiconductor substrate 1 and the n ^- semiconductor layer 2
A structure in which an n ⁺ buffer layer 31 is interposed between
These first to third modified examples are also the IGBT of the first embodiment.
The same effect as T can be obtained. Similarly, the first
~ The third modification can be applied to the MCT of the fourth embodiment.

In the first, third and fourth embodiments, the shape of the groove 13 has a constant formation width and a constant formation depth as shown in FIG. It may be formed in a shape such as a hole in which the formation depth is larger than the formation width.

[0086]

As described above, in the semiconductor device according to the first aspect of the present invention, the plurality of insulating layers respectively formed on the plurality of groove portions have inclined surfaces, and the inclined surfaces have X: Conditional expression: Y / X ≦ 5 is satisfied, where Y is the in-plane length of one main surface of the base body, and Y is the height of the inclined surface formed from the one main surface of the base body. Therefore, the step from the one main surface of the base body caused by the formation of the plurality of insulating layers does not adversely affect the overlying layer.

As a result, a first layer is formed on these insulating layers.
Since it is possible to form the main electrode with good coverage, it is possible to obtain a semiconductor device in which the first main electrode is formed without any defect without being affected by the underlying pattern.

In the semiconductor device according to the second aspect of the present invention, the plurality of insulating layers formed on the plurality of grooves have an inclined surface, and the inclined surface has the above conditional expression: Y / X.
Since ≦ 5 is satisfied, the step from the one main surface of the substrate caused by the formation of the plurality of insulating layers does not adversely affect the layer to be stacked.

Further, since the plurality of insulating layers satisfy the above conditional expression: H2 ≧ H1, the plurality of insulating layers are formed so as to cover the control electrode layer formed on the one main surface of the base. It is possible to obtain a plurality of insulating layers having a relatively flat surface.

As a result, the first main electrode can be formed on the plurality of insulating layers with good coverage, so that the first main electrode can be formed without any defect without being affected by the underlying pattern. Can be obtained.

Further, in the semiconductor device according to the third aspect of the present invention, further, the plurality of groove portions are formed at a predetermined distance, and W: the predetermined distance, H: one main body of each of the plurality of insulating layers. In the case of the formation height from the surface, since the conditional expression: (W / H) ≦ 8 is satisfied, the integration degree can be maintained at a relatively high level.

As a result, it is possible to obtain a semiconductor device in which the first main electrode is formed without being affected by the underlying pattern and without any defects while maintaining a high degree of integration.

According to the semiconductor device of claim 4,
Since each of the plurality of insulating layers is composed of a base insulating layer formed on the control electrode layer and a main insulating layer formed on the base insulating layer, interference between the main insulating layer and the control electrode layer is prevented. It can be prevented by an insulating layer.

As a result, even if there is a possibility that the main insulating layer may adversely affect the control electrode layer during manufacturing, it can be reliably avoided due to the presence of the base insulating layer, so that a highly accurate semiconductor device can be obtained. it can.

In addition, in the semiconductor device according to the present invention, the auxiliary insulating layer is formed on the main insulating layer so that the formation height of the insulating layer can be relatively easily formed to a desired formation height. Therefore, it becomes easy to achieve the conditional expression H2 ≧ H1.

As a result, the first main electrode can be formed on the plurality of insulating layers with good coverage.

In the semiconductor device according to claim 6 of the present invention, the plurality of insulating layers formed on the plurality of grooves have an inclined surface, and the inclined surface is X: one main part of the base of the inclined surface. Where Y is the in-plane length of the surface, and Y is the height of the inclined surface formed from one main surface of the substrate, the conditional expression:
Since Y / X ≦ 5 is satisfied, the step difference from the one main surface of the substrate caused by the formation of the plurality of insulating layers does not have a bad influence on the overlying layer.

As a result, a first layer is formed on these insulating layers.
Since it is possible to form the main electrode with good coverage, it is possible to obtain a semiconductor device in which the first main electrode is formed without any defect without being affected by the underlying pattern.

Further, in the semiconductor device according to the present invention, further, the plurality of control electrodes are formed so as to be separated from each other by a predetermined distance, and W: the predetermined distance, H: one of the bases of each of the plurality of insulating layers. When forming height from the main surface, the conditional expression: (W / H) ≦ 8 is satisfied, so that the degree of integration can be maintained at a relatively high level.

As a result, it is possible to obtain a semiconductor device in which the first main electrode is formed without being affected by the underlying pattern and without any defects while maintaining a high degree of integration.

Further, in the method of manufacturing a semiconductor device according to the eighth aspect, the inclined surface of the insulating layer is X: the length of the inclined surface in the direction of the one main surface of the substrate, and Y: the inclined surface. When the height of formation from one main surface of the substrate is defined as conditional formula: Y / X ≦ 5, the step from the one main surface of the substrate caused by the formation of this insulating layer is It does not have a bad influence.

As a result, another layer can be formed on the insulating layer with good coverage, so that the layer can be formed without any defect without being affected by the underlying pattern of the insulating layer.

Further, in the method of manufacturing a semiconductor device according to the ninth aspect, the plurality of control electrodes are formed at a predetermined distance, and W: the predetermined distance, H: one of the bases of each of the plurality of insulating layers. When forming height from the main surface,
Since the conditional expression: (W / H) ≦ 8 is satisfied, the degree of integration can be maintained at a relatively high level.

As a result, it is possible to form a layer without any defect without being affected by the underlying pattern made of an insulating layer while maintaining a high degree of integration.

[Brief description of drawings]

FIG. 1 is a sectional view showing a structure of a trench gate type IGBT according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the manufacturing method of the first embodiment.

FIG. 3 is a cross-sectional view showing the manufacturing method of the first embodiment.

FIG. 4 is a cross-sectional view showing the manufacturing method of the first embodiment.

FIG. 5 is a cross-sectional view showing the manufacturing method of the first embodiment.

FIG. 6 is a cross-sectional view showing the manufacturing method of the first embodiment.

FIG. 7 is a cross-sectional view showing the manufacturing method of the first embodiment.

FIG. 8 is a cross-sectional view showing the manufacturing method of the first embodiment.

FIG. 9 is a cross-sectional view showing the manufacturing method of the first embodiment.

FIG. 10 is a cross-sectional view showing the manufacturing method of the first embodiment.

FIG. 11 is a graph for explaining effects of the first embodiment.

FIG. 12 is a plan view showing a part of a planar structure of the IGBT according to the first embodiment.

13 is a cross-sectional view showing a cross section taken along the line AA of FIG.

14 is a cross-sectional view showing a BB cross section of FIG.

FIG. 15 is a cross-sectional view showing a C-C cross section of FIG. 12.

16 is a cross-sectional view showing a DD cross section of FIG.

FIG. 17 is a sectional view showing an EE section in FIG.

FIG. 18 is a surface M according to a second embodiment of the present invention.
It is sectional drawing which shows the structure of OS gate type IGBT.

FIG. 19 is a cross-sectional view showing the surface structure of the IGBT according to the second embodiment.

FIG. 20 is a plan view showing a first example of the surface structure of the IGBT according to the second embodiment.

FIG. 21 is a plan view showing a second example of the surface structure of the IGBT according to the second embodiment.

FIG. 22 is a cross-sectional view showing the surface structure of the IGBT according to the second embodiment.

FIG. 23 is a sectional view showing the structure of a trench gate type MOSFET according to a third embodiment of the invention.

FIG. 24 is a sectional view showing a structure of a trench gate type MCT according to a fourth embodiment of the present invention.

FIG. 25 is a cross-sectional view showing a first modified example of the IGBT according to the first embodiment.

FIG. 26 is a cross-sectional view showing a second modified example of the IGBT according to the first embodiment.

FIG. 27 is a cross-sectional view showing a third modification example of the IGBT according to the first embodiment.

FIG. 28 is a cross-sectional view showing the structure of a conventional trench gate type IGBT.

[Explanation of symbols]

1 p ⁺ semiconductor substrate, 2 n ⁻ semiconductor layer, 3 p semiconductor layer, 4 n ⁺ semiconductor layer, 5 doped polysilicon, 6
Electrode wiring layer, 7 Silicon oxide film, 8 Refractory metal film, 10 BPSG film, 12 Silicon oxide film, 15
Collector electrode, 16 gate oxide film, 17 gate electrode,
18 insulating layers, 30 cap portions, 42 emitter electrodes.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/749 H01L 29/78 658F (72) Inventor Tadatsugen Minato 4-chome, Mizuhara, Itami City, Hyogo Prefecture Mitsubishi Denki Electric Co., Ltd. ULS Development Research Center (72) Inventor Shuichi Tominaga 1-1-1, Imajuku Higashi, Nishi-ku, Fukuoka City Fukuryo Semicon Engineering Co., Ltd. (72) Inventor Katsuomi Shiozawa Amagasaki, Hyogo Prefecture 8-1, 1-1 Tsukaguchihonmachi Sanryu Electric Co., Ltd. Semiconductor Basic Research Laboratory F-term (reference) 5F005 AB02 AE09 BA02 GA02

Claims (9)

[Claims] 1. A first semiconductor region having one main surface and the other main surface, the first semiconductor region having a predetermined conductivity type in one main surface, and the second semiconductor region having the predetermined conductivity type in another main surface. A base body including the plurality of groove portions, each of which is selectively formed at a predetermined depth from one main surface of the base body; a plurality of insulating films formed on inner walls of the plurality of groove portions; A plurality of control electrode layers filled in the inside of the plurality of grooves via a film; a plurality of insulating layers formed on the plurality of control electrode layers so as to project from the surface of the base; A plurality of first main electrodes formed on at least half the formation area of the first semiconductor region; and a second main electrode formed on the second semiconductor region of the base. The first and second main electrodes are connected between the first and second main electrodes by a control voltage commonly applied to the control electrode layer. And a semiconductor device for controlling a current flowing through the second semiconductor region, wherein each of the plurality of insulating layers has a gently sloping surface from an upper portion to a lower portion, and X: one of the main surfaces of the base body of the sloping surface. In-plane length Y: When a height of the inclined surface is formed from one main surface of the base body, a conditional expression: Y / X ≦ 5 is satisfied. 2. A first semiconductor region having a predetermined conductivity type in one main surface and a second semiconductor region having a predetermined conductivity type in the other main surface. A base body including the plurality of groove portions, each of which is selectively formed at a predetermined depth from one main surface of the base body; and extending from an inner wall of the plurality of groove portions onto a part of one main surface of the base body. A plurality of insulating films to be formed, and while filling the inside of the plurality of grooves through the plurality of insulating films, and extending over the part of the one main surface of the base body through the plurality of insulating films. A plurality of control electrode layers formed, a plurality of insulating layers formed on the plurality of control electrode layers in the plurality of groove portions so as to project from one main surface of the base, and the first of the bases A first main electrode formed on at least half the formation area of a semiconductor region; A second main electrode formed on the second semiconductor region, and a control voltage commonly applied to the plurality of control electrode layers is provided between the first and second main electrodes. In a semiconductor device for controlling a current flowing through a semiconductor region, each of the plurality of insulating layers on the plurality of trenches has a sloping inclined surface from an upper portion to a lower portion, and X: one main body of the base body of the inclined surface. Length Y in the plane direction: height of the inclined surface formed from one main surface of the base body H1: of the base body of each of the plurality of control electrode layers formed on the part of the one main surface of the base body Forming height H2 from one main surface: When forming height of each of the plurality of insulating layers on the plurality of groove portions from one main surface of the substrate, conditional expression: H2 ≧ H1 conditional expression: Y / X ≦ Characterized by satisfying both 5 Semiconductor device. 3. The plurality of groove portions are formed at a predetermined distance from each other, and W: the predetermined distance H: a height of each of the plurality of insulating layers formed from one main surface of the substrate, the conditional expression: (W / H) ≦ 8 is satisfied, claim 1 or claim 2 characterized in that
The semiconductor device according to. 4. The insulating layer according to claim 1 or 2, wherein each of the plurality of insulating layers includes a base insulating layer formed on the control electrode layer and a main insulating layer formed on the base insulating layer. The semiconductor device described. 5. The plurality of insulating layers are respectively formed on a base insulating layer formed on the control electrode layer, a main insulating layer formed on the base insulating layer, and formed on the main insulating layer. The semiconductor device according to claim 1 or 2, comprising an auxiliary insulating layer. 6. A substrate having one main surface and the other main surface, comprising an upper layer portion on one main surface side and a lower layer portion on the other main surface side, and at least the upper layer portion made of a semiconductor of a first conductivity type. A plurality of second conductive type first semiconductor regions selectively formed in the upper layer portion of the base; and a first selectively formed on the surfaces of the plurality of first semiconductor regions. A plurality of conductive type second semiconductor regions, and a plurality of insulating films formed on one region of each of the first semiconductor regions between the upper layer portion of the base and each of the second semiconductor regions. A plurality of control electrodes formed on the plurality of insulating films, a plurality of insulating layers formed to cover the plurality of insulating films and the plurality of control electrodes, and formed on one main surface of the base body And a second main electrode formed on the other main surface of the base body. In a semiconductor device that controls a current flowing between the first and second main electrodes by a control voltage that is commonly applied to the plurality of control electrodes, the plurality of insulating layers each have a gentle sloped surface from an upper portion to a lower portion. And X: the length of the inclined surface in the in-plane direction of the one main surface of the base body, Y: the forming height of the inclined surface from the one main surface of the base body, conditional expression: Y / X ≦ 5 A semiconductor device characterized in that 7. The conditional expression, wherein the plurality of control electrodes are formed at a predetermined distance from each other, and W: the predetermined distance H: a formation height of each of the plurality of insulating layers from one main surface of the substrate. 7. The semiconductor device according to claim 6, wherein: (W / H) ≦ 8 is satisfied. 8. (a) One main surface and the other main surface, wherein the one main surface side upper layer portion and the other main surface side lower layer portion are formed, and the upper layer portion is made of a semiconductor of the first conductivity type. A second base, which is selectively formed on the upper layer portion of the base.
A plurality of first semiconductor regions of conductivity type, and the plurality of first semiconductor regions
Selectively formed on the surface of each semiconductor region of the first
A plurality of second semiconductor regions of conductivity type, and a plurality of second semiconductor regions formed on one region of each of the first semiconductor regions between the upper layer portion of the base and each of the second semiconductor regions. Forming a MOS structure composed of an insulating film and a plurality of control electrodes respectively formed on the plurality of insulating films; (b) an insulating layer on one main surface of the base body including the plurality of control electrodes. And (c) patterning the insulating layer to form an opening at a predetermined location, and (d) heat treating the patterned insulating layer to form the opening in the insulating layer. Forming a gently sloping surface in the region near the portion, (e) forming a first main electrode on one main surface of the base body, and (f) forming a second main surface on the other main surface of the base body. After the completion of the device, including the step of forming electrodes In the method for manufacturing a semiconductor device in which a current flowing between the first and second main electrodes is controlled by a control voltage commonly applied to the plurality of control electrodes, the heat treatment in step (d) is performed on the insulating layer. Is performed at a temperature equal to or higher than the temperature at which the softening occurs, and the sloped surface of the insulating layer is: When the above condition is satisfied, the conditional expression: Y / X ≦ 5 is satisfied. 9. The plurality of control electrodes are formed at a predetermined distance from each other, and W: the predetermined distance H: height of the insulating layer formed from one main surface of the substrate, conditional expression: (W 9. The method for manufacturing a semiconductor device according to claim 8, wherein / H) ≦ 8 is satisfied.