JP2003324183A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JP2003324183A
JP2003324183A JP2002131505A JP2002131505A JP2003324183A JP 2003324183 A JP2003324183 A JP 2003324183A JP 2002131505 A JP2002131505 A JP 2002131505A JP 2002131505 A JP2002131505 A JP 2002131505A JP 2003324183 A JP2003324183 A JP 2003324183A
Authority
JP
Japan
Prior art keywords
semiconductor device
semiconductor chip
semiconductor
substrate
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002131505A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003324183A5 (enExample
Inventor
Shinji Baba
伸治 馬場
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2002131505A priority Critical patent/JP2003324183A/ja
Priority to US10/283,208 priority patent/US20030209808A1/en
Publication of JP2003324183A publication Critical patent/JP2003324183A/ja
Priority to US10/953,059 priority patent/US20050104211A1/en
Publication of JP2003324183A5 publication Critical patent/JP2003324183A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0652—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00 the devices being arranged next and on each other, i.e. mixed assemblies
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    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
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    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
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    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
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    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Wire Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
JP2002131505A 2002-05-07 2002-05-07 半導体装置 Pending JP2003324183A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2002131505A JP2003324183A (ja) 2002-05-07 2002-05-07 半導体装置
US10/283,208 US20030209808A1 (en) 2002-05-07 2002-10-30 Semiconductor device having semiconductor chips mounted on package substrate
US10/953,059 US20050104211A1 (en) 2002-05-07 2004-09-30 Semiconductor device having semiconductor chips mounted on package substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002131505A JP2003324183A (ja) 2002-05-07 2002-05-07 半導体装置

Publications (2)

Publication Number Publication Date
JP2003324183A true JP2003324183A (ja) 2003-11-14
JP2003324183A5 JP2003324183A5 (enExample) 2005-09-29

Family

ID=29397351

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002131505A Pending JP2003324183A (ja) 2002-05-07 2002-05-07 半導体装置

Country Status (2)

Country Link
US (1) US20030209808A1 (enExample)
JP (1) JP2003324183A (enExample)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007274000A (ja) * 2007-05-01 2007-10-18 Seiko Instruments Inc 半導体装置、その製造方法、及び、表示装置の製造方法、
JP2008187050A (ja) * 2007-01-30 2008-08-14 Toshiba Corp システムインパッケージ装置
JP2011192893A (ja) * 2010-03-16 2011-09-29 Zycube:Kk 半導体デバイスの実装方法
US8237289B2 (en) 2007-01-30 2012-08-07 Kabushiki Kaisha Toshiba System in package device
KR20140098160A (ko) * 2011-12-22 2014-08-07 인텔 코포레이션 윈도우 인터포저를 갖는 3d 집적 회로 패키지
JP2015530757A (ja) * 2012-09-27 2015-10-15 インテル・コーポレーション パッケージ基板にダイを含むスタックダイパッケージ
WO2018125061A1 (en) * 2016-12-27 2018-07-05 Intel Corporation Stacking multiple dies having dissimilar interconnect structure layout and pitch
JP2018117160A (ja) * 2009-06-24 2018-07-26 インテル・コーポレーション マルチチップパッケージ

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US7247932B1 (en) 2000-05-19 2007-07-24 Megica Corporation Chip package with capacitor
US6825567B1 (en) * 2003-08-19 2004-11-30 Advanced Semiconductor Engineering, Inc. Face-to-face multi-chip flip-chip package
JP4591886B2 (ja) * 2004-07-21 2010-12-01 ローム株式会社 半導体装置を用いた電源回路装置
US8654538B2 (en) * 2010-03-30 2014-02-18 Ibiden Co., Ltd. Wiring board and method for manufacturing the same
US20150255411A1 (en) * 2014-03-05 2015-09-10 Omkar G. Karhade Die-to-die bonding and associated package configurations
US10667399B1 (en) * 2018-11-27 2020-05-26 Nokia Solutions And Networks Oy Discrete component carrier
US11721677B2 (en) 2018-12-27 2023-08-08 Intel Corporation Microelectronic assemblies having an integrated capacitor
CN113474887B (zh) * 2019-01-30 2024-08-06 超极存储器股份有限公司 半导体模块、半导体部件及其制造方法
US20240079337A1 (en) * 2022-09-02 2024-03-07 Intel Corporation Microelectronic assemblies having power delivery routed through a bridge die

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TW373308B (en) * 1995-02-24 1999-11-01 Agere Systems Inc Thin packaging of multi-chip modules with enhanced thermal/power management
EP1427016A3 (en) * 1997-03-10 2005-07-20 Seiko Epson Corporation Semiconductor device and circuit board mounted with the same
US6150724A (en) * 1998-03-02 2000-11-21 Motorola, Inc. Multi-chip semiconductor device and method for making the device by using multiple flip chip interfaces
US6369444B1 (en) * 1998-05-19 2002-04-09 Agere Systems Guardian Corp. Packaging silicon on silicon multichip modules
US6228682B1 (en) * 1999-12-21 2001-05-08 International Business Machines Corporation Multi-cavity substrate structure for discrete devices
JP3677429B2 (ja) * 2000-03-09 2005-08-03 Ｎｅｃエレクトロニクス株式会社 フリップチップ型半導体装置の製造方法
US7247932B1 (en) * 2000-05-19 2007-07-24 Megica Corporation Chip package with capacitor
US6734539B2 (en) * 2000-12-27 2004-05-11 Lucent Technologies Inc. Stacked module package

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008187050A (ja) * 2007-01-30 2008-08-14 Toshiba Corp システムインパッケージ装置
US8237289B2 (en) 2007-01-30 2012-08-07 Kabushiki Kaisha Toshiba System in package device
JP2007274000A (ja) * 2007-05-01 2007-10-18 Seiko Instruments Inc 半導体装置、その製造方法、及び、表示装置の製造方法、
US10763216B2 (en) 2009-06-24 2020-09-01 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
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