JP2003318129A - Method for manufacturing semiconductor device and semiconductor device manufactured by the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device having the step of forming the upper side end of a contact hole of an interlayer insulating film in a protruding shape on the upper side end without necessity of ion implanting for suppressing the increase in the contact resistance after reflowing process and to provide the semiconductor device obtained by the same. <P>SOLUTION: The method for manufacturing the semiconductor device comprises the steps of: forming a p-type base region 5 on an n<SP>-</SP>-type layer 2 front layer in a semiconductor substrate 3 having an n<SP>-</SP>-type layer 2 and forming an n<SP>+</SP>type source region 6 on the surface layer of the p-type base region 5; then forming an interlayer insulating film 11 on the layer 2; etching to the midway of the film 11 in a contact hole forming region; and then reflowing in the state that an interlayer insulating film 11a is retained on the layer 2. Thus, the upper side end of a contact hole 15 on the film 11 becomes a protruding curve shape on the upper side end. Thereafter, the film 11 is removed, and a source electrode 16 is formed. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a contact hole and a semiconductor device obtained by the manufacturing method.

[0002]

2. Description of the Related Art As a method for forming an interlayer insulating film on the surface of a semiconductor substrate and forming a metal electrode electrically connected to the semiconductor substrate through a contact hole formed in the interlayer insulating film, FIG. There are methods shown in (a) to (c).

First, in the step shown in FIG. 11A, for example, a base region 32 is formed in the surface layer of the semiconductor substrate 31. After that, the interlayer insulating film 33 is formed on the surface of the semiconductor substrate 31. Then, after forming a photoresist 34 on the interlayer insulating film 33, a contact hole 35 is formed by using a well-known photo-etching technique.

Subsequently, in the step shown in FIG. 11B, the photoresist 34 formed in the previous step is removed and the interlayer insulating film 33 is reflowed. As a result, the interlayer insulating film 33 is fluidized, and the upper end portion of the contact hole 35 in the interlayer insulating film 33 is curved upward.

Then, in a step shown in FIG. 11C, a source electrode 36 is formed in the contact hole 35 and on the interlayer insulating film 33. In this way, the source electrode 36 electrically connected to the semiconductor substrate 31 is formed on the semiconductor substrate 31.
Is formed.

[0006]

Normally, the interlayer insulating film 33 is formed.
Impurities such as P and B are contained in advance in order to facilitate gettering and fluidization of the interlayer insulating film 33. In the method described above, high temperature heat treatment is performed after the contact hole 35 is formed. Therefore, in the surface layer of the semiconductor substrate 3 below the contact hole 35,
Impurities in the interlayer insulating film 33 are diffused, and contact resistance increases.

Therefore, conventionally, in order to compensate for the impurity concentration in the surface layer of the semiconductor substrate 3, ion implantation using a photolithography process is performed before the source electrode 36 is formed in the process of FIG. 11C. To do. This suppresses the increase in contact resistance. As described above, since the ion implantation has conventionally been required, the cost is high.

In view of the above points, the present invention does not require ion implantation for suppressing an increase in contact resistance after the reflow treatment, and the upper end portion of the contact hole in the interlayer insulating film is convex upward. It is an object of the present invention to provide a method of manufacturing a semiconductor device having a step of forming a curved line and a semiconductor device obtained by this manufacturing method.

[0009]

In order to achieve the above object, in the invention described in claim 1, a semiconductor substrate (3) is prepared and an interlayer insulating film (11) is formed on the semiconductor substrate (3). A step of forming a contact hole (15) by opening the interlayer insulating film (11) halfway and leaving an interlayer insulating film (11a) of a predetermined thickness, and a contact hole of the semiconductor substrate (3) A step of performing a reflow process in a state where an interlayer insulating film (11) having a predetermined thickness is provided on a region located below (15), and an interlayer insulating film (1) having a predetermined thickness.
By removing 1), the surface of the semiconductor substrate 3 is exposed from the interlayer insulating film 11 and the contact hole 15 is formed.
And a step of forming a metal electrode (16) in the contact hole (15) and on the interlayer insulating film (11).

When the contact hole (15) is formed in this way, a reflow process is performed in this state with a part of the interlayer insulating film (11) left. This can prevent impurities in the interlayer insulating film (11) from entering the surface layer of the substrate during the reflow process. Therefore, it is possible to prevent the contact resistance from increasing and it is possible to omit the ion implantation step for compensating the impurity concentration after the reflow treatment.

As described in claim 2, in the step of leaving the interlayer insulating film (11a) having a predetermined thickness, for example, the predetermined thickness is d.
_{1. When} the film thickness of the interlayer insulating film (11) before opening is d ₂ , it is preferable to set the predetermined thickness so as to satisfy the relationship of d ₂ > 2d ₁ .

Further, in the invention described in claim 3, the step of preparing the semiconductor substrate (3) and forming the protective film (21) on the surface of the semiconductor substrate (3), and the step of forming an interlayer on the protective film (21). In the step of forming the insulating film (11) and in the region where the contact hole (15) is to be formed in the interlayer insulating film (11),
A step of forming a contact hole (14) in the interlayer insulating film (11) while leaving the protective film (21), and a step of forming a contact hole (14) in the semiconductor substrate (3) below the contact hole (15). In the state of having the protective film (21), a step of performing a reflow treatment, a step of removing the protective film (21) and exposing the surface of the semiconductor substrate (3) from the interlayer insulating film (11), and a contact hole (15). ) And a step of forming a metal electrode (16) on the interlayer insulating film (11).

As described above, the protective film (21) is formed on the surface of the semiconductor substrate (3), and the reflow treatment is performed in the state where the protective film is provided. Therefore, during the reflow treatment, impurities in the interlayer insulating film (11) are not removed. It is possible to prevent it from entering the surface layer of the substrate.

As a result, it is possible to prevent the contact resistance from increasing, and it is possible to omit the ion implantation step for compensating the impurity concentration after the reflow treatment.

Further, in the invention described in claim 4, a step of preparing a semiconductor substrate (3) and forming an interlayer insulating film (11) on the semiconductor substrate (3), and contacting the interlayer insulating film (11). Forming a hole (17) and exposing the surface of the semiconductor substrate (3) from the interlayer insulating film (11); performing a reflow treatment on the interlayer insulating film (11); The method includes removing a region exposed from the interlayer insulating film (11) to a predetermined depth from the surface, and forming a metal electrode (25) in the contact hole (24) and on the interlayer insulating film (11). It is characterized by that.

As described above, according to the present invention, the region in which the impurities in the interlayer insulating film (11) penetrate and the contact resistance is increased is removed during the reflow process. Then, in the surface layer of the semiconductor substrate (3), the region of the interlayer insulating film (11) where no impurities have entered is connected to the metal electrode (25).

As a result, the ion implantation step for compensating the impurity concentration after the reflow treatment can be omitted.

Further, as described in claim 5, the interlayer insulating film (11) is isotropically and anisotropically etched so that the opening width at the upper end of the interlayer insulating film (11) is smaller than that at the lower end. It is preferable to form a large contact hole.

As a result, the upper end portion of the contact hole (15) of the interlayer insulating film (11) is subjected to the reflow process more than when the upper end opening of the contact hole is not wider than the lower end thereof. Can be easily formed into a curved shape that is convex upward.

In the invention according to claim 6, the semiconductor substrate (3) having the semiconductor layer (2) of the first conductivity type on the main surface side and the groove (formed in the surface layer of the semiconductor layer (2) ( 4)
And the gate electrode (9) formed in the groove (4) via the gate insulating film (7) and the surface layer of the semiconductor layer (2),
A second conductivity type base region (5) formed adjacent to the groove (4) and a first conductivity type source region () formed adjacent to the groove in the surface layer of the base region (5). 6) and an interlayer insulating film (11) formed on the surface of the semiconductor layer (2),
A contact hole (15) formed in the interlayer insulating film (11) and a base region (5) and a source region (6) formed on the interlayer insulating film (11) via the contact hole (15). Source electrode (1
6) and a drain electrode (19) formed on the back side of the semiconductor substrate (3), and the upper end of the contact hole (15) in the interlayer insulating film (11) has a curved shape convex upward. It is characterized by being.

By the manufacturing method according to the first to fifth aspects, for example, such a semiconductor device is obtained.

The reference numerals in parentheses of the above-mentioned means indicate the correspondence with the concrete means described in the embodiments described later.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 is a sectional view of a semiconductor device according to the first embodiment of the present invention. Further, FIGS. 2A to 2C, FIGS. 3C to 4C, and FIGS. 4A to 4C show a method of manufacturing this semiconductor device.
In this embodiment, the CONCAVE type DMOSF is used.
ET will be described as an example.

The DMOSFET of FIG. 1 includes a semiconductor substrate 3 having an N ⁻ type layer 2 on an N ⁺ type substrate 1 (main surface side). A groove 4 having a CONCAVE structure is formed in the surface layer of the N ⁻ type layer 2. A gate oxide film 7 as a gate insulating film is formed on the inner wall of the groove 4. Also,
A gate electrode 9 made of PolySi is formed on the gate oxide film 7.

Further, a P-type base region 5 is formed on the surface layer of the N ⁻ -type layer 2 adjacent to the groove 4, and in the surface layer of the P-type base region 5 is adjacent to the groove 4. As a result, the N ⁺ type source region 6 is formed. This P-type base region 5
Of these, a region adjacent to the groove 4 becomes a channel region.

Then, the N ^-- type layer 2 including on the gate electrode 9 is formed.
An interlayer insulating film 11 is formed on the surface. A contact hole 15 is formed in the interlayer insulating film 11, and its upper end has a curved shape that is convex upward. Further, the source electrode 16 is formed on the interlayer insulating film 11. The source electrode 16 is electrically connected to the P type base region 5 and the N ⁺ type source region 6 through the contact hole 15.

A drain electrode 19 is provided on the back side of the semiconductor substrate 3. Then, on the source electrode 16,
The aluminum bonding wire 20 is formed.

Next, this CONCAVE type DMOSF
A method for manufacturing ET will be described. 2 to 4 are shown in FIG.
The area in which the contact hole 15 is formed is mainly shown.

First, although not shown, a semiconductor substrate 3 having an N ⁻ type layer 2 formed on an N ⁺ type silicon substrate 1 is prepared.

[Step shown in FIG. 2A] Subsequently, a groove 4 having a CONCAVE structure is formed in the surface layer of the N ⁻ type layer 2. Then, a P-type base region 5 is formed on the surface layer of the N ⁻ -type layer 2 adjacent to the groove 4, and in the surface layer of the P-type base region 5, adjacent to the groove 4 and on the N ⁺ -type source region To form.

Next, a gate oxide film 7 is formed on the inner wall of the groove 4, and an oxide film 8 is formed on the surfaces of the P type base region 5 and the N ⁺ type source region 6. Then, the gate electrode 9 made of PolySi is formed on the gate oxide film 7. Then, the oxide film 10 is formed on the gate electrode 9.

[Step shown in FIG. 2B] Next, an interlayer insulating film 11 made of, for example, BPSG is formed over the P-type base region 5 and the N ⁺ -type source region 6 and over the gate electrode 9. As a forming method, the AP-CVD method or the SA-CVD method is used. At this time, the interlayer insulating film 1
The interlayer insulating film 11 is formed so that the thickness of 1 is thicker than the depth of the groove 4, and further that the lowest position on the surface of the interlayer insulating film 11 is higher than the upper surface of the gate electrode 9 at the highest position.

Specifically, for example, the depth of the groove 4 is 1.5 μm.
Then, the interlayer insulating film 11 is formed to have a thickness of about 2.2 μm.
Then, heat treatment is performed to reflow the interlayer insulating film 11.
The heat treatment conditions are, for example, 950 ° C. and 3 ° C. in a nitrogen atmosphere.
0 minutes. As a result, the surface of the interlayer insulating film 11 is made smooth. Since the oxide films 8 and 10 become a part of the interlayer insulating film 11, they are omitted in the drawing.

[Step shown in FIG. 2C] On the reflowed interlayer insulating film 11, for example, SOG 12 is applied in order to further smooth the surface. This SOG12
The thickness depends on the unevenness of the reflowed interlayer insulating film 11, but is, for example, 300 to 600 nm. It is self-evident that this step may be omitted if the unevenness of the interlayer insulating film 11 after reflow is small.

[Step shown in FIG. 3A] Then, SOG
12 is cured (heat treatment). At this time, for example, 15
Set the temperature to 0 ° C, 250 ° C, 400 ° C and 3 stages,
Heat treatment. After that, the SOG 12 and the interlayer insulating film 11
Are etched to planarize the surface of the interlayer insulating film 11.
At this time, it is desirable that the SOG 12 be completely removed. Therefore, about twice the SOG12 film thickness, for example,
Etching of about 1.2 μm is performed.

[Step shown in FIG. 3B] Next, a photoresist 13 is formed on the interlayer insulating film 11 and a photolithography step is performed. At this time, a portion of the photoresist 13 located on the P-type base region 5 and the N ⁺ -type source region 6 is opened. Then, using the photoresist 13 as a mask, the P-type base region 5 of the interlayer insulating film 11 is formed.
And isotropic etching is performed in the contact hole formation planned region on the N ⁺ type source region 6. At this time, for example, CF ₄ gas is used as the etching gas.

[Step shown in FIG. 3C] Subsequently, anisotropic etching is performed to form the contact hole 15. As the etching gas, for example, CF ₄ , CH
F ₃ gas is used. In this step, the contact hole is not yet completely formed. That is, the interlayer insulating film 11 is opened halfway, and a part of the interlayer insulating film 11 having a predetermined thickness is left on the surface of the semiconductor substrate 3 in the contact hole formation planned region.

At this time, the remaining interlayer insulating film 11a
D ₁ and the thickness of the interlayer insulating film 11 before isotropic etching is d ₂ as shown in FIG. 3A, d ₂ > 2d ₁ is satisfied. Then, the film thickness d ₁ of the interlayer insulating film 11a is set.

In this embodiment, for example, when the film thickness of the SOG 12 is 0.6 μm, the film thickness d ₂ of the interlayer insulating film 11 is 1.6 μm. Then, the film thickness d of the interlayer insulating film 11a
₁ is 0.3 μm. Therefore, in this embodiment, the relationship of d ₂ > 2d ₁ is satisfied. As a result, even if the interlayer insulating film 11a is removed by etching the entire surface of the interlayer insulating film 11 in a later step, the interlayer insulating film 11 can be provided on the gate electrode 9.

The total height of the gate oxide film 7 and the gate electrode 9 is 0.5 μm, and the film thickness d ₃ of the interlayer insulating film 11 on the gate electrode 9 is 1.1 μm.

[Step shown in FIG. 4A] After the anisotropic etching, the photoresist 13 is removed and heat treatment is performed to reflow the interlayer insulating film 11. The heat treatment corresponds to the reflow treatment described in the claims.

At this time, for example, in a nitrogen atmosphere, 900
Heat at about 10 minutes. Thereby, the interlayer insulating film 1
1 is fluidized, and the upper end wall of the contact hole 15 in the interlayer insulating film 11 has a curved shape that is convex upward. In other words, the opening end portion of the interlayer insulating film 11 faces outward,
It is inflated.

At this time, in the region where the contact portion is to be formed on the surface of the N ⁻ type layer 2, the interlayer insulating film 11a remains, so that the entry of impurities from the interlayer insulating film 11 is prevented.

[Step shown in FIG. 4 (b)] Subsequently, the interlayer insulating film 11 is entirely etched to remove the portion shown by the dotted line in FIG. 4 (b). As a result, the interlayer insulating film 11a is removed, and the P-type base region 5 of the N ⁻ -type layer 2 is removed.
The surface of the region where the N ⁺ type source region 6 is formed is exposed from the interlayer insulating film 11. At this time, specifically, for example, the interlayer insulating film 11 is etched to a depth of 0.3 μm from the surface. Therefore, the film thickness d ₄ of the interlayer insulating film 11 on the gate electrode 9 is 0.8 μm.

The film thickness d ₄ of the interlayer insulating film 11 on the gate electrode 9 is changed according to the rating of the device. Therefore, in consideration of the film thickness d ₁ of the interlayer insulating film 11a in advance with respect to this thickness d ₄ , the interlayer insulating film 1 before isotropic etching is used.
The film thickness d ₂ of 1 is set in advance. As a result, the entire surface of the interlayer insulating film 11 can be etched without using a mask.

[Step shown in FIG. 4C] Then, an Al (aluminum) film is deposited by a known method to form the source electrode 16.

Thereafter, although not shown, a step of forming a passivation film on the front surface of the semiconductor substrate 3, a step of forming a drain electrode 19 after grinding the back surface side of the semiconductor substrate 3, a dicing step, and an aluminum wire. By performing a bonding process and the like, the semiconductor device shown in FIG. 1 is obtained.

In this embodiment, when the contact hole 15 is formed in this way, the interlayer insulating film 11 is partially left. Then, by performing the reflow treatment in this state, it is possible to prevent impurities in the interlayer insulating film 11 from entering the surface layer of the substrate 3. As a result, it is possible to prevent the contact resistance from increasing and it is possible to omit the ion implantation step for compensating the impurity concentration after the reflow treatment.

Further, in this embodiment, the contact hole 15 is formed in a tapered shape by a combination of isotropic etching and anisotropic etching.
That is, the contact hole 15 before the reflow process has an opening width larger in the upper part than in the lower part.
Therefore, as compared with the case where the opening at the upper part of the contact hole is not wider than that at the lower part, in the step of performing the reflow process, the contact hole 1 of the interlayer insulating film 11
The upper end portion of 5 can be easily formed into a curved shape that is convex upward.

As in the present embodiment, as a method of manufacturing a semiconductor device in which a contact hole is formed in a tapered shape by a combination of isotropic etching and anisotropic etching, there is disclosed in Japanese Unexamined Patent Publication No. 2002-026322. There is a method disclosed in the publication. The manufacturing method disclosed in this publication reduces unevenness on the surface of a source electrode in a groove type DMOS.

The manufacturing method in this case is shown in FIG.
It shows in (b). In this manufacturing method, after the step shown in FIG. 3B, anisotropic etching is performed so that the surface of the N ⁻ type layer 2 is exposed from the interlayer insulating film 11, as shown in FIG. Form 17. After that, FIG. 5 (b)
As shown in, the photoresist 13 is removed and the source electrode 18 is formed by a known method.

In this way, the contact hole 17 is formed in a tapered shape by the combination of isotropic etching and anisotropic etching. Thus, when the source electrode 18 is formed thereafter, the film thickness of the source electrode 18 on the interlayer insulating film 11 and the film thickness on the contact hole are made approximately the same, and so-called step coverage can be improved. ing.

However, when the diameter of the contact hole 17 is reduced to miniaturize the device, the aspect ratio (contact depth / width ratio) increases. in this case,
If the shape of the upper end 17a of the contact hole 17 in the interlayer insulating film 11 is a downwardly convex curved shape as shown in FIG. 5B, the step coverage of the source electrode 18 becomes poor. Further, the slit 18a is deeply formed in the source electrode 18 on the contact portion.

In the method disclosed in the publication, when the diameter of the contact hole is small, the unevenness of the source electrode 18 is insufficiently reduced, which may cause a problem that the joining reliability of the aluminum wire connected thereto is deteriorated. There is a nature.

In the step of forming the source electrode 18, since the upper end portion 17a of the contact hole 17 has a downwardly convex shape, the aluminum film grown from both side wall surfaces of the contact hole 17 can be grown early. Bump,
At that point, the growth stops and the slit 18a is formed.
This is the reason why the aluminum slit 18a deeply enters the contact portion.

On the other hand, in this embodiment, the upper end 15a of the contact hole 15 in the interlayer insulating film 11 is formed.
Is a curved shape that is convex upward. As a result, in the step of forming the source electrode 16, it is possible to delay the point where the aluminum film growing from both side wall surfaces of the contact hole 15 collides. In other words, the aluminum films grown from both side wall surfaces of the contact hole 15 can collide with each other at a high position.

Therefore, even when the diameter of the contact hole 17 is small and the aspect ratio is large, the slit 16a of the source electrode 16 formed on the contact portion can be made shallow, and the unevenness on the surface of the source electrode 16 can be reduced. can do. Then, it is possible to prevent the joining reliability of the aluminum wire 20 connected to the source electrode 16 from being lowered.

(Second Embodiment) In the first embodiment, a reflow process is performed in a state in which a contact hole 15 is formed while leaving the interlayer insulating film 11a and the surface of the semiconductor substrate 3 is protected by the interlayer insulating film 11a. However, a reflow process can be performed by forming a separate protective film instead of the interlayer insulating film 11a.

FIGS. 6A to 6C and FIGS. 7A to 7C.
A method of manufacturing a semiconductor device according to a second embodiment of the present invention is shown in FIG. In this embodiment, as in the first embodiment, the process shown in FIG. 2A is performed, and then the process shown in FIG.
7A to 7C, the steps shown in FIGS. 7A to 7C are performed. The same parts as those in the first embodiment are designated by the same reference numerals.

[Step shown in FIG. 6A] After the step shown in FIG. 2A, a Si nitride film 21, for example, is deposited as a protective film on the oxide films 8 and 10. The film thickness of the nitride film 21 is, eg, 50-150 nm.

[Steps shown in FIGS. 6B and 6C] After that, the interlayer insulating film 11 is formed on the nitride film 21. next,
After applying SOG12, it is cured to make the surface flat. Then, the SOG 12 and the interlayer insulating film 11 are etched to flatten the surface of the interlayer insulating film 11.

[Step shown in FIG. 7A] Then, in the photolithography step, the photoresist 13 having the contact pattern printed thereon is formed. Then, using this as a mask, the interlayer insulating film 11 is subjected to isotropic etching and anisotropic etching to form a contact hole 15.

At the time of this anisotropic etching, for example, dry etching using C ₄ F ₈ gas is performed to etch only the interlayer insulating film 11 and prevent the nitride film 21 from being etched. As a result, the surface of the N ⁻ type layer 2 below the contact hole 15 is covered with the nitride film 21 and the oxide film 8.

[Step shown in FIG. 7B] Subsequently, the photoresist 13 is removed. Then, with the nitride film 21 and the oxide film 8 covering the surface of the N ⁻ type layer 2 below the contact hole 15, a reflow process is performed to reflow the interlayer insulating film 11. Thereby, the interlayer insulating film 1
1 is fluidized, and the upper end portion of the contact hole 15 in the interlayer insulating film 11 has a curved shape that is convex upward.

At this time, since the nitride film 21 and the oxide film 8 are left on the surface of the N ⁻ type layer 2 below the contact hole 15, the interlayer insulating film 11 on the surface layer of the N ⁻ type layer 2 is left.
It is possible to prevent infiltration of impurities from the.

[Step shown in FIG. 8A] After the reflow treatment, the nitride film 21 and the oxide film 8 are etched. At this time, for example, CF ₄ or CHF ₃ gas is used as the etching gas. As a result, the surface of the N ⁻ type layer 2 below the contact hole 15 is exposed from the interlayer insulating film 11.

[Step shown in FIG. 8B] After that, the source electrode 16 is formed.

As described above, in this embodiment, after the nitride film 21 is separately formed as the protective film on the surface of the semiconductor substrate 3,
The interlayer insulating film 11 is formed and the contact hole 15 is formed. Then, the reflow process is performed with the nitride film 21 on the surface of the semiconductor substrate 3. This has the same effect as the first embodiment.

In the first embodiment, since the interlayer insulating film 11 is partially etched to form the interlayer insulating film 11a in the step of forming the contact hole 15, the thickness of the interlayer insulating film 11a varies. Occurs. Then, depending on the site, the film thickness may become too thin, and there may be a case in which it is not possible to prevent impurities from entering during the reflow process.

On the other hand, in the present embodiment, the nitride film 21 having a predetermined thickness is formed on the semiconductor substrate 3 in the region where the contact hole is to be formed. This allows
It is possible to reliably prevent impurities from entering during the reflow process. Therefore, it is possible to manufacture a semiconductor device of which quality is more stable than that of the first embodiment.

(Third Embodiment) In the present embodiment, the reflow process is performed after the contact holes are formed as in the conventional case. After that, in the surface layer of the semiconductor substrate 3, the region in which the impurities are diffused is etched during the reflow process.

9A to 9C show a method of manufacturing a semiconductor device according to this embodiment. The same parts as those in the first embodiment are designated by the same reference numerals.

In this embodiment, first, as shown in FIG. 5A, the contact hole 17 is formed.

[Step shown in FIG. 9A] After that, a reflow process is performed. As a result, the contact hole 15 having a curved shape whose upper end is convex upward is formed. At this time, the contact hole 15 allows the interlayer insulating film 11 to be opened.
The interlayer insulating film 1 is formed on the surface layer of the N ⁻ type layer 2 exposed from
Impurities infiltrate from 1.

[Step shown in FIG. 9 (b)]
Exposed from the interlayer insulating film 11 using the edge film 11 as a mask
N being ^-The surface layer of the mold layer 2 is removed by dry etching.
It At this time, as the etching gas, for example, HB
r, SF₆Use gas. And N^-From the surface of mold layer 2
For example, a region having a depth of 150 to 300 nm is removed. This
As a result, the region where the impurities have penetrated from the interlayer insulating film 11
Completely removed.

[Step shown in FIG. 9C] Then, the source electrode 2 is formed in the contact hole 15 and on the interlayer insulating film 11.
5 is formed.

As described above, in the present embodiment, the region where impurities have entered is removed during the reflow process, and the surface of the region of the N ⁻ type layer 2 where the impurities have not entered the interlayer insulating film 11 is removed. It is connected to the source electrode 25. Thereby, the ion implantation process for compensating the impurity concentration after the reflow process can be omitted.

Further, as in the first embodiment, since the upper end portion of the contact hole 15 has a curved shape that is convex upward, it is possible to reduce irregularities on the surface of the source electrode 25.

(Fourth Embodiment) FIG. 10 shows part of a process for manufacturing a semiconductor device according to the fourth embodiment.

In the first embodiment, the interlayer insulating film 11a was removed in the step shown in FIG. 4B, but not only the interlayer insulating film 11a, but the lower side thereof as in the third embodiment. The surface layer of the semiconductor substrate 3 may be removed.

In this embodiment, as in the first embodiment,
The steps shown in FIGS. 2A to 4A are performed. That is,
The interlayer insulating film 11 is partially etched to form the interlayer insulating film 1.
A reflow process is performed with 1a left on the surface of the semiconductor substrate 3. As a result, the upper end portion of the contact hole 15 in the interlayer insulating film 11 has a curved shape that is convex upward.

At this time, in the first embodiment, the P-type base region 5 is electrically connected to the source electrode 16,
The N ⁺ -type source region 6 is the P-type base region 5 surface layer,
It was formed only in the vicinity of the gate electrode 9. That is, the adjacent N ⁺ type source regions 6 were formed apart from each other from the beginning when the N ⁺ type source regions 6 were formed.

On the other hand, in this embodiment, for example,
As shown in FIG. 10, an N ⁺ type source region 26 is formed in the entire surface layer of the P type base region 5.

Subsequently, as in the step shown in FIG. 4B of the first embodiment, the interlayer insulating film 11 is entirely etched to remove the interlayer insulating film 11a. Thereafter, the surface layer of the N ⁻ type layer 2 is etched in the same manner as the step shown in FIG. 9A of the third embodiment. At this time, in the present embodiment, etching is performed so that the N ⁺ type source region 26 is penetrated.

After that, the source electrode 25 is formed. Also by forming in this way, the semiconductor device shown in FIG. 9C of the third embodiment can be formed.

(Other Embodiments) In the fourth embodiment, the first
The case where the embodiment and the third embodiment are combined has been described, but similarly, the second embodiment and the third embodiment may be combined. That is, FIG. 8A in the second embodiment.
In the step shown in, the nitride film 21 is removed. After that, FIG.
In the steps shown in (b) and (c), the N-type layer 2 surface layer can be etched.

In each of the above-described embodiments, the semiconductor device having the CONCAVE type gate electrode has been described as an example. However, the structure of the gate electrode is not limited to the CONCAVE type, but may be a planar type or trench type semiconductor device. Also, the present invention can be applied.

[Brief description of drawings]

FIG. 1 is a view showing a cross section of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment of the invention.

FIG. 3 is a diagram showing the manufacturing process of the semiconductor device, following FIG. 2;

FIG. 4 is a diagram showing the manufacturing process of the semiconductor device, following FIG. 3;

FIG. 5 is a diagram showing a manufacturing process of a conventional semiconductor device as a first example.

FIG. 6 is a diagram showing a manufacturing process of the semiconductor device according to the second embodiment of the invention.

FIG. 7 is a diagram showing the manufacturing process of the semiconductor device, following FIG. 6;

FIG. 8 is a diagram showing the manufacturing process of the semiconductor device, following FIG. 7;

FIG. 9 is a diagram showing a manufacturing process of the semiconductor device according to the third embodiment of the invention.

FIG. 10 is a diagram showing a manufacturing process of the semiconductor device according to the fourth embodiment of the invention.

FIG. 11 is a diagram showing a manufacturing process of a conventional semiconductor device as a second example.

[Explanation of symbols]

1 ... N ⁺ type substrate, 2 ... N ⁻ type layer, 3 ... Semiconductor substrate, 4 ...
Grooves, 5 ... P-type base region, 6, 26 ... N ⁺ type source region, 7 ... Gate oxide film, 8, 10 ... Oxide film, 9 ... Gate electrode, 11 ... Interlayer insulating film, 12 ... SOG, 15, 17 …
Contact holes, 16, 18, 25 ... Source electrodes.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Ken Miyajima             1-1, Showa-cho, Kariya city, Aichi stock market             Inside the company DENSO (72) Inventor Tsuyoshi Fukasawa             1-1, Showa-cho, Kariya city, Aichi stock market             Inside the company DENSO F-term (reference) 4M104 AA01 BB01 BB02 CC01 CC05                       DD06 DD08 DD12 DD17 DD19                       DD24 EE03 EE12 EE16 FF02                       FF27 GG09 HH13 HH15                 5F033 HH04 HH08 JJ01 JJ08 KK01                       MM30 NN32 QQ07 QQ09 QQ10                       QQ11 QQ16 QQ18 QQ22 QQ25                       QQ31 QQ34 QQ37 QQ74 QQ75                       RR03 RR06 RR09 RR15 RR25                       SS11 SS22 TT02 VV06 VV07                       XX02 XX09

Claims (6)

[Claims] 1. A semiconductor substrate (3), an interlayer insulating film (11) formed on the semiconductor substrate (3), and a contact hole (15) formed in the interlayer insulating film (11).
And a metal electrode (16) formed on the interlayer insulating film (11) and electrically connected to the semiconductor substrate (3) through the contact hole (15). In the step of preparing a semiconductor substrate (3) and forming an interlayer insulating film (11) on the semiconductor substrate (3); A step of forming a contact hole (15) by opening the insulating film (11) halfway and leaving an interlayer insulating film (11a) of a predetermined thickness, and forming the contact hole (15) in the semiconductor substrate (3). ) A step of performing a reflow process in a state where the interlayer insulating film (11a) having the predetermined thickness is provided on a region located below, and removing the interlayer insulating film (11a) having the predetermined thickness. , Said half A step of exposing the surface of the conductor substrate (3) from the interlayer insulating film (11); and a step of forming the metal electrode (16) in the contact hole (15) and on the interlayer insulating film (11). A method for manufacturing a semiconductor device, comprising: 2. In the step of partially opening the interlayer insulating film (11) and leaving an interlayer insulating film (11a) of a predetermined thickness,
When the predetermined thickness is d ₁ and the film thickness of the interlayer insulating film (11) before opening is d ₂ , the predetermined thickness is set so as to satisfy the relationship of d ₂ > 2d _1. The method for manufacturing a semiconductor device according to claim 1, further comprising: 3. A semiconductor substrate (3), an interlayer insulating film (11) formed on the semiconductor substrate (3), and a contact hole (15) formed in the interlayer insulating film (11).
And a metal electrode (16) formed on the interlayer insulating film (11) and electrically connected to the semiconductor substrate (3) through the contact hole (15). A step of preparing a semiconductor substrate (3) and forming a protective film (21) on the surface of the semiconductor substrate (3); and a step of forming the interlayer insulating film (11) on the protective film (21) In the region where the contact hole (15) is to be formed in the interlayer insulating film (11), the contact hole (1) is formed in the interlayer insulating film (11), leaving the protective film (21).
5), and forming the protective film (2) on the region of the semiconductor substrate (3) located below the contact hole (15).
1), a reflow process is performed, the protective film (21) is removed to expose the surface of the semiconductor substrate (3) from the interlayer insulating film (11), and the contact hole ( 15) a step of forming the metal electrode (16) inside and on the interlayer insulating film (11). 4. A semiconductor substrate (3), an interlayer insulating film (11) formed on the semiconductor substrate (3), and a contact hole (24) formed in the interlayer insulating film (11).
And a metal electrode (25) formed on the interlayer insulating film (11) and electrically connected to the semiconductor substrate (3) through the contact hole (24). A step of preparing a semiconductor substrate (3) and forming an interlayer insulating film (11) on the semiconductor substrate (3); forming a contact hole (17) in the interlayer insulating film (11); A step of exposing the surface of the substrate (3) from the interlayer insulating film (11); a step of performing a reflow treatment on the interlayer insulating film (11);
1) A step of removing a region exposed from the surface to a predetermined depth, and a step of forming the metal electrode (25) in the contact hole (24) and on the interlayer insulating film (11). A method for manufacturing a semiconductor device, comprising: 5. In the step of forming the contact hole (15), the opening width at the upper end is larger than the opening width at the lower end by isotropic etching and anisotropic etching of the interlayer insulating film (11). The method for manufacturing a semiconductor device according to claim 1, wherein a contact hole (15) is formed. 6. A semiconductor layer (2) of the first conductivity type on the main surface side.
A semiconductor substrate (3) having a groove, a groove (4) formed in a surface layer of the semiconductor layer (2), and a gate electrode (9) formed in the groove (4) via a gate insulating film (7). A second conductivity type base region (5) formed adjacent to the groove (4) in the surface layer of the semiconductor layer (2), and in the surface layer of the base region (5), A first conductivity type source region (6) formed adjacent to the groove, an interlayer insulating film (11) formed on the surface of the semiconductor layer (2), and an interlayer insulating film (11). A contact hole (15) formed on the interlayer insulating film (11) and electrically connected to the base region (5) and the source region (6) through the contact hole (15). A source electrode (16) and a drain formed on the back side of the semiconductor substrate (3) A semiconductor device comprising an electrode (19), wherein an upper end of the contact hole (15) of the interlayer insulating film (11) has a curved shape that is convex upward.