JP4039153B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an insulated gate semiconductor device such as a MOSFET or IGBT having an insulating film and a gate electrode formed in a trench.
[0002]
[Prior art]
FIGS. 18 to 23 are cross-sectional views of main processes shown in the order of steps in the conventional method for manufacturing a semiconductor device having a trench structure. Here, the semiconductor device is exemplified as a MOSFET.
A p base region 52 (also referred to as a p channel region) is formed in the surface layer of the first main surface of n semiconductor substrate 200, and reaches n semiconductor substrate 200 from the surface of p base region 52 through p base region 52. A trench groove 53 is formed (FIG. 18).
[0003]
Next, an insulating film 54 such as an oxide film is formed in the trench groove 53 and on the p base region 52, and a polycrystalline silicon 55 for filling the trench groove 53 is formed on the insulating film 54 (FIG. 19). .
Next, the polycrystalline silicon to be the gate electrode layer 56 filled in the trench groove 53 is left, and the polycrystalline silicon 55 is removed using a planarization technique until the insulating film 54 is exposed. At this time, since the polycrystalline silicon 55 is etched at over-over so that the residue of the polycrystalline silicon 55 on the insulating film 54 is not generated, the surface of the polycrystalline silicon (gate electrode layer 56) in the trench groove 53 is high. The height is lower than the height of the surface of the p base region 52. (FIG. 20).
[0004]
Next, the insulating film 54 exposed on the surface is removed by isotropic etching using an HF solution (hydrofluoric acid solution) while leaving the insulating film to be the gate insulating film 57 formed in the trench 53. The surface of the p base region 52 is exposed. Next, a thin oxide film 58 is formed on the p base region 52, the gate electrode layer 56, and the exposed surface of the gate insulating film 57, and the n-type impurities 61 are masked through the thin oxide film 58 using the resist 59 as a mask. Ion implantation 60 is performed (FIG. 21).
[0005]
Next, heat treatment is performed to form an n source region 62 in contact with the trench groove 53 (FIG. 22).
Next, an n drain region 63 is formed on the surface layer of the second main surface of the n semiconductor substrate 200, and an interlayer insulating film 64 is formed on the gate electrode layer 56. A source electrode 65 and a drain electrode 66 are formed on the n source region 62 and the n drain region 63 (FIG. 23). The n semiconductor substrate 200 sandwiched between the n source region 62 and the n drain region 63 becomes the n drift region 51.
[0006]
24 and 25 are enlarged views of part C in FIGS. 21 and 22. A portion of the gate insulating film 57 on the side wall of the trench groove 53 that is higher than the surface of the gate electrode layer 56 is removed by isotropic etching, and the gate insulating film 57 sandwiched between the gate electrode layer 56 and the p base region 52 is removed. Since the upper portion of the gate insulating film 57 is also removed by etching, a recess is formed on the surface of the upper end portion of the gate insulating film 57. Therefore, during the ion implantation 60 for forming the n source region 62, a large amount of the impurity 61 is implanted into the p base region 52 from the recess without the gate insulating film 57 and the sidewall of the trench groove 53, and the recess and the sidewall are subjected to heat treatment. Impurity 61 implanted from above diffuses to a deep position in the p base region 52, and the n source region 62 has a two-stage shape as shown in FIG.
[0007]
When the diffusion depth of the n source region 62 becomes deeper at a location in contact with the trench groove 53, the impurity concentration of the p base region 52 in contact with the n source region 62 at this deep location becomes lower. When the impurity concentration of the p base region 52 is lowered, the gate voltage for forming the n channel, that is, the gate threshold voltage is also lowered.
FIG. 26 is a diagram showing the relationship between the height difference H2 between the surface of the gate electrode layer and the surface of the n source region and the gate threshold voltage.
[0008]
As the height difference H2 increases, the gate threshold voltage decreases. This is because the impurity 61 is also ion-implanted from the side wall surface of the trench groove 53 higher than the surface of the gate electrode layer 56. Therefore, when the height difference H2 increases, the amount of ion implantation from the side wall surface increases. This is because the diffusion depth of n becomes deep and the gate threshold voltage becomes small. Further, since the impurity 61 is also ion-implanted from the recess at the upper end of the gate insulating film 57, the diffusion depth of the n source region 62 in contact with the trench groove 53 is further increased, and the gate threshold voltage is lowered. It can be seen that a is when there is no recess, b is when there is a recess, and c is when the recess is large, and the gate threshold voltage changes depending on the size of the recess (the depth of the bottom of the recess).
[0009]
FIGS. 27 to 32 are cross-sectional views of main steps shown in the order of steps in another method for manufacturing a conventional semiconductor device having a trench structure.
A p base region 52 is formed in the surface layer of the first main surface of the n semiconductor substrate 200, and a trench groove 53 penetrating the p base region 52 from the surface of the p base region 52 and reaching the n semiconductor substrate 200 is formed ( FIG. 27).
[0010]
Next, an insulating film 54 such as an oxide film is formed in the trench groove 53 and on the p base region 52, and a polycrystalline silicon 55 filling the trench groove 53 is formed on the insulating film 54 (FIG. 28).
Next, the polycrystalline silicon to be the gate electrode layer 56 filled in the trench groove 53 is left, and the polycrystalline silicon 55 is removed using a planarization technique until the insulating film 54 is exposed. At this time, the height of the surface of the insulating film 54 and the height of the surface of the polycrystalline silicon (gate electrode layer 56) in the trench groove 53 are made substantially the same. This point is different from FIG. 20 (FIG. 29).
[0011]
Next, the insulating film 54 formed on the trench groove 53 to be the gate insulating film 57 is left, and the insulating film 54 exposed on the surface is removed by isotropic etching using an HF solution, so that the surface of the p base region 52 is removed. Expose. Next, a thin insulating film 58 is formed on the p base region 52 and the gate electrode layer 56, and ion implantation 60 of n-type impurities 61 is performed through the thin insulating film 58 using the resist 59 as a mask (FIG. 30). ).
[0012]
Next, heat treatment is performed to form an n source region 62 in contact with the trench groove 53 (FIG. 31).
Next, an n drain region 63 is formed on the surface layer of the second main surface of the n semiconductor substrate 200, and an interlayer insulating film 64 is formed on the gate electrode layer 53. A source electrode 65 and a drain electrode 66 are formed on the n source region 62 and the n drain region 63, respectively (FIG. 32).
[0013]
33 and 34 are enlarged views of the D part in FIGS. 30 and 31. FIG. The gate oxide film 57 on the sidewall of the trench groove 53 is etched lower than the surface of the p base region 52 by isotropic etching, and a recess is also formed at the upper end of the gate insulating film 57. Therefore, when the n source region 62 having a shallow diffusion depth is formed, the impurity 61 is implanted into the p base region 52 from the upper side wall of the trench groove 53 where the gate insulating film 57 is not present. 61 diffuses in the p base region 52, and the n source region 62 has a two-stage shape as shown in FIG.
[0014]
As described above, when the diffusion depth of n source region 62 is increased, the n channel layer formed in the surface layer of p base region 52 in contact with the side wall surface of trench groove 53 is formed with a low gate voltage. As a result, the gate threshold voltage decreases.
[0015]
[Problems to be solved by the invention]
That is, in the case of the semiconductor device of FIG. 23 described above, the height difference H2 and the upper end portion of the gate insulating film are concave, so that impurities are ion-implanted from this location and the n source region in contact with the trench groove is formed. The depth becomes deeper and the gate threshold voltage becomes smaller than the design value. Further, since the depth of the concave portion cannot be controlled, the depth of the concave portion varies, and the gate threshold voltage varies.
[0016]
In the case of the semiconductor device shown in FIG. 32, since the upper end portion of the gate insulating film is concave, impurities are ion-implanted from this location, and the depth of the n source region in contact with the trench groove is deep. Thus, the gate threshold voltage becomes smaller than the design value. Further, since the depth of the concave portion cannot be controlled, the depth of the concave portion varies, and the gate threshold voltage varies.
[0017]
In addition, the receding surface of the gate insulating film etched down from the gate electrode layer is filled with an interlayer insulating film that covers the subsequent gate electrode layer. However, when a voltage is applied to the gate electrode layer, It is inevitable that a gate voltage is also applied to the interlayer insulating film, and the reliability of the interlayer insulating film is inferior to that of the gate insulating film, leading to a decrease in reliability.
[0018]
The object of the present invention is to solve the above-mentioned problems, eliminate the influence of the height difference H2 between the surface of the gate electrode layer and the p-well region, prevent the upper end portion of the gate insulating film from becoming a recess, An object of the present invention is to provide a semiconductor device that can design a threshold voltage to a predetermined value, reduce variations in gate threshold voltage, and increase the reliability of gate breakdown voltage characteristics, and a method of manufacturing the same.
[0019]
[Means for Solving the Problems]
To achieve the above object, (1) a first semiconductor region of a second conductivity type formed in a surface layer of a first main surface of a semiconductor substrate of a first conductivity type, and a surface of the first main surface. A trench groove formed so as to penetrate the first semiconductor region and reach the semiconductor substrate, a gate insulating film formed so as to cover a side wall surface and a bottom surface of the trench groove, and via the gate insulating film A gate electrode layer formed in the trench groove; a second semiconductor region of a first conductivity type in contact with the trench groove and selectively formed in a surface layer of the first semiconductor region; and on the second semiconductor region And a first main electrode formed on the first semiconductor region, and a second main electrode formed on the second main surface side of the semiconductor substrate, wherein the surface of the gate electrode layer is The height is equal to the height of the surface of the second semiconductor region, or Ku, the height of the upper portion of the gate insulating film, may be identical to the height of the surface of the second semiconductor region.
(2) forming a first semiconductor region of the second conductivity type in a surface layer of the first main surface of the first conductivity type semiconductor substrate, penetrating the first semiconductor region from the surface of the first main surface, Forming a trench groove reaching the semiconductor substrate; forming a first insulating film in the trench groove and on the first semiconductor region; forming polycrystalline silicon on the first insulating film; A step of filling the trench, a step of removing the polycrystalline silicon leaving the polycrystalline silicon to be a gate electrode layer in the trench trench, and a first insulating film being a gate insulating film in the trench trench. Removing the first insulating film on the first semiconductor region; and a second semiconductor region of a first conductivity type in contact with a sidewall surface of the trench groove and selectively on a surface layer of the first semiconductor region And a method of manufacturing a semiconductor device having a step of forming In the step of removing the polycrystalline silicon, the height of the surface of the gate electrode layer is made lower than the height of the surface of the second semiconductor region, and the first insulating film on the first semiconductor region is removed. In this step, the first insulating film is removed by anisotropic etching, so that the height of the upper end portion of the gate insulating film formed on the sidewall surface of the trench groove and in contact with the trench groove is increased. In the manufacturing method, the height of the upper end portion of the gate electrode layer at a position in contact with the gate insulating film is set higher.
(3) forming a first semiconductor region of the second conductivity type on the surface layer of the first main surface of the semiconductor substrate of the first conductivity type, penetrating the first semiconductor region from the surface of the first main surface, Forming a trench groove reaching the semiconductor substrate; forming a first insulating film in the trench groove and on the first semiconductor region; forming polycrystalline silicon on the first insulating film; A step of filling the trench, a step of removing the polycrystalline silicon leaving the polycrystalline silicon to be a gate electrode layer in the trench trench, and a first insulating film being a gate insulating film in the trench trench. Removing the first insulating film on the first semiconductor region; and a second semiconductor region of a first conductivity type in contact with a sidewall surface of the trench groove and selectively on a surface layer of the first semiconductor region And a method of manufacturing a semiconductor device having a step of forming In the step of removing the polycrystalline silicon, the height of the surface of the gate electrode layer is the same as or higher than the height of the surface of the second semiconductor region, and the first insulating film on the first semiconductor region is formed. In the manufacturing process, the first insulating film is removed using anisotropic etching so that the height of the upper end portion of the gate insulating film is the same as the height of the surface of the second semiconductor region. The method.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
In the following description, an n-channel semiconductor device is described, but a p-channel semiconductor device may be used.
FIGS. 1 to 6 are cross-sectional views of essential steps shown in the order of steps in the method of manufacturing a semiconductor device according to the first embodiment of the present invention. Here, the semiconductor device has been described by taking MOSFET as an example, but it is naturally applicable to other insulated gate semiconductor devices such as IGBT.
[0021]
A p base region 2 is formed in the surface layer of the first main surface of n semiconductor substrate 100, and a trench that penetrates p base region 2 from the surface of p base region 2 and reaches n semiconductor substrate 100 (non-diffusion region 1 a). A groove 3 is formed (FIG. 1).
Next, an insulating film 4 (oxide film, nitride film and laminated film thereof) is formed in the trench groove 3 and on the p base region 2, and the polycrystalline silicon 5 filling the trench groove 3 is formed on the insulating film 4. (FIG. 2).
[0022]
Next, the polycrystalline silicon to be the gate electrode layer 6 filled in the trench groove 3 is left, and the polycrystalline silicon 5 is removed using a planarization technique until the insulating film 4 is exposed. At this time, in order to remove the polycrystalline silicon 5 so that the residue of the polycrystalline silicon 5 on the insulating film 4 does not occur, the height of the surface of the gate electrode layer 6 of polycrystalline silicon formed in the trench 3 is removed. Is lower than the height of the surface of the p base region 2. (Figure 3).
[0023]
Next, leaving the insulating film to be the gate insulating film 7 formed in the trench 3, the exposed insulating film 4 is removed by anisotropic etching using RIE (Reactive Ion Etching) or the like to form the p base region 2. To expose the surface. A thin insulating film 8 is formed on the p base region 2, the gate electrode layer 6 and the exposed surface of the gate insulating film 7, and the resist 9 is used as a mask through the thin insulating film 8 (a film called a screen oxide film). Ion implantation 10 of n-type impurity 11 (arsenic: As or the like) is performed (FIG. 4).
[0024]
Next, heat treatment is performed to form the n source region 12 in contact with the trench 3 (FIG. 5).
Next, the n drain region 13 is formed on the surface layer of the second main surface of the n semiconductor substrate 100, and the interlayer insulating film 14 is formed on the gate electrode layer 6. A source electrode 15 and a drain electrode 16 are formed on the n source region 12 and the n drain region 13, respectively (FIG. 6). A non-diffusion region of the n semiconductor substrate 100 sandwiched between the n source region 12 and the n drain region 13 becomes the n drift region 1. FIG. 6 is a cross-sectional view of the main part of the semiconductor device formed by the manufacturing method of the first embodiment.
[0025]
7 and 8 are enlarged views of a part A in FIGS. 4 and 5. Due to the anisotropic etching, the gate insulating film 7 formed on the side wall surface of the trench groove 3 remains almost unetched. Therefore, no recess is formed in the upper end portion of the gate insulating film 57 as in isotropic etching, and as shown in the figure, the trench groove extends from the upper end portion (a) of the gate insulating film 7 at a location in contact with the gate electrode layer 6. The height (H) of the surface (c) of the gate insulating film 7 increases monotonously up to the upper end (b) of the gate insulating film 7 at a location in contact with 3.
[0026]
In other words, the concave portion as shown in FIG. 24 is not formed on the surface of the upper end portion of the gate insulating film 7. The gate insulating film 7 covers the entire side wall of the trench 3. Therefore, the impurity 11 is not implanted from the side wall of the trench groove 3. Therefore, since the diffusion depth of the n source region 12 can be set to a predetermined value, the gate threshold voltage can also be set to a predetermined value.
[0027]
Further, as shown by a dotted line in FIG. 8, even if the gate insulating film 7 in the vicinity of the opening of the trench groove 3 is partially removed (about 1/10 of the diffusion depth of the n source region 12), The effect on the value is small and there is no problem. Also, in anisotropic etching by RIE, the variation in the etching amount is small, so that the variation in the diffusion depth of the n source region is small even when it is partially removed. Therefore, variation in gate threshold voltage can be reduced.
[0028]
FIG. 9 is a diagram showing the relationship between the height difference H1 between the surface of the gate electrode layer and the surface of the n source region and the gate threshold voltage.
Even if the height difference H1 is increased, the gate oxide film is formed on the side wall surface of the trench groove, so that the diffusion depth of the n source region does not change. Therefore, the gate threshold voltage does not change and can be set to a predetermined value.
[0029]
Further, since the gate insulating film 7 covers the entire side wall of the trench groove 3, the gate insulating film 7 is not affected by the film quality of the thin insulating film 8 or the interlayer insulating film 14 formed on the gate electrode layer 6. The reliability of the gate voltage characteristics can be secured.
FIGS. 10 to 16 are cross-sectional views showing main steps of the semiconductor device manufacturing method according to the second embodiment of the present invention shown in the order of steps.
[0030]
A p base region 2 is formed in the surface layer of the first main surface of the n semiconductor substrate 100, and a trench 3 is formed from the surface of the p base region 2 to the n semiconductor substrate 100 through the p base region 2. FIG. 10).
Next, an insulating film 4 is formed in the trench groove 3 and on the p base region 2, and a polycrystalline silicon 5 filling the trench groove 3 is formed on the insulating film 4 (FIG. 11).
[0031]
Next, using the planarization technique, the polycrystalline silicon 5 is removed until the insulating film 4 is exposed, leaving the polycrystalline silicon to be the gate electrode layer 6 filled in the trench 3. At this time, the height of the surface of the insulating film 4 and the height of the surface of the gate electrode layer 6 of polycrystalline silicon formed in the trench 3 are made substantially the same. Strictly speaking, in order to remove the remaining polycrystalline silicon on the insulating film 4, the height of the surface of the gate electrode layer 6 is slightly lowered, but is made higher than the height of the surface of the p base region 2 (L1). This point is different from FIG. 3 of the first embodiment. In order to ensure that the height of the surface of the gate electrode layer 6 is higher than the height of the surface of the p base region 2 (L1), a resist (not shown) is coated on the polycrystalline silicon to be the gate electrode layer 6, and this Other polysilicon may be removed using the resist as a mask. Further, a thick insulating film (not shown) is formed on the insulating film 4 at a portion other than the opening of the trench groove 3, and after filling the trench groove 3 with polycrystalline silicon, an insulating film (not shown) is formed using a planarization technique. The polycrystalline silicon may be removed until it is exposed (FIG. 12).
[0032]
Next, leaving the insulating film to be the gate insulating film 7 formed in the trench 3, the exposed insulating film 4 is removed by anisotropic etching such as RIE to expose the surface of the p base region 2. A thin insulating film 8 is formed on the p base region 2, the gate electrode layer 6, and the exposed surface of the gate insulating film 7, and the n-type impurity 11 ( An ion implantation 10 of arsenic: As or the like is performed (FIG. 13).
[0033]
Next, heat treatment is performed to form the n source region 12 in contact with the trench 3 (FIG. 14).
Next, the n drain region 13 is formed on the surface layer of the second main surface of the n semiconductor substrate 100, and the interlayer insulating film 14 is formed on the gate electrode layer 6. A source electrode 15 and a drain electrode 16 are formed on the n source region 12 and the n drain region 13 (FIG. 15). The n semiconductor substrate 100 sandwiched between the n source region 12 and the n drain region 13 becomes the n drift region 1. FIG. 15 is a fragmentary cross-sectional view of a semiconductor device formed by the manufacturing method of the second embodiment.
[0034]
16 and 17 are enlarged views of a portion B in FIGS. 13 and 14. The gate insulating film 7 is anisotropically etched so that the exposed surface (the surface of the upper end portion) of the gate insulating film 7 has the same height as the surface of the p base region 2. Accordingly, since the ion implantation 10 of the impurity 11 for forming the n source region 12 is performed from the surface of the p base region, even when the n source region 12 having a shallow diffusion depth (about 1 μm) is formed, the diffusion shape is formed. Can have a predetermined diffusion depth without forming a two-stage shape. As a result, the gate threshold voltage can be set to a predetermined value. In addition, variations in gate threshold voltage can be reduced.
[0035]
【The invention's effect】
According to the present invention, by adopting anisotropic etching in the step of leaving the insulating film in the trench groove and removing the insulating film on the p base region, the trench groove side wall located on the gate electrode layer is formed. The gate insulating film can be left, and the diffusion depth of the n source region can be set to a predetermined depth.
[0036]
Further, variation in the diffusion depth of the n source region can be reduced. Further, the reliability of the gate voltage characteristic can be improved by covering the sidewall of the trench groove with the gate insulating film.
[Brief description of the drawings]
1 is a cross-sectional view of main steps of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view of main steps of a semiconductor device according to a first embodiment of the present invention following FIG. 2 is a fragmentary process cross-sectional view of the semiconductor device of the first embodiment of the present invention following FIG. 4. FIG. 4 is a fragmentary process cross-sectional view of the semiconductor device of the first embodiment of the present invention following FIG. 4 is a fragmentary process cross-sectional view of the semiconductor device of the first embodiment of the present invention continued from FIG. 4. FIG. 6 is a fragmentary process cross-sectional view of the semiconductor device of the first embodiment of the present invention continued from FIG. FIG. 8 is an enlarged view of part A of FIG. 4. FIG. 9 is an enlarged view of part A of FIG. 5. FIG. 10 is a cross-sectional view of main steps of a semiconductor device according to a second embodiment of the present invention. FIG. 11 is a cross-sectional view of main steps of a semiconductor device according to the second embodiment of the present invention following FIG. FIG. 12 is a cross-sectional view of the principal part of the semiconductor device according to the second embodiment of the present invention continued from FIG. 11. FIG. 13 is a cross-sectional view of the principal part of the semiconductor device according to the second embodiment of the present invention continued from FIG. FIG. 14 is a cross-sectional view of main steps of a semiconductor device according to a second embodiment of the present invention continued from FIG. 13. FIG. 15 is a cross-sectional view of main steps of a semiconductor device according to a second embodiment of the present invention continued from FIG. FIG. 16 is an enlarged view of part B in FIG. 13. FIG. 17 is an enlarged view of part B in FIG. 14. FIG. 18 is a cross-sectional view of essential steps of a conventional semiconductor device having a trench structure. FIG. 20 is a fragmentary process cross-sectional view of a conventional semiconductor device continued from FIG. 19. FIG. 21 is a fragmentary process cross-sectional view of a conventional semiconductor device continued from FIG. 22 is a cross-sectional view of main steps of a conventional semiconductor device continued from FIG. 21. FIG. FIG. 24 is an enlarged view of part C in FIG. 21. FIG. 25 is an enlarged view of part C in FIG. 22. FIG. 26 is a difference in height H2 between the surface of the gate electrode layer and the surface of the n source region. FIG. 27 is a cross-sectional view of main steps of another conventional semiconductor device having a trench structure. FIG. 28 is a main portion of another conventional semiconductor device continued from FIG. FIG. 29 is a cross-sectional view of a main part of another conventional semiconductor device continued from FIG. 28. FIG. 30 is a cross-sectional view of a main part of another conventional semiconductor device continued from FIG. FIG. 32 is a fragmentary process sectional view of another conventional semiconductor device continued from FIG. 30. FIG. 32 is a fragmentary process sectional view of another conventional semiconductor device continued from FIG. 34] Enlarged view of part D in FIG.
1 n drift region 1a non-diffusion region 2 p base region 3 trench groove 4 insulating film 5 polycrystalline silicon 6 gate electrode layer 7 gate insulating film 8 thin insulating film 9 resist 10 ion implantation 11 impurity 12 n source region 13 n drain region 14 Interlayer insulating film 15 Source electrode 16 Drain electrode 100 n Semiconductor substrate

Claims (2)

Forming a first semiconductor region of the second conductivity type on the surface layer of the first main surface of the semiconductor substrate of the first conductivity type;
Forming a trench groove that penetrates the first semiconductor region from the surface of the first main surface and reaches the semiconductor substrate;
Forming a first insulating film in the trench and on the first semiconductor region;
Forming polycrystalline silicon on the first insulating film and filling the trench groove;
The polycrystalline silicon on the first insulating film is left as a gate electrode so that the height of the surface in the trench groove is lower than the height of the surface of the first semiconductor region. Removing until the first insulating film on the region is exposed ;
Subsequently, the height of the upper end portion of the first insulating film formed on the side wall surface of the trench is higher than the height of the upper portion of the gate electrode layer, and said to cover the sidewalls entire surface of the trench Leaving the first insulating film in the trench groove and removing the first insulating film by anisotropic etching so that the surface of the first semiconductor region is exposed;
Forming a second semiconductor region by selectively implanting ions of a first conductivity type into the surface layer of the first semiconductor region using the first insulating film as a mask in contact with the sidewall surface of the trench groove; Have
A method of manufacturing a semiconductor device, wherein the steps are performed in order. Forming a first semiconductor region of the second conductivity type on the surface layer of the first main surface of the semiconductor substrate of the first conductivity type;
Forming a trench groove that penetrates the first semiconductor region from the surface of the first main surface and reaches the semiconductor substrate;
Forming a first insulating film in the trench and on the first semiconductor region;
Forming polycrystalline silicon on the first insulating film and filling the trench groove;
The polycrystalline silicon on the first insulating film is left as a gate electrode so that the height of the surface in the trench groove is higher than the height of the surface of the first semiconductor region, and the semiconductor Removing until the first insulating film on the region is exposed;
Subsequently, the trench is formed such that the height of the upper end portion of the first insulating film formed on the sidewall surface of the trench groove is equal to the height of the surface of the first semiconductor region and covers the entire sidewall of the trench groove. Leaving the first insulating film in the trench and removing the first insulating film by anisotropic etching so that the surface of the first semiconductor region is exposed;
Forming a second semiconductor region by selectively implanting ions of a first conductivity type into the surface layer of the first semiconductor region using the first insulating film as a mask in contact with the sidewall surface of the trench groove; Have
A method of manufacturing a semiconductor device, wherein the steps are performed in order.

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