JP2003224852A - メモリ回路及びビデオデータデコーダ - Google Patents

メモリ回路及びビデオデータデコーダ

Info

Publication number
JP2003224852A
JP2003224852A JP2002178595A JP2002178595A JP2003224852A JP 2003224852 A JP2003224852 A JP 2003224852A JP 2002178595 A JP2002178595 A JP 2002178595A JP 2002178595 A JP2002178595 A JP 2002178595A JP 2003224852 A JP2003224852 A JP 2003224852A
Authority
JP
Japan
Prior art keywords
data
words
memory circuit
component
components
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2002178595A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003224852A5 (https=
Inventor
Anne Lafage
アンヌ、ラファージュ
Lien Nguyen-Phuc
リアン、ヌユイアン‐フュック
Jacky Talayssat
ジャキー、タレイサ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of JP2003224852A publication Critical patent/JP2003224852A/ja
Publication of JP2003224852A5 publication Critical patent/JP2003224852A5/ja
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Image Input (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
  • Image Processing (AREA)
JP2002178595A 2001-06-19 2002-06-19 メモリ回路及びビデオデータデコーダ Withdrawn JP2003224852A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0108046 2001-06-19
FR0108046A FR2826226A1 (fr) 2001-06-19 2001-06-19 Circuit memoire concu pour un acces parallele en lecture ou en ecriture de donnees a plusieurs composantes

Publications (2)

Publication Number Publication Date
JP2003224852A true JP2003224852A (ja) 2003-08-08
JP2003224852A5 JP2003224852A5 (https=) 2005-09-29

Family

ID=8864508

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002178595A Withdrawn JP2003224852A (ja) 2001-06-19 2002-06-19 メモリ回路及びビデオデータデコーダ

Country Status (4)

Country Link
US (1) US6667931B2 (https=)
EP (1) EP1271963A2 (https=)
JP (1) JP2003224852A (https=)
FR (1) FR2826226A1 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10013075B2 (en) 1999-09-15 2018-07-03 Michael Shipman Illuminated keyboard
US7304646B2 (en) * 2004-08-19 2007-12-04 Sony Computer Entertainment Inc. Image data structure for direct memory access
US11216078B2 (en) 2005-01-18 2022-01-04 Michael Shipman Illuminated keyboard

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6279116B1 (en) * 1992-10-02 2001-08-21 Samsung Electronics Co., Ltd. Synchronous dynamic random access memory devices that utilize clock masking signals to control internal clock signal generation
US5920352A (en) * 1994-10-28 1999-07-06 Matsushita Electric Industrial Co., Ltd. Image memory storage system and method for a block oriented image processing system
JP3722619B2 (ja) * 1997-07-10 2005-11-30 沖電気工業株式会社 メモリ装置及びそのアクセス制御方法
US5959929A (en) * 1997-12-29 1999-09-28 Micron Technology, Inc. Method for writing to multiple banks of a memory device
JPH11339005A (ja) * 1998-05-22 1999-12-10 Sony Corp 画像処理装置ならびに特殊効果装置、および画像処理方法
JP4224876B2 (ja) * 1998-09-11 2009-02-18 ソニー株式会社 記憶装置、並びに書き込み方法および読み出し方法

Also Published As

Publication number Publication date
US6667931B2 (en) 2003-12-23
FR2826226A1 (fr) 2002-12-20
EP1271963A2 (fr) 2003-01-02
US20030016584A1 (en) 2003-01-23

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