FR2826226A1 - Circuit memoire concu pour un acces parallele en lecture ou en ecriture de donnees a plusieurs composantes - Google Patents

Circuit memoire concu pour un acces parallele en lecture ou en ecriture de donnees a plusieurs composantes Download PDF

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Publication number
FR2826226A1
FR2826226A1 FR0108046A FR0108046A FR2826226A1 FR 2826226 A1 FR2826226 A1 FR 2826226A1 FR 0108046 A FR0108046 A FR 0108046A FR 0108046 A FR0108046 A FR 0108046A FR 2826226 A1 FR2826226 A1 FR 2826226A1
Authority
FR
France
Prior art keywords
data
words
component
banks
contiguous
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
FR0108046A
Other languages
English (en)
French (fr)
Inventor
Anne Lafage
Phuc Lien Nguyen
Jacky Talayssat
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Priority to FR0108046A priority Critical patent/FR2826226A1/fr
Priority to EP02077381A priority patent/EP1271963A2/fr
Priority to JP2002178595A priority patent/JP2003224852A/ja
Priority to US10/175,411 priority patent/US6667931B2/en
Publication of FR2826226A1 publication Critical patent/FR2826226A1/fr
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Image Input (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
  • Image Processing (AREA)
FR0108046A 2001-06-19 2001-06-19 Circuit memoire concu pour un acces parallele en lecture ou en ecriture de donnees a plusieurs composantes Pending FR2826226A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
FR0108046A FR2826226A1 (fr) 2001-06-19 2001-06-19 Circuit memoire concu pour un acces parallele en lecture ou en ecriture de donnees a plusieurs composantes
EP02077381A EP1271963A2 (fr) 2001-06-19 2002-06-14 Circuit mémoire conçu pour un accès parallèle en lecture ou en écriture de données à plusieurs composantes
JP2002178595A JP2003224852A (ja) 2001-06-19 2002-06-19 メモリ回路及びビデオデータデコーダ
US10/175,411 US6667931B2 (en) 2001-06-19 2002-06-19 Memory circuit designed for a parallel reading or writing access to data comprising various components

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0108046A FR2826226A1 (fr) 2001-06-19 2001-06-19 Circuit memoire concu pour un acces parallele en lecture ou en ecriture de donnees a plusieurs composantes

Publications (1)

Publication Number Publication Date
FR2826226A1 true FR2826226A1 (fr) 2002-12-20

Family

ID=8864508

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0108046A Pending FR2826226A1 (fr) 2001-06-19 2001-06-19 Circuit memoire concu pour un acces parallele en lecture ou en ecriture de donnees a plusieurs composantes

Country Status (4)

Country Link
US (1) US6667931B2 (https=)
EP (1) EP1271963A2 (https=)
JP (1) JP2003224852A (https=)
FR (1) FR2826226A1 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10013075B2 (en) 1999-09-15 2018-07-03 Michael Shipman Illuminated keyboard
US7304646B2 (en) * 2004-08-19 2007-12-04 Sony Computer Entertainment Inc. Image data structure for direct memory access
US11216078B2 (en) 2005-01-18 2022-01-04 Michael Shipman Illuminated keyboard

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0828238A2 (en) * 1996-08-30 1998-03-11 Matsushita Electric Industrial Co., Ltd. Image memory storage system and method for a block oriented image processing system
EP0959428A2 (en) * 1998-05-22 1999-11-24 Sony Corporation Image processing apparatus, special effect apparatus and image processing method
EP0986266A2 (en) * 1998-09-11 2000-03-15 Sony Corporation Image memory device and writing/reading out method therefor

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6279116B1 (en) * 1992-10-02 2001-08-21 Samsung Electronics Co., Ltd. Synchronous dynamic random access memory devices that utilize clock masking signals to control internal clock signal generation
JP3722619B2 (ja) * 1997-07-10 2005-11-30 沖電気工業株式会社 メモリ装置及びそのアクセス制御方法
US5959929A (en) * 1997-12-29 1999-09-28 Micron Technology, Inc. Method for writing to multiple banks of a memory device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0828238A2 (en) * 1996-08-30 1998-03-11 Matsushita Electric Industrial Co., Ltd. Image memory storage system and method for a block oriented image processing system
EP0959428A2 (en) * 1998-05-22 1999-11-24 Sony Corporation Image processing apparatus, special effect apparatus and image processing method
EP0986266A2 (en) * 1998-09-11 2000-03-15 Sony Corporation Image memory device and writing/reading out method therefor

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
HEER C ET AL: "CO-PROCESSOR ARCHITECTURE FOR MPEG-4M VIDEO OBJECT RENDERING", PROCEEDINGS OF THE SPIE, SPIE, BELLINGHAM, VA, US, vol. 4067, no. PART 1-3, 20 June 2000 (2000-06-20), pages 1451 - 1458, XP001058369 *

Also Published As

Publication number Publication date
US6667931B2 (en) 2003-12-23
JP2003224852A (ja) 2003-08-08
EP1271963A2 (fr) 2003-01-02
US20030016584A1 (en) 2003-01-23

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