JP2003218282A - Semiconductor element built-in board and multi-layer circuit board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To quickly transmit an electric signal without any delay, and to realize high dense wiring by shortening a distance between mounted semiconductor chips, and eliminating any failure due to a wiring resistance or inductance. <P>SOLUTION: This semiconductor element built-in board 50 comprises an insulating base material 10, a semiconductor element 26 housed in a recessed part or an opening 25 formed in the insulating base material 10, a via hole 20 made of conductive substance filled in a hole put through the insulating base material 10, an insulating layer 30 formed to cover the surface of the insulating base material 10 and the surface of the semiconductor element 26 and formed with openings 32 and 34 at positions corresponding to the respective positions of the via hole 20 and an electrode pad 27 of the semiconductor element 26, a wiring pattern 42 formed along the surface of the insulating layer 30 for electrically connecting the via hole 20 to the electrode pad 27, and a conductive bump 44 formed at the second surface side of the insulating base material 10 and electrically connected to the via hole 20. Also, a multi-layer circuit board is configured by laminating the plurality of boards. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board containing a semiconductor element and a multilayer circuit board formed by laminating and integrating the circuit boards.

[0002]

2. Description of the Related Art In recent years, in response to demands for complicated circuit configurations in various electronic devices and high-density mounting of electronic components,
Various high-density packaging structures have been proposed. For example, in Japanese Patent Laid-Open No. 8-88471, a circuit in which an electronic component is built in a concave cavity provided in an insulating substrate, and at least one of the front and back surfaces of the insulating substrate is electrically connected to the electronic component. Using a printed wiring board having a pattern and an electrode portion as a unit, a plurality of layers of these boards are laminated with an insulating resin interposed therebetween, and the insulating resin layer is cured by heat treatment to form a multilayer printed wiring board. It is disclosed.

The semiconductor element internally fixed in the concave cavity is electrically connected to a circuit pattern formed in a region including the cavity by a metal wire and is sealed in the cavity by a resin. In addition, a plurality of portions of the circuit pattern are configured as electrode portions, and a conductive resin layer is formed on the electrode portions.

Each printed wiring board formed in this way is
Insulating resin is adhered to each other while maintaining an insulating state to be integrally bonded to form a multi-layer. In this case, the electrode portion of each printed wiring board has a conductive resin on the electrode portion of the adjacent printed wiring board. The wiring patterns are electrically connected to each other, whereby the wiring patterns are electrically connected to each other.

[0005]

By the way, in such a conventional multilayer printed wiring board, a printed wiring board in which electronic components such as semiconductor elements are previously embedded in a concave cavity can be formed into a multilayer structure. Although it is possible to improve the mounting density of electronic parts with respect to the area, semiconductor elements are electrically connected to the circuit pattern formed in the cavity of each printed wiring board by the wire bonding method. And the electrical connection between the wiring patterns of the adjacent printed wiring boards is made through the conductive resin, which increases the distance between the semiconductor elements and increases the wiring resistance. There is.

Therefore, the present invention has been made in view of the above-mentioned problems of the prior art, and an object of the present invention is to achieve high density and thinness and to electrically connect with electronic parts such as semiconductor elements. You can connect securely,
Wiring drawn out from electronic parts is shortened as much as possible,
Another object of the present invention is to provide a semiconductor element built-in substrate having a structure in which the wiring can be laminated.

Another object of the present invention is to provide a multi-layer circuit board in which a plurality of semiconductor element-embedded substrates are laminated and integrated to enable high-density mounting and thinning of electronic components such as semiconductor elements. Especially.

[0008]

Therefore, as a result of earnest research for realizing the above-mentioned object, the inventor of the present invention has conceived the present invention having the following contents. That is,

(1) The semiconductor element-embedded substrate of the present invention is
A semiconductor element is accommodated in a recess or an opening provided in the insulating base material, a via hole is formed in the insulating base material, and the first surface of the insulating base material and the surface of the semiconductor element are covered, and A connection wiring pattern for providing an insulating layer having openings at positions corresponding to respective positions of the via hole and the electrode pad of the semiconductor element, and electrically connecting the via hole and the electrode pad along the surface of the insulating layer. And a conductive bump electrically connected to the via hole is formed on the second surface side of the insulating base material.

According to the above configuration (1), the semiconductor element can be stacked with other circuit boards in a state where the semiconductor element is accommodated in the recess or opening provided in the insulating base material. Manufacture of multi-layer circuit boards that can increase the density of boards and shorten the distance between semiconductor chips, reduce defects due to wiring resistance and inductance, and transmit electrical signals at high speed without delay Will be very advantageous to.

(2) Further, the multilayer circuit board of the present invention is manufactured by laminating a plurality of the semiconductor element-embedded substrates described in (1) above and integrating the laminated plurality of substrates. The electrode pad of the semiconductor element is electrically connected to the via hole through a connection wiring pattern formed along the surface of the resin insulating layer, and the via hole is provided with another semiconductor element via a conductive bump. It is characterized in that it is connected to the substrate.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION A semiconductor element-embedded substrate according to the present invention is characterized in that a semiconductor element such as an IC chip is accommodated in a recess or opening provided in the substrate and another semiconductor element is accommodated therein. It is suitable for manufacturing a multi-layer circuit board that can be laminated with other circuit boards and can quickly perform signal transmission between semiconductor elements.

That is, the semiconductor element-embedded substrate according to the present invention accommodates the semiconductor element in the recess or opening provided in the insulating base material, and fills the hole penetrating the insulating base material with a conductive substance. An insulating layer having a via hole formed therein to cover the first surface of the insulating base material and the surface of the semiconductor element and having openings at positions corresponding to respective positions of the via hole and the electrode pad of the semiconductor element. And a connection wiring pattern for electrically connecting the via hole and the electrode pad is formed along the surface of the insulating layer, and electrically connected to the via hole on the second surface side of the insulating base material. Conductive bumps are formed.

The insulating base material has a region for accommodating a semiconductor element, that is, a recess or an opening corresponding to the size of the semiconductor element, in a substantially central portion thereof, and extends outward from the accommodating region for the semiconductor element. In addition, a large number of fine through holes are formed in the peripheral portion, and via holes made of a conductive material are formed in the fine holes to electrically connect the electrode pads of the semiconductor element to the via holes. Is performed by the connection wiring pattern formed along the surface of the resin insulating layer formed so as to cover the first surface of the insulating base material and the electrode pad of the semiconductor element.

In addition, a conductive bump for electrical connection to another substrate adjacent to the via hole provided in the peripheral portion of the insulating base material is formed so as to protrude from the second surface of the insulating base material. To be done.

A substrate having such a semiconductor element built-in is laminated together with another substrate having another semiconductor element built-in and having substantially the same structure, and if necessary, heat-pressed via an adhesive to be integrated. Thus, a multi-layer circuit board is formed that can achieve higher density and higher functionality.

When a semiconductor element (logic IC) mainly having an arithmetic function and a semiconductor element (memory IC) mainly having a memory function are mixed in the multilayer circuit board, from the viewpoint of heat dissipation, for example, A circuit board having a semiconductor element (logic IC) mainly having a calculation function is arranged on the outer layer side, and a circuit board having a semiconductor element (memory IC) mainly having a memory function is arranged on the inner layer side. It is desirable that the heating is performed by stacking and pressing all at once.

In the above-mentioned laminated / integrated multilayer circuit board, the semiconductor element accommodated in the recess or opening provided in the insulating base material has an insulating substrate through the connection wiring pattern and the corresponding via hole. It is connected to the conductive bumps provided on the opposite side of the material, and the conductive bumps are connected to the connection wiring pattern or via hole pad of the adjacent circuit board. Problems caused by resistance and inductance are reduced, and as a result, electric signals can be transmitted at high speed without delay.

The insulating resin base material used in the circuit board of the present invention may be any organic insulating base material, specifically, aramid nonwoven fabric-epoxy resin base material, glass cloth epoxy resin base material, From aramid non-woven fabric-polyimide base material, bismaleimide triazine resin base material, rigid (hard) laminated base material selected from FR-4 and FR-5, or film such as polyphenylene ether (PPE) film and polyimide (PI) It is desirable to be one kind selected from the following flexible base materials.

In particular, since the hard insulating resin base material is formed of a completely cured resin material, not a semi-cured prepreg as in the past, by using such a material, for example, insulation When the copper foil is pressure-bonded onto the flexible base material by hot pressing, the final thickness of the insulating base material does not fluctuate due to the pressing pressure, so the misalignment of the via hole is minimized and the via hole Pad diameter can be reduced. Therefore, the wiring pitch can be reduced to improve the wiring density. Further, since the thickness of the base material can be kept substantially constant, it is easy to set the laser irradiation conditions when forming a filling via hole forming opening described later by laser processing.

The via-hole pad provided on the first surface of the above-mentioned insulating base material is obtained by attaching a metal foil such as a copper foil to the insulating base material via an appropriate resin adhesive, and as described below, After the steps, it is performed by performing an appropriate etching process.

Instead of sticking the copper foil on the insulating base material as described above, a single-sided copper-clad laminate in which the copper foil is stuck on the insulating base material in advance can be used. It may be matt-treated to improve its properties. This single-sided copper-clad laminate is a rigid substrate, is easy to handle, and is most advantageous in terms of cost, and the use thereof is the most preferable embodiment. Alternatively, the metal layer may be formed on the surface of the insulating resin substrate by vapor deposition of metal and then electrolytic plating.

The thickness of the insulating resin base material is 10 to 20.
0 μm, preferably 15 to 100 μm, 20 to 8
0 μm is optimal. If the thickness is less than these ranges, the strength is lowered and handling becomes difficult, and conversely, if it is too thick, it becomes difficult to form fine via holes and fill with a conductive material.

On the other hand, the thickness of the copper foil is 5 to 36 μm,
The thickness is preferably 8 to 30 μm, and more preferably 12 to 25 μm. The reason is that when the via hole forming opening is provided by laser processing, as will be described later, it penetrates if it is too thin, and conversely, if it is too thick, it is difficult to form a fine pattern by etching. .

The opening diameter of the via hole is 50 to 200 μm.
It is desirable that it is m. This is because if it is less than 50 μm, it becomes difficult to fill the inside of the opening with a conductive substance and the connection reliability becomes low, and if it exceeds 200 μm, it becomes difficult to achieve high density.

Before filling the inside of the opening with a conductive substance to form a via hole, a desmear treatment for removing resin residue remaining on the inner wall surface of the opening, for example, acid, permanganate, chromic acid, etc. From the viewpoint of securing the connection reliability, it is preferable to perform the treatment by a chemical removal method of immersing in the above oxidizer or the like, or a physical removal method using plasma discharge or corona discharge. Although the via hole forming opening is preferably formed by laser processing, the invention is not limited to this, and it is also possible to make a hole by a mechanical method such as drilling or punching.

As a method of forming a via hole by filling a conductive material in the opening subjected to the desmear treatment, there are a plating filling method by a plating treatment and a filling method by a conductive paste.

The plating filling can be performed by either electrolytic plating treatment or electroless plating treatment, but electrolytic plating treatment is preferable.

For electrolytic plating, for example, Sn, P
Although b, Ag, Au, Cu, Zn, In, Bi, solder, tin alloy, or the like can be used, electrolytic copper plating is particularly suitable.

Further, instead of the filling of the conductive material by the plating treatment, a method of filling the conductive paste, or a portion of the opening is filled by the electrolytic plating treatment or the electroless plating treatment, and the remaining portion is filled with the conductive paste. You can also do it.

The conductive paste includes silver, copper,
A conductive paste made of one or more kinds of metal particles selected from gold, nickel and various solders can be used.

Further, as the above-mentioned metal particles, those obtained by coating the surface of the metal particles with a different metal can also be used.
Specifically, metal particles obtained by coating the surfaces of copper particles with a noble metal such as gold or silver can be used. As the conductive paste, thermosetting resin such as epoxy resin or polyphenylene sulfide (PP
Organic conductive paste containing S) resin is desirable.

The via-hole pad corresponds to each via-hole opening position by filling the via-hole forming opening with a conductive material and then appropriately etching the copper foil attached to the insulating base material. It is desirable to provide it.

That is, after attaching a photosensitive dry film to the copper foil surface or applying a liquid photosensitive resist, a mask having a pad pattern having a diameter slightly larger than the via hole opening is placed, and exposure / development processing is performed. After forming the plating resist layer by doing so, it is formed by etching the copper foil in the portion where the etching resist is not formed.

During such etching treatment, the second surface of the insulating base material is covered with an etching protection film such as a polyethylene terephthalate film (PET film) so that the conductive metal filled in the via hole forming opening is not corroded. It is desirable to do so.

In the substrate with a built-in semiconductor element according to the present invention, the via hole is provided in the peripheral portion of the insulating base material, which extends outward from the central portion, while the semiconductor element is provided in the substantially central portion of the insulating base material. A recess or a through hole is formed as a mounting area for housing. Such a mounting area is provided according to the size and thickness of the semiconductor element,
The semiconductor element is housed in the recess or the through hole and fixed by a suitable adhesive.

In the semiconductor element housed in the recess or through hole of the insulating base material, the electrode pad of the semiconductor element is made of the insulating resin.
It is preferable to fix the via hole pad formed on the surface of the surface at a position substantially on the same plane as the surface, and by maintaining such a positional relationship, the insulating base material of With respect to the resin insulating layer provided to cover the first surface and the surface of the semiconductor element, the depths of the openings provided at the positions corresponding to the via hole pad and the electrode pad can be made constant. This is because it becomes easy to set exposure conditions or laser processing conditions when forming openings that reach the via hole pads and the electrode pads from the surface of the insulating layer.

The resin insulating layer provided to cover the first surface of the insulating base material and the surface of the semiconductor element is a thermosetting resin,
A thermoplastic resin or a composite of a thermosetting resin and a thermoplastic resin can be used.

As the thermosetting resin, epoxy resin, polyimide resin, phenol resin, thermosetting polyphenylene ether (PPE) or the like can be used.

As the thermoplastic resin, a phenoxy resin,
Fluorine resin such as polytetrafluoroethylene (PTFE),
Polyethylene terephthalate (PET), polysulfone (PSF), polyphenylene sulfide (PPS), thermoplastic polyphenylene ether (PPE), polyether sulfone (PES), polyetherimide (PEI), polyphenylene sulfone (PPES), tetrafluoride Ethylene hexafluoropropylene copolymer (FEP), tetrafluoroethylene perfluoroalkoxy copolymer (PFA), polyethylene naphthalate (PEN), polyether ether ketone (PEEK),
Polyolefin resin can be used.

As the composite of the thermosetting resin and the thermoplastic resin, epoxy resin-PES, epoxy resin-PSF, epoxy resin-PPS, epoxy resin-PPES and the like can be used.

In the present invention, the resin insulating layer covering the insulating resin base material containing the semiconductor element is a resin film which is softened under a predetermined heating condition, for example,
It is preferably formed from a resin film containing a thermosetting polyolefin resin or epoxy resin as a main component. As the polyolefin resin, a cycloolefin resin as one of them can be used. Since this cycloolefin resin has a low dielectric constant and dielectric loss tangent, signal propagation delays and errors are unlikely to occur even when a high frequency signal in the GHz band is used, and further, it has excellent mechanical properties such as rigidity. is there.

The cycloolefin resin is preferably a homopolymer or copolymer of a monomer consisting of 2-norbornene, 5-ethylidene-2-nobornene or a derivative thereof.

Examples of the above-mentioned derivative include those obtained by binding a cycloolefin such as 2-norbornene with an amino acid residue for forming a crosslink or a maleic acid-modified one. Examples of the monomer for synthesizing the copolymer include ethylene and propylene.
Among them, the thermosetting cycloolefin resin is preferable. By heating to form crosslinks, the rigidity becomes higher and the mechanical properties are improved.

The resin film containing such a polyolefin resin as a main component has a temperature of 50 to 250 ° C. and a pressure of 9.8 ×.
It is a preferred embodiment to form by hot pressing under conditions of 10 ^{4 to} 4.9 × 10 ⁶ Pa and a pressing time of 1 to 120 minutes.

In order to electrically connect the electrode pad of the semiconductor element and the via hole pad to the resin insulation layer,
Openings are formed from the surface of the resin insulating layer to the via hole pad and the electrode pad, respectively, and wiring for electrically connecting the via hole pad and the electrode pad along the surface of the resin insulating layer including the inner walls of the openings. A pattern is formed.

It is desirable that the opening be formed with an opening diameter corresponding to the sizes of the electrode pad and the via hole pad, respectively. When the resin insulating layer is formed of a photosensitive resin, the opening is formed by exposure and development processing, and when the resin insulating layer is formed of a thermosetting resin or a thermoplastic resin, the opening is formed by laser irradiation. At this time, as the laser light used, carbon dioxide laser, ultraviolet laser,
An excimer laser or the like is preferable.

After the opening is formed, the surface of the resin insulating layer may be roughened if necessary to improve the adhesion with the connection wiring pattern formed on the resin insulating layer.

When the above wiring pattern is formed by electroless plating, a catalyst nucleus for electroless plating is provided on the surface of the resin insulating layer. A general catalyst nucleus is a palladium-tin colloid. The substrate is immersed in this solution, dried, and heat-treated to fix the catalyst nuclei on the surface of the resin insulating layer.

Further, metal nuclei can be implanted into the resin surface by CVD, sputtering, or plasma to form catalyst nuclei. In this case, the metal nuclei are embedded in the resin surface, and plating is deposited around the metal nuclei to form the conductor layer. Therefore, it is difficult to roughen the resin or fluororesin (polytetrafluoroethylene etc.). Even if the resin has a poor adhesion between the resin and the conductor layer, the adhesion can be secured.

Examples of such metal nuclei include palladium,
At least one selected from silver, gold, platinum, titanium, copper and nickel is preferable. The amount of metal nuclei is 20μ
It is preferably g / cm ² or less. This is because if it exceeds this amount, the metal nuclei must be removed.

On the surface of the via hole pad, the surface of the electrode pad of the semiconductor element, and the surface of the resin insulating layer, a thin conductive layer forming a connection wiring pattern is formed. This thin conductor layer is formed by sputtering or electroless plating, and copper sputtering or electroless copper plating is preferable, respectively.

After laminating a photosensitive dry film on the thinned conductor layer, a plating resist is formed by exposure and development treatment, and further electrolytic plating treatment is performed to thicken the conductor layer portion. The openings corresponding to the via hole pads and the openings corresponding to the electrode pads of the semiconductor element are filled with plating. The electrolytic plating is preferably formed by electrolytic copper plating, and the thickness thereof is preferably 5 to 30 μm.

Further, after the plating resist is peeled off, the thin conductor layer below the plating resist is treated with an aqueous solution of sulfuric acid-hydrogen peroxide, an aqueous solution of persulfate such as ammonium persulfate, sodium persulfate, potassium persulfate, or chloride. The solution is dissolved and removed by an etching process that uses either an aqueous solution of ferric iron or cupric chloride as an etching solution.
A connection wiring pattern for electrically connecting the electrode pad of the IC and the via hole pad is formed along the surface of the resin insulating layer.

The connection wiring pattern is a fine line width pattern extending from the electrode pad of the semiconductor element fixed to the substantially central portion of the substrate toward the outer peripheral portion, and has a thickness of 5 to 30 μm. 12 μm is desirable
Is most preferable. The ratio (L / D) between the line width and the line distance is 50 μm / 50 μm to 100 μm / 1.
It is preferably 00 μm. Further, the pad formed on the wiring pattern has a diameter of 150 to 500 μm.
m is desirable, and 350 μm is particularly desirable.

The conductive bumps directly connected to the via holes exposed on the second surface of the insulating resin substrate are:
It is preferably formed by plating or printing a conductive paste.

The filling by the plating treatment can be carried out by either electrolytic plating treatment or electroless plating treatment, but electrolytic plating treatment is preferable. Examples of the electrolytic plating treatment include Sn, Pb, Ag, Au, C
Although u, Zn, In, Bi, solder, tin alloy, or the like can be used, electrolytic tin plating is most suitable in this embodiment.

The height of the conductive bumps is 3 to 3
The range of 0 μm is desirable. The reason is that if the thickness is less than 3 μm, variations in bump height cannot be tolerated due to bump deformation, and if it exceeds 30 μm, migration and whiskers increase.
In particular, it is most preferable that the height is 5 μm.

The conductive bumps are formed by screen printing using a metal mask instead of plating.
It can also be formed by printing a conductive paste on the via hole.

The bumps made of this conductive paste are preferably in a semi-cured state. This is because the conductive paste is hard even in a semi-cured state and can penetrate the softened organic adhesive layer during hot pressing. Further, it is because the contact area is increased due to deformation during hot pressing, which can reduce the conduction resistance and can correct the variation in the bump height.

In addition to this, for example, the conductive bumps can be formed by a method of printing a solder paste which is a low melting point metal, a method of performing solder plating, or a method of immersing in a solder melt.

As the low melting point metal, Pb—Sn based solder, Ag—Sn based solder, indium solder or the like can be used.

It is desirable that an adhesive layer is formed on the second surface of the insulating base material. This adhesive layer is formed by applying a resin on the entire second surface of the insulating base material and drying it. Therefore, it is desirable that it is in an uncured state.

The adhesive layer is preferably formed of an organic adhesive, and as the organic adhesive, an epoxy resin, a polyimide resin, a thermosetting polyphenylene ether (PPE) is used.
r), at least one resin selected from a composite resin of an epoxy resin and a thermoplastic resin, a composite resin of an epoxy resin and a silicone resin, and a BT resin. Here, as the solvent of the organic adhesive, NMP, D
MF, acetone, ethanol can be used.

A curtain coater, a spin coater, a roll coater, a spray coater, screen printing or the like can be used as a method for applying the uncured resin which is the organic adhesive. The thickness of the adhesive layer is preferably 5 to 50 μm.
The adhesive layer is preferably pre-cured because it is easy to handle.

A plurality of substrates according to the present invention in which a semiconductor element is housed in an insulating base material are laminated in a predetermined direction,
It is desirable to integrate them to form a multilayer circuit board, for example by hot pressing.

For stacking and unifying a plurality of substrates according to the present invention, for example, a substrate containing a semiconductor element (logic IC) mainly having an arithmetic function is arranged on the surface side,
On the inner layer side, it is desirable to arrange a substrate containing a semiconductor element (memory IC) mainly having a memory function, and stack those circuit boards in the same direction to integrate them.

The multilayer circuit board according to the present invention is a semiconductor element (memory IC) mainly having a memory function.
After stacking a plurality of semiconductor element-embedded boards in the same direction and integrating them, a part of the connection wiring pattern of the board on the outermost surface side of the integrated multilayer circuit board is formed in the form of a pad, It can also be manufactured by forming a solder bump on the pad and flip-mounting a semiconductor element (logic IC) mainly having an arithmetic function through the solder bump.

The lamination of the above-mentioned substrates is carried out while optically detecting the positioning holes provided in advance on each substrate by a CCD camera or the like and performing the alignment, and such a laminated body is formed.
While being heated at a temperature of 0 to 250 ° C, 0.5 to 5MP
By pressing with the pressure of a, all the circuit boards are integrated by one-time press molding. Particularly preferable heating temperature is in the range of 160 to 200 ° C.

For the lamination of the above-mentioned respective boards, after all the boards are integrated in a state in which they are oriented in the same direction, a solder body is supplied onto the pads of the connection wiring pattern of the circuit board of the outermost layer,
It is possible to mount electronic components other than the semiconductor element. In the case of such a laminated form, the conductive bump or the adhesive layer is not formed on the circuit board located at the bottom layer, and the conductive bump is formed immediately above the via hole after the lamination and integration. Is desirable.

Further, an adhesive is applied to the lowermost circuit board on which the conductive bumps are formed, a copper foil is pressure-bonded through the adhesive, and then an I / O wiring including a pad is appropriately etched. A pattern can be formed, for example, a nickel-gold layer is formed on the pad of the wiring pattern, and a solder ball or a T pin can be bonded on the gold-nickel layer to form a connection terminal to a mother board. .

Hereinafter, an example of a method for manufacturing a semiconductor element-embedded substrate and a multilayer circuit board according to the present invention will be specifically described with reference to the accompanying drawings. (1) In manufacturing a circuit board for mounting a semiconductor chip according to the present invention, one surface of an insulating resin base material 10 made of a glass cloth epoxy resin base material (hereinafter, referred to as “first insulating base material”).
The surface of which the copper foil 12 is attached is used as a starting material (see FIG. 1 (a)). As the insulating base material 10 and the copper foil 12, it is preferable to use a single-sided copper-clad laminate obtained by pressing a copper foil onto a glass cloth epoxy resin base material.

(2) The surface of the insulating base material 10 opposite to the first surface (hereinafter referred to as "second surface").
Then, a protective film 13 made of a polyethylene terephthalate (PET) film having an adhesive layer on the surface is attached.

(3) Next, laser irradiation is performed from above the PET film 13 attached to the second surface of the insulating base material 10 so as to penetrate the PET film 13 and penetrate the surface of the insulating base material 10. The opening 16 reaching the copper foil 12 is formed (see FIG. 1B). The opening 16 is an insulating base material 1.
It is formed in a peripheral region located outside the semiconductor chip mounting region occupying substantially the center of 0.

(4) Opening 16 formed in step (3)
In order to remove the resin residue remaining on the inner wall surface of the, dry desmear treatment using plasma discharge or corona discharge is performed.

(5) Next, the PET film 14 is attached to the first surface of the insulating resin substrate 10, and electrolytic copper plating is applied to the substrate which has been desmeared in (3) above. ,
The via hole 20 is formed (see FIG. 1 (c)).

(6) After that, the first insulating resin substrate 10
The PET film 14 attached to the surface of the film is peeled off, and PE as an etching protection film is formed on the second surface.
After attaching the T film 15, unnecessary portions of the copper foil 12 are removed by etching to form the via hole pads 40.

In this processing step, first, the copper foil 12
After applying a photosensitive dry film resist covering
The resist layer 24 is exposed and developed to form an etching resist layer 24 (see FIG. 1D), and the copper foil in a portion where the etching resist is not formed is etched to form a via hole pad 40 having a predetermined pattern (see FIG. 1E). )reference). The via hole pad 40 has an inner diameter substantially similar to the via hole diameter, but the outer diameter is preferably formed in the range of 50 to 250 μm.

(7) Next, the second step of the insulating resin substrate 10
After the PET film 15 attached to the surface of the is peeled off, an opening (through hole) 25 slightly larger in size than the semiconductor element 26 is formed by laser irradiation or punching in the substantially central portion of the insulating base material. The semiconductor element 26 is fitted with the adhesive applied to the inner wall of the opening 25, and the semiconductor element 26 is bonded and fixed to the inner wall of the opening 25. At that time, the surface of the electrode pad 27 of the semiconductor element 26 is housed so as to be on the same plane as the surface of the via hole pad 40 formed on the first surface of the insulating resin (FIG. 1 (f)). reference).

(8) A resin film that softens under a predetermined heating condition, for example, a thermosetting polyolefin-based resin, on the first surface of the insulating base material in which the semiconductor element 26 is housed and fixed. Alternatively, the resin insulating layer 30 is formed from a resin film containing an epoxy resin as a main component (see FIG. 2A).

As the polyolefin resin, a cycloolefin resin as one of them can be used. Since this cycloolefin resin has a low dielectric constant and dielectric loss tangent, signal propagation delays and errors are unlikely to occur even when a high frequency signal in the GHz band is used, and further, it has excellent mechanical properties such as rigidity. is there. A resin film containing such a polyolefin resin as a main component is heated at a temperature of 50 to
250 ° C., pressure 9.8 × 10 ^{4 to} 4.9 × 10 ⁶ Pa,
The resin insulating layer 30 is formed by hot pressing under a pressing time of 1 to 120 minutes.

(9) On the surface of the resin insulating layer 30 formed in (8) above, openings 32 and 34 reaching the via hole pad 40 and the electrode pad 27 from the surface of the resin insulating layer are formed by laser irradiation, respectively ( See Fig. 2 (b).

(10) After forming metal nuclei on the surface of the insulating resin substrate 10 on which the resin insulating layer 30 is formed by CVD, sputtering or plasma to form catalyst nuclei, the surface of the via hole pad 40, A thin conductor layer (not shown) is formed on the surface of the electrode pad 27 of the semiconductor element 26 and the surface of the resin insulating layer 30 by electroless copper plating. The thickness of this electroless copper plating is 0.1 to 5 μm, and more preferably 0.5 to 3 μm.

(11) After laminating a photosensitive dry film on the thin conductor layer, a plating resist is formed by exposure and development, and electrolytic copper plating is further performed to thicken the conductor layer portion. At the same time, the opening 32 corresponding to the via hole pad 40 and the opening 34 corresponding to the electrode pad 27 of the semiconductor element 26 are filled with electrolytic copper plating.

(12) Further, after the plating resist is peeled off, the thinned conductor layer under the plating resist is dissolved and removed by an etching process to electrically connect the electrode pad 27 of the memory IC 26 and the via hole pad 40. The wiring pattern 42 is formed along the surface of the resin insulating layer 30 (see FIG. 2C).

(13) The connection wiring pattern 42 in (12) above.
After the PET film 17 is attached to the first surface of the insulative base material 10 on which is formed, electrolytic tin plating treatment is performed,
The conductive bumps 44 are located directly above the via holes 20.
Are formed (see FIG. 2 (e)).

(14) If necessary, on the second surface of the insulating base material 10 on which the conductive bumps 44 are formed in (13) above,
An adhesive made of epoxy resin is applied and dried to leave an uncured state (see FIG. 2 (f)).

The substrate with a built-in semiconductor element according to the present invention is manufactured according to the steps (1) to (13) described above, but after the adhesive layer 46 in the uncured state is formed, a plurality of them are predetermined. The multilayer circuit boards 50 are manufactured by stacking them in the same direction and integrating them by, for example, a heating press.

Four semiconductor element-embedded substrates 50A, 50
When B, 50C, and 50D are sequentially stacked in the same direction, for example, the logic IC is accommodated and fixed in the uppermost semiconductor element-embedded substrate 50D, while the semiconductor element-embedded substrates 50A to 50C on the inner layer side are stacked. Holds and fixes the memory IC. Further, the lowermost semiconductor element-embedded substrate 50
In A, the conductive bumps 44 and the adhesive layer 46 are not formed, and after the lamination and heat pressing, the process according to the above (13) is performed to form the conductive bumps 44.

FIG. 3 shows a multilayer circuit board obtained by integrally laminating four layers of laminated body by one-time hot press molding. At this time, by heating at the same time as applying pressure, the adhesive layer provided on each circuit board is cured, and the semiconductor element-embedded substrate 5
Strong adhesion is performed between 0A and 50D. A vacuum hot press was used as the hot press.

The conductive bumps 44 are formed on the via holes 20 of the lowermost circuit board 50A constituting the multilayer circuit board integrally formed as described above. At this time, the PET film 19 is attached to the surface of the uppermost circuit board 50D.

In place of the adhesive layer 46 previously formed on the second surface of the insulating resin base material 10, the adhesive is applied to an appropriate place at the stage of multilayering after each circuit board is manufactured. Can be applied to form an adhesive layer made of an uncured resin in a dried state.

In the above-described embodiment, four semiconductor element-embedded substrates 50A to 50D are sequentially laminated to form four layers, but the present invention is not limited to such an example, and the characteristics of the semiconductor element to be mounted are not limited thereto. It is needless to say that the present invention can be applied to the manufacture of a multilayer circuit board having three layers or less or five layers or more, depending on the capacity, thickness, etc. or the type, thickness, etc. of the insulating resin substrate.

[0094]

EXAMPLES (Example 1) (1) A single-sided copper-clad laminate obtained by laminating a prepreg, which is a B stage made by crushing an epoxy resin in a glass cloth, and a copper foil, and heat-pressing the substrate is used as a substrate. Used as. The insulating resin substrate 10 has a thickness of 50 μm, and the copper foil 1
The thickness of 2 was 18 μm (see FIG. 1 (a)).

(2) PE having a thickness of 22 μm is formed on the first surface of the insulating base material 10 to which the copper foil 12 is attached.
Attach the T film 13. The PET film is composed of an adhesive layer having a thickness of 10 μm and a PET film base having a thickness of 12 μm.

(3) Next, a pulse oscillation type carbon dioxide laser is irradiated from above the PET film 13 to form the via hole forming opening 16, and then the resin remaining on the inner wall of the opening 16 is removed. A plasma cleaning process was performed (see FIG. 1 (b)).

(4) Next, the PET film 13 is peeled off from the second surface of the insulating resin base material 10 and the PET film 14 is attached to the first surface, followed by electrolytic copper plating with a commercially available electrolytic plating aqueous solution. After processing, the inside of the opening 16 is filled with electrolytic copper plating, and the diameter is 150 μm and the pitch is 5
A via hole 20 of 00 μm was formed (see FIG. 1 (c)).

(5) Next, after peeling the PET film 14 attached to the first surface of the insulating base material 10, an etching resist layer 24 is formed on the copper foil surface (see FIG. 1 (d)).
The copper foil of the portion where the etching resist is not formed is treated with an etching solution of cupric chloride to form a via hole pad 40 having a diameter of 250 μm at a position corresponding to the via hole 20.

(6) In the substantially central portion of the insulating base material 10,
An opening 25 (through hole) slightly larger in size than the semiconductor element 26 is formed by using the same laser processing apparatus as in (3) above.
Is formed (see FIG. 1 (e)), the semiconductor element 26 is fitted to the inner wall of the opening 25 with an adhesive made of epoxy resin applied, and the semiconductor element 26 is bonded to the inner wall of the opening.
It was fixed (see Fig. 1 (f)). At that time, the surface of the electrode pad 27 of the semiconductor element 26 was fixed so that it was on the same plane as the surface of the via hole pad 40 formed on the first surface of the insulating base material 10.

(7) Next, on the surface of the insulating base material 10 on which the via hole pad 40 is formed, a thermosetting polyolefin resin sheet having a thickness of 50 μm is heated to a temperature of 50 to 180 ° C. and 9.8 ×. A resin insulation layer 30 made of a polyolefin resin is laminated by being hot pressed at a pressure of 10 ³ Pa.
Was provided (see FIG. 2 (a)).

(8) Laser irradiation is performed from the surface side of the resin insulating layer 30 made of a polyolefin resin to provide an opening 32 reaching the via hole pad 40 and an opening 34 reaching the electrode pad 27 of the semiconductor element 26 ( Figure 2
(See (b)).

Further, the surface of the desmear and the polyolefin resin insulating layer was modified by plasma treatment of CF ₄ and oxygen mixed gas. Due to this modification, O
Hydrophilic groups such as H group, carbonyl group and COOH group were confirmed.

(9) Further, sputtering is performed using copper as a target to form a conductor on the surface of the resin insulating layer 30 made of the polyolefin resin formed in (8) above and the inner wall surfaces of the openings 32 and 34. A copper sputter layer (not shown) having a thickness of 0.1 μm was formed as a base layer.

(10) On the copper sputtered layer formed in (9) above, a photosensitive dry film was used to form a film having a thickness of 15
A μm plating resist (not shown) was provided.

(11) Further, electrolytic copper plating treatment is performed according to the treatment of (4) above to form electrolytic copper plating having a thickness of 15 μm, and a conductor layer to be the connection wiring pattern 42 is thickened. The openings 32 and 34 were plating filled.

(12) Next, after removing the plating resist formed in (10) above, the copper sputtered layer and electrolytic copper plating under the plating resist are removed by dissolution,
Wiring pattern 4 consisting of electrolytic copper plating and copper sputter layer
Form 2. As a result, the electrode pad 27 of the semiconductor element 26 and the via hole 20 are electrically connected (see FIG. 2 (c)).

(13) Further, electrolytic tin plating treatment is performed with a commercially available electrolytic plating solution, and electrolytic tin plating is performed on the via holes 20 to have a diameter of 150 μm and a height of 5 μm.
The conductive bumps 44 having a pitch of m and a pitch of 500 μm were formed (see FIG. 2E). At this time, the PET film 17 is attached to the first surface of the insulating base material 10 (see FIG. 2 (d)).

(14) An adhesive agent made of epoxy resin is applied to the second surface of the insulating base material 10 on which the conductive bumps 44 are formed in (13) above, and the adhesive agent layer 4 is dried.
6 was formed (see FIG. 2 (f)).

(15) Next, the above (1) to (14)
According to the process of three semiconductor element built-in substrate 50B ~
50D is manufactured, and one semiconductor element-embedded substrate 50A is manufactured according to the steps (1) to (12), and these four substrates are integrated into the semiconductor element-embedded substrate 50A.
Are laminated in the same direction so that they are located in the lowermost layer, heated at a temperature of 180 ° C. and pressed at a pressure of 2 MPa to integrate all circuit boards by one-time press molding (see FIG. 3). ).

(16) Further, in the above-mentioned integrated circuit board, the PET film 19 as a protective film is attached to the surface of the uppermost board 50D, and the above (1)
By performing the process according to 3), the conductive bumps 44 are formed on the via holes 20 of the substrate 50A of the lowermost layer to manufacture a multilayer circuit board (see FIG. 4).

(Example 2) (1) After manufacturing four semiconductor element-embedded substrates 50A to 50D according to the steps (1) to (13) of Example 1, the four semiconductor element-embedded substrates are formed. Among the substrates, a resin adhesive is applied to the surface of the substrate 50A to be arranged as the lowermost layer on the side of the conductive bumps 44, and an adhesive layer which is dried and semi-cured is provided, and these substrates are oriented in the same direction. And the conductive bumps 2 of the substrate located at the bottom layer
The copper foil 60 is arranged so as to face the surface on the second side, and the four substrates and the copper foil 60 are bonded to each other to integrate the four semiconductor element-embedded substrates and the copper foil 60 (see FIG. 5). ).

(2) A PET film is attached to the surface of the uppermost substrate 50D of the above integrated substrate, and a position corresponding to the conductive bump 44 is provided on the surface of the copper foil 60 attached to the lowermost substrate 50A. After forming an etching resist layer on the substrate, an etching process is performed to form a circular connecting pad 62 electrically connected to the conductive bump 44.

(3) After forming the solder resist layer 64 so as to cover the connection pad 62 formed in (2) above, an opening 66 is provided at a position corresponding to the connection pad 62, and the opening 66 is provided in the opening 66. A nickel-gold layer (not shown) is formed on the exposed pad 62, and solder balls 68 connected to the terminals of the motherboard are arranged on the nickel-gold layer to form a multi-layer having a BGA structure. A circuit board was produced (see FIG. 6).

Example 3 A conductive bump 44 having a diameter of 80 μm, a height of 30 μm and a pitch of 600 μm was formed by printing using a conductive paste made of tin-silver based solder which is a low melting point metal. The same process as in Example 1 was performed to manufacture a multilayer circuit board.

[0115]

As described above, according to the present invention,
Since the distance between the semiconductor elements housed and fixed on each board can be shortened and problems caused by wiring resistance and inductance can be reduced, electrical signals can be transmitted at high speed without delay, and wiring is also possible. It is possible to achieve high density and high functionality of the substrate.

[Brief description of drawings]

1A to 1F are views showing a part of a manufacturing process of a semiconductor device-embedded substrate according to a first embodiment of the present invention.

2A to 2F are views showing a part of the manufacturing process of the semiconductor element embedded substrate according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a part of the manufacturing process of the multilayer circuit board in which the semiconductor element built-in substrates according to the first embodiment of the present invention are laminated.

FIG. 4 is a diagram showing a part of the manufacturing process of the multilayer circuit board in which the semiconductor element built-in substrates according to the first embodiment of the present invention are laminated.

FIG. 5 is a diagram showing a part of the manufacturing process of the multilayer circuit board in which the semiconductor element built-in substrates according to the second embodiment of the present invention are laminated.

FIG. 6 is a diagram showing a part of the manufacturing process of the multilayer circuit board in which the semiconductor element built-in substrates according to the second embodiment of the present invention are laminated.

[Explanation of symbols]

10 Insulating base material 12 Copper foil 13 PET film 14 PET film 16 Aperture forming openings 20 Filled via holes 24 Etching resist layer 25 Semiconductor element housing opening 26 Semiconductor devices 27 electrode pad 30 resin insulation layer 32, 34 openings 42 Connection wiring pattern 44 Conductive bump 46 Adhesive layer 50A-50D Semiconductor element built-in substrate 62 connection pad 64 Solder resist layer 66 openings 68 Solder ball

Claims (2)

[Claims] 1. An insulating base material, a semiconductor element housed in a recess or an opening provided in the insulating base material, a via hole provided in the insulating base material, and an insulating base material. An insulating layer which covers the first surface and the surface of the semiconductor element and has openings at positions corresponding to the positions of the via hole and the electrode pad of the semiconductor element; and the surface of the insulating layer. A connection wiring pattern that is formed along the line and electrically connects the via hole and the electrode pad,
A semiconductor element-embedded substrate having a conductive bump provided on the second surface side of the insulating base material and electrically connected to the via hole. 2. An insulating base material, a semiconductor element accommodated in a recess or an opening provided in the insulating base material, a via hole provided in the insulating base material, and an insulating base material of the insulating base material. An insulating layer which covers the first surface and the surface of the semiconductor element and has openings at positions corresponding to the positions of the via hole and the electrode pad of the semiconductor element; and the surface of the insulating layer. A wiring pattern formed along the wiring pattern for electrically connecting the via hole and the electrode pad, and a conductive bump provided on the second surface side of the insulating base material and electrically connected to the via hole. A multi-layer circuit board in which a plurality of semiconductor element-embedded boards each having and are laminated and integrated.