JP2003203924A - Method for manufacturing field effect transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the number of times of patterning processes and the number of photomasks, and to improve throughput and yield in a field effect transistor, such as a thin film transistor. <P>SOLUTION: An oxidized film, formed by processing the surface of a crystalline semiconductor by ozonous water or hydrogen peroxide-water is made as an etching stopper. The gate electrode, the source electrode and the drain electrode of the field effect transistor are formed simultaneously from the same start film only with one patterning by using one photomask. The gate electrode, the source electrode and the drain electrode are formed, and they are heated for prescribed time at 800°C or higher. Thus, the contact resistance of the source electrode and the drain electrode with the crystalline semiconductor is reduced, and electrical connection is improved. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor such as a thin film transistor, a method of manufacturing the same, a method of manufacturing a display device using the field effect transistor, and a display device thereof. In particular, the present invention relates to a field effect transistor such as a thin film transistor and the like, in which a gate electrode, a source electrode and a drain electrode of a field effect transistor such as a thin film transistor are simultaneously formed by patterning the same starting film using a photolithography method. .

[0002]

2. Description of the Related Art An example of a conventional thin film transistor manufacturing process is shown below. An amorphous silicon film is formed above the glass substrate, the amorphous silicon film is crystallized to form a crystalline silicon film, the crystalline silicon film is patterned into islands, and gate insulation is provided on the islands of crystalline silicon film. Forming a film, patterning the conductive film formed on the gate insulating film to form a gate electrode,
Using the gate electrode as a mask, impurities are introduced into the island-shaped crystalline silicon film by an ion doping method to form a source region and a drain region, and a first region is formed on the gate electrode and the island-shaped crystalline silicon film. An interlayer insulating film is formed, a hole (contact hole) reaching the source region and the drain region is formed in the first interlayer insulating film by patterning, and then a conductive film connected to the source region and the drain region is formed. It is manufactured through a process of patterning this to form a source electrode and a drain electrode. The above process is known (for example, refer to Patent Document 1). When the thin film transistor manufactured by this known technique is applied to a pixel portion of a display device, a second interlayer insulating film is formed on a source electrode and a drain electrode, and the source electrode or the drain electrode is formed on the second interlayer insulating film. The holes reaching to are opened by patterning, a transparent conductive film is further formed, and this is patterned to form pixel electrodes.

[0003]

[Patent Document 1] Japanese Patent Laid-Open No. 8-330602 (FIG. 1)
(A) to (F), Example 1)

As described above, in the conventional process, the source electrode and the drain electrode are formed after the gate electrode is formed. That is, the formation of the gate electrode and the formation of the source electrode and the drain electrode are usually performed separately. Therefore, in the above-mentioned conventional process, the patterning process until the source electrode and the drain electrode are formed is four times, and the number of photomasks used at that time is four. The patterning process until the pixel electrode is formed is increased by 2 times to 6 times, and the number of photomasks used at that time is 6.

[0005]

At present, in the manufacture of field effect transistors such as thin film transistors and the manufacture of display devices using the field effect transistors,
There is a strong demand for improvement in throughput (quantity that can be processed per unit time) and improvement in yield (ratio of non-defective products to the number of products input to the manufacturing line).

However, since the number of steps is large in the conventional process, it is not easy to reduce the time required for manufacturing the field effect transistor and the display device, and it is difficult to realize the improvement in yield. For example, the position of a fine pattern formed in a subsequent patterning process may be displaced due to contraction of the substrate or other causes. The positional deviation of the pattern thus generated causes a defective product and reduces the yield. For example, since the source electrode and the drain electrode are formed, when forming a hole (contact hole) by patterning, the position of the hole deviates from the source region and the drain region, which originally have to be opened. is there.

Even if the pattern position is misaligned by one patterning process, the misalignment may be slight and within an allowable range, and may not be a degree that adversely affects the operation of the completed display device. However, by repeating the number of patterning steps, a slight misalignment of the pattern position is amplified and becomes large, and the probability of defective products is increased.

An object of the present invention is to improve the yield by reducing the number of patterning steps, reduce the number of photomasks, reduce the number of steps by combining a plurality of steps into one step, and reduce the manufacturing time. It is to shorten.

[0009]

According to the present invention, the surface of a crystalline semiconductor is oxidized with an aqueous solution of an oxidant, for example, an aqueous solution of ozone or an aqueous solution of hydrogen peroxide to form an oxide film on the surface of the crystalline semiconductor. It is characterized in that the gate electrode, the source electrode and the drain electrode of the field effect transistor are simultaneously formed from the same starting film using the oxide film as an etching stopper. Further, after the gate electrode, the source electrode, and the drain electrode are formed, they are heated in an inert gas at 800 ° C. or higher for a predetermined time. The inert gas is a rare gas such as argon or nitrogen.

Further, the present invention is a method for manufacturing a field effect transistor, wherein a first insulating film is formed on a crystalline semiconductor, the first insulating film is patterned, and a part of the crystalline semiconductor is formed. A gate insulating film is formed on the gate insulating film, and the surface of the crystalline semiconductor is oxidized by using an aqueous solution of an oxidizing agent, for example, an aqueous solution of ozone or an aqueous solution of hydrogen peroxide to form an oxide film. A conductive film having a semiconductor layer containing N-type impurities is formed on an insulating film, and the conductive film is patterned to simultaneously form a gate electrode, a source electrode, and a drain electrode without etching the crystalline semiconductor. Using the gate electrode, the source electrode, and the drain electrode as a mask, N is added to the crystalline semiconductor.
Type impurities are introduced. At this point, an oxide film exists between the source and drain electrodes and the crystalline semiconductor, and the oxide film has SiO _x (0 <X <2) and SiO ₂ . After that, the crystalline semiconductor, the oxide film, the gate insulating film, the gate electrode, the source electrode, and the drain electrode are placed in an inert gas such as nitrogen at 800 ° C.
Heat at 50 ° C. for 30 minutes to 4 hours. By the heating, the N-type impurities contained in the source electrode and the drain electrode can be diffused into the crystalline semiconductor and the N-type impurities can be activated. Further, the heating reduces the contact resistance between the source electrode and the crystalline semiconductor and the contact resistance between the drain electrode and the crystalline semiconductor.
Further, a semiconductor layer containing P-type impurities may be used instead of the semiconductor layer containing N-type impurities, and P-type impurities may be introduced instead of introducing N-type impurities into the crystalline semiconductor.

In the present invention, an oxide film formed by oxidizing the surface of a crystalline semiconductor with an aqueous solution of an oxidant, for example, an aqueous solution of ozone or an aqueous solution of hydrogen peroxide, includes a conductive film, a gate electrode, a source electrode, and Since it serves as an etching stopper when simultaneously forming the drain electrode,
Even the crystalline semiconductor is not etched. It is known that ozone and hydrogen peroxide used when forming the oxide film are water-soluble and are oxidizing agents that oxidize other substances. Further, as the conductive film, a material having a melting point higher than the temperature of heat treatment must be used. N
On the crystalline silicon containing type impurities, copper, palladium,
Any metal having a melting point of 800 ° C. or higher, such as chromium, cobalt, titanium, molybdenum, niobium, tantalum, or tungsten, or metal silicide such as cobalt silicide, titanium silicide, molybdenum silicide, niobium silicide, tantalum silicide, or tungsten silicide. May be laminated to form the conductive film. Further, the structure may be combined with a metal nitride such as titanium nitride, tantalum nitride, or tungsten nitride.

In the present invention, the crystalline semiconductor is a single crystal or polycrystalline semiconductor and is not limited to a thin film. When a thin film is used as the crystalline semiconductor, it is possible to use a semiconductor film formed above the substrate and crystallized to form a crystalline semiconductor film. In the present invention, 800 ° C-
Since heat treatment is performed at a temperature of 1050 ° C., a substrate that can be used must be a substrate that is not deformed by heat treatment, such as a quartz substrate, a silicon substrate, or a stainless steel substrate.

In the present invention, before forming a conductive film for forming a gate electrode, a source electrode, and a drain electrode, an N-type impurity is introduced into a crystalline semiconductor using a gate insulating film as a mask, After forming the source electrode and the drain electrode, a method of introducing an N-type impurity into the crystalline semiconductor again and performing heat treatment at a temperature of 800 ° C. to 1050 ° C. can be used. In this case, P-type impurities may be introduced instead of N-type impurities. Further, in this case, as a material forming the conductive film,
It is not always necessary to use a semiconductor containing N-type impurities or P-type impurities.

The method for manufacturing a field effect transistor described above can be adopted for manufacturing a display device using the field effect transistor. Examples of the display device include an active matrix driving liquid crystal display and an active matrix driving display using a light emitting element.

Further, the present invention is a field effect transistor manufactured by using the above method for manufacturing a field effect transistor, wherein the field effect transistor includes an island-shaped crystalline semiconductor film formed above a substrate. A gate insulating film formed on a part of the island-shaped crystalline semiconductor film, a source electrode and a drain electrode formed on the island-shaped crystalline semiconductor film, and a gate insulating film formed on the gate insulating film. The island-shaped crystalline semiconductor film has a source region, a drain region, a low-concentration impurity region (LDD region), and a channel region, and is provided between the source electrode and the source region and the drain. S between the electrode and the drain region
iO _x (0 <X <2).

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) FIG. 1 (A) to (E) and FIG. 2 (A) to Embodiment 1 of the present invention.
This will be described with reference to (E) and FIGS. 10 (A) and 10 (B).

As shown in FIG. 1A, a first insulating film 102 is formed over the substrate 101 to have a thickness of 100 to 1000 nm. As the first insulating film 102, a silicon nitride oxide film formed by a CVD method using SiH ₄ , N ₂ O, and NH ₃ as a raw material, and a CVD method using SiH ₄ and N ₂ O as a raw material Any of a silicon oxynitride film, a silicon oxide film, a silicon oxide film containing nitrogen, and a silicon nitride film may be formed, and two or more kinds of these films may be combined and formed to be stacked. Also, the substrate 101
For, a quartz substrate, a silicon substrate, or a stainless substrate is used. When the quartz substrate is used, the first insulating film 102 may not be formed.

Next, a semiconductor film 103 is formed to a thickness of 30 to 80 nm on the substrate 101 or the first insulating film 102. The semiconductor film 103 may be a silicon film, a germanium film, or a film containing silicon and germanium. The thickness of the semiconductor film is 30 nm to 8
As the thickness is reduced within the range of 0 nm, the off current of the thin film transistor is effectively reduced.

Next, the semiconductor film 103 is crystallized by a known method. As means for crystallization, solid phase growth by heat treatment in an electric furnace, laser crystallization by irradiation with pulsed or continuous wave gas laser or solid laser, RTA (Rapid Thermal Annea)
ling) may be used. Further, when a method of adding an element that promotes crystallization of the semiconductor film, such as nickel, to the semiconductor film 103 during the solid phase growth and performing heat treatment is used, the heating temperature can be lowered and the heating time can be shortened. This is effective because it can be done, but after crystallization, the semiconductor film 10
The nickel contained in 3 must be gettered and removed as much as possible.

Currently, as a means for crystallizing a semiconductor film,
Laser crystallization has been actively studied, and a laser used for crystallization will be described in detail below.

Examples of gas lasers include excimer lasers, Ar lasers, and Kr lasers, and examples of solid-state lasers include YAG lasers, glass lasers, ruby lasers, alexandrite lasers, and Ti: sapphire lasers.

As the solid-state laser, Cr, Nd, E
A laser using crystals of YAG, YVO ₄ , YLF, YAlO ₃ or the like doped with r, Ho, Ce, Co, Ti or Tm is applied. The fundamental wave of the laser is
Depending on the material to be doped, laser light having a fundamental wave of about 1 μm can be obtained. The harmonic wave with respect to the fundamental wave can be obtained by using a non-linear optical element.

In order to obtain crystals with a large grain size when crystallizing a semiconductor film, a solid-state laser capable of continuous oscillation is used, and the second harmonic, the third harmonic, and the fourth harmonic of the fundamental wave are applied. Preferably. Typically, the second harmonic (532n) of an Nd: YVO ₄ laser (fundamental wave 1064nm) is used.
m), the third harmonic (355 nm) is applied.

Laser light emitted from a continuous oscillation YVO ₄ laser having an output of 10 W is converted into a harmonic by a non-linear optical element. There is also a method in which a YVO ₄ crystal and a non-linear optical element are put in a resonator to emit a higher harmonic wave.
Then, it is preferably shaped into a rectangular or elliptical laser beam on the irradiation surface by an optical system, and the object to be processed is irradiated. Energy density at this time is 0.1-100M
W / cm ² (preferably 0.1-10 MW / cm ² )
is necessary. Then, the semiconductor film is moved relative to the laser light at a speed of about 0.5 to 2000 cm / s for irradiation.

The semiconductor film 103 thus crystallized is
As shown in FIG. 1B, patterning is performed by a photolithography method to form an island-shaped crystalline semiconductor film 104. With this patterning, the first photomask is used.

Next, as shown in FIG. 1C, the substrate 1
01 or the first insulating film 102 and the crystalline semiconductor film 104, the second insulating film 105 is formed with a thickness of 20 to 130 nm. As the second insulating film 105, SiH
It may be any of a silicon oxynitride film, a silicon oxide film, a silicon oxide film containing nitrogen, and a silicon nitride film formed by a CVD method using ₄ and N ₂ O as raw materials, and a combination of two or more of these films. It may be formed by overlapping. Then, as shown in FIG. 1D, the second insulating film 105 is patterned by a photolithography method so that part of the surface of the crystalline semiconductor film 104 is exposed and the island-shaped second insulating film 105 to be a gate insulating film is formed. The insulating film 106 is formed. A second photomask is used in this patterning. Note that before patterning the second insulating film 105, a P-type impurity such as boron may be introduced into the entire crystalline semiconductor film 104. This is a known method that is called so-called channel doping and is performed to introduce a P-type impurity into a portion that will later become a channel region.

Next, the native oxide film is removed from the surface of the island-shaped crystalline semiconductor film 104 exposed when the second insulating film 106 is formed, and then the surface is oxidized. As a result, as shown in FIG.
07 is formed. The oxide film 107 is formed by applying an aqueous solution of an oxidant to the surface to be oxidized by spin coating. Specifically, the substrate 1 on which at least the crystalline semiconductor film 104 and the second insulating film 106 are formed
While rotating 01, an aqueous solution of ozone (O ₃ ) (hereinafter, referred to as ozone water in the present specification) is continuously flowed on the surface of the crystalline semiconductor film 104 for 30 to 120 seconds at room temperature.
Ozone is a gas at room temperature and pressure, is water-soluble, and exhibits a strong oxidizing action. The water used as the solvent of the ozone water is pure water from which fine dust and impurities are removed, and the concentration of the ozone water is 8 to 15 mg / l. After that, the surface is washed with pure water to wash away the ozone water, and then the substrate 101 is rotated and dried while blowing nitrogen.

Oxide film 107 thus formed
Since it is extremely thin, it is not easy to measure its accurate film thickness, but it is in the range of 0.7 to 2.0 nm. It should be noted that even if the time (treatment time) for flowing the ozone water is changed, there is no great change in the film thickness of the formed oxide film.
Between 0 to 120 seconds, the thickness of the oxide film is 0.7 to 2.0.
It is in the range of nm.

In order to investigate the composition of the oxide film formed by ozone water, the oxide film formed by flowing 14 mg / l ozone water on the surface ((100) surface) of the silicon wafer for 60 seconds at room temperature was tested. ESCA (Electro Micro) that can specify the chemical bond state of elements
n Spectroscopy for Chemica
l Analysis) or XPS (X-ray P)
photoelectron Spectroscop
The spectrum of Si2p was measured with an analyzer called y). As a result, the binding energy is 96 to 106e.
Two peaks were seen in the V range. One is the Si ⁴⁺ peak and the other is the Si peak. The peak of Si is detected from the silicon wafer because the oxide film is thin. Si ⁴⁺ peaks are Si ¹⁺ , S
Since it contains small peaks of i ²⁺ and Si ³⁺ ,
Waveform decomposition by Gaussian function and Lorentz function was performed.
Then, the oxidation state of silicon was analyzed based on these peak shapes. As a result, when the total of Si ¹⁺ , Si ²⁺ , Si ³⁺ , and Si ⁴⁺ is 100%, Si ¹⁺ is 8.
8%, Si ²⁺ was 8.8%, Si ³⁺ was 6.4%, and Si ⁴⁺ was 76.0%. Where Si ¹⁺ , Si ²⁺ ,
And Si ³⁺ is called suboxide. Suboxide means a state in which silicon does not sufficiently react with oxygen and remains partially bonded to silicon. Si ⁴⁺
Is 100% and the suboxide is 0%, it can be said that the oxide film is sufficiently oxidized and made of stable SiO ₂ . Regarding the oxide film formed on the surface of the silicon wafer by ozone water, SiO _x (0 <X <
2) and a silicon oxide film composed of SiO ₂ . The thickness of this oxide film was measured by an analyzer called spectroscopic ellipsometry and found to be 0.81 nm.

As a comparative example, T on a silicon wafer
A silicon oxide film formed by a CVD method using Si (OC ₂ H ₅ ) ₄ and O ₂ called EOS as a raw material is
The Si2p spectrum was measured by SCA. Then, the same analysis as for the oxide film formed by ozone water was performed.
As a result, ^assuming that the total of Si ¹⁺ , Si ²⁺ , Si ³⁺ , and Si ⁴⁺ is 100%, Si ¹⁺ is 1.8%, Si ²⁺ is 0.9%, and Si ³⁺ is The proportion was 4.6% and Si ⁴⁺ was 92.7%. That is, it was found that the silicon oxide film formed by the CVD method had a higher proportion of SiO ₂ than the oxide film formed by ozone water.

Next, as shown in FIG. 2A, the conductive film 108 is formed over the substrate 101 (or the first insulating film 102).
Upper), the oxide film 107, and the island-shaped second insulating film 10
200 to 500 nm is formed on the entire surface of the substrate 6. Conductive film 10
As No. 8, a crystalline silicon film containing an N-type impurity is formed by a CVD method at a film forming temperature of 500 ° C. or higher. The formed crystalline silicon film has a size of 1 × 10 ^{19 to} 5 × 10 ^21.
It contains cm ⁻³ N-type impurities. Examples of N-type impurities include phosphorus. The conductive film 108 may have a multi-layer structure. That is, on the crystalline silicon layer containing N-type impurities, titanium, molybdenum, tungsten,
The conductive film 108 may have low resistance by forming a layer formed of a heat-resistant material such as molybdenum silicide or tungsten silicide. If a titanium nitride, molybdenum nitride, or tungsten nitride layer is further provided between the crystalline silicon layer containing N-type impurities and the titanium, molybdenum, or tungsten layer, the crystalline silicon layer containing N-type impurities and titanium, molybdenum , Or interdiffusion with the tungsten layer can be prevented.

Next, as shown in FIG. 2B, the gate electrode 109, the source electrode 110, and the drain electrode 11
1 is simultaneously formed by patterning the conductive film 108 by a photolithography method. that time,
The oxide film 107 serves as an etching stopper and the crystalline semiconductor film 104 is not etched. A third photomask is used in this patterning.

Next, an N-type impurity such as phosphorus is introduced into the crystalline semiconductor film 104. The introduction method may be either an ion implantation method with mass separation or an ion doping method without mass separation, but with the ion doping method, hydrogen is also introduced in addition to the N-type impurities. When introducing the N-type impurity, the N-type impurity is introduced into the first region of the crystalline semiconductor film 104 which is covered only with the oxide film 107 and the second region of the crystalline semiconductor film 104 which is covered only with the second insulating film 106. The N-type impurity is introduced so as not to be introduced into the lower region of the gate electrode 109. As a result, the concentration of the N-type impurity in the second region is lower than that in the first region, and the second region becomes the low-concentration impurity region (LDD region) 112. The first region becomes part of the source region 113 and the drain region 114. A region below the gate electrode 109 and sandwiched between the low-concentration impurity regions (LDD regions) 112 becomes a channel region 115. By introducing the N-type impurity only once, the low concentration impurity region (LDD region) 112 and the source region 113
And a first region which is a part of the drain region 114 may be formed, but then, the concentration of the N-type impurity introduced into the first region becomes low to form the source region and the drain region. It is possible. In that case, N
It is necessary to introduce the type impurities in two steps. Specifically, in the first introduction, the low-concentration impurity region (LDD region) 112 is formed with high acceleration so that the N-type impurity is introduced to the bottom of the second insulating film 106 and with a low dose amount. In the second introduction, the source region 113 and the drain region 114 are accelerating at a lower dose and with a higher dose amount than the first introduction.
Forming a first region which will be a part of. First introduction and 2
The order of the second introduction may be reversed.

In the state after the N-type impurities are introduced as described above, the source electrode 110 and the drain electrode 1
Oxide film 107 still exists between 11 and crystalline semiconductor film 104. The oxide film 107 has an extremely thin film thickness of 0.7 to 2.0 nm as described above, but it is not preferable because the contact resistance between the source electrode 110 and the drain electrode 111 and the crystalline semiconductor film 104 is large. The oxide film 107 includes a gate electrode 109, a source electrode 110,
When the formation of the drain electrode 111 is completed, it becomes unnecessary. Therefore, even if oxygen is released from the oxide film to a film in which a large number of lattice defects are formed, the film may not be in the form of a film, and it is rather preferable.

Therefore, in order to reduce the contact resistance between the source electrode 110 and the drain electrode 111 and the crystalline semiconductor film 104 and to improve the electrical connection, at least the crystalline semiconductor film 104, the oxide film 107, the source electrode 110,
And the drain electrode 111 in nitrogen at 800 to 1050
Heat at ℃. The atmosphere at the time of heating is not limited to nitrogen and may be any inert gas. The heating time is 30 minutes to 4 hours. If the heating temperature is 800 ° C., 2 to 4 hours are preferable, and if it is 950 ° C., it may be about 30 minutes. In addition,
To improve throughput, heating time should not be extended more than necessary. The upper limit of the heating temperature depends on the type of the substrate 101, the material forming the conductive film 108, and the heating means. When stainless steel is used for the substrate 101,
It should be noted that depending on the heating temperature and the heating time, embrittlement or corrosion resistance of stainless steel may be impaired.

By the heating at 800 to 1050 ° C., the characteristics of the oxide film 107 change and the oxide film 107 does not function as an etching stopper. Further, the damage of the crystalline silicon film 104 caused by the introduction of the N-type impurity is repaired, and the crystallinity of the amorphous portion and the region which was insufficiently crystallized when the semiconductor film 103 was crystallized is further enhanced. Thus, phosphorus contained in the source electrode 110 and the drain electrode 111 diffuses into the crystalline semiconductor film 104. By this diffusion, an impurity region in which phosphorus is introduced is also formed in the lower regions of the source electrode 110 and the drain electrode 111 of the crystalline semiconductor film 104, and the impurity region and the first region in which phosphorus is already introduced are formed. To form a source region 113 and a drain region 114.

The inventor of the present application considers the reason why the characteristics of the oxide film 107 change as follows. 800-105
Since the oxide film 107 does not function as an etching stopper by heating at 0 ° C., oxygen is desorbed from the oxide film 107 and SiO _x (0
In the case of <X ≦ 2), the value of “X” becomes small, and the case of “X = 0” is also included. Therefore, the N-type impurities are easily diffused, and the source electrode 110 and the drain electrode 11 are diffused.
1 and the crystalline semiconductor film 104 are electrically connected.

An experiment was conducted to clarify that the contact resistance changes due to the heat treatment. First, Fig. 1
A sample for resistance measurement whose cross section is shown at 0 (A) was prepared.
In FIG. 10A, 1001 is a quartz substrate, 1002 is an island-shaped crystalline silicon film containing phosphorus, 1003 is an oxide film, 10
Reference numeral 04 represents an electrode. The oxide film 1003 is formed by oxidizing the surface of the crystalline silicon film 1002 by treatment with ozone water, and the electrode 1004 is formed by sequentially stacking a crystalline silicon layer 1005 containing phosphorus, a tungsten nitride layer 1006, and a tungsten layer 1007. It was formed. The sample for the actual resistance measurement is the crystalline silicon film 10.
A part 02 is covered by the electrode 1004 (a part where the crystalline silicon film 1002 and the electrode 1004 are adjacent to each other with the oxide film 1003 in between) is formed continuously by 1000 pieces, and FIG. Only a part of the cross section of the sample is shown.

With respect to the sample thus prepared,
Condition 1 when the heat treatment is performed at 50 ° C. for 30 minutes,
Condition 2 is the case where the heat treatment is not performed,
Contact resistance was measured at 8 points for each of Condition 1 and Condition 2, and the plotted results are shown in FIG. The contact resistance in the case of condition 1 is in the range of 1 × 10 ⁵ Ω to 1 × 10 ⁶ Ω, and the contact resistance in the case of condition 2 is 1 × 10 ⁸ Ω to 1
It is in the range of × 10 ¹³ Ω. This result shows the effect of the heat treatment that the condition 1 in which the heat treatment is performed has a smaller contact resistance than the condition 2 in which the heat treatment is not performed, and further, the variation in the contact resistance at 8 points is smaller. ing. As described above, in this sample, the portion where the crystalline silicon film 1002 was covered with the electrode 1004 was 1.
Since 000 pieces are configured in series, 1 connected in series
It can be regarded as a resistance of 000 steps. Therefore, the contact resistance per part of the crystalline silicon film 1002 covered with the electrode 1004 is 10 which is the value shown in FIG.
It should be noted that this corresponds to 1/00.
That is, the contact resistance per part of the crystalline silicon film 1002 covered with the electrode 1004 is 1 in the case of the condition 1.
It is in the range of × 10 ² to 1 × 10 ³ Ω, and in the case of condition 2, 1
It is in the range of × 10 ⁵ Ω to 1 × 10 ¹⁰ Ω.

Next, as shown in FIG. 2C, a third insulating film 116 is formed to a thickness of 100 to 1000 nm. As the third insulating film, a silicon oxynitride film formed by a CVD method using SiH ₄ and N ₂ O as raw materials, Si
Any of a silicon nitride oxide film formed by a CVD method using H ₄ , N ₂ O, and NH ₃ as a raw material, a silicon oxide film, a silicon oxide film containing nitrogen, or a silicon nitride film may be used. Two or more kinds may be combined and formed from the inside so as to be stacked. After that, in order to activate the N-type impurities contained in the crystalline semiconductor film 104, the gate electrode 109, the source electrode 110, and the drain electrode 111, 800 to 1050 ° C., 30
Heat for minutes to 2 hours. At that time, hydrogen may be added to the nitrogen atmosphere, or after heat treatment in nitrogen, heating may be performed for about 1 hour in an atmosphere containing nitrogen and hydrogen. 800-1 performed to change the characteristics of the oxide film 107
If the N-type impurities are sufficiently activated by the heating at 050 ° C., the heating in nitrogen for activating the N-type impurities may be omitted here. In addition, before forming the third insulating film 116, the temperature is 800 to 1050 ° C. in nitrogen.
Instead of performing heat treatment for 30 minutes to 4 hours,
800 to 10 in nitrogen after forming the third insulating film 116
You may heat-process at 50 degreeC for 30 minutes-4 hours. In that case, the third insulating film 116 functions as a passivation film in the heat treatment.

Next, as shown in FIG. 2D, a fourth insulating film 117 is formed over the third insulating film 116 in order to obtain a flat surface. As the fourth insulating film 117, polyimide resin, acrylic resin, benzocyclobutene (B
Organic resin film such as CB) or SOG (Spin On)
A silicon oxide film formed by a coating method called “Glass” may be used. The surface of the inorganic insulating film such as a silicon oxide film is subjected to a known chemical mechanical polishing method (CM
The fourth insulating film 117 may be obtained by polishing with P). Then, the third insulating film 116 and the fourth insulating film 117 are patterned by a photolithography method to form the drain electrode 111 (or the source electrode 110).
To form a hole 118 reaching. A fourth photomask is used in this patterning.

Next, as shown in FIG. 2E, a transparent conductive film is formed over the entire surface of the fourth insulating film 117 in a thickness of 50 to 150 nm, and then patterned by a known photolithography method to form a pixel electrode 119. Form. As the transparent conductive film, tin oxide, indium tin oxide (IT
It may be a compound called indium oxide and tin oxide, or a compound called indium oxide and zinc oxide. A fifth photomask is used in this patterning.

In this embodiment mode, the number of times of patterning is three in the process until the source electrode 110 and the drain electrode 111 are formed, and three photomasks are used. On the other hand, in the process described in the item [Prior Art], the number of patterning times until the formation of the source electrode and the drain electrode is four, and four photomasks are used. Therefore, in the present embodiment, the patterning step can be performed once and the number of photomasks can be reduced as compared with the conventional technique. In addition, in this embodiment mode, the gate electrode 109, the source electrode 110, and the drain electrode 111.
Are simultaneously formed using only one photomask, the following effects can be obtained. That is, the gate electrode 1
09, the gap between the source electrode 110 and the gate electrode 1
The gap between 09 and the drain electrode 111 can be easily changed. The minimum value of the gap is determined by the design rule, but the gap can be made as small as possible according to the design rule without considering the margin.
Therefore, the size of the transistor can be reduced and the integration of the transistor can be increased. Further, the area of the portion where the source electrode 110 covers the source region 113 and the area of the portion where the drain electrode 111 covers the drain region 114 can be easily changed so as to obtain optimum electric characteristics.

(Embodiment 2) In Embodiment 1 of the present invention, N is used as the conductive film 108 for forming the gate electrode 109, the source electrode 110 and the drain electrode 111.
Although a crystalline silicon film containing a type impurity is used, a crystalline silicon film containing an N type impurity may not be used as the conductive film in this embodiment mode. In this embodiment, the conductive film 10
This is different from the first embodiment of the present invention in that N-type impurities or P-type impurities are introduced into the crystalline semiconductor film 104 using the second insulating film 106 as a mask before forming 8. In this embodiment, the processes corresponding to FIGS. 1A to 1D are common to the first embodiment of the present invention, so only the processes after FIG. 1D will be described with reference to FIGS. This will be described below using (E).

After formation up to FIG. 1D, an N-type impurity such as phosphorus is introduced into the crystalline semiconductor film 104 using the island-shaped second insulating film 106 as a mask. At this time, an N-type impurity is not introduced into a portion covered with the second insulating film 106 and an impurity is introduced into a portion not covered with the second insulating film 106, so that a source region 313 and a drain region 314 are formed. To be done. The method of introducing the N-type impurity may be either an ion implantation method with mass separation or an ion doping method without mass separation. In the present embodiment, P-type impurities such as boron can be used instead of N-type impurities. After that, an oxide film 307 is formed as shown in FIG. 3A by the same method as that of the first embodiment of the present invention.

Next, as shown in FIG. 3A, a conductive film 308 is formed over the entire surface of the substrate 101 or the first insulating film 102, the oxide film 307, and the second insulating film 106.
It is formed to a thickness of 00 to 500 nm. As the conductive film 308,
It may be any of copper, palladium, chromium, cobalt, titanium, molybdenum, niobium, tantalum, tungsten, etc., and further titanium nitride, tantalum nitride, tungsten nitride, cobalt silicide, titanium silicide, molybdenum silicide, niobium silicide, tantalum silicide, tungsten silicide. It may be configured in combination with the above. Further, similarly to Embodiment Mode 1 of the present invention, also in this embodiment mode, crystalline silicon containing an N-type impurity can be used as at least part of the material forming the conductive film 308.

Next, as shown in FIG. 3B, the conductive film 308 is patterned by a photolithography method to form the gate electrode 309, the source electrode 310, and the drain electrode 311 at the same time. At that time, the oxide film 30
7 serves as an etching stopper, and the crystalline semiconductor film 10 is formed.
4 is not etched.

Next, again, an N-type impurity such as phosphorus is introduced into the region of the crystalline semiconductor film 104 which is covered only by the second insulating film 106, and the N-type impurity concentration is increased from the source region 313 and the drain region 314. And a low-concentration impurity region (LDD region) 312 having a low temperature is formed. Under the gate electrode 309, a low concentration impurity region (LDD region) 312 is formed.
The N-type impurity is not introduced into the region sandwiched by and becomes the channel region 315. P-type impurities may be used instead of N-type impurities. Then, at least the crystalline semiconductor film 104, the oxide film 307, the source electrode 310, and the drain electrode 311 are placed in nitrogen at 800 to 1050 ° C.
Then, heat for 30 minutes to 4 hours. The atmosphere at the time of heating is not limited to nitrogen and may be any inert gas. By the heating, the contact resistance between the source electrode 310 and the source region 313, and the drain electrode 311 and the drain region 314.
The contact resistance with

Next, as shown in FIG. 3C, a third insulating film 316 is formed to a thickness of 100 to 1000 nm. As the third insulating film 316, a silicon oxynitride film formed by a CVD method using SiH ₄ and N ₂ O as a raw material, Si
Any of a silicon nitride oxide film, a silicon oxide film, and a silicon nitride film formed by a CVD method using H ₄ , N ₂ O, and NH ₃ as a raw material may be used, and two or more kinds of these films may be combined. They may be formed in a stack. Also,
Before forming the third insulating film 316, in the nitrogen,
Instead of performing the heat treatment at 50 ° C. for 30 minutes to 4 hours, the third insulating film 316 is formed, and then, the heat treatment is performed in nitrogen at 800 ° C.
You may perform heat processing for 30 minutes-4 hours at 1050 degreeC.

Next, as shown in FIG. 3D, a fourth planarization insulating film 317 for planarization is formed on the third insulating film 316.
Formed to have a thickness of 00 to 4000 nm. As the fourth insulating film 317, a polyimide resin, an acrylic resin, benzocyclobutene (BCB), or a silicon oxide film (SOG) formed by a coating method is used. Then, the third insulating film 316 and the fourth insulating film 317 are patterned by a photolithography method to form the drain electrode 311.
A hole 318 reaching (or the source electrode 310) is formed.

Next, as shown in FIG. 3E, a transparent conductive film is formed on the entire surface of the fourth insulating film 317 and then patterned by photolithography to form the pixel electrode 31.
9 is formed. The transparent conductive film may be either tin oxide, a compound called indium tin oxide (ITO) made of indium oxide and tin oxide, or a compound made of indium oxide and zinc oxide.

Similar to Embodiment Mode 1 of the present invention, also in this embodiment mode, the source electrode 310 and the drain electrode 311 are provided.
The patterning process is performed three times and three photomasks are used in the process up to the formation of. Therefore, it is possible to reduce the number of photomasks by one patterning step as compared with the conventional technique. Moreover, since the gate electrode 309, the source electrode 310, and the drain electrode 311 are simultaneously formed using only one photomask, the following effects can be obtained. That is, the gap between the gate electrode 309 and the source electrode 310 and the gap between the gate electrode 309 and the drain electrode 311 can be made as small as possible in terms of design rules. Therefore, the size of the transistor can be reduced and the integration of the transistor can be increased. Further, the area of the portion where the source electrode 310 covers the source region 313 and the area of the portion where the drain electrode 311 covers the drain region 314 can be easily changed so as to obtain optimum electric characteristics.

(Third Embodiment) In the first embodiment of the present invention, ozone water is used to form the oxide film 107.
In this embodiment mode, an aqueous solution of hydrogen peroxide (H ₂ O ₂ ) (hereinafter referred to as hydrogen peroxide solution in this specification) is used. Only the points different from the first embodiment of the present invention will be described below.

While rotating the substrate 101 on which at least the crystalline semiconductor film 104 and the second insulating film 106 are formed, room temperature or 8
Continue flowing hydrogen peroxide solution at 0 ° C. for 30 to 600 seconds. As hydrogen peroxide water, 30 to 35 wt%, for example, 31 w
A solution with a concentration of t% is used. Hydrogen peroxide is a liquid at room temperature and pressure and is water-soluble and exhibits an oxidizing effect. As the water used as the solvent, pure water similar to the case of ozone water is used.

Since the oxide film formed in this embodiment is also extremely thin as in the first embodiment of the present invention,
Although it is not easy to measure the accurate film thickness, it is in the range of 0.7 to 1.5 nm for the treatment at room temperature and 1.0 to 2.0 nm for the treatment at 80 ° C. It should be noted that even if the time for flowing the hydrogen peroxide solution (processing time) is changed, the film thickness of the oxide film formed does not change significantly.

The subsequent process is the same as in the first embodiment of the present invention.
But the conductive film 108 is the same as that of the second embodiment.
As shown in, any of copper, palladium, chromium, cobalt, titanium, molybdenum, niobium, tantalum, tungsten, etc., and further titanium nitride, tantalum nitride, tungsten nitride, cobalt silicide, titanium silicide, molybdenum silicide, niobium silicide, silicide The structure is combined with tantalum, tungsten silicide, etc., and the crystalline silicon film containing N-type impurities may not be used. In that case, the process described in Embodiment 2 may be followed.

(Embodiment 4) In Embodiment 1 of the present invention, the first insulating film 102 is formed on the substrate 101, but in the present embodiment, between the substrate 101 and the first insulating film 102, A light shielding film is provided on. Only the points different from the first embodiment of the present invention will be described below with reference to FIGS.

As shown in FIG. 4A, the light shielding film 400 is formed on the substrate 101 to have a thickness of 100 to 300 nm. The light-shielding film 400 is provided in order to prevent the crystalline semiconductor film 104 to be formed later from being irradiated with light, and is patterned into an island shape so as to overlap at least the channel region of the crystalline semiconductor film 104. As the light-shielding film 400,
A film of chromium, tungsten, molybdenum, niobium, tantalum, titanium, titanium silicide, molybdenum silicide, niobium silicide, tantalum silicide, tungsten silicide, or the like may be used. Further, a so-called polycide structure in which a metal silicide film such as tungsten silicide is overlaid on a crystalline silicon film containing N-type impurities may be used. If the light shielding film 400 is a conductive film, it can also function as a gate electrode.

Next, as in the first embodiment, FIG.
As shown in, the first insulating film 102, the island-shaped crystalline semiconductor film 104, and the second insulating film 105 are formed, and a P-type impurity is introduced into the crystalline semiconductor film 104 for channel doping. When forming the first insulating film 102, the thickness of the first insulating film 102 is made larger than that of the light shielding film 400, and the first insulating film is formed by a known chemical mechanical polishing (CMP) method. The surface of 102 may be polished and planarized.

Next, as shown in FIG. 4C, the second insulating film 105 and the first insulating film 102 are patterned by a photolithography method to open holes 401. The hole 401 is formed to electrically connect the gate electrode 109 to be formed later and the light shielding film 400, and is not opened in the crystalline semiconductor film 104. Further, this hole is not opened if the light shielding film 400 is a film having no conductivity. Then, the second insulating film 105 is patterned by a photolithography method to form the island-shaped second insulating film 106.

The subsequent process is the same as in the first embodiment of the present invention.
1E and FIGS. 2A to 2E. As a method of forming oxide film 107, hydrogen peroxide solution may be used as shown in the third embodiment. Further, when the conductive film 108 is formed, it must be formed so as to completely fill the hole 401. As the conductive film 108, as shown in Embodiment Mode 2, any one of copper, palladium, chromium, cobalt, titanium, molybdenum, niobium, tantalum, tungsten, titanium nitride, tantalum nitride, tungsten nitride, cobalt silicide, and the like can be used. It is not necessary to use a crystalline silicon film containing an N-type impurity by using a structure in which titanium silicide, molybdenum silicide, niobium silicide, tantalum silicide, tungsten silicide, or the like is combined. In that case, the process described in Embodiment 2 may be followed.

An example in which the above-described embodiment of the present invention is more specified will be shown below.

[0063]

EXAMPLES Example 1 In this example, a method for manufacturing an active matrix drive liquid crystal display (AMLCD) adopting the first and fourth embodiments of the present invention will be described with reference to FIG.
(A)-(E), FIG. 6 (A)-(D), and FIG.
A description will be given according to (A) to (C). First, as shown in FIG. 5A, a crystalline silicon film and a tungsten silicide film are formed on a quartz substrate 501 by a known method. In this embodiment, SiH ₄ and PH ₃ are used as raw materials,
A crystalline silicon film is formed by LPCVD at a film forming temperature of 600 ° C., and a tungsten silicide film is formed by sputtering a target made of tungsten and silicon with argon ions. The tungsten silicide film may be formed by another method, for example, a CVD method using WF ₆ and SiH ₂ Cl ₂ as raw materials. Then, the crystalline silicon film and the tungsten silicide film are patterned by photolithography to form a first light shielding film 502.

Next, as shown in FIG. 5B, a silicon oxynitride film 503 is formed over the light-shielding film 502 by a plasma CVD method using SiH ₄ and N ₂ O as raw materials, and the film formation temperature is further increased. Temperature of 800 ° C. and the inside of the reaction chamber is kept in a depressurized state by the LPCVD method.
To form 04. Here, the silicon oxynitride film 503
Is L used when the silicon oxide film 504 is formed next.
The PCVD device is formed to prevent the material forming the light-shielding film 502 from being contaminated. If LP
The silicon oxynitride film 503 may be omitted as long as the CVD device is not contaminated. Silicon oxynitride film 50
3 and the silicon oxide film 504 correspond to the first insulating film 102 in the first and fourth embodiments of the present invention. Then, the LPCV is formed on the silicon oxide film 504.
A silicon film 505 is formed by the D method.

Next, a solution containing nickel, which is an element that promotes crystallization of the silicon film, a nickel acetate solution in this example, is applied to the quartz substrate 501 by spin coating.
Is rotated to apply it on the silicon film 505, and then the quartz substrate 501 is rotated to remove excess nickel acetate solution and dry. Then, in order to release hydrogen contained in the silicon film 505 from the film, an electric furnace is used to remove hydrogen.
Heat at 0 ° C. for 1 hour. In an electric furnace, 600 ℃, 1
The silicon film 505 is crystallized by heating for 2 hours.

As a method of crystallizing the silicon film 505, the following method may be used. That is, the silicon film 505 is irradiated with a rectangular solid laser (second harmonic (532 nm) of Nd: YVO ₄ laser).
Light having a wavelength of 532 nm is hardly absorbed by the quartz substrate 501 but absorbed by the silicon film 505.
Rather than crystallize by heating in an electric furnace,
Crystallization by laser irradiation can shorten the time required for crystallization of the silicon film. In that case, the step of applying a solution containing nickel and the gettering step described below may be omitted.

Next, nickel contained in the crystallized silicon film 505 must be gettered and removed. First, a silicon oxide film is formed over the crystallized silicon film 505 by an LPCVD method at a film formation temperature of 400 ° C., and the silicon oxide film is patterned by a photolithography method, so that a mask 506 as illustrated in FIG.
To form. The mask 506 is for introducing phosphorus into only a part of the crystallized silicon film 505.

Next, on the crystallized silicon film 505,
10kV of phosphorus from above the mask 506, 2 × 10 ¹⁵ cm ^-2
And is introduced by ion doping under the above condition, and phosphorus is introduced into the region 507. After that, when heated at 700 ° C. for 12 hours in nitrogen, nickel in the crystallized silicon film 505 moves and collects in the region 507.

Next, as shown in FIG. 5D, the mask 5
06 is removed by etching, and the crystallized silicon film 505 is patterned by a photolithography method to form an island-shaped crystalline silicon film 508. At that time, the region 507 is completely removed. Further, the crystalline silicon film 508 is made to completely overlap with the light shielding film 502.

Next, as shown in FIG. 5E, SiH
_A silicon oxynitride film 509 is formed by a plasma CVD method using ₄ and N ₂ O as raw materials. Then, 60 kV, 3.6 × 10 ¹³ are formed on the entire surface of the crystalline silicon film 508.
Channel doping is performed by introducing boron under the condition of cm ⁻² .

Next, as shown in FIG. 6A, photolithography is performed to open a hole 510 reaching the light-blocking film 502 in the silicon oxynitride film 503, the silicon oxide film 504, and the silicon oxynitride film 509. Patterning by the method. The holes 510 are formed in the crystalline silicon film 50.
No openings are made in 8. Then, the silicon oxynitride film 5
09 is patterned by a photolithography method to form an island-shaped gate insulating film 511.

Next, as shown in FIG.
A silicon oxide film 512 is formed on the surface of the silicon film 508.
To do. The method for forming the silicon oxide film 512 is the same as that of the present invention.
The method described in Embodiment 1 is used. That is, the gate insulating film
Crystalline silicon film 5 exposed when forming 511
The natural oxide film was removed from the surface of No. 08 with diluted hydrofluoric acid solution,
Then, the light-shielding film 502 and oxynitride are formed by spin coating.
Silicon film 503, silicon oxide film 504, crystalline silicon
The con film 508 and the gate insulating film 511 were formed.
While rotating the quartz substrate 501, the crystalline silicon film 5
On the surface of 08, ozone water with a concentration of 14 mg / l at room temperature
Continue running for 60 seconds. Then, wash the surface with pure water
Rinse the ozone water and then blow it with nitrogen while blowing
The plate 501 is rotated and dried. Oxidized silicon formed
The con film 512 is made of Si ¹⁺, Si²⁺, Si³⁺, And Si
⁴⁺Have. In other words, SiO_X(0 <X <2) and
And SiO₂Have.

Next, as shown in FIG. 6C, SiH
LP with ₄ and PH ₃ as raw materials and film formation temperature of 600 ° C
A crystalline silicon film 513 containing phosphorus is formed over the silicon oxide film 504, the silicon oxide film 512, and the gate insulating film 511 by a CVD method.

Next, as shown in FIG. 6D, the crystalline silicon film 513 containing phosphorus is patterned by a photolithography method to form a gate electrode 514, a source electrode 515, and a drain electrode 516 at the same time. As an etching method for patterning, wet etching using an alkaline solution is used. Since the silicon oxide film 512 functions as an etching stopper, the crystalline silicon film 508 is not etched.

Next, phosphorus is introduced into the crystalline silicon film 508 by an ion doping method. First, in order to form a low-concentration impurity region (LDD region) 517, a region of the crystalline silicon film 508 covered only by the gate insulating film 511 is phosphorus-doped under the conditions of 60 kV and 5 × 10 ¹³ cm ^−2. To introduce. Then, the crystalline silicon film 5 is formed to form the source region 519 and the drain region 520.
Of the 08, phosphorus is introduced into a region covered with only the silicon oxide film 512 under the conditions of 50 kV and 2 × 10 ¹⁵ cm ⁻² . Below the gate electrode 514, phosphorus is not introduced into the region sandwiched by the low-concentration impurity regions (LDD regions) 517 and becomes a channel region 518. Note that after the gate insulating film 511 is formed and before the silicon oxide film 512 is formed, the source region 519 and the drain region 520 are formed.
May be introduced into the crystalline silicon film 508 to form the. In that case, the low concentration impurity region (LDD
The step of introducing phosphorus for forming the source region 519 and the drain region 520, which is performed after the formation of the region 517, is unnecessary.

After the phosphorus is introduced as described above, the silicon oxide film 512 still exists between the source region 519 and the source electrode 515 and between the drain region 520 and the drain electrode 516. Moreover, phosphorus having a concentration enough to form the source region and the drain region is not introduced into the portion of the source region 519 covered with the source electrode 515 and the portion of the drain region 520 covered with the drain electrode 516. Therefore, the substrate 5 on which at least the crystalline silicon film 508, the silicon oxide film 512, the source electrode 515, and the drain electrode 516 are formed in an electric furnace in nitrogen at 950 ° C. for 30 minutes.
01 is heated to source electrode 515 and drain electrode 5
Diffuse phosphorus from 16 into source region 519 and drain region 520. By the heating, the source region 51
9 and the contact resistance between the source electrode 515 and the drain region 520 and the drain electrode 516 are small.

Next, as shown in FIG. 7A, SiH
_A silicon oxynitride film is formed by a plasma CVD method using ₄ and N ₂ O as raw materials, and an interlayer insulating film 521
And Then, the crystalline silicon film 508, the gate electrode 514, the source electrode 515, and the drain electrode 516.
In order to activate the N-type impurities contained therein, it is heated in nitrogen at 950 ° C. for 30 minutes. Then, the crystalline silicon film 50 is heated in hydrogen at 350 ° C. for 1 hour.
8, dangling bonds (a type of point defect) in silicon forming the gate electrode 514, the source electrode 515, and the drain electrode 516 are terminated (t) by hydrogen.
terminate).

Next, as shown in FIG. 7B, an acrylic resin film is formed as a planarization film 522 over the interlayer insulating film 521. Instead of the acrylic resin film , a polyimide resin film, a benzocyclobutene (BCB) film, or a silicon oxide film (SOG) formed by a coating method may be used.

Next, as shown in FIG. 7C, in order to form the second light-shielding film 523, a film made of an alloy of aluminum and titanium is formed by sputtering and patterned by photolithography. . In this embodiment, if the second light-shielding film 523 has light-shielding properties and conductivity, a metal film of chromium or the like, a conductive polymer (a polymer substance exhibiting conductivity), instead of an alloy of aluminum and titanium. Alternatively, an electrically conductive resin (a resin mixed with a conductive substance such as metal or carbon) may be formed. Since the insulating film 524 is formed on the second light shielding film 523, Si
Plasma CV using H ₄ , N ₂ O, and NH ₃ as raw materials
A silicon nitride oxide film is formed by the D method. And
The first interlayer insulating film 521, the planarizing film 522, and the insulating film 524 are patterned by a photolithography method to form a hole reaching the drain electrode 516 (or the source electrode 515). Then, the IT is formed on the insulating film 524.
A transparent conductive film made of O is formed by a sputtering method and patterned to form a pixel electrode 525. In this embodiment, tin oxide or a compound of indium oxide and zinc oxide may be used instead of ITO as the transparent conductive film.

As is clear from FIG. 7C, a capacitor is formed by the second light-shielding film 523 which is a conductive film, the pixel electrode 525, and the insulating film 524 between them.

As described above, the TFT of the active matrix liquid crystal display is manufactured by the process described in this embodiment.
The process is completed until the pixel electrode is formed on the substrate on which the pixel is formed. After that, the liquid crystal display may be completed by a known method.

(Embodiment 2) This embodiment shows another method of gettering nickel contained in the crystallized silicon film 505 shown in Embodiment 1 of the present invention. Only the points of this embodiment different from the first embodiment of the present invention will be described below.

This embodiment is the same as the first embodiment of the present invention until the silicon film 505 shown in FIG. 5B is coated with a nickel acetate solution and the silicon film 505 is heated to be crystallized. is there.

Next, the natural oxide film is removed from the surface of the crystallized silicon film 505 with a dilute hydrofluoric acid solution, and ozone water is used in the same manner as in the first embodiment of the present invention.
An oxide film 806 as shown in (A) is formed. Then, an amorphous silicon film 807 is formed on the silicon oxide film 806.
Are formed by LPCVD, and the amorphous silicon film 8 is formed.
Argon, which is a rare gas element, is introduced into 07. Helium, neon, krypton, or xenon may be used instead of argon.

Next, it is heated in an electric furnace at 550 ° C. for 4 hours. By this heating, nickel contained in the crystallized silicon film 505 passes through the silicon oxide film 806, moves to the amorphous silicon film 807 into which argon is introduced, and is gettered. The heating temperature is 550
It may be higher than or equal to ℃, and its upper limit is determined by the performance of the furnace used and the type of substrate. Further, if the heating temperature is raised, gettering is possible even if the heating time is shorter than 4 hours.

Next, the amorphous silicon film 807 is coated with an Al film.
It is removed by wet etching using a potassium solution.
At that time, the silicon oxide film 806 is an etching stopper.
The crystallized silicon film 505 functions as
Not touched. Thus, the crystallized silicon film 5
The concentration of nickel in 05 is 1 x 10¹⁷cm ^-3Reduced to
Can be made.

Next, as shown in FIG. 8B, the crystallized silicon film 505 is patterned by a photolithography method to form an island-shaped crystalline silicon film 808. The silicon oxide film 806 is an island-shaped crystalline silicon film 8
It exists only on the upper surface of 08 and does not exist on the side surface.

Next, as shown in FIG. 8C, a hole 810 and an island-shaped gate insulating film 811 are formed by a method similar to that of the first embodiment of the present invention. When the island-shaped gate insulating film 811 is formed by patterning, a portion of the silicon oxide film 806 which is not covered with the gate insulating film 811 is etched. Therefore, by using ozone water again and by the same method as in the first embodiment of the present invention, as shown in FIG.
A silicon oxide film 812 as shown in (D) is formed.

Since the subsequent process is the same as that of the first embodiment of the present invention, FIG. 6 (7C) to (D) and FIG.
It suffices to follow (A) to (C).

Example 3 In this example, an active matrix drive display using a light emitting element manufactured by adopting the first and second embodiments of the present invention is shown.

FIG. 9 is a sectional view of a pixel portion of a display. Normally, one pixel is provided with one switching TFT connected to the gate signal line and the source signal line and one TFT for current control (also referred to as driving) connected to the light emitting element. Only TFTs are shown. Although the driving TFT may be an N-channel type or a P-channel type, it is a P-channel type TFT in this embodiment.

The first insulating film 90 is formed on the quartz substrate 901.
2, an island-shaped crystalline silicon film 903, and an island-shaped gate insulating film 904 which is a second insulating film.
5, a source electrode 906, and a drain electrode 907. The gate electrode 905, the source electrode 906, and the drain electrode 907 are made of the same conductive material. The island-shaped crystalline silicon film 903 has a source region, a drain region, and a low-concentration impurity region (LDD region) containing boron which is a P-type impurity, and is provided between the source electrode 906 and the source region and the drain electrode. SiO _x (0 <X <2) (not shown) is provided between 907 and the drain region. SiO _x (0 <X <2) may be in the form of a film or may not be in the form of a film.

Further, a third insulating film 908 and a planarization film 909 which are provided so as to cover the gate electrode 905, the source electrode 906, and the drain electrode 907 are provided, and the drain electrode 907 has a transparent conductive film with a large work function. Membrane (I
An anode 910 made of TO) is connected, and a fourth insulating film 911 is provided thereon. The fourth insulating film 911 is
A hole is formed to expose a part of the surface of the anode 910.

Further, an organic compound layer 912 containing a light-emitting body, which is in contact with the anode 910 and over the fourth insulating film 911,
And a cathode 913 made of a metal or alloy having a low work function (alloy of Mg and Ag). The anode 910, the organic compound layer 912 including a light emitting body, and the cathode 913 are combined to form a light emitting element. The active matrix driving display using the light emitting element in this embodiment is a bottom emission type in which light is emitted from the light emitting element in the direction of the quartz substrate 901.

(Embodiment 4) This embodiment shows examples of various products incorporating the display device manufactured by the present invention. The display device is an active matrix driving liquid crystal display or an active matrix driving display using a light emitting element.

Although not shown in particular, the display device manufactured by the present invention includes a notebook personal computer, a mobile phone, a digital camera, a video camera, a personal digital assistant (PDA), a television receiver, an in-vehicle navigation system, and a head. It is applied to the display of electronic devices such as mount displays. Further, the present invention is applied to a display device incorporated in a front projector or a rear projector.

[0097]

EFFECTS OF THE INVENTION The present invention has its origin in focusing on an oxide film formed by treating the surface of a semiconductor film with ozone water or hydrogen peroxide water. By using the oxide film as an etching stopper, the gate electrode, the source electrode, and the drain electrode of the field-effect transistor can be formed at the same time with one patterning using only one photomask. Therefore,
The gap between the gate electrode and the source electrode and the gap between the gate electrode and the drain electrode can be made as small as possible, and the area of the portion where the source electrode covers the source region and the area of the portion where the drain electrode covers the drain region are easy. Can be changed to Further, the present invention does not require patterning for forming an opening in the interlayer insulating film in order to connect the source electrode to the source region and the drain electrode to the drain region. After the gate electrode, the source electrode, and the drain electrode are formed, heat treatment is performed at a high temperature of 800 ° C. or higher for a predetermined time, so that electrical connection between the source electrode and the source region and drain can be performed even if the oxide film remains. Good electrical connection between the electrode and the drain region.

According to the present invention, the number of patterning steps and the number of photomasks can be reduced,
Throughput and yield can be improved. The present invention can be applied to various products in which an active matrix-driving liquid crystal display or an active matrix-driving display using a light emitting element is incorporated in a display unit of an electronic device or an electronic device.

Note that the present invention is not limited to the thin film transistor including a crystalline semiconductor film as shown in FIGS. 1 to 9 and is also applicable to a field effect transistor formed on a silicon substrate. Can be applied.

[Brief description of drawings]

FIG. 1 is a sectional view illustrating a first embodiment of the present invention.

FIG. 2 is a sectional view for explaining the first embodiment of the present invention.

FIG. 3 is a sectional view illustrating a second embodiment of the present invention.

FIG. 4 is a sectional view illustrating a fourth embodiment of the present invention.

FIG. 5 is a sectional view for explaining the first embodiment of the present invention.

FIG. 6 is a sectional view for explaining the first embodiment of the present invention.

FIG. 7 is a cross-sectional view illustrating the first embodiment of the present invention.

FIG. 8 is a sectional view illustrating a second embodiment of the present invention.

FIG. 9 is a sectional view illustrating a third embodiment of the present invention.

FIG. 10 is a diagram showing the effect of the heat treatment of the present invention.

[Explanation of symbols]

101 quartz substrate 102 first insulating film 103 semiconductor film 104 Island-shaped crystalline semiconductor film 105 Second insulating film 106 island-shaped second insulating film (gate insulating film) 107 oxide film 108 conductive film 109 gate electrode 110 source electrode 111 drain electrode 112 low concentration impurity region (LDD region) 113 Source area 114 drain region 115 channel region 116 third insulating film 117 Fourth insulating film 118 holes 119 Pixel electrode

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/50 M 29/78 616A F term (reference) 2H092 JA25 KA04 KA07 KA10 MA07 MA14 MA20 MA23 MA29 NA27 NA29 4M104 AA01 AA08 AA09 BB01 BB04 BB07 BB13 BB14 BB16 BB17 BB18 BB20 BB24 BB25 BB26 BB27 BB28 BB30 BB32. DA03 EA16 FA06 JA01 JA04 5F110 AA16 BB01 BB02 BB04 CC02 DD01 DD03 DD05 DD13 DD14 DD15 DD17 EE01 EE02 EE04 EE05 EE09 EE14 EE45 FF02 FF03 FF04 FF09 FF29 GG01 GG02 GG03 GG12 GG13 GG25 GG32 GG34 GG47 HJ01 HJ04 HJ12 HJ13 HJ21 HJ23 HK01 HK02 HK04 HK05 HK09 HK14 HK21 HK34 HK42 HL07 HM02 HM15 NN03 NN22 NN23 NN24 NN27 NN35 NN42 NN45 NN46 NN54 NN55 NN72 PP01 PP02 PP03 PP03 PP06 PP10 PP34 QQ08 QQ11 QQ19 QQ24 QQ28

Claims (9)

[Claims] 1. A first insulating film is formed on a crystalline semiconductor, and the first insulating film is patterned to form a gate insulating film on a part of the crystalline semiconductor. The surface of the crystalline semiconductor is oxidized to form an oxide film, a conductive film having a semiconductor layer containing an N-type impurity is formed on the oxide film and the gate insulating film, and the conductive film is patterned. A gate electrode, a source electrode, and a drain electrode at the same time by using the gate electrode, the source electrode, and the drain electrode as a mask to introduce an N-type impurity into the crystalline semiconductor. An electric field characterized by heating the film, the gate insulating film, the gate electrode, the source electrode, and the drain electrode in an inert gas at 800 ° C. to 1050 ° C. for 30 minutes to 4 hours. Method of manufacturing an effect transistor. 2. A semiconductor film is formed above a substrate, the semiconductor film is crystallized to form a crystalline semiconductor film, and the crystalline semiconductor film is patterned to form an island-shaped crystalline semiconductor film, A first insulating film is formed on the island-shaped crystalline semiconductor film, and the first insulating film is patterned to form a gate insulating film on a part of the island-shaped crystalline semiconductor film. Forming an oxide film by oxidizing the surface of the island-shaped crystalline semiconductor film using an aqueous solution of, and having a semiconductor layer containing an N-type impurity above the substrate, on the oxide film, and on the gate insulating film. A conductive film is formed, and the conductive film is patterned to simultaneously form a gate electrode, a source electrode, and a drain electrode, and the island-shaped crystalline semiconductor is formed by using the gate electrode, the source electrode, and the drain electrode as a mask. N type on the membrane A pure substance is introduced, and the substrate on which at least the island-shaped crystalline semiconductor film, the oxide film, the gate insulating film, the gate electrode, the source electrode, and the drain electrode are formed is placed in an inert gas at 800 ° C. A method for manufacturing a field effect transistor, which comprises heating at 1050 ° C. for 30 minutes to 4 hours. 3. A first insulating film is formed on a crystalline semiconductor, and the first insulating film is patterned to form a gate insulating film on a part of the crystalline semiconductor. N is used as a mask for the crystalline semiconductor.
Type impurities are introduced, the surface of the crystalline semiconductor is oxidized using an aqueous solution of an oxidizing agent to form an oxide film, and a conductive film is formed on the oxide film and the gate insulating film. Patterning is performed to simultaneously form a gate electrode, a source electrode, and a drain electrode, and an N-type impurity is introduced into the crystalline semiconductor using the gate electrode, the source electrode, and the drain electrode as a mask, the crystalline semiconductor, Manufacturing the field effect transistor, characterized in that the oxide film, the gate insulating film, the gate electrode, the source electrode, and the drain electrode are heated in an inert gas at 800 ° C. to 1050 ° C. for 30 minutes to 4 hours. Method. 4. A semiconductor film is formed above a substrate, the semiconductor film is crystallized to form a crystalline semiconductor film, and the crystalline semiconductor film is patterned to form an island-shaped crystalline semiconductor film, Forming a first insulating film on the island-shaped crystalline semiconductor film; patterning the first insulating film to form a gate insulating film on a part of the island-shaped crystalline semiconductor film; N-type impurities are introduced into the island-shaped crystalline semiconductor film using the insulating film as a mask, and the surface of the island-shaped crystalline semiconductor film is oxidized using an aqueous solution of an oxidant to form an oxide film. A conductive film is formed over the substrate, on the oxide film, and on the gate insulating film, and the conductive film is patterned to simultaneously form a gate electrode, a source electrode, and a drain electrode, the gate electrode, the source electrode, And the drain electrode Is used as a mask to introduce an N-type impurity into the island-shaped crystalline semiconductor film, the island-shaped crystalline semiconductor film, the oxide film, the gate insulating film, the gate electrode, the source electrode, and the drain electrode. A method for manufacturing a field effect transistor, characterized in that the substrate on which at least is formed is heated in an inert gas at 800 ° C. to 1050 ° C. for 30 minutes to 4 hours. 5. The field effect according to claim 1, wherein N-type impurities contained in the source electrode and N-type impurities contained in the drain electrode are diffused into the crystalline semiconductor during the heating. Type transistor manufacturing method. 6. The method according to claim 2, wherein during the heating, N-type impurities contained in the source electrode and N-type impurities contained in the drain electrode are diffused into the island-shaped crystalline semiconductor film. A method for manufacturing the field effect transistor described. 7. The method of manufacturing a field effect transistor according to claim 2, wherein the substrate is a quartz substrate. 8. The method for manufacturing a field effect transistor according to claim 1, wherein the aqueous solution of the oxidizing agent is an aqueous solution of ozone or an aqueous solution of hydrogen peroxide. 9. The method for manufacturing a field effect transistor according to claim 1, wherein the N-type impurities are replaced with P-type impurities.