JP3600229B2 - Method for manufacturing field effect transistor - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a field effect transistor such as a thin film transistor and a method for manufacturing the same, and a method for manufacturing a display device using the field effect transistor and the display device. In particular, the present invention relates to a field-effect transistor such as a thin-film transistor in which a gate electrode, a source electrode, and a drain electrode of a field-effect transistor such as a thin-film transistor are simultaneously formed by patterning the same starting film by using a photolithography method and a method for manufacturing the same. .
[0002]
[Prior art]
An example of a conventional thin film transistor manufacturing process is described below. An amorphous silicon film is formed above a glass substrate, and the amorphous silicon film is crystallized into a crystalline silicon film, and the crystalline silicon film is patterned into islands, and gate insulating is performed on the island-shaped crystalline silicon film. A film is formed, a conductive film formed on the gate insulating film is patterned to form a gate electrode, and impurities are introduced into the island-shaped crystalline silicon film by an ion doping method using the gate electrode as a mask. Forming a source region and a drain region, forming a first interlayer insulating film on the gate electrode and the island-shaped crystalline silicon film, and forming a hole (a hole) reaching the source region and the drain region in the first interlayer insulating film; The contact hole is opened by patterning, and then a conductive film connected to the source and drain regions is formed. It is produced through a process of forming a source electrode and a drain electrode by patterning the. The above process is known (for example, refer to Patent Document 1). When a thin film transistor manufactured by this known technique is applied to a pixel portion of a display device, a second interlayer insulating film is formed on a source electrode and a drain electrode, and the source electrode or the drain electrode is formed on the second interlayer insulating film. Is formed by patterning, a transparent conductive film is further formed, and this is patterned to form a pixel electrode.
[0003]
[Patent Document 1]
JP-A-8-330602 (FIGS. 1A to 1F, Example 1)
[0004]
As described above, in the conventional process, after the gate electrode is formed, the source electrode and the drain electrode are formed. That is, the formation of the gate electrode and the formation of the source electrode and the drain electrode are usually performed separately. Therefore, in the above-described conventional process, the patterning process until the formation of the source electrode and the drain electrode is performed four times, and the number of photomasks used at that time is four. The number of patterning steps until the formation of the pixel electrode is further increased two times to six, and the number of photomasks used at that time is six.
[0005]
[Problems to be solved by the invention]
At present, in the production of field-effect transistors such as thin-film transistors and the production of display devices using the field-effect transistors, the throughput (the number that can be processed per unit time) is improved, and the yield (the number of finished products corresponding to the number of products put into a production line) is improved. Is strongly demanded.
[0006]
However, in the conventional process, since the number of steps is large, it is not easy to shorten the time required for manufacturing the field-effect transistor and the display device, and it is difficult to improve the yield. For example, the position of a fine pattern formed in a subsequent patterning step may be shifted due to shrinkage of the substrate or other causes. Such a shift in the position of the pattern causes the occurrence of a defective product and lowers the yield. For example, when a hole (contact hole) is formed by patterning to form a source electrode and a drain electrode, the position of the hole is shifted from the source region and the drain region which should be opened. is there.
[0007]
Even if the position of the pattern is shifted by one patterning step, the shift is slight and allowable, and may not be a degree that adversely affects the operation of the completed display device. However, by increasing the number of times of the patterning process, a slight shift in the position of the pattern is amplified and increased, and the probability of occurrence of a defective product is increased.
[0008]
An object of the present invention is to improve the yield by reducing the number of patterning steps, reduce the number of photomasks, reduce the number of steps by combining a plurality of steps into one step, and shorten the manufacturing time. It is.
[0009]
[Means for Solving the Problems]
According to the present invention, an oxide film is formed by oxidizing the surface of the crystalline semiconductor using an aqueous solution of an oxidizing agent, for example, an aqueous solution of ozone or an aqueous solution of hydrogen peroxide. The feature is that the gate electrode, the source electrode, and the drain electrode of the field effect transistor are formed simultaneously from the same starting film. Further, the method is characterized in that after forming the gate electrode, the source electrode, and the drain electrode, heating is performed in an inert gas at 800 ° C. or higher for a predetermined time. The inert gas is a rare gas such as argon or nitrogen.
[0010]
The present invention also relates to a method for manufacturing a field effect transistor, comprising forming a first insulating film on a crystalline semiconductor, patterning the first insulating film, and forming a gate on a part of the crystalline semiconductor. An insulating film is formed, and the surface of the crystalline semiconductor is oxidized using an aqueous solution of an oxidizing agent, for example, an aqueous solution of ozone or an aqueous solution of hydrogen peroxide to form an oxide film, on the oxide film and on the gate insulating film. Forming a conductive film having a semiconductor layer containing an N-type impurity, patterning the conductive film to form a gate electrode, a source electrode, and a drain electrode simultaneously without etching the crystalline semiconductor; Using the source electrode and the drain electrode as a mask, an N-type impurity is introduced into the crystalline semiconductor. At this point, an oxide film exists between the source and drain electrodes and the crystalline semiconductor, and the oxide film is formed of SiO 2. _X (0 <X <2) and SiO ₂ Having. Then, the crystalline semiconductor, the oxide film, the gate insulating film, the gate electrode, the source electrode, and the drain electrode are heated in an inert gas, for example, nitrogen at 800 ° C. to 1050 ° C. for 30 minutes to 4 hours. By the heating, the N-type impurities contained in the source electrode and the drain electrode can be diffused into the crystalline semiconductor and the N-type impurities can be activated. Further, by the heating, the contact resistance between the source electrode and the crystalline semiconductor and the contact resistance between the drain electrode and the crystalline semiconductor are reduced. Further, a semiconductor layer containing a P-type impurity may be used instead of the semiconductor layer containing an N-type impurity, and a P-type impurity may be introduced instead of introducing the N-type impurity into the crystalline semiconductor.
[0011]
In the present invention, an oxide film formed by oxidizing the surface of a crystalline semiconductor using an aqueous solution of an oxidizing agent, for example, an aqueous solution of ozone or an aqueous solution of hydrogen peroxide, forms a gate electrode, a source electrode, and a drain electrode from a conductive film. Since it serves as an etching stopper for simultaneous formation, the crystalline semiconductor is not etched. It is known that ozone and hydrogen peroxide used for forming the oxide film are water-soluble and are oxidizing agents that oxidize other substances. In addition, a material having a melting point higher than the temperature of the heat treatment must be used for the conductive film. Any of metals having a melting point of 800 ° C. or more, such as copper, palladium, chromium, cobalt, titanium, molybdenum, niobium, tantalum, and tungsten, or cobalt silicide, titanium silicide, or silicide on crystalline silicon containing N-type impurities. The conductive film may be formed by stacking metal silicides such as molybdenum, niobium silicide, tantalum silicide, and tungsten silicide. Further, a configuration in which a metal nitride such as titanium nitride, tantalum nitride, and tungsten nitride is combined may be used.
[0012]
In the present invention, a crystalline semiconductor is a single crystal or polycrystalline semiconductor and is not limited to a thin film. In the case where a thin film is used as the crystalline semiconductor, a semiconductor film can be used in which a semiconductor film is formed over a substrate and the semiconductor film is crystallized to be a crystalline semiconductor film. In the present invention, since the heat treatment is performed at a temperature of 800 ° C. to 1050 ° C., a substrate that can be used must be a substrate that is not deformed by the heat treatment, such as a quartz substrate, a silicon substrate, and a stainless steel substrate.
[0013]
In the present invention, before forming a conductive film for forming a gate electrode, a source electrode, and a drain electrode, an N-type impurity is introduced into a crystalline semiconductor using a gate insulating film as a mask, and the gate electrode, the source electrode, After the formation of the drain electrode, a method of introducing an N-type impurity into the crystalline semiconductor again and performing a heat treatment at a temperature of 800 ° C. to 1050 ° C. can be adopted. In this case, a P-type impurity may be introduced instead of the N-type impurity. In this case, it is not always necessary to use a semiconductor containing an N-type impurity or a P-type impurity as a material for forming the conductive film.
[0014]
The above method for manufacturing a field-effect transistor can be employed for manufacturing a display device using the field-effect transistor. Examples of the display device include an active matrix driven liquid crystal display and an active matrix driven display using a light emitting element.
[0015]
Further, the present invention is a field-effect transistor manufactured by using the method for manufacturing a field-effect transistor, wherein the field-effect transistor includes an island-shaped crystalline semiconductor film formed above a substrate, A gate insulating film formed on a portion of the crystalline semiconductor film, a source electrode and a drain electrode formed on the crystalline semiconductor film, and a gate electrode formed on the gate insulating film The island-shaped crystalline semiconductor film has a source region, a drain region, a low-concentration impurity region (LDD region), and a channel region, and is provided between the source electrode and the source region and between the source electrode and the drain electrode. SiO between the region _X (0 <X <2).
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiment 1 Embodiment 1 of the present invention will be described with reference to FIGS. 1A to 1E, 2A to 2E, and 10A and 10B. .
[0017]
As shown in FIG. 1A, a first insulating film 102 is formed over a substrate 101 to have a thickness of 100 to 1000 nm. As the first insulating film 102, SiH ₄ , N ₂ O, and NH ₃ Silicon nitride oxide film formed by a CVD method using ₄ And N ₂ Any of a silicon oxynitride film, a silicon oxide film, a silicon oxide film containing nitrogen, and a silicon nitride film formed by a CVD method using O as a raw material may be used. You may. As the substrate 101, a quartz substrate, a silicon substrate, or a stainless steel substrate is used. When a quartz substrate is used, the first insulating film 102 need not be formed.
[0018]
Next, a semiconductor film 103 is formed to a thickness of 30 to 80 nm over the substrate 101 or the first insulating film 102. As the semiconductor film 103, any of a silicon film, a germanium film, and a film containing silicon and germanium may be used. As for the thickness of the semiconductor film, the thinner the thickness is in the range of 30 nm to 80 nm, the more effectively the off current of the thin film transistor is reduced.
[0019]
Next, the semiconductor film 103 is crystallized by a known method. As a means of crystallization, any of solid phase growth by heat treatment in an electric furnace, laser crystallization by irradiating a pulsed or continuous oscillation gas laser or solid laser, and RTA (Rapid Thermal Annealing) may be used. Further, in the case of using a method in which an element which promotes crystallization of a semiconductor film, for example, nickel is added to the semiconductor film 103 and heat treatment is performed during solid phase growth, the heating temperature can be reduced and the heating time can be reduced. This is effective because it can be performed, but it is necessary to getter nickel contained in the semiconductor film 103 after crystallization to remove as much as possible.
[0020]
At present, laser crystallization is being actively studied as a means of crystallizing a semiconductor film, and a laser used for crystallization is described in detail below.
[0021]
Examples of the gas laser include an excimer laser, an Ar laser, and a Kr laser, and examples of the solid laser include a YAG laser, a glass laser, a ruby laser, an alexandrite laser, and a Ti: sapphire laser.
[0022]
As a solid-state laser, YAG, YVO doped with Cr, Nd, Er, Ho, Ce, Co, Ti or Tm is used. ₄ , YLF, YAlO ₃ A laser using a crystal such as is applied. The fundamental wave of the laser depends on the material to be doped, and a laser beam having a fundamental wave of about 1 μm is obtained. Harmonics with respect to the fundamental wave can be obtained by using a nonlinear optical element.
[0023]
In order to obtain a crystal having a large grain size during crystallization of a semiconductor film, it is necessary to use a solid-state laser capable of continuous oscillation and apply the second, third, and fourth harmonics of a fundamental wave. preferable. Typically, Nd: YVO ₄ A second harmonic (532 nm) and a third harmonic (355 nm) of a laser (a fundamental wave of 1064 nm) are applied.
[0024]
Continuous oscillation YVO with output 10W ₄ The laser light emitted from the laser is converted into a harmonic by a nonlinear optical element. In addition, YVO ₄ There is also a method of emitting a harmonic by putting a crystal and a nonlinear optical element. Then, the laser light is preferably shaped into a rectangular or elliptical laser beam on the irradiation surface by an optical system, and the laser light is irradiated on the object to be processed. The energy density at this time is 0.1 to 100 MW / cm ² Degree (preferably 0.1 to 10 MW / cm ² )is necessary. Then, the semiconductor film is irradiated while being moved relatively to the laser light at a speed of about 0.5 to 2000 cm / s.
[0025]
The crystallized semiconductor film 103 is patterned by photolithography as shown in FIG. 1B to form an island-shaped crystalline semiconductor film 104. In this patterning, a first photomask is used.
[0026]
Next, as shown in FIG. 1C, a second insulating film 105 is formed with a thickness of 20 to 130 nm over the substrate 101 or the first insulating film 102 and the crystalline semiconductor film 104. As the second insulating film 105, SiH ₄ And N ₂ Any of a silicon oxynitride film, a silicon oxide film, a nitrogen-containing silicon oxide film, and a silicon nitride film formed by a CVD method using O as a raw material may be used. May be. Then, as shown in FIG. 1D, the second insulating film 105 is patterned by photolithography to expose a part of the surface of the crystalline semiconductor film 104 and to form an island-shaped second insulating film serving as a gate insulating film. Is formed. In this patterning, a second photomask is used. Note that before patterning the second insulating film 105, a P-type impurity, for example, boron may be introduced into the entire crystalline semiconductor film 104. This is performed in order to introduce a P-type impurity into a portion to be a channel region later, and is a known method called so-called channel doping.
[0027]
Next, after removing the natural oxide film from the surface of the island-shaped crystalline semiconductor film 104 exposed when the second insulating film 106 is formed with a diluted hydrofluoric acid solution, the surface is oxidized. An oxide film 107 is formed as shown in FIG. The oxide film 107 is formed by applying an oxidizing agent aqueous solution to a surface to be oxidized by a spin coating method. Specifically, while the substrate 101 on which at least the crystalline semiconductor film 104 and the second insulating film 106 are formed is rotated, ozone (O ₃ ) (Hereinafter referred to as ozone water) at room temperature for 30 to 120 seconds. Ozone is a gas at normal temperature and pressure, is water-soluble, and has a strong oxidizing effect. The water used as the solvent of the ozone water is pure water from which fine dust and impurities are removed, and the concentration of the ozone water is 8 to 15 mg / l. After that, the surface is washed with pure water to wash out ozone water, and then the substrate 101 is rotated and dried while blowing nitrogen.
[0028]
Since the oxide film 107 formed in this way is extremely thin, it is not easy to measure the exact film thickness, but it is in the range of 0.7 to 2.0 nm. It should be noted that the thickness of the oxide film to be formed does not change significantly even when the time for flowing ozone water (treatment time) is changed. 0.0 nm.
[0029]
In order to examine the composition of the oxide film due to ozone water, the chemical composition of the elements on the sample surface was determined for an oxide film formed by flowing 14 mg / l ozone water over the surface ((100) surface) of a silicon wafer at room temperature for 60 seconds. The spectrum of Si2p was measured by an analyzer called ESCA (Electron Spectroscopy for Chemical Analysis) or XPS (X-ray Photoelectron Spectroscopy) capable of specifying the bonding state. As a result, two peaks were observed in a binding energy range of 96 to 106 eV. One is Si ⁴⁺ And the other is a Si peak. The Si peak was detected from the silicon wafer because the thickness of the oxide film was small. Si ⁴⁺ Peak is Si ¹⁺ , Si ²⁺ , And Si ³⁺ Therefore, the waveform was decomposed by the Gaussian function and the Lorentz function. The oxidation state of silicon was analyzed based on these peak shapes. As a result, Si ¹⁺ , Si ²⁺ , Si ³⁺ , And Si ⁴⁺ When the total of ¹⁺ Is 8.8%, Si ²⁺ Is 8.8%, Si ³⁺ Is 6.4%, Si ⁴⁺ Was 76.0%. Where Si ¹⁺ , Si ²⁺ , And Si ³⁺ Is called a suboxide. Suboxide means a state in which silicon does not sufficiently react with oxygen and remains partially bonded to silicon. Si ⁴⁺ Is 100% and the suboxide is 0%, the oxide film is sufficiently oxidized and stable SiO 2 ₂ It can be said that it consists of. The oxide film formed on the surface of the silicon wafer by the ozone water is SiO 2 _X (0 <X <2) and SiO ₂ It can be expressed as a silicon oxide film composed of The thickness of the oxide film was measured with an analyzer called spectro-Ellipsometry, and was found to be 0.81 nm.
[0030]
As a comparative example, Si (OC, called TEOS) was formed on a silicon wafer. ₂ H ₅ ) ₄ And O ₂ The silicon oxide film formed by the CVD method using as a raw material was measured for the spectrum of Si2p by ESCA. Then, the same analysis as that of the oxide film formed by the ozone water was performed. As a result, Si ¹⁺ , Si ²⁺ , Si ³⁺ , And Si ⁴⁺ When the total of ¹⁺ 1.8%, Si ²⁺ Is 0.9%, Si ³⁺ Is 4.6%, Si ⁴⁺ Was 92.7%. That is, the silicon oxide film formed by the CVD method is more SiO 2 than the oxide film formed by the ozone water. ₂ Was found to be high.
[0031]
Next, as shown in FIG. 2A, a conductive film 108 is entirely formed over the substrate 101 (or over the first insulating film 102), over the oxide film 107, and over the island-shaped second insulating film 106. It is formed to a thickness of 200 to 500 nm. As the conductive film 108, a crystalline silicon film containing an N-type impurity is formed by a CVD method at a film formation temperature of 500 ° C. or higher. The formed crystalline silicon film is 1 × 10 ¹⁹ ~ 5 × 10 ²¹ cm ^-3 Of N-type impurities. An example of the N-type impurity is phosphorus. The conductive film 108 may have a multilayer structure. That is, a layer made of a heat-resistant material such as titanium, molybdenum, tungsten, molybdenum silicide, or tungsten silicide is formed over the crystalline silicon layer containing an N-type impurity, so that the conductive film 108 has low resistance. Is also good. If a titanium nitride, molybdenum nitride, or tungsten nitride layer is further provided between the crystalline silicon layer containing an N-type impurity and a titanium, molybdenum, or tungsten layer, the crystalline silicon layer containing an N-type impurity and a titanium, molybdenum, , Or with the tungsten layer.
[0032]
Next, as shown in FIG. 2B, a gate electrode 109, a source electrode 110, and a drain electrode 111 are formed at the same time by patterning the conductive film 108 by photolithography. At this time, the oxide film 107 serves as an etching stopper, and the crystalline semiconductor film 104 is not etched. In this patterning, a third photomask is used.
[0033]
Next, an N-type impurity, for example, phosphorus is introduced into the crystalline semiconductor film 104. The introduction method may be either an ion implantation method with mass separation or an ion doping method without mass separation. However, in the ion doping method, hydrogen is introduced in addition to the N-type impurity. When the N-type impurity is introduced, the N-type impurity is introduced into the first region of the crystalline semiconductor film 104 covered only by the oxide film 107 and the second region covered by only the second insulating film 106. The N-type impurity is not introduced into the lower region of the gate electrode 109. As a result, the concentration of the N-type impurity is lower in the second region than in the first region, and the second region is a low-concentration impurity region (LDD region) 112. The first region becomes part of the source region 113 and the drain region 114. A region under the gate electrode 109 and sandwiched between the low-concentration impurity regions (LDD regions) 112 becomes a channel region 115. By introducing the N-type impurity only once, the low-concentration impurity region (LDD region) 112 and the first region which is a part of the source region 113 and the drain region 114 may be formed. It is conceivable that the concentration of the N-type impurity introduced into the region becomes low to form the source region and the drain region. In that case, it is necessary to introduce the N-type impurity twice. Specifically, in the first introduction, a low-concentration impurity region (LDD region) 112 is formed at a high acceleration and at a low dose so that the N-type impurity is introduced below the second insulating film 106. In the second introduction, a first region to be a part of the source region 113 and the drain region 114 is formed at a lower acceleration and a higher dose than the first introduction. The order of the first introduction and the second introduction may be reversed.
[0034]
After the introduction of the N-type impurity as described above, the oxide film 107 still exists between the source electrode 110 and the drain electrode 111 and the crystalline semiconductor film 104. The thickness of the oxide film 107 is as extremely small as 0.7 to 2.0 nm as described above, but the contact resistance between the source electrode 110 and the drain electrode 111 and the crystalline semiconductor film 104 is large, which is not preferable. The oxide film 107 becomes unnecessary when the formation of the gate electrode 109, the source electrode 110, and the drain electrode 111 is completed. Therefore, even if oxygen is released from the oxide film to change to a film in which a large number of lattice defects are formed, a state in which the film does not form may be used, but it is more preferable.
[0035]
Therefore, in order to reduce the contact resistance between the source electrode 110 and the drain electrode 111 and the crystalline semiconductor film 104 and improve the electrical connection, at least the crystalline semiconductor film 104, the oxide film 107, the source electrode 110, and the drain electrode Heat 111 at 800 to 1050 ° C. in nitrogen. The atmosphere at the time of the heating is not limited to nitrogen, and may be any inert gas. The heating time is 30 minutes to 4 hours. If the heating temperature is 800 ° C., 2 to 4 hours are preferable, and if it is 950 ° C., it may be about 30 minutes. Note that the heating time should not be extended more than necessary to improve the throughput. The upper limit of the heating temperature is determined by the type of the substrate 101, the material of the conductive film 108, and the heating means. When stainless steel is used for the substrate 101, it should be noted that depending on the heating temperature and the heating time, the stainless steel may become brittle or impair the corrosion resistance.
[0036]
By the heating at 800 to 1050 ° C., the characteristics of the oxide film 107 change, and the oxide film 107 does not function as an etching stopper. Further, the damage of the crystalline silicon film 104 caused by the introduction of the N-type impurity is repaired, and the crystallinity of the amorphous portion and the region where the crystallization is insufficient when the semiconductor film 103 is crystallized is further improved. Then, phosphorus contained in the source electrode 110 and the drain electrode 111 diffuses into the crystalline semiconductor film 104. Due to this diffusion, an impurity region into which phosphorus has been introduced is also formed in a region below the source electrode 110 and the drain electrode 111 of the crystalline semiconductor film 104, and the impurity region and the first region into which phosphorus has already been introduced are formed. Are combined to form a source region 113 and a drain region 114.
[0037]
The inventor of the present application considers the reason why the characteristics of the oxide film 107 change as follows. Since the oxide film 107 does not function as an etching stopper by heating at 800 to 1050 ° C., oxygen is desorbed from the oxide film 107 and SiO 2 forming the oxide film 107 is removed. _X In the case of (0 <X ≦ 2), the value of “X” becomes small, and the case of “X = 0” is included. Therefore, the N-type impurity is easily diffused, and the electrical connection between the source electrode 110 and the drain electrode 111 and the crystalline semiconductor film 104 is improved.
[0038]
An experiment was conducted to clarify that the contact resistance changes due to the heat treatment. First, a sample for resistance measurement whose cross section is shown in FIG. In FIG. 10A, reference numeral 1001 denotes a quartz substrate, 1002 denotes an island-shaped crystalline silicon film containing phosphorus, 1003 denotes an oxide film, and 1004 denotes an electrode. The oxide film 1003 is formed by oxidizing the surface of the crystalline silicon film 1002 by treatment with ozone water, and the electrode 1004 is formed by sequentially stacking a crystalline silicon layer 1005 containing phosphorus, a tungsten nitride layer 1006, and a tungsten layer 1007. It was formed. In the actual sample for resistance measurement, a portion in which the crystalline silicon film 1002 is covered with the electrode 1004 (a portion in which the crystalline silicon film 1002 and the electrode 1004 are adjacent via the oxide film 1003) is continuous 1000 pieces. FIG. 10A shows only a part of the cross section of the sample.
[0039]
The contact resistance of each of the thus prepared samples was set to 8 when the heat treatment was further performed at 950 ° C. for 30 minutes as Condition 1 and when the heat treatment was not performed as Condition 2. The measured and plotted results are shown in FIG. The contact resistance in condition 1 is 1 × 10 ⁵ Ω ~ 1 × 10 ⁶ Ω, and the contact resistance under condition 2 is 1 × 10 ⁸ Ω ~ 1 × 10 ^Thirteen Ω range. The result shows that the effect of the heat treatment is that the contact resistance is smaller in the condition 1 in which the heat treatment is performed than in the condition 2 in which the heat treatment is not performed, and the variation of the contact resistance at eight points is smaller. ing. Note that, as described above, this sample is formed of 1000 continuous portions in which the crystalline silicon film 1002 is covered with the electrode 1004, and thus can be regarded as a series-connected 1000-stage resistor. Therefore, it should be noted that the contact resistance per part where the crystalline silicon film 1002 is covered with the electrode 1004 is 1/1000 of the value shown in FIG. That is, the contact resistance per one part where the crystalline silicon film 1002 is covered with the electrode 1004 is 1 × 10 ² ~ 1 × 10 ³ Ω, and 1 × 10 ⁵ Ω ~ 1 × 10 ¹⁰ Ω range.
[0040]
Next, as shown in FIG. 2C, a third insulating film 116 is formed to a thickness of 100 to 1000 nm. As the third insulating film, SiH ₄ And N ₂ Silicon oxynitride film formed by a CVD method using O as a raw material, SiH ₄ , N ₂ O, and NH ₃ May be any of a silicon nitride oxide film, a silicon oxide film, a silicon oxide film containing nitrogen, and a silicon nitride film formed by a CVD method using silicon as a raw material, or a combination of two or more of these films. May be. Thereafter, in order to activate N-type impurities contained in the crystalline semiconductor film 104, the gate electrode 109, the source electrode 110, and the drain electrode 111, the film is heated at 800 to 1050 ° C. for 30 minutes to 2 hours in nitrogen. Heat. At that time, hydrogen may be added to a nitrogen atmosphere, or after heat treatment in nitrogen, heating may be performed in an atmosphere containing nitrogen and hydrogen for about one hour. If the N-type impurity is sufficiently activated by the heating at 800 to 1050 ° C. performed to change the characteristics of oxide film 107, the N-type impurity is activated in nitrogen for activation here. May be omitted. Further, instead of performing the heat treatment at 800 to 1050 ° C. for 30 minutes to 4 hours in nitrogen before forming the third insulating film 116, 800 to 1050 ° C. in nitrogen after forming the third insulating film 116. For 30 minutes to 4 hours. In that case, the third insulating film 116 functions as a passivation film during heat treatment.
[0041]
Next, as shown in FIG. 2D, a fourth insulating film 117 is formed over the third insulating film 116 in order to obtain a flat surface. As the fourth insulating film 117, an organic resin film such as a polyimide resin, an acrylic resin, or benzocyclobutene (BCB), or a silicon oxide film formed by a coating method called SOG (Spin On Glass) can be used. Good. The surface of an inorganic insulating film such as a silicon oxide film may be polished by a known chemical mechanical polishing method (CMP) to form a fourth insulating film 117. Then, the third insulating film 116 and the fourth insulating film 117 are patterned by photolithography to form a hole 118 reaching the drain electrode 111 (or the source electrode 110). In this patterning, a fourth photomask is used.
[0042]
Next, as shown in FIG. 2E, a transparent conductive film is formed over the entire surface of the fourth insulating film 117 to have a thickness of 50 to 150 nm, and then patterned by a known photolithography method to form a pixel electrode 119. The transparent conductive film may be any of tin oxide, a compound called indium tin oxide (ITO) composed of indium oxide and tin oxide, and a compound composed of indium oxide and zinc oxide. In this patterning, a fifth photomask is used.
[0043]
In this embodiment mode, the number of times of patterning is three in the process until the source electrode 110 and the drain electrode 111 are formed, and three photomasks are used. On the other hand, in the process described in the section of [Prior Art], the number of times of patterning until formation of the source electrode and the drain electrode is four, and four photomasks are used. Therefore, in this embodiment, it is possible to reduce the number of photomasks by one in the patterning step and one in comparison with the related art. In this embodiment mode, the gate electrode 109, the source electrode 110, and the drain electrode 111 are formed at the same time using only one photomask, and thus have the following effects. That is, the gap between the gate electrode 109 and the source electrode 110 and the gap between the gate electrode 109 and the drain electrode 111 can be easily changed. Although the minimum value of the gap is determined by the design rule, the gap can be made as small as possible according to the design rule without considering the margin. Therefore, the size of the transistor can be reduced and the integration of the transistor can be increased. Further, the area of the portion where the source electrode 110 covers the source region 113 and the area of the portion where the drain electrode 111 covers the drain region 114 can be easily changed so as to obtain optimal electric characteristics.
[0044]
(Embodiment 2) In Embodiment 1 of the present invention, a crystalline silicon film containing an N-type impurity is used as the conductive film 108 for forming the gate electrode 109, the source electrode 110, and the drain electrode 111. In the embodiment, a crystalline silicon film containing an N-type impurity may not be used as the conductive film. This embodiment mode is different from the first embodiment mode in that an N-type impurity or a P-type impurity is introduced into the crystalline semiconductor film 104 using the second insulating film 106 as a mask before forming the conductive film 108. Is different from In the present embodiment, since the processes corresponding to FIGS. 1A to 1D are common to the first embodiment of the present invention, only the processes after FIG. This will be described below using (E).
[0045]
1D, an N-type impurity, for example, phosphorus is introduced into the crystalline semiconductor film 104 using the island-shaped second insulating film 106 as a mask. At this time, an N-type impurity is not introduced into a portion covered with the second insulating film 106, and an impurity is introduced into a portion not covered with the second insulating film 106, so that a source region 313 and a drain region 314 are formed. Is done. The method for introducing the N-type impurity may be any of an ion implantation method with mass separation and an ion doping method without mass separation. In this embodiment, a P-type impurity, for example, boron can be used instead of the N-type impurity. Thereafter, an oxide film 307 is formed by the same method as in Embodiment 1 of the present invention, as shown in FIG.
[0046]
Next, as shown in FIG. 3A, a conductive film 308 is formed over the entire surface of the substrate 101 or the first insulating film 102, the oxide film 307, and the second insulating film 106 to have a thickness of 200 to 500 nm. . The conductive film 308 may be any of copper, palladium, chromium, cobalt, titanium, molybdenum, niobium, tantalum, tungsten, and the like. , Tantalum silicide, tungsten silicide, or the like. Further, similarly to Embodiment 1 of the present invention, in this embodiment, crystalline silicon containing an N-type impurity can be used as at least a part of the material for forming the conductive film 308.
[0047]
Next, as shown in FIG. 3B, the conductive film 308 is patterned by a photolithography method, so that a gate electrode 309, a source electrode 310, and a drain electrode 311 are formed at the same time. At that time, the oxide film 307 serves as an etching stopper, and the crystalline semiconductor film 104 is not etched.
[0048]
Next, an N-type impurity, for example, phosphorus is introduced again into the region of the crystalline semiconductor film 104 which is covered only by the second insulating film 106, and the N-type impurity concentration is lower than that of the source region 313 and the drain region 314. A concentration impurity region (LDD region) 312 is formed. An N-type impurity is not introduced into a region below the gate electrode 309 and sandwiched between the low-concentration impurity regions (LDD regions) 312, and the region becomes a channel region 315. Instead of the N-type impurity, a P-type impurity can be used. Then, at least the crystalline semiconductor film 104, the oxide film 307, the source electrode 310, and the drain electrode 311 are heated in nitrogen at 800 to 1050 ° C. for 30 minutes to 4 hours. The atmosphere at the time of the heating is not limited to nitrogen, and may be any inert gas. By the heating, the contact resistance between the source electrode 310 and the source region 313 and the contact resistance between the drain electrode 311 and the drain region 314 are reduced.
[0049]
Next, as shown in FIG. 3C, a third insulating film 316 is formed to a thickness of 100 to 1000 nm. As the third insulating film 316, SiH ₄ And N ₂ Silicon oxynitride film formed by a CVD method using O as a raw material, SiH ₄ , N ₂ O, and NH ₃ May be any one of a silicon nitride oxide film, a silicon oxide film, and a silicon nitride film formed by a CVD method using silicon as a raw material, or may be formed by combining two or more of these films. Further, instead of performing heat treatment at 800 to 1050 ° C. in nitrogen for 30 minutes to 4 hours before forming the third insulating film 316, 800 to 1050 ° C. in nitrogen after forming the third insulating film 316. For 30 minutes to 4 hours.
[0050]
Next, as shown in FIG. 3D, a fourth insulating film 317 for planarization is formed over the third insulating film 316 to a thickness of 1000 to 4000 nm. As the fourth insulating film 317, a polyimide resin, an acrylic resin, benzocyclobutene (BCB), or a silicon oxide film (SOG) formed by a coating method is used. Then, the third insulating film 316 and the fourth insulating film 317 are patterned by photolithography to form a hole 318 reaching the drain electrode 311 (or the source electrode 310).
[0051]
Next, as shown in FIG. 3E, a pixel electrode 319 is formed by forming a transparent conductive film over the entire surface of the fourth insulating film 317 and then patterning the same by photolithography. The transparent conductive film may be any of tin oxide, a compound called indium tin oxide (ITO) composed of indium oxide and tin oxide, and a compound composed of indium oxide and zinc oxide.
[0052]
In this embodiment as well as in the first embodiment of the present invention, in the process up to the formation of the source electrode 310 and the drain electrode 311, the patterning process is performed three times, and three photomasks are used. Therefore, the number of patterning steps can be reduced by one and the number of photomasks can be reduced by one compared with the prior art. In addition, since the gate electrode 309, the source electrode 310, and the drain electrode 311 are simultaneously formed using only one photomask, the following effects are obtained. That is, the gap between the gate electrode 309 and the source electrode 310 and the gap between the gate electrode 309 and the drain electrode 311 can be made as small as possible according to design rules. Therefore, the size of the transistor can be reduced and the integration of the transistor can be increased. Further, the area of a portion where the source electrode 310 covers the source region 313 and the area of a portion where the drain electrode 311 covers the drain region 314 can be easily changed so as to obtain optimal electric characteristics.
[0053]
(Embodiment 3) In Embodiment 1 of the present invention, ozone water is used to form oxide film 107. In this embodiment, hydrogen peroxide (H ₂ O ₂ ) (Hereinafter referred to as aqueous hydrogen peroxide in the present specification). Only the differences from the first embodiment of the present invention will be described below.
[0054]
While rotating the substrate 101 on which at least the crystalline semiconductor film 104 and the second insulating film 106 are formed, a hydrogen peroxide solution at room temperature or 80 ° C. is continuously supplied to the surface of the crystalline semiconductor film 104 for 30 to 600 seconds. As the hydrogen peroxide solution, a solution having a concentration of 30 to 35 wt%, for example, 31 wt% is used. Hydrogen peroxide is liquid at normal temperature and pressure, is water-soluble, and has an oxidizing effect. As the water used as the solvent, pure water similar to the case of ozone water is used.
[0055]
Since the oxide film formed in the present embodiment is also extremely thin similarly to the first embodiment of the present invention, it is not easy to accurately measure the film thickness. In the case of processing at 0.7 to 1.5 nm and 80 ° C., the range is 1.0 to 2.0 nm. Note that there is no significant change in the thickness of the formed oxide film even when the time (treatment time) for flowing the hydrogen peroxide solution is changed.
[0056]
Subsequent processes are the same as those of the first embodiment of the present invention. However, as shown in the second embodiment, the conductive film 108 is made of copper, palladium, chromium, cobalt, titanium, molybdenum, niobium, tantalum, tungsten, or the like. And any combination of titanium nitride, tantalum nitride, tungsten nitride, cobalt silicide, titanium silicide, molybdenum silicide, niobium silicide, tantalum silicide, tungsten silicide, etc., without using a crystalline silicon film containing N-type impurities You may. In that case, the process described in Embodiment Mode 2 may be followed.
[0057]
(Embodiment 4) In Embodiment 1 of the present invention, a first insulating film 102 is formed on a substrate 101. In this embodiment, a light-shielding film is provided between the substrate 101 and the first insulating film 102. Is provided. Only the differences from the first embodiment of the present invention will be described below with reference to FIGS.
[0058]
As shown in FIG. 4A, a light-shielding film 400 is formed over the substrate 101 to have a thickness of 100 to 300 nm. The light-shielding film 400 is provided so as not to irradiate the crystalline semiconductor film 104 formed later with light, and is patterned in an island shape so as to overlap at least a channel region of the crystalline semiconductor film 104. As the light-blocking film 400, a film of chromium, tungsten, molybdenum, niobium, tantalum, titanium, titanium silicide, molybdenum silicide, niobium silicide, tantalum silicide, tungsten silicide, or the like may be used. Further, a so-called polycide structure in which a metal silicide film such as tungsten silicide is stacked on a crystalline silicon film containing an N-type impurity may be used. If the light-blocking film 400 is a film having conductivity, it can function as a gate electrode.
[0059]
Next, as in Embodiment 1, as illustrated in FIG. 4B, a first insulating film 102, an island-shaped crystalline semiconductor film 104, and a second insulating film 105 are formed. P-type impurities are introduced into 104 for channel doping. When the first insulating film 102 is formed, the thickness of the first insulating film 102 is formed to be larger than the thickness of the light shielding film 400, and the first insulating film is formed by a known chemical mechanical polishing method (CMP). The surface of 102 may be polished and flattened.
[0060]
Next, as shown in FIG. 4C, the second insulating film 105 and the first insulating film 102 are patterned by photolithography to form a hole 401. The hole 401 is formed to electrically connect the gate electrode 109 to be formed later and the light-shielding film 400, and is not formed in the crystalline semiconductor film 104. This hole is not opened if the light shielding film 400 is a film having no conductivity. Then, the second insulating film 105 is patterned by photolithography to form an island-shaped second insulating film 106.
[0061]
Subsequent processes are the same as those in Embodiment 1 of the present invention, and may be performed in accordance with FIG. 1E and FIGS. 2A to 2E. As a method for forming oxide film 107, a hydrogen peroxide solution may be used as described in Embodiment Mode 3. When the conductive film 108 is formed, the conductive film 108 must be formed so as to completely fill the hole 401. As described in Embodiment 2, any of copper, palladium, chromium, cobalt, titanium, molybdenum, niobium, tantalum, tungsten, and the like, and titanium nitride, tantalum nitride, tungsten nitride, cobalt silicide, A structure in which titanium silicide, molybdenum silicide, niobium silicide, tantalum silicide, tungsten silicide, or the like is used, and a crystalline silicon film containing an N-type impurity may not be used. In that case, the process described in Embodiment Mode 2 may be followed.
[0062]
An example in which the above-described embodiment of the present invention is made more concrete is shown below.
[0063]
【Example】
Example 1 In this example, a method for manufacturing an active matrix driven liquid crystal display (AMLCD) employing Embodiments 1 and 4 of the present invention will be described with reference to FIGS. 5A to 5E and 6A. ) To (D) and FIGS. 7A to 7C. First, as shown in FIG. 5A, a crystalline silicon film and a tungsten silicide film are formed over a quartz substrate 501 by a known method. In this embodiment, SiH ₄ And PH ₃ Is used as a raw material, a crystalline silicon film is formed by an LPCVD method at a film formation temperature of 600 ° C., and a tungsten silicide film is formed thereon by sputtering a target made of tungsten and silicon with argon ions. Tungsten silicide film may be formed by other methods, for example, WF ₆ And SiH ₂ Cl ₂ May be formed by a CVD method using as a raw material. Then, the crystalline silicon film and the tungsten silicide film are patterned by photolithography to form a first light-shielding film 502.
[0064]
Next, as shown in FIG. 5B, a silicon oxynitride film 503 is ₄ And N ₂ A silicon oxide film 504 is formed by a plasma CVD method using O as a raw material, and further, by a LPCVD method at a film formation temperature of 800 ° C. and a reduced pressure in the reaction chamber. Here, the silicon oxynitride film 503 is formed in order to prevent the LPCVD apparatus used for forming the silicon oxide film 504 next from being contaminated with the material forming the light-blocking film 502. If there is no concern about contamination of the LPCVD apparatus, the silicon oxynitride film 503 may be omitted. The silicon oxynitride film 503 and the silicon oxide film 504 correspond to the first insulating film 102 in Embodiment Modes 1 and 4 of the present invention. Then, a silicon film 505 is formed over the silicon oxide film 504 by an LPCVD method.
[0065]
Next, a solution containing nickel which is an element for accelerating crystallization of the silicon film, in this embodiment, a nickel acetate solution is applied onto the silicon film 505 by rotating the quartz substrate 501 by spin coating, Then, while rotating the quartz substrate 501, the excess nickel acetate solution is removed and dried. Then, in order to release hydrogen contained in the silicon film 505 from the film, the silicon film is heated at 450 ° C. for 1 hour in an electric furnace. Further, the silicon film 505 is crystallized by heating at 600 ° C. for 12 hours in an electric furnace.
[0066]
As a method for crystallizing the silicon film 505, the following method may be used. That is, a solid laser (Nd: YVO) formed into a rectangular shape ₄ The silicon film 505 is irradiated with the second harmonic (532 nm) of a laser. Light having a wavelength of 532 nm is hardly absorbed by the quartz substrate 501 but is absorbed by the silicon film 505. Crystallization by laser irradiation can shorten the time required for crystallization of the silicon film, rather than crystallization by heating in an electric furnace. In that case, the step of applying a solution containing nickel and the gettering step described below may be omitted.
[0067]
Next, nickel contained in the crystallized silicon film 505 must be gettered and removed. First, a silicon oxide film is formed on the crystallized silicon film 505 by LPCVD at a film formation temperature of 400 ° C., and is patterned by photolithography to form a mask 506 as shown in FIG. To form This mask 506 is for introducing phosphorus into only a part of the crystallized silicon film 505.
[0068]
Next, phosphorus is applied to the crystallized silicon film 505 from the mask 506 at 10 kV and 2 × 10 ^Fifteen cm ^-2 Is introduced by ion doping under the conditions described above, and phosphorus is introduced into the region 507. Thereafter, when the film is heated in nitrogen at 700 ° C. for 12 hours, nickel in the crystallized silicon film 505 moves and collects in the region 507.
[0069]
Next, as shown in FIG. 5D, the mask 506 is removed by etching, and the silicon film 505 crystallized by photolithography is patterned to form an island-shaped crystalline silicon film 508. At that time, the region 507 is completely removed. Further, the crystalline silicon film 508 is made to completely overlap with the light-shielding film 502.
[0070]
Next, as shown in FIG. ₄ And N ₂ A silicon oxynitride film 509 is formed by a plasma CVD method using O as a raw material. Then, 60 kV, 3.6 × 10 5 ^Thirteen cm ^-2 Channel doping is performed by introducing boron under the following conditions.
[0071]
Next, as shown in FIG. 6A, a hole 510 reaching the light-shielding film 502 is formed in the silicon oxynitride film 503, the silicon oxide film 504, and the silicon oxynitride film 509 by photolithography. I do. The holes 510 are not opened in the crystalline silicon film 508. Then, the silicon oxynitride film 509 is patterned by photolithography to form an island-shaped gate insulating film 511.
[0072]
Next, as shown in FIG. 6B, a silicon oxide film 512 is formed over the surface of the crystalline silicon film 508. As a method for forming the silicon oxide film 512, the method described in Embodiment 1 of the present invention is used. That is, the natural oxide film is removed with a diluted hydrofluoric acid solution from the surface of the crystalline silicon film 508 exposed when the gate insulating film 511 is formed, and then the light shielding film 502 and the silicon oxynitride film 503 are formed by spin coating. While rotating the quartz substrate 501 on which the silicon oxide film 504, the crystalline silicon film 508, and the gate insulating film 511 are formed, ozone water having a concentration of 14 mg / l is applied to the surface of the crystalline silicon film 508 at room temperature for 60 hours. Keep flowing for seconds. After that, the surface is washed with pure water to remove ozone water, and then the substrate 501 is rotated and dried while blowing nitrogen. The formed silicon oxide film 512 is made of Si ¹⁺ , Si ²⁺ , Si ³⁺ , And Si ⁴⁺ Having. In other words, SiO _X (0 <X <2) and SiO ₂ Having.
[0073]
Next, as shown in FIG. ₄ And PH ₃ Is used as a raw material, a crystalline silicon film 513 containing phosphorus is formed over the silicon oxide film 504, the silicon oxide film 512, and the gate insulating film 511 by an LPCVD method at a film formation temperature of 600 ° C.
[0074]
Next, as shown in FIG. 6D, the crystalline silicon film 513 containing phosphorus is patterned by photolithography, and a gate electrode 514, a source electrode 515, and a drain electrode 516 are formed at the same time. As an etching method at the time of patterning, wet etching using an alkaline solution is used. Since the silicon oxide film 512 functions as an etching stopper, the crystalline silicon film 508 is not etched.
[0075]
Next, phosphorus is introduced into the crystalline silicon film 508 by an ion doping method. First, in order to form the low-concentration impurity region (LDD region) 517, a region of the crystalline silicon film 508 that is covered only with the gate insulating film 511 has a voltage of 60 kV and 5 × 10 ^Thirteen cm ^-2 Phosphorus is introduced under the following conditions. Then, in order to form the source region 519 and the drain region 520, a region of the crystalline silicon film 508 covered with only the silicon oxide film 512 has a potential of 50 kV, 2 × 10 ^Fifteen cm ^-2 Phosphorus is introduced under the following conditions. Phosphorus is not introduced into a region under the gate electrode 514 and sandwiched between the low-concentration impurity regions (LDD regions) 517, and the region becomes a channel region 518. Note that after forming the gate insulating film 511 and before forming the silicon oxide film 512, phosphorus may be introduced into the crystalline silicon film 508 in order to form the source region 519 and the drain region 520. In that case, the step of introducing phosphorus for forming the source region 519 and the drain region 520, which is performed after the formation of the low-concentration impurity regions (LDD regions) 517, is unnecessary.
[0076]
After the phosphorus is introduced as described above, the silicon oxide film 512 still exists between the source region 519 and the source electrode 515 and between the drain region 520 and the drain electrode 516. In addition, phosphorus is not introduced into a portion of the source region 519 covered with the source electrode 515 and a portion of the drain region 520 covered with the drain electrode 516 at a concentration enough to form the source and drain regions. Therefore, the substrate 501 on which at least the crystalline silicon film 508, the silicon oxide film 512, the source electrode 515, and the drain electrode 516 are formed is heated in an electric furnace at 950 ° C. for 30 minutes in nitrogen. Phosphorus is diffused from the drain electrode 516 to the source region 519 and the drain region 520. By the heating, the contact resistance between the source region 519 and the source electrode 515 and the contact resistance between the drain region 520 and the drain electrode 516 are reduced.
[0077]
Next, as shown in FIG. ₄ And N ₂ A silicon oxynitride film is formed by a plasma CVD method using O as a raw material, and this is used as an interlayer insulating film 521. After that, the substrate is heated at 950 ° C. for 30 minutes in nitrogen in order to activate N-type impurities contained in the crystalline silicon film 508, the gate electrode 514, the source electrode 515, and the drain electrode 516. Then, the film is heated at 350 ° C. for one hour in hydrogen, and a dangling bond (a kind of point defect) in silicon constituting the crystalline silicon film 508, the gate electrode 514, the source electrode 515, and the drain electrode 516 is hydrogenated. Terminate.
[0078]
Next, as shown in FIG. 7B, an acrylic resin film is formed as a planarizing film 522 over the interlayer insulating film 521. acrylic resin film Instead, a polyimide resin film, a benzocyclobutene (BCB) film, or a silicon oxide film (SOG) formed by a coating method may be used.
[0079]
Next, as shown in FIG. 7C, in order to form the second light-shielding film 523, a film made of an alloy of aluminum and titanium is formed by sputtering, and is patterned by photolithography. In this embodiment, if the second light-shielding film 523 has light-shielding properties and conductivity, instead of an alloy of aluminum and titanium, a metal film such as chromium or a conductive polymer (a polymer material having conductivity) is used. Alternatively, an electrically conductive resin (a mixture of a resin and a conductive material such as metal or carbon) may be formed. Since the insulating film 524 is formed on the second light-shielding film 523, ₄ , N ₂ O, and NH ₃ A silicon nitride oxide film is formed by a plasma CVD method using as a raw material. Then, the first interlayer insulating film 521, the planarizing film 522, and the insulating film 524 are patterned by photolithography to form holes reaching the drain electrode 516 (or the source electrode 515). Then, a transparent conductive film made of ITO is formed on the insulating film 524 by a sputtering method, and is patterned to form a pixel electrode 525. In this embodiment, as the transparent conductive film, instead of ITO, tin oxide or a compound composed of indium oxide and zinc oxide can be used.
[0080]
As is clear from FIG. 7C, a capacitor is formed by the second light-blocking film 523 and the pixel electrode 525, which are conductive films, and the insulating film 524 between them.
[0081]
As described above, the processes described in this embodiment are completed until the pixel electrodes are formed on the substrate of the active matrix liquid crystal display on which the TFT is formed. Thereafter, the liquid crystal display may be completed by a known method.
[0082]
Embodiment 2 In this embodiment, another method for gettering nickel contained in the crystallized silicon film 505 shown in Embodiment 1 of the present invention will be described. Only the differences between the present embodiment and the first embodiment of the present invention will be described below.
[0083]
This embodiment is the same as the first embodiment of the present invention until a nickel acetate solution is applied to the silicon film 505 shown in FIG. 5B and the silicon film 505 is heated to be crystallized.
[0084]
Next, the natural oxide film is removed from the surface of the crystallized silicon film 505 with a dilute hydrofluoric acid solution, and using ozone water by the same method as in the first embodiment of the present invention, as shown in FIG. An oxide film 806 is formed. Then, an amorphous silicon film 807 is formed over the silicon oxide film 806 by an LPCVD method, and argon, which is a rare gas element, is introduced into the amorphous silicon film 807. Helium, neon, krypton, or xenon may be used instead of argon.
[0085]
Next, heating is performed at 550 ° C. for 4 hours in an electric furnace. By this heating, nickel contained in the crystallized silicon film 505 passes through the silicon oxide film 806, moves to the amorphous silicon film 807 into which argon is introduced, and is gettered. The heating temperature may be 550 ° C. or higher, and the upper limit is determined by the performance of the furnace used and the type of substrate. If the heating temperature is increased, gettering is possible even if the heating time is shorter than 4 hours.
[0086]
Next, the amorphous silicon film 807 is removed by wet etching using an alkaline solution. At this time, since the silicon oxide film 806 functions as an etching stopper, the crystallized silicon film 505 is not etched. Thus, the concentration of nickel in the crystallized silicon film 505 is set to 1 × 10 ¹⁷ cm ^-3 It can be reduced to:
[0087]
Next, as shown in FIG. 8B, the crystallized silicon film 505 is patterned by photolithography to form an island-shaped crystalline silicon film 808. The silicon oxide film 806 exists only on the upper surface of the island-shaped crystalline silicon film 808 and does not exist on the side surface.
[0088]
Next, as shown in FIG. 8C, a hole 810 and an island-shaped gate insulating film 811 are formed by the same method as in the first embodiment of the present invention. When the island-shaped gate insulating film 811 is formed by patterning, a portion of the silicon oxide film 806 that is not covered with the gate insulating film 811 is etched. Therefore, a silicon oxide film 812 as shown in FIG. 8D is formed again using ozone water by the same method as in the first embodiment of the present invention.
[0089]
Subsequent processes are the same as those in the first embodiment of the present invention, and thus may be performed according to FIGS. 6 (7C) to 6 (D) and FIGS.
[0090]
(Embodiment 3) In this embodiment, an active matrix driven display using a light emitting element manufactured by employing Embodiment Modes 1 and 2 of the present invention will be described.
[0091]
FIG. 9 is a cross-sectional view of a pixel portion of the display. Usually, one switching TFT connected to the gate signal line and the source signal line and one current control (also referred to as drive) TFT connected to the light emitting element are provided for each pixel. Only the TFT is shown. The driving TFT may be an N-channel type or a P-channel type. In this embodiment, the driving TFT is a P-channel type TFT.
[0092]
On a quartz substrate 901, a first insulating film 902, an island-shaped crystalline silicon film 903, and an island-shaped gate insulating film 904 which is a second insulating film are provided, and a gate electrode 905, a source electrode 906, A drain electrode 907 is provided. The gate electrode 905, the source electrode 906, and the drain electrode 907 are made of the same conductive material. The island-shaped crystalline silicon film 903 has a source region, a drain region, and a low-concentration impurity region (LDD region) containing boron as a P-type impurity, and is formed between the source electrode 906 and the source region and between the source electrode 906 and the drain electrode. Not shown between the drain region 907 and the drain region. _X (0 <X <2). SiO _X (0 <X <2) may be in the form of a film or may not be in the form of a film.
[0093]
Further, a third insulating film 908 and a planarizing film 909 are provided to cover the gate electrode 905, the source electrode 906, and the drain electrode 907, and the drain electrode 907 is provided with a transparent conductive film having a large work function (ITO). ) Is connected thereto, and a fourth insulating film 911 is provided thereon. The fourth insulating film 911 is opened to expose a part of the surface of the anode 910.
[0094]
Further, an organic compound layer 912 including a light-emitting body and a cathode 913 made of a metal or an alloy (an alloy of Mg and Ag) having a small work function are provided over the fourth insulating film 911 in contact with the anode 910. The anode 910, the organic compound layer 912 including a light-emitting body, and the cathode 913 together form a light-emitting element. The active matrix drive display using the light emitting element in this embodiment is a bottom emission type in which light is emitted from the light emitting element toward the quartz substrate 901.
[0095]
Embodiment 4 In this embodiment, examples of various products incorporating the display device manufactured according to the present invention will be described. The display device is an active matrix driven liquid crystal display or an active matrix driven display using light emitting elements.
[0096]
Although not particularly shown, the display device manufactured according to the present invention includes a notebook personal computer, a mobile phone, a digital camera, a video camera, a personal digital assistant (PDA), a television receiver, an in-vehicle navigation system, a head mounted display, and the like. This is applied to the display unit of the electronic device. Further, the present invention is applied to a display device incorporated in a front projector or a rear projector.
[0097]
【The invention's effect】
The present invention is based on the observation of an oxide film formed by treating the surface of a semiconductor film with ozone water or hydrogen peroxide solution. With the use of the oxide film as an etching stopper, the gate electrode, the source electrode, and the drain electrode of the field-effect transistor can be formed simultaneously with only one patterning using one photomask. Therefore, the gap between the gate electrode and the source electrode and the gap between the gate electrode and the drain electrode can be made as small as possible, and furthermore, the area of the portion where the source electrode covers the source region and the area of the portion where the drain electrode covers the drain region. Can be easily changed. Further, in the present invention, patterning for opening a hole in the interlayer insulating film is not necessary for connecting the source electrode to the source region and the drain electrode to the drain region. After forming the gate electrode, the source electrode, and the drain electrode, by performing heat treatment at a high temperature of 800 ° C. or higher for a predetermined time, even if the oxide film remains, electrical connection between the source electrode and the source region, The electrical connection between the electrode and the drain region is improved.
[0098]
According to the present invention, the number of patterning steps and the number of photomasks can be reduced, and throughput and yield can be improved. The present invention can be applied to various products in which an active matrix driven liquid crystal display or an active matrix driven display using a light-emitting element is incorporated in a display portion of an electronic device or in an electronic device.
[0099]
The present invention is not limited to a thin film transistor using a crystalline semiconductor film as shown in FIGS. 1 to 9, but is also applied to a field effect transistor formed on a silicon substrate. be able to.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view illustrating Embodiment 1 of the present invention.
FIG. 2 is a cross-sectional view illustrating Embodiment 1 of the present invention.
FIG. 3 is a sectional view illustrating Embodiment 2 of the present invention.
FIG. 4 is a sectional view illustrating Embodiment 4 of the present invention.
FIG. 5 is a sectional view illustrating Embodiment 1 of the present invention.
FIG. 6 is a sectional view illustrating Embodiment 1 of the present invention.
FIG. 7 is a cross-sectional view illustrating Embodiment 1 of the present invention.
FIG. 8 is a sectional view illustrating a second embodiment of the present invention.
FIG. 9 is a sectional view illustrating a third embodiment of the present invention.
FIG. 10 is a diagram showing the effect of the heat treatment of the present invention.
[Explanation of symbols]
101 quartz substrate
102 First insulating film
103 semiconductor film
104 island-shaped crystalline semiconductor film
105 Second insulating film
106 island-shaped second insulating film (gate insulating film)
107 oxide film
108 conductive film
109 Gate electrode
110 source electrode
111 drain electrode
112 Low concentration impurity region (LDD region)
113 source area
114 Drain region
115 channel area
116 third insulating film
117 fourth insulating film
118 holes
119 pixel electrode

Claims (8)

Forming a first insulating film on the crystalline semiconductor,
Patterning the first insulating film to form a gate insulating film on a portion of the crystalline semiconductor;
Oxidizing the surface of the crystalline semiconductor using ozone water or hydrogen peroxide to form an oxide film,
Forming a conductive film having a semiconductor layer containing an N-type impurity on the oxide film and the gate insulating film;
The oxide film is used as an etching stopper for preventing the crystalline semiconductor from being etched, and the conductive film is patterned to form a gate electrode, a source electrode, and a drain electrode simultaneously,
Introducing an N-type impurity into the crystalline semiconductor using the gate electrode, the source electrode, and the drain electrode as a mask,
The electric field wherein the crystalline semiconductor, the oxide film, the gate insulating film, the gate electrode, the source electrode, and the drain electrode are heated in an inert gas at 800 ° C. to 1050 ° C. for 30 minutes to 4 hours. Manufacturing method of effect type transistor. Forming a semiconductor film on the substrate,
Crystallizing the semiconductor film to form a crystalline semiconductor film,
Patterning the crystalline semiconductor film to form an island-shaped crystalline semiconductor film,
Forming a first insulating film on the island-shaped crystalline semiconductor film;
Patterning the first insulating film to form a gate insulating film on a part of the island-shaped crystalline semiconductor film;
Oxidizing the surface of the island-shaped crystalline semiconductor film using ozone water or hydrogen peroxide water to form an oxide film,
Forming a conductive film having a semiconductor layer containing an N-type impurity on the substrate, the oxide film, and the gate insulating film;
The oxide film is used as an etching stopper for preventing the island-shaped crystalline semiconductor film from being etched, and the conductive film is patterned to form a gate electrode, a source electrode, and a drain electrode simultaneously,
N-type impurities are introduced into the island-shaped crystalline semiconductor film using the gate electrode, the source electrode, and the drain electrode as a mask,
The substrate on which at least the island-shaped crystalline semiconductor film, the oxide film, the gate insulating film, the gate electrode, the source electrode, and the drain electrode are formed is heated at 800 ° C. to 1050 ° C. for 30 minutes in an inert gas. A method for manufacturing a field-effect transistor, comprising heating for 4 to 4 hours. Forming a first insulating film on the crystalline semiconductor,
Patterning the first insulating film to form a gate insulating film on a portion of the crystalline semiconductor;
N-type impurities are introduced into the crystalline semiconductor using the gate insulating film as a mask,
Oxidizing the surface of the crystalline semiconductor using ozone water or hydrogen peroxide to form an oxide film,
Forming a conductive film on the oxide film and the gate insulating film;
The oxide film is used as an etching stopper for preventing the crystalline semiconductor from being etched, and the conductive film is patterned to form a gate electrode, a source electrode, and a drain electrode simultaneously,
Introducing an N-type impurity into the crystalline semiconductor using the gate electrode, the source electrode, and the drain electrode as a mask,
The electric field wherein the crystalline semiconductor, the oxide film, the gate insulating film, the gate electrode, the source electrode, and the drain electrode are heated in an inert gas at 800 ° C. to 1050 ° C. for 30 minutes to 4 hours. Manufacturing method of effect type transistor. Forming a semiconductor film on the substrate,
Crystallizing the semiconductor film to form a crystalline semiconductor film,
Patterning the crystalline semiconductor film to form an island-shaped crystalline semiconductor film,
Forming a first insulating film on the island-shaped crystalline semiconductor film;
Patterning the first insulating film to form a gate insulating film on a part of the island-shaped crystalline semiconductor film;
N-type impurities are introduced into the island-shaped crystalline semiconductor film using the gate insulating film as a mask,
Oxidizing the surface of the island-shaped crystalline semiconductor film using ozone water or hydrogen peroxide water to form an oxide film,
Forming a conductive film on the substrate, the oxide film, and the gate insulating film;
The oxide film is used as an etching stopper for preventing the island-shaped crystalline semiconductor film from being etched, and the conductive film is patterned to form a gate electrode, a source electrode, and a drain electrode simultaneously,
N-type impurities are introduced into the island-shaped crystalline semiconductor film using the gate electrode, the source electrode, and the drain electrode as a mask,
The substrate on which at least the island-shaped crystalline semiconductor film, the oxide film, the gate insulating film, the gate electrode, the source electrode, and the drain electrode are formed is heated at 800 ° C. to 1050 ° C. for 30 minutes in an inert gas. A method for manufacturing a field-effect transistor, comprising heating for 4 to 4 hours. 2. The method according to claim 1, wherein, during the heating, an N-type impurity included in the source electrode and an N-type impurity included in the drain electrode are diffused into the crystalline semiconductor. . 3. The field-effect type according to claim 2, wherein, during the heating, N-type impurities included in the source electrode and N-type impurities included in the drain electrode are diffused into the island-shaped crystalline semiconductor film. A method for manufacturing a transistor. The method according to claim 2, wherein the substrate is a quartz substrate. Method for producing a field effect transistor according to any one of claims 1 to 7, characterized in that the N-type impurity was replaced with P-type impurities.

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