WO2010092891A1 - Organic semiconductor element and method for manufacturing same - Google Patents

Organic semiconductor element and method for manufacturing same Download PDF

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Publication number
WO2010092891A1
WO2010092891A1 PCT/JP2010/051519 JP2010051519W WO2010092891A1 WO 2010092891 A1 WO2010092891 A1 WO 2010092891A1 JP 2010051519 W JP2010051519 W JP 2010051519W WO 2010092891 A1 WO2010092891 A1 WO 2010092891A1
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layer
organic semiconductor
forming
glass coating
electrode
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PCT/JP2010/051519
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French (fr)
Japanese (ja)
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栗田雅章
板垣元士
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ブラザー工業株式会社
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/80—Constructional details
    • H10K10/88—Passivation; Containers; Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/466—Lateral bottom-gate IGFETs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/125—Active-matrix OLED [AMOLED] displays including organic TFTs [OTFT]

Definitions

  • the present invention relates to an organic semiconductor element and a method for manufacturing the same, and in particular, an organic semiconductor element in which a protective film is formed without damaging the organic semiconductor layer and without deteriorating device characteristics, and a method for manufacturing the same. It is about.
  • inorganic semiconductor materials such as silicon have been used for various semiconductor devices.
  • silicon-based inorganic semiconductor transistors using amorphous silicon or polycrystalline silicon as a semiconductor layer.
  • inorganic semiconductor devices require expensive manufacturing equipment such as vacuum equipment and high-purity materials for their production, there is a problem that the manufacturing cost increases, and heat treatment at high temperatures is required. There are restrictions on the substrates that can be used.
  • a device using an organic semiconductor can be manufactured by a coating method or a dipping method at a relatively low temperature, and can easily be enlarged at a low cost. Further, it can be formed on a flexible substrate having no heat resistance such as plastic. It is also stable against mechanical shock. For this reason, in recent years, research and development of organic semiconductor devices such as TFTs have been actively conducted assuming application to next-generation display devices.
  • the organic semiconductor layer deteriorates due to oxygen and moisture entering from the outside, and the semiconductor performance deteriorates. Therefore, in order to manufacture a highly reliable organic semiconductor device, it is necessary to form a structure that completely blocks the organic semiconductor layer from the outside by a protective film (passivation film) or the like.
  • an inorganic protective film such as a silicon nitride film or a silicon oxide film is generally formed as a protective film by a plasma CVD method or a sputtering method.
  • a plasma CVD method or a sputtering method.
  • damage due to plasma is likely to occur in the organic semiconductor layer, and when a protective film is formed by CVD or sputtering, damage due to plasma occurs in the organic semiconductor layer, degrading device characteristics. .
  • an organic film such as polyimide is generally applied by a coating method to form a protective layer.
  • an organic protective film to prevent intrusion of oxygen and moisture is inferior to that of the inorganic protective film.
  • Patent Document 1 a first protective film made of polyvinyl alcohol, polyvinylphenol, polymethyl methacrylate, polyimide, or the like is formed on the organic semiconductor layer by a coating method, a printing method, or the like, and the first protective film is covered.
  • a second protective film made of a silicon nitride film or a silicon oxide film by a CVD method or a sputtering method, the performance of preventing the entry of oxygen and moisture without causing damage to the organic semiconductor device Proposals for forming a high protective film have been made.
  • the threshold voltage as a transistor device increases due to the influence of polarity. For this reason, there is also a problem that the transistor characteristics deteriorate.
  • An object of the present invention is to provide an organic semiconductor element on which a protective film is formed without damaging the organic semiconductor layer as described above and without deteriorating device characteristics, and a method for manufacturing the same.
  • an organic semiconductor element includes a fluororesin layer, a water-soluble resin layer, and a glass coating layer on an organic semiconductor layer formed on an insulating layer. And are sequentially stacked.
  • An organic semiconductor element includes a gate electrode provided on a substrate, a gate insulating layer that is an insulating layer provided so as to cover the gate electrode, and the gate insulation.
  • An organic semiconductor element comprising: an organic semiconductor layer provided on an upper surface of a layer; and a source electrode and a drain electrode provided to be in contact with the organic semiconductor layer and spaced apart from each other.
  • a fluorine resin layer provided so as to cover each upper surface of the source electrode and the drain electrode, a water-soluble resin layer provided on the fluorine resin layer, and a glass coating layer provided on the water-soluble resin layer
  • a pixel electrode provided on the glass coating layer.
  • An organic semiconductor element is provided so as to be in contact with a substrate which is an insulating layer having an insulating function, an organic semiconductor layer provided on the substrate, and the organic semiconductor layer. And a source electrode and a drain electrode that are spaced apart from each other, a fluororesin layer provided so as to cover the upper surfaces of the organic semiconductor layer, the source electrode, and the drain electrode, and the fluororesin layer.
  • the water-soluble resin layer, the first glass coating layer provided on the water-soluble resin layer, the fluororesin layer, the water-soluble resin layer, and the first glass coating layer are laminated.
  • a gate electrode provided on the gate insulating layer facing the organic semiconductor layer, and provided to cover each upper surface of the first glass coating layer and the gate electrode.
  • a second glass coating layer characterized in that it is constituted by a pixel electrode provided on the second glass coating layer.
  • a method for manufacturing an organic semiconductor device comprising: a gate electrode forming step for forming a gate electrode on a substrate; and a gate insulating layer forming step for forming a gate insulating layer so as to cover the gate electrode.
  • an organic semiconductor layer forming step for forming an organic semiconductor layer on the gate insulating layer, and a source for forming a source electrode and a drain electrode provided in contact with the organic semiconductor layer and spaced apart from each other
  • a drain electrode forming step a fluororesin layer forming step of forming a fluororesin layer so as to cover each upper surface of the organic semiconductor layer, the source electrode and the drain electrode, and a hydrophilization treatment on the exposed surface of the fluororesin layer Fluororesin layer surface hydrophilization treatment step to be applied and water-soluble resin layer to form a water-soluble resin layer on the fluororesin layer whose exposed surface has been subjected to hydrophilization treatment
  • an organic semiconductor element manufacturing method comprising: an organic semiconductor layer forming step for forming an organic semiconductor layer on a substrate; A source / drain electrode forming step for forming a source electrode and a drain electrode spaced apart from each other, and a fluororesin layer for forming a fluororesin layer so as to cover each upper surface of the organic semiconductor layer, the source electrode, and the drain electrode Forming a hydrophilic resin layer on the exposed surface of the fluororesin layer, and forming a water-soluble resin layer on the top surface of the fluororesin layer on which the exposed surface has been hydrophilized
  • the organic semiconductor element of the invention according to claim 1 is a device in which a fluororesin layer, a water-soluble resin layer, and a glass coating layer are sequentially laminated on an organic semiconductor layer without damaging the organic semiconductor layer. An organic semiconductor element having excellent characteristics can be obtained.
  • the protective film can be formed without damaging the organic semiconductor layer by forming the fluororesin layer directly on the organic semiconductor layer. Further, by forming the glass coating layer, it is possible to form a protective film that is not damaged by the photoresist when the through hole is formed. Further, by forming the glass coating layer, the pixel electrode can be easily formed as compared with the case where the pixel electrode is formed on the water-soluble resin layer. Moreover, the damage to the organic-semiconductor layer at the time of glass coating layer formation can be reduced by forming a water-soluble resin layer in the middle of a fluororesin layer and a glass coating layer. As described above, it is possible to obtain an organic semiconductor element with little damage during formation, excellent device characteristics, and high workability.
  • a gate insulating laminate can be formed without damaging the organic semiconductor layer.
  • the pixel electrode can be easily formed as compared with the case where the pixel electrode is formed on the water-soluble resin layer.
  • the damage to the organic-semiconductor layer at the time of glass coating layer formation can be reduced by forming a water-soluble resin layer in the middle of a fluororesin layer and a 1st glass coating layer.
  • the second glass coating layer it is possible to form a protective film that is not damaged by the photoresist when the through hole is formed. As described above, it is possible to obtain an organic semiconductor element with little damage during formation, excellent device characteristics, and high workability.
  • the method for producing an organic semiconductor element of the invention according to claim 4 makes it possible to produce an organic semiconductor element having little process damage, excellent device characteristics, and high processability.
  • the method for producing an organic semiconductor element of the invention according to claim 5 makes it possible to produce an organic semiconductor element with little damage during formation, excellent device characteristics, and high workability.
  • FIG. 6 is a longitudinal sectional view of an organic semiconductor element 1a of Comparative Example 1.
  • FIG. 6 is a longitudinal sectional view of an organic semiconductor element 1b of Comparative Example 2.
  • FIG. It is a longitudinal cross-sectional view of the organic-semiconductor element 1c of the comparative example 3.
  • FIG. 3 is a voltage-current characteristic diagram of the organic semiconductor element 1 of the first embodiment. 6 is a voltage-current characteristic diagram of an organic semiconductor element 1a of Comparative Example 1.
  • FIG. 3 is a voltage-current characteristic diagram of the organic semiconductor element 1 of the first embodiment.
  • FIG. 6 is a voltage-current characteristic diagram of an organic semiconductor element 1b of Comparative Example 2.
  • FIG. 10 is a voltage-current characteristic diagram of an organic semiconductor element 1c of Comparative Example 3.
  • FIG. It is sectional drawing of the organic-semiconductor element 100 of 2nd Embodiment. It is a flowchart which shows the manufacturing process of the organic-semiconductor element 100 of 2nd Embodiment.
  • the organic semiconductor device 1 of the first embodiment is a so-called “bottom gate type” organic semiconductor device in which the gate electrode 3 is located below the source electrode 7 and the drain electrode 8.
  • the source electrode 7, the drain electrode 8, and the protective film 10 for the organic semiconductor layer 6 have a three-layer structure of a fluororesin layer 11, a water-soluble resin layer 12, and a glass coating layer 13. It has a special feature.
  • the lower side of the drawing (substrate 2 side) is the lower side
  • the upper side of the drawing is the upper side.
  • the lower side of the drawing is described as the lower side
  • the upper side of the drawing is described as the upper side.
  • An organic semiconductor element 1 shown in FIG. 1 has a plate-like substrate 2.
  • a gate electrode 3 is provided on the upper surface of the substrate 2.
  • a gate insulating layer 4 is laminated on the upper surface of the gate electrode 3 and the upper surface of the substrate 2 on which the gate electrode 3 is not provided.
  • a source electrode 7 and a drain electrode 8 are provided on the upper surface of the gate insulating layer 4 so as to be separated from each other. This spaced space is opposed to the gate electrode 3 with the gate insulating layer 4 interposed therebetween.
  • An organic semiconductor layer 6 is provided on the upper surface of the gate insulating layer 4 sandwiched between the source electrode 7 and the drain electrode 8 so as to be in contact with the gate electrode 7 and the drain electrode 8.
  • a protective film 10 is provided on the upper surface of the organic semiconductor layer 6, the source electrode 7, the drain electrode 8, and the gate insulating layer 4 where these are not provided.
  • the protective film 10 has a three-layer structure, and a fluororesin layer 11, a water-soluble resin layer 12, and a glass coating layer 13 are laminated in this order from the bottom.
  • a pixel electrode 21 is formed on the upper surface of the protective film 10. The pixel electrode 21 is electrically connected to the source electrode 7 through a contact hole 31.
  • the substrate 2 is a plate-like member having a flat surface.
  • Various materials can be applied as the material of the substrate 2, but when a conductive material is applied, it is necessary to provide an insulating film on the surface of the substrate 2.
  • an insulating material is used as the material of the substrate 2
  • a glass substrate, a silicon substrate, or a plastic substrate is used.
  • plastic substrate is particularly used. Examples of plastic materials include polyethersulfone (PES), polyethylene terephthalate (PET), polyimide (PI), polyethylene naphthalate (PEN), polyetherimide (PEI), polystyrene (PS), and polyvinyl chloride (PVC). ), Polyethylene (PE), polypropylene (PP) and the like.
  • a glass barrier film made of SiO 2 or SiNx is formed on the surface of the substrate 2.
  • a gate electrode 3 is provided on the upper surface of the substrate 2.
  • the material of the gate electrode 3 is a single metal such as Au, Ag, Cu, Pd, Al, Mo, Cr, Ti, Ta, Ni, Pt, W (tungsten), or a composite containing at least one of the metals.
  • a conductive oxide such as indium tin oxide (ITO), and a conductive polymer such as polyethylene dioxythiophene (PEDOT) and polyparaphenylene vinylene (PPV) are applicable.
  • the gate insulating layer is formed of an insulating material.
  • an inorganic insulating material Al 2 O 3 , SiO 2 , SiN, TiO 2, etc. can be applied.
  • an organic insulating material is employed as the insulating material, PI (polyimide), PMMA (polymethyl methacrylate), PVP (polyparavinylphenol), or the like can be applied.
  • the organic semiconductor layer 6 is provided on the upper surface of the gate insulating layer 4 so as to face each other with the gate electrode 3 and the gate insulating layer 4 interposed therebetween.
  • a source electrode 7 and a drain electrode 8 are provided so as to sandwich the organic semiconductor layer 6 therebetween.
  • the source electrode 7 and the drain electrode 8 are spaced apart from each other.
  • the organic semiconductor 6, the source electrode 7 and the drain electrode 8 are provided in contact with each other.
  • Examples of the material of the organic semiconductor layer 6 include acenes such as pentacene, tetracene, and anthracene, phthalocyanines such as copper phthalocyanine, polyalkylthiophenes such as poly (3-hexylthiophene), alkyl oligothiophenes, and the like.
  • the material of the source electrode 7 and the drain electrode 8 includes a single metal such as Au, Ag, Cu, Pd, Al, Mo, Cr, Ti, Ta, Ni, Pt, and W (tungsten), or at least one of the metals.
  • a single metal such as Au, Ag, Cu, Pd, Al, Mo, Cr, Ti, Ta, Ni, Pt, and W (tungsten), or at least one of the metals.
  • the laminated structure of multiple types of metals may be sufficient.
  • the protective film 10 is configured by laminating a lower fluororesin layer 11, a middle water-soluble resin layer 12, and an upper glass coating layer 13.
  • Examples of the material of the fluororesin layer 11 include polytetrafluoroethylene (for example, fluorosurf FG3030: manufactured by Fluoro Technology, Cytop: manufactured by Asahi Glass), 1,1,1,2,3,4,4,5,5,5. -Decafluoropentane (for example, fluorine plastic coat: manufactured by Fine Chemical Japan Co.) fluoroethylene propylene copolymer, perfluoroalkoxy fluorine, ethylene tetrafluoride ethylene and the like.
  • polytetrafluoroethylene for example, fluorosurf FG3030: manufactured by Fluoro Technology, Cytop: manufactured by Asahi Glass
  • -Decafluoropentane for example, fluorine plastic coat: manufactured by Fine Chemical Japan Co.
  • polyvinyl alcohol for example, Poval: manufactured by Kuraray Co., Ltd.
  • polyethylene oxide for example, Alcox: manufactured by Meisei Chemical Co., Ltd.
  • water-soluble polymers such as sodium polyacrylate, ethylene vinyl acetate emulsion, Water-soluble emulsions such as acrylic emulsion, vinyl acetate emulsion, and acrylic styrene emulsion are listed.
  • Examples of the material of the glass coating layer 13 include polysilazane (for example, Aquamica: manufactured by AZ Electronic Materials).
  • a pixel electrode 21 is provided on the upper surface of the protective film 10.
  • the pixel electrode 21 is made of ITO (indium tin oxide).
  • the manufacturing process of the organic semiconductor element 1 includes a gate electrode forming step (S1) for forming the gate electrode 3 on the upper surface of the substrate 2, and gate insulation so as to cover the upper surface of the gate electrode 3 and the substrate 2.
  • the protective film forming step (S5) includes a fluororesin layer forming step (S51) for forming the fluororesin layer 11, and a water soluble resin layer forming step (S52) for forming the water soluble resin layer 12 on the upper surface of the fluororesin layer 11. And a glass coating layer forming step (S53) for forming the glass coating layer 13 on the upper surface of the water-soluble resin layer 12.
  • a fluororesin layer forming step (S51) for forming the fluororesin layer 11
  • a water soluble resin layer forming step (S52) for forming the water soluble resin layer 12 on the upper surface of the fluororesin layer 11.
  • a glass coating layer forming step (S53) for forming the glass coating layer 13 on the upper surface of the water-soluble resin layer 12.
  • the gate electrode forming step of S1 is performed.
  • the gate electrode 3 is formed on the upper surface of the substrate 2.
  • the Cr thin film is formed on the upper surface of the substrate 2 after cleaning the substrate 2 made of glass.
  • the gate electrode 3 was formed by patterning the formed Cr thin film and removing an unnecessary part.
  • the Cr thin film was formed by a sputtering method. At this time, Cr was used as the target, and a DC sputtering apparatus was used as the apparatus.
  • a resist pattern was formed on the upper surface of the formed Cr thin film using a photolithography method, and then the Cr thin film was etched using an etching method. The unnecessary photoresist was removed by washing with acetone.
  • the step S2 of forming a gate insulating layer is performed.
  • a mixed solution obtained by dissolving polyvinyl phenol and melamine formaldehyde in polyethylene glycol monomethyl ether acetate was formed by spin coating so as to cover the upper surface of the substrate 2 provided with the gate electrode 3.
  • annealing treatment was performed in an environment of 180 ° C. for 2 hours.
  • the gate insulating layer 4 composed of polyvinylphenol crosslinked with melamine formaldehyde was formed on the upper surface of the substrate 2 provided with the gate electrode 3.
  • the source / drain electrode forming step of S3 is performed.
  • a Cr laminated thin film was formed on the upper surfaces of the organic semiconductor layer 6 and the gate insulating layer 4.
  • an Au thin film was formed, and finally a thin film (Au / Cr thin film) in which Au and Cr were laminated was formed.
  • a source electrode 7 and a drain electrode 8 are formed that are separated from each other with a portion facing the gate electrode 3 on the upper surface of the gate insulating layer 4 interposed therebetween. did.
  • the Au / Cr thin film was formed by a sputtering method.
  • Au and Cr were respectively used as targets, and a DC sputtering apparatus was used as an apparatus.
  • a resist pattern was formed on the upper surface of the formed Au / Cr thin film using a photolithography method, and then the Au / Cr thin film was etched using an etching method. The unnecessary photoresist was removed by washing with acetone.
  • the organic semiconductor layer forming step of S4 is performed.
  • the organic semiconductor layer 6 was formed in contact with the source electrode 7 and the drain electrode 8 at a position facing the gate electrode 3 on the gate insulating layer 4.
  • triisopropylsilylethynylpentacene was formed by an inkjet method. Thereafter, annealing treatment was performed for 5 minutes in a 120 ° C. environment.
  • the protective film forming step of S5 includes a fluororesin layer forming step (S51), a water-soluble resin layer forming step (S52), and a glass coating layer forming step (S53).
  • a fluorine plastic coat (manufactured by Fine Chemical Japan) was formed by a spin coat method so as to cover the upper surfaces of the source electrode 7, the drain electrode 8, and the organic semiconductor layer 6. Next, annealing was performed for 5 minutes in a 120 ° C. environment. Thus, the fluororesin layer 11 was formed.
  • the water-soluble resin layer forming step of S52 is performed.
  • the surface of the fluororesin layer 11 was hydrophilized by treating the surface of the fluororesin layer 11 with a plasma cleaner (low pressure plasma apparatus “FEMTO” manufactured by diener electronic) for 3 seconds.
  • a 5% by weight aqueous solution of Poval manufactured by Kuraray Co., Ltd.
  • annealing treatment was performed for 5 minutes in 120 degreeC environment.
  • the water-soluble resin layer 12 was formed.
  • the glass coating layer forming step of S53 is performed.
  • aquamica manufactured by AZ Electronic Materials
  • annealing treatment was performed for 5 minutes in 120 degreeC environment. In this way, the glass coating layer 13 was formed.
  • the contact hole forming step of S6 is performed.
  • a contact hole 31 that penetrates the fluororesin layer 11, the water-soluble resin layer 12, and the glass coating layer 13 is formed.
  • a resist mask having an opening at a location corresponding to the contact hole 31 is formed on the upper surface of the glass coating layer 13 by photolithography.
  • a part of the glass coating layer 13 and the water-soluble resin layer 12 is etched using buffered hydrofluoric acid.
  • the photoresist is stripped using acetone.
  • the remainder of the water-soluble resin layer 12 and the fluororesin layer 11 are etched by dry etching with oxygen plasma, using the glass coating layer 13 as a resist.
  • a contact hole 31 is thus formed.
  • the pixel electrode forming step of S7 is performed.
  • the pixel electrode 21 composed of ITO was formed by patterning to remove unnecessary portions.
  • the ITO film was formed by a sputtering method. After the ITO film was formed, a resist pattern was formed, the ITO film was etched, and unnecessary photoresist was removed by washing with acetone.
  • the curve a represents the voltage-current characteristics of the organic semiconductor elements 1, 1a, 1b, and 1c before the formation of the protective films 10, 10a, 10b, and 10c
  • the curve b represents the protective film 10.
  • the voltage-current characteristics of the organic semiconductor elements 1, 1a, 1b and 1c after the formation of 10a, 10b and 10c are shown.
  • the vertical axis represents the drain current value
  • the horizontal axis represents the gate voltage value. When these evaluations were performed, the drain voltage was 30V.
  • the organic semiconductor element 1 of the first embodiment has no change in TFT characteristics due to the formation of the protective film 10 (threshold voltage: 5 V remains unchanged, on / off ratio: 10 6 . Retention).
  • the organic semiconductor element 1a of Comparative Example 1 has a high threshold voltage (5V ⁇ 20V) and a decrease in on / off ratio (10 6 ⁇ 10 3 ). The transistor characteristics are getting worse.
  • the curve b is almost flat as shown in FIGS. This indicates that the organic semiconductor elements 1b and 1c of Comparative Examples 2 to 3 no longer operate as transistors due to the formation of the protective films 10b and 10c.
  • the organic semiconductor element 1 a of Comparative Example 1 has a structure in which the protective resin 10 is missing the fluororesin layer 11.
  • the water-soluble resin layer 12 having polarity directly on the organic semiconductor layer 6 it is presumed that the threshold voltage of the organic semiconductor increases and the on / off ratio decreases.
  • the organic semiconductor elements 1b and 1c of Comparative Examples 2 to 3 having a protective film having a structure without the water-soluble resin layer 12 are affected by the organic solvent used as the solvent when the glass coating layer 13 is formed. It is presumed that the organic semiconductor is damaged, and as a result, it does not operate as a transistor.
  • the protective film 10 is first formed from the fluororesin layer 11 so that the water-soluble resin layer 12 and the glass coating layer 13 are formed on the organic semiconductor layer 6.
  • the pixel electrode 21 can be easily formed as compared with the case where the pixel electrode 21 is formed on the water-soluble resin layer 12,
  • damage to the organic semiconductor layer 6 during the formation of the glass coating layer 13 can be reduced. A semiconductor element can be obtained.
  • the organic semiconductor element 100 of the second embodiment is a so-called “top gate type” organic semiconductor element in which the gate electrode 103 is located above the source electrode 107 and the drain electrode 108.
  • the organic semiconductor device 100 according to the second embodiment is characterized by having a gate insulating laminate 104 constituted by a three-layer structure of a fluororesin layer 110, a water-soluble resin layer 120, and a first glass coating layer 130.
  • An organic semiconductor element 100 shown in FIG. 10 has a plate-like substrate 2.
  • a source electrode 107 and a drain electrode 108 are provided apart from each other on the upper surface of the substrate 2.
  • An organic semiconductor layer 106 is provided on the upper surface of the substrate 2 between the source electrode 107 and the drain electrode 108 so as to be in contact with the source electrode 107 and the drain electrode 108.
  • a gate insulating laminate 104 is provided on the top surfaces of the organic semiconductor layer 106, the source electrode 107, and the drain electrode 108.
  • the gate insulating laminate 104 has a three-layer structure, and is provided by laminating a lower fluororesin layer 110, a middle water-soluble resin layer 120, and an upper first glass coating layer 130 in this order.
  • a gate electrode 103 is provided on the upper surface of the gate insulating laminate 104 facing the organic semiconductor layer 106 with the gate insulating laminate 104 interposed therebetween.
  • a second glass coating layer 140 is provided on the upper surface of the gate insulating laminate 104 where the gate electrode 103 and the gate electrode 103 are not provided.
  • a pixel electrode 121 is formed on the upper surface of the second glass coating layer 140, and the pixel electrode 121 is electrically connected to the source electrode 107 through a contact hole 131.
  • the gate electrode 103, the organic semiconductor layer 106, the source electrode 107, the drain electrode 108, the fluororesin layer 110, the water-soluble resin layer 120, the glass coating layer 130, and the pixel electrode 121 which are components of the organic semiconductor element of the second embodiment.
  • the material is a component of the organic semiconductor element 1 of the first embodiment, which is the gate electrode 3, the organic semiconductor layer 6, the source electrode 7, the drain electrode 8, the fluororesin layer 11, the water-soluble resin layer 12, and the glass coating layer. 13 and the pixel electrode 21, respectively.
  • Examples of the material of the second glass coating layer 140 include polysilazane (for example, Aquamica: manufactured by AZ Electronic Materials), which is the same as the first glass coating layer 130.
  • the manufacturing process of the organic semiconductor device 100 includes a source / drain electrode formation step (S101) in which the source electrode 107 and the drain electrode 108 are formed on the upper surface of the substrate 2 apart from each other, and the source electrode 107 and the drain electrode.
  • the gate insulating layer forming step (S103) includes a fluororesin layer forming step (S131) for forming the fluororesin layer 110, and a water soluble resin layer forming step (S132) for forming the water soluble resin layer 120 on the upper surface of the fluororesin layer 110. ), And a first glass coating layer forming step (S133) for forming the first glass coating layer 130 on the upper surface of the water-soluble resin layer 120.
  • S131 fluororesin layer forming step
  • S132 water soluble resin layer forming step
  • S133 first glass coating layer forming step
  • the source / drain electrode forming step of S101 is performed.
  • the source electrode 107 and the drain electrode 108 are formed apart from each other on the upper surface of the substrate 2.
  • the Au / Cr thin film is formed on the upper surface of the substrate 2 after cleaning the substrate 2 made of glass. Then, by patterning the formed Au / Cr thin film and removing unnecessary portions, the source electrode 107 and the drain electrode 108 were formed. Details are the same as in the source / drain electrode formation step (S4) in the first embodiment, and a description thereof will be omitted.
  • the organic semiconductor layer forming step of S102 is performed. Since this step is the same as the organic semiconductor layer forming step (S3) in the first embodiment, the description thereof is omitted.
  • the gate insulating layer forming step of S103 is performed.
  • This step includes a fluororesin layer forming step (S131), a water-soluble resin layer forming step (S132), and a first glass coating layer forming step (S133).
  • the fluororesin layer forming step (S131), the water-soluble resin layer forming step (S132), and the first glass coating layer forming step (S133) are respectively the fluororesin layer forming step (S51) and the water-soluble resin of the first embodiment. Since it is the same as the layer forming step (S52) and the glass coating layer forming step (S53), description thereof is omitted.
  • the gate electrode forming step of S104 is performed.
  • a Cr thin film was formed on the upper surface of the gate insulating laminate 104.
  • the gate electrode 103 was formed by patterning the formed Cr thin film and removing an unnecessary part. Details are the same as those in the gate electrode formation step (S1) in the first embodiment, and thus the description thereof is omitted.
  • the second glass coating layer forming step of S105 is performed.
  • the second glass coating layer 140 is formed so as to cover the gate electrode 103 and the gate insulating layer 104 of the second embodiment in which the gate electrode 103 is not formed.
  • aquamica manufactured by AZ Electronic Materials
  • the contact hole forming step of S106 is performed, and then the pixel electrode forming step of S107 is performed.
  • These steps are the same as the contact hole forming step (S6) and the pixel electrode forming step (S7) of the first embodiment, respectively, and thus description thereof is omitted.
  • the gate insulating laminate 104 is first formed from the fluororesin layer 110, thereby forming the water-soluble resin layer 120 and the glass coating layer 130 directly on the organic semiconductor layer 106.
  • the pixel electrode 121 can be easily formed as compared with the case where the pixel electrode 121 is formed on the water-soluble resin layer 120.
  • the water-soluble resin layer 120 is formed between the fluororesin layer 110 and the first glass coating layer 130, damage to the organic semiconductor layer 106 when the glass coating layer 130 is formed can be reduced, so that stable TFT characteristics can be obtained. An organic semiconductor element can be obtained.
  • the present invention is not limited to the embodiments described in detail, and various modifications may be made without departing from the scope of the present disclosure.
  • the materials, sizes, and shapes of the substrate, the gate electrode, the source electrode, the drain electrode, the gate insulating layer, and the organic semiconductor layer that constitute the organic semiconductor element are not limited to the embodiment, and do not depart from the gist of the present disclosure. It can be changed as appropriate within the range.
  • the organic semiconductor layer is formed after forming the source electrode and the drain electrode. However, after forming the organic semiconductor layer, the source electrode and the drain electrode are formed. May be.
  • the oxide thin film transistor and the method for manufacturing the oxide thin film transistor of the present invention can be applied to a so-called bottom gate type or top gate type oxide thin film transistor and a method for manufacturing the same.

Abstract

Disclosed is an organic semiconductor element wherein a protective film, which does not damage the organic semiconductor layer nor deteriorate the device characteristics, is formed.  Also disclosed is a method for manufacturing the organic semiconductor element.  Specifically disclosed is an organic semiconductor element (1) which comprises a substrate (2) and a gate electrode (3) that is formed on the upper surface of the substrate (2).  A gate insulating layer (4) is formed on the upper surface of the gate electrode (3) and the upper surface of the substrate (2).  A source electrode (7) and a drain electrode (8) are formed apart from each other on the upper surface of the gate insulating layer (4).  An organic semiconductor layer (6) is formed on the upper surface of the gate insulating layer (4) between the source electrode (7) and the drain electrode (8).  A protective film (10), which has a three-layer structure composed of a fluororesin layer (11), a water-soluble resin layer (12) and a glass coating layer (13) arranged in this order from the bottom, is formed on the upper surface of the organic semiconductor layer (6), the source electrode (7), the drain electrode (8) and the gate insulating layer (4).  A pixel electrode (21) is formed on the upper surface of the protective film (10), and the pixel electrode (21) is electrically connected to the source electrode (7) through a contact hole (31).

Description

有機半導体素子、及びその製造方法Organic semiconductor device and manufacturing method thereof
　本発明は、有機半導体素子、及びその製造方法に関するものであり、特に、有機半導体層にダメージを与えることなく、またデバイス特性を低下させることのない保護膜を形成した有機半導体素子及びその製造方法に関するものである。 The present invention relates to an organic semiconductor element and a method for manufacturing the same, and in particular, an organic semiconductor element in which a protective film is formed without damaging the organic semiconductor layer and without deteriorating device characteristics, and a method for manufacturing the same. It is about.
　従来、様々な半導体デバイスにはシリコン等の無機半導体材料が使用されてきた。例えば、液晶ディスプレイのアクティブマトリクス回路にスイッチング素子として広く使用されている薄膜トランジスタのほとんどが、半導体層としてアモルファスシリコンあるいは多結晶シリコンを用いるシリコン系の無機半導体トランジスタである。 Conventionally, inorganic semiconductor materials such as silicon have been used for various semiconductor devices. For example, most of thin film transistors widely used as switching elements in active matrix circuits of liquid crystal displays are silicon-based inorganic semiconductor transistors using amorphous silicon or polycrystalline silicon as a semiconductor layer.
　しかし、無機半導体デバイスは、その製造に真空装置などの高価な製造設備や高純度の材料を必要とするため、製造コストが高くなる問題点がある、また、高温での熱処理が必要となるため、使用できる基板に制約がある。 However, since inorganic semiconductor devices require expensive manufacturing equipment such as vacuum equipment and high-purity materials for their production, there is a problem that the manufacturing cost increases, and heat treatment at high temperatures is required. There are restrictions on the substrates that can be used.
　一方、有機半導体を使用したデバイスは、比較的低い温度下で塗布法や浸漬法などで製造でき、低コストで、容易に大面積化が可能である。また、プラスチックなどの耐熱性のないフレキシブルな基板などに形成することができる。また、機械的衝撃に対しても安定である。このため、近年、次世代の表示装置への応用を想定して、ＴＦＴなどの有機半導体デバイスの研究開発が盛んにおこなわれている。 On the other hand, a device using an organic semiconductor can be manufactured by a coating method or a dipping method at a relatively low temperature, and can easily be enlarged at a low cost. Further, it can be formed on a flexible substrate having no heat resistance such as plastic. It is also stable against mechanical shock. For this reason, in recent years, research and development of organic semiconductor devices such as TFTs have been actively conducted assuming application to next-generation display devices.
　しかし、有機半導体デバイスは、外部から侵入してくる酸素及び水分によって有機半導体層が変質し、半導体性能が劣化する。そのため、信頼性の高い有機半導体デバイスを作製するためには、保護膜（パッシベーション膜）などによって有機半導体層を外部から完全に遮断する構造を形成する必要がある。 However, in the organic semiconductor device, the organic semiconductor layer deteriorates due to oxygen and moisture entering from the outside, and the semiconductor performance deteriorates. Therefore, in order to manufacture a highly reliable organic semiconductor device, it is necessary to form a structure that completely blocks the organic semiconductor layer from the outside by a protective film (passivation film) or the like.
　このような場合、無機半導体デバイスでは、プラズマＣＶＤ法やスパッタリング法などにより、保護膜として窒化シリコン膜や酸化シリコン膜等の無機保護膜を形成するのが一般的である。しかし、有機半導体デバイスではプラズマによるダメージが有機半導体層に生じやすく、ＣＶＤ法やスパッタリング法によって保護膜を形成すると、プラズマによるダメージが有機半導体層に生じ、かえってデバイス特性を劣化させてしまうことになる。 In such a case, in an inorganic semiconductor device, an inorganic protective film such as a silicon nitride film or a silicon oxide film is generally formed as a protective film by a plasma CVD method or a sputtering method. However, in organic semiconductor devices, damage due to plasma is likely to occur in the organic semiconductor layer, and when a protective film is formed by CVD or sputtering, damage due to plasma occurs in the organic semiconductor layer, degrading device characteristics. .
　これを避けるために、ポリイミド等の有機膜を塗布法にて塗布して保護層とすることが一般的に行われている。しかし、有機保護膜の酸素や水分の侵入を阻止する性能は、無機保護膜のそれに比べて劣っている。 In order to avoid this, an organic film such as polyimide is generally applied by a coating method to form a protective layer. However, the performance of the organic protective film to prevent intrusion of oxygen and moisture is inferior to that of the inorganic protective film.
　そこで、特許文献１では塗布法、印刷法などにより、ポリビニルアルコール、ポリビニルフェノール、ポリメタクリル酸メチル、ポリイミドなどによる第１の保護膜を有機半導体層上に形成し、前記第１の保護膜を被覆するようにＣＶＤ法やスパッタリング法により窒化シリコン膜や酸化シリコン膜による第２の保護膜を形成することで、プラズマによるダメージを有機半導体デバイスに与えることなく、酸素や水分の侵入を阻止する性能の高い保護膜を形成する提案がなされている。 Therefore, in Patent Document 1, a first protective film made of polyvinyl alcohol, polyvinylphenol, polymethyl methacrylate, polyimide, or the like is formed on the organic semiconductor layer by a coating method, a printing method, or the like, and the first protective film is covered. Thus, by forming a second protective film made of a silicon nitride film or a silicon oxide film by a CVD method or a sputtering method, the performance of preventing the entry of oxygen and moisture without causing damage to the organic semiconductor device Proposals for forming a high protective film have been made.
特開２００７－５３１４７号公報JP 2007-53147 A
　特許文献１に示されている構成においては、第１の保護膜を形成する際に、上述したような有機材料を、請求項１５に示されているような、２－プロパノール、ブタノール、シクロペンタノン、１，４－ジオキサン、γ－ブチルラクトン、アニソール、ポリエチレングリコールモノメチルエーテルアセテートといった、有機半導体層を溶解させる性質が乏しい溶媒に溶解させ、その上で有機半導体層上に塗布、印刷等が行われている。 In the configuration shown in Patent Document 1, when forming the first protective film, the organic material as described above is replaced with 2-propanol, butanol, cyclopenta as shown in claim 15. Dissolve the organic semiconductor layer in a solvent with poor properties, such as non, 1,4-dioxane, γ-butyllactone, anisole, polyethylene glycol monomethyl ether acetate, and then apply, print, etc. on the organic semiconductor layer It has been broken.
　しかし、有機半導体層を溶解させる性質が乏しいとはいえ、これら溶媒は有機半導体層にダメージを与える結果となり、デバイス特性を保つという点において問題がある。 However, although the property of dissolving the organic semiconductor layer is poor, these solvents result in damage to the organic semiconductor layer and have a problem in maintaining device characteristics.
　また、ポリビニルアルコール等の極性のある樹脂を使用した場合、極性の影響で、トランジスタデバイスとしてのしきい電圧が高くなってしまう。このため、トランジスタ特性が低下してしまう問題もある。 Also, when a polar resin such as polyvinyl alcohol is used, the threshold voltage as a transistor device increases due to the influence of polarity. For this reason, there is also a problem that the transistor characteristics deteriorate.
　本発明は、上述したような有機半導体層にダメージを与えることなく、またデバイス特性を低下させることのない保護膜を形成した有機半導体素子及びその製造方法を提供することを目的とする。 An object of the present invention is to provide an organic semiconductor element on which a protective film is formed without damaging the organic semiconductor layer as described above and without deteriorating device characteristics, and a method for manufacturing the same.
　上記目的を達成するために、本発明の請求項１に係る発明の有機半導体素子は、絶縁層上に形成された有機半導体層上に、フッ素樹脂層と、水溶性樹脂層と、ガラスコーティング層とを順次積層して形成したことを特徴とする。 In order to achieve the above object, an organic semiconductor element according to a first aspect of the present invention includes a fluororesin layer, a water-soluble resin layer, and a glass coating layer on an organic semiconductor layer formed on an insulating layer. And are sequentially stacked.
　また、本発明の請求項２に係る発明の有機半導体素子は、基板上に設けられているゲート電極と、前記ゲート電極を覆うように設けられた絶縁層であるゲート絶縁層と、前記ゲート絶縁層の上面に設けられた有機半導体層と、前記有機半導体層に接触するよう設けられると共に、互いに離間して配置されたソース電極及びドレイン電極とにより構成される有機半導体素子において、前記有機半導体層、ソース電極及びドレイン電極の各上面を覆うようにして設けられたフッ素樹脂層と、前記フッ素樹脂層上に設けられた水溶性樹脂層と、前記水溶性樹脂層上に設けられたガラスコーティング層と、前記ガラスコーティング層上に設けられた画素電極とにより構成されることを特徴とする。 An organic semiconductor element according to a second aspect of the present invention includes a gate electrode provided on a substrate, a gate insulating layer that is an insulating layer provided so as to cover the gate electrode, and the gate insulation. An organic semiconductor element comprising: an organic semiconductor layer provided on an upper surface of a layer; and a source electrode and a drain electrode provided to be in contact with the organic semiconductor layer and spaced apart from each other. , A fluorine resin layer provided so as to cover each upper surface of the source electrode and the drain electrode, a water-soluble resin layer provided on the fluorine resin layer, and a glass coating layer provided on the water-soluble resin layer And a pixel electrode provided on the glass coating layer.
　また、本発明の請求項３に係る発明の有機半導体素子は、絶縁機能を有する絶縁層である基板と、前記基板上に設けられた有機半導体層と、前記有機半導体層に接触するよう設けられると共に、互いに離間して配置されたソース電極及びドレイン電極と、前記有機半導体層、ソース電極及びドレイン電極の各上面を覆うようにして設けられたフッ素樹脂層と、前記フッ素樹脂層上に設けられた水溶性樹脂層と、前記水溶性樹脂層上に設けられた第１のガラスコーティング層と、前記フッ素樹脂層と前記水溶性樹脂層と前記第１のガラスコーティング層とが積層されて形成されるゲート絶縁積層上の、前記有機半導体層と相対する場所に設けられたゲート電極と、前記第１のガラスコーティング層と前記ゲート電極の各上面を覆うように設けられた第２のガラスコーティング層と、前記第２のガラスコーティング層上に設けられた画素電極とにより構成されることを特徴とする。 An organic semiconductor element according to a third aspect of the present invention is provided so as to be in contact with a substrate which is an insulating layer having an insulating function, an organic semiconductor layer provided on the substrate, and the organic semiconductor layer. And a source electrode and a drain electrode that are spaced apart from each other, a fluororesin layer provided so as to cover the upper surfaces of the organic semiconductor layer, the source electrode, and the drain electrode, and the fluororesin layer. The water-soluble resin layer, the first glass coating layer provided on the water-soluble resin layer, the fluororesin layer, the water-soluble resin layer, and the first glass coating layer are laminated. A gate electrode provided on the gate insulating layer facing the organic semiconductor layer, and provided to cover each upper surface of the first glass coating layer and the gate electrode. A second glass coating layer, characterized in that it is constituted by a pixel electrode provided on the second glass coating layer.
　本発明の請求項４に係る発明の有機半導体素子の製造方法は、基板上にゲート電極を形成させるゲート電極形成工程と、前記ゲート電極を覆うようにゲート絶縁層を形成させるゲート絶縁層形成工程と、前記ゲート絶縁層上に有機半導体層を形成させる有機半導体層形成工程と、前記有機半導体層に接触するよう設けられると共に、互いに離間して配置されているソース電極及びドレイン電極を形成させるソース・ドレイン電極形成工程と、前記有機半導体層、ソース電極及びドレイン電極の各上面を覆うようにしてフッ素樹脂層を形成させるフッ素樹脂層形成工程と、前記フッ素樹脂層の露出面に親水化処理を施すフッ素樹脂層表面親水化処理工程と、露出面に親水化処理を施された前記フッ素樹脂層上に水溶性樹脂層を形成させる水溶性樹脂層形成工程と、前記水溶性樹脂層上にガラスコーティング層を形成させるガラスコーティング層形成工程と、前記ガラスコーティング層上に画素電極を形成させる画素電極形成工程と、により構成されることを特徴とする。 According to a fourth aspect of the present invention, there is provided a method for manufacturing an organic semiconductor device comprising: a gate electrode forming step for forming a gate electrode on a substrate; and a gate insulating layer forming step for forming a gate insulating layer so as to cover the gate electrode. And an organic semiconductor layer forming step for forming an organic semiconductor layer on the gate insulating layer, and a source for forming a source electrode and a drain electrode provided in contact with the organic semiconductor layer and spaced apart from each other A drain electrode forming step, a fluororesin layer forming step of forming a fluororesin layer so as to cover each upper surface of the organic semiconductor layer, the source electrode and the drain electrode, and a hydrophilization treatment on the exposed surface of the fluororesin layer Fluororesin layer surface hydrophilization treatment step to be applied and water-soluble resin layer to form a water-soluble resin layer on the fluororesin layer whose exposed surface has been subjected to hydrophilization treatment A resin layer forming step, a glass coating layer forming step for forming a glass coating layer on the water-soluble resin layer, and a pixel electrode forming step for forming a pixel electrode on the glass coating layer. And
　また、本発明の請求項５に係る発明の有機半導体素子の製造方法は、基板上に、有機半導体層を形成させる有機半導体層形成工程と、前記有機半導体層に接触するよう設けられると共に、互いに離間して配置されているソース電極及びドレイン電極を形成させるソース・ドレイン電極形成工程と、前記有機半導体層、ソース電極及びドレイン電極の各上面を覆うようにしてフッ素樹脂層を形成させるフッ素樹脂層形成工程と、前記フッ素樹脂層の露出面に親水化処理を施すフッ素樹脂層表面親水化処理工程と、露出面に親水化処理を施された前記フッ素樹脂層の上面に水溶性樹脂層を形成させる水溶性樹脂層形成工程と、前記水溶性樹脂層の上面に第１のガラスコーティング層を形成させる第１のガラスコーティング層形成工程と、前記第１のガラスコーティング層上の、前記有機半導体層と相対する場所にゲート電極を形成させるゲート電極形成工程と、前記第１のガラスコーティング層と前記ゲート電極の各上面を覆うように第２のガラスコーティング層を形成させる第２のガラスコーティング層形成工程と、前記第２のガラスコーティング層上面に画素電極を形成する画素電極形成工程と、により構成されることを特徴とする。 According to a fifth aspect of the present invention, there is provided an organic semiconductor element manufacturing method according to a fifth aspect of the present invention, comprising: an organic semiconductor layer forming step for forming an organic semiconductor layer on a substrate; A source / drain electrode forming step for forming a source electrode and a drain electrode spaced apart from each other, and a fluororesin layer for forming a fluororesin layer so as to cover each upper surface of the organic semiconductor layer, the source electrode, and the drain electrode Forming a hydrophilic resin layer on the exposed surface of the fluororesin layer, and forming a water-soluble resin layer on the top surface of the fluororesin layer on which the exposed surface has been hydrophilized A water-soluble resin layer forming step, a first glass coating layer forming step of forming a first glass coating layer on an upper surface of the water-soluble resin layer, and the first A gate electrode forming step of forming a gate electrode on the glass coating layer at a location facing the organic semiconductor layer, and a second glass coating so as to cover each upper surface of the first glass coating layer and the gate electrode The method includes a second glass coating layer forming step for forming a layer and a pixel electrode forming step for forming a pixel electrode on the upper surface of the second glass coating layer.
　請求項１に係る発明の有機半導体素子は、有機半導体層上に、フッ素樹脂層と、水溶性樹脂層と、ガラスコーティング層を順次積層することにより、有機半導体層にダメージを与えることなく、デバイス特性の優れた有機半導体素子を得ることができる。 The organic semiconductor element of the invention according to claim 1 is a device in which a fluororesin layer, a water-soluble resin layer, and a glass coating layer are sequentially laminated on an organic semiconductor layer without damaging the organic semiconductor layer. An organic semiconductor element having excellent characteristics can be obtained.
　請求項２に係る発明の有機半導体素子は、フッ素樹脂層を有機半導体層の直上に形成することにより、有機半導体層にダメージを与えずに保護膜が形成することができる。また、ガラスコーティング層を形成することにより、スルーホール形成時のフォトレジストによるダメージを受けない保護膜が形成することができる。また、ガラスコーティング層を形成することにより、水溶性樹脂層上に画素電極を形成する場合と比べて画素電極を容易に形成することが可能となる。また、フッ素樹脂層とガラスコーティング層の中間に水溶性樹脂層を形成することにより、ガラスコーティング層形成時の有機半導体層へのダメージを軽減することができる。以上のことにより、形成時のダメージが少なく、デバイス特性に優れ、加工性の高い有機半導体素子を得ることができる。 In the organic semiconductor element of the invention according to claim 2, the protective film can be formed without damaging the organic semiconductor layer by forming the fluororesin layer directly on the organic semiconductor layer. Further, by forming the glass coating layer, it is possible to form a protective film that is not damaged by the photoresist when the through hole is formed. Further, by forming the glass coating layer, the pixel electrode can be easily formed as compared with the case where the pixel electrode is formed on the water-soluble resin layer. Moreover, the damage to the organic-semiconductor layer at the time of glass coating layer formation can be reduced by forming a water-soluble resin layer in the middle of a fluororesin layer and a glass coating layer. As described above, it is possible to obtain an organic semiconductor element with little damage during formation, excellent device characteristics, and high workability.
　請求項３に係る発明の有機半導体素子は、フッ素樹脂層を有機半導体層の直上に形成することにより、有機半導体層にダメージを与えずにゲート絶縁積層が形成することができる。また、第１のガラスコーティング層を形成することにより、水溶性樹脂層上に画素電極を形成する場合と比べて、画素電極を容易に形成することが可能となる。また、フッ素樹脂層と第１のガラスコーティング層の中間に水溶性樹脂層を形成することにより、ガラスコーティング層形成時の有機半導体層へのダメージを軽減することができる。また、第２のガラスコーティング層を形成することにより、スルーホール形成時のフォトレジストによるダメージを受けない保護膜が形成することができる。以上のことにより、形成時のダメージが少なく、デバイス特性に優れ、加工性の高い有機半導体素子を得ることができる。 In the organic semiconductor element of the invention according to claim 3, by forming the fluororesin layer directly on the organic semiconductor layer, a gate insulating laminate can be formed without damaging the organic semiconductor layer. Further, by forming the first glass coating layer, the pixel electrode can be easily formed as compared with the case where the pixel electrode is formed on the water-soluble resin layer. Moreover, the damage to the organic-semiconductor layer at the time of glass coating layer formation can be reduced by forming a water-soluble resin layer in the middle of a fluororesin layer and a 1st glass coating layer. Further, by forming the second glass coating layer, it is possible to form a protective film that is not damaged by the photoresist when the through hole is formed. As described above, it is possible to obtain an organic semiconductor element with little damage during formation, excellent device characteristics, and high workability.
　請求項４に係る発明の有機半導体素子の製造方法は、形成時のダメージが少なく、デバイス特性に優れ、加工性の高い有機半導体素子を製造することが可能となる。 The method for producing an organic semiconductor element of the invention according to claim 4 makes it possible to produce an organic semiconductor element having little process damage, excellent device characteristics, and high processability.
　請求項５に係る発明の有機半導体素子の製造方法は、形成時のダメージが少なく、デバイス特性に優れ、加工性の高い有機半導体素子を製造することが可能となる。 The method for producing an organic semiconductor element of the invention according to claim 5 makes it possible to produce an organic semiconductor element with little damage during formation, excellent device characteristics, and high workability.
第１実施形態の有機半導体素子１の縦断面図である。It is a longitudinal cross-sectional view of the organic-semiconductor element 1 of 1st Embodiment. 第１実施形態の有機半導体素子１の製造工程を示すフローチャートである。It is a flowchart which shows the manufacturing process of the organic-semiconductor element 1 of 1st Embodiment. 比較例１の有機半導体素子１ａの縦断面図である。6 is a longitudinal sectional view of an organic semiconductor element 1a of Comparative Example 1. FIG. 比較例２の有機半導体素子１ｂの縦断面図である。6 is a longitudinal sectional view of an organic semiconductor element 1b of Comparative Example 2. FIG. 比較例３の有機半導体素子１ｃの縦断面図である。It is a longitudinal cross-sectional view of the organic-semiconductor element 1c of the comparative example 3. 第１実施形態の有機半導体素子１の電圧－電流特性図である。FIG. 3 is a voltage-current characteristic diagram of the organic semiconductor element 1 of the first embodiment. 比較例１の有機半導体素子１ａの電圧－電流特性図である。6 is a voltage-current characteristic diagram of an organic semiconductor element 1a of Comparative Example 1. FIG. 比較例２の有機半導体素子１ｂの電圧－電流特性図である。6 is a voltage-current characteristic diagram of an organic semiconductor element 1b of Comparative Example 2. FIG. 比較例３の有機半導体素子１ｃの電圧－電流特性図である。10 is a voltage-current characteristic diagram of an organic semiconductor element 1c of Comparative Example 3. FIG. 第２実施形態の有機半導体素子１００の断面図である。It is sectional drawing of the organic-semiconductor element 100 of 2nd Embodiment. 第２実施形態の有機半導体素子１００の製造工程を示すフローチャートである。It is a flowchart which shows the manufacturing process of the organic-semiconductor element 100 of 2nd Embodiment.
＜第１実施形態＞
　以下、本発明の有機半導体素子について、図面を参照して説明する。 <First Embodiment>
Hereinafter, the organic semiconductor element of the present invention will be described with reference to the drawings.
　第１実施形態の有機半導体素子１は、ゲート電極３がソース電極７やドレイン電極８よりも下側に位置する、所謂「ボトムゲート型」の有機半導体素子である。第1実施形態の有機半導体素子１は、ソース電極７、ドレイン電極８及び有機半導体層６の保護膜１０が、フッ素樹脂層１１、水溶性樹脂層１２及びガラスコーティング層１３の３層構造であることに特徴を有する。以下の説明では、図１において、図面下側（基板２側）を下側、図面上側を上側として説明する。なお、以降の図面においても同様に、図面下側を下側、図面上側を上側として説明する。 The organic semiconductor device 1 of the first embodiment is a so-called “bottom gate type” organic semiconductor device in which the gate electrode 3 is located below the source electrode 7 and the drain electrode 8. In the organic semiconductor device 1 of the first embodiment, the source electrode 7, the drain electrode 8, and the protective film 10 for the organic semiconductor layer 6 have a three-layer structure of a fluororesin layer 11, a water-soluble resin layer 12, and a glass coating layer 13. It has a special feature. In the following description, in FIG. 1, the lower side of the drawing (substrate 2 side) is the lower side, and the upper side of the drawing is the upper side. In the following drawings, similarly, the lower side of the drawing is described as the lower side, and the upper side of the drawing is described as the upper side.
　初めに、有機半導体素子１の断面構造について説明する。図１に示す有機半導体素子１は、板状の基板２を有する。基板２の上面にはゲート電極３が設けられている。ゲート電極３の上面及びゲート電極３の設けられていない基板２の上面にはゲート絶縁層４が積層されている。ゲート絶縁層４の上面には、ソース電極７とドレイン電極８が離間して設けられている。この離間しているスペースは、ゲート絶縁層４を挟んでゲート電極３と対向している。ソース電極７とドレイン電極８に挟まれるゲート絶縁層４の上面には前記ゲート電極７と前記ドレイン電極８とに接触するように有機半導体層６が設けられている。有機半導体層６、ソース電極７、ドレイン電極８、これらが設けられていないゲート絶縁層４の上面には保護膜１０が設けられている。保護膜１０は３層構造からなっており、下側からフッ素樹脂層１１、水溶性樹脂層１２、ガラスコーティング層１３の順に積層されている。保護膜１０の上面には画素電極２１が形成されている。この画素電極２１は、コンタクトホール３１により、ソース電極７と導通している。 First, the cross-sectional structure of the organic semiconductor element 1 will be described. An organic semiconductor element 1 shown in FIG. 1 has a plate-like substrate 2. A gate electrode 3 is provided on the upper surface of the substrate 2. A gate insulating layer 4 is laminated on the upper surface of the gate electrode 3 and the upper surface of the substrate 2 on which the gate electrode 3 is not provided. A source electrode 7 and a drain electrode 8 are provided on the upper surface of the gate insulating layer 4 so as to be separated from each other. This spaced space is opposed to the gate electrode 3 with the gate insulating layer 4 interposed therebetween. An organic semiconductor layer 6 is provided on the upper surface of the gate insulating layer 4 sandwiched between the source electrode 7 and the drain electrode 8 so as to be in contact with the gate electrode 7 and the drain electrode 8. A protective film 10 is provided on the upper surface of the organic semiconductor layer 6, the source electrode 7, the drain electrode 8, and the gate insulating layer 4 where these are not provided. The protective film 10 has a three-layer structure, and a fluororesin layer 11, a water-soluble resin layer 12, and a glass coating layer 13 are laminated in this order from the bottom. A pixel electrode 21 is formed on the upper surface of the protective film 10. The pixel electrode 21 is electrically connected to the source electrode 7 through a contact hole 31.
　基板２は、表面が平坦である板状部材である。基板２の材質としては、各種材質が適用可能であるが、導電性の材質を適用する場合には、基板２の表面には絶縁膜を設ける必要がある。基板２の材質として絶縁性の材質が用いられる場合には、ガラス基板、シリコン基板、プラスチック基板が用いられる。基板２に可撓性を付与したい場合には、特にプラスチック基板を用いる。プラスチックの材質としては、例えば、ポリエーテルスルホン（ＰＥＳ）、ポリエチレンテレフタレート（ＰＥＴ）、ポリイミド（ＰＩ）、ポリエチレンナフタレート（ＰＥＮ）、ポリエーテルイミド（ＰＥＩ）、ポリスチレン（ＰＳ）、ポリ塩化ビニル（ＰＶＣ）、ポリエチレン（ＰＥ）、ポリプロピレン（ＰＰ）等が挙げられる。基板２の耐水性を向上させる場合には、基板２の表面にＳｉＯ2やＳｉＮｘなどからなるガラスバリア膜が形成される。 The substrate 2 is a plate-like member having a flat surface. Various materials can be applied as the material of the substrate 2, but when a conductive material is applied, it is necessary to provide an insulating film on the surface of the substrate 2. When an insulating material is used as the material of the substrate 2, a glass substrate, a silicon substrate, or a plastic substrate is used. When it is desired to impart flexibility to the substrate 2, a plastic substrate is particularly used. Examples of plastic materials include polyethersulfone (PES), polyethylene terephthalate (PET), polyimide (PI), polyethylene naphthalate (PEN), polyetherimide (PEI), polystyrene (PS), and polyvinyl chloride (PVC). ), Polyethylene (PE), polypropylene (PP) and the like. In order to improve the water resistance of the substrate 2, a glass barrier film made of SiO 2 or SiNx is formed on the surface of the substrate 2.
　基板２の上面にはゲート電極３が設けられている。このゲート電極３の材質としては、Ａｕ，Ａｇ，Ｃｕ，Ｐｄ，Ａｌ，Ｍｏ，Ｃｒ，Ｔｉ，Ｔａ，Ｎｉ，Ｐｔ，Ｗ（タングステン）等の金属単体、または少なくともいずれかの金属を含む複合体、酸化インジウムスズ（ＩＴＯ）などの導電性酸化物、ポリエチレンジオキシチオフェン（ＰＥＤＯＴ）、ポリパラフェニレンビニレン（ＰＰＶ）等の導電性ポリマーが適用可能である。 A gate electrode 3 is provided on the upper surface of the substrate 2. The material of the gate electrode 3 is a single metal such as Au, Ag, Cu, Pd, Al, Mo, Cr, Ti, Ta, Ni, Pt, W (tungsten), or a composite containing at least one of the metals. In addition, a conductive oxide such as indium tin oxide (ITO), and a conductive polymer such as polyethylene dioxythiophene (PEDOT) and polyparaphenylene vinylene (PPV) are applicable.
　ゲート電極３及びゲート電極３の設けられていない基板２の各上面は、ゲート絶縁層４によって覆われている。ゲート絶縁層は、絶縁物質により形成されている。絶縁物質として無機絶縁物質を採用する場合は、Ａｌ2Ｏ3，ＳｉＯ2，ＳｉＮ，ＴｉＯ2等が適用可能である。また、絶縁物質として有機絶縁物質を採用する場合は、ＰＩ（ポリイミド）、ＰＭＭＡ（ポリメチルメタクリレート）、ＰＶＰ（ポリパラビニルフェノール）等が適用可能である。 Each upper surface of the substrate 2 on which the gate electrode 3 and the gate electrode 3 are not provided is covered with a gate insulating layer 4. The gate insulating layer is formed of an insulating material. When an inorganic insulating material is employed as the insulating material, Al 2 O 3 , SiO 2 , SiN, TiO 2, etc. can be applied. When an organic insulating material is employed as the insulating material, PI (polyimide), PMMA (polymethyl methacrylate), PVP (polyparavinylphenol), or the like can be applied.
　ゲート絶縁層４の上面には、有機半導体層６が、ゲート電極３とゲート絶縁層４を挟んで対向して設けられている。また、有機半導体層６を間に挟むように、ソース電極７とドレイン電極８が設けられている。ソース電極７とドレイン電極８とは互いに離間して配置されている。有機半導体６とソース電極７、及びドレイン電極８は接触して設けられている。 The organic semiconductor layer 6 is provided on the upper surface of the gate insulating layer 4 so as to face each other with the gate electrode 3 and the gate insulating layer 4 interposed therebetween. A source electrode 7 and a drain electrode 8 are provided so as to sandwich the organic semiconductor layer 6 therebetween. The source electrode 7 and the drain electrode 8 are spaced apart from each other. The organic semiconductor 6, the source electrode 7 and the drain electrode 8 are provided in contact with each other.
　有機半導体層６の材質としては、ペンタセン、テトラセン、アントラセン等のアセン類、銅フタロシアニン等のフタロシアニン類、ポリ（３－ヘキシルチオフェン）等のポリアルキルチオフェン類、アルキルオリゴチオフェン類等が挙げられる。 Examples of the material of the organic semiconductor layer 6 include acenes such as pentacene, tetracene, and anthracene, phthalocyanines such as copper phthalocyanine, polyalkylthiophenes such as poly (3-hexylthiophene), alkyl oligothiophenes, and the like.
　ソース電極７及びドレイン電極８の材質は、Ａｕ，Ａｇ，Ｃｕ，Ｐｄ，Ａｌ，Ｍｏ，Ｃｒ，Ｔｉ，Ｔａ，Ｎｉ，Ｐｔ，Ｗ（タングステン）等の金属単体、または少なくともいずれかの金属を含む複合体、酸化インジウムスズ（ＩＴＯ）などの導電性酸化物、ポリエチレンジオキシチオフェン（ＰＥＤＯＴ）、ポリパラフェニレンビニレン（ＰＰＶ）等の導電性ポリマーが適用可能である。また、複数種の金属の積層構造であってもよい。 The material of the source electrode 7 and the drain electrode 8 includes a single metal such as Au, Ag, Cu, Pd, Al, Mo, Cr, Ti, Ta, Ni, Pt, and W (tungsten), or at least one of the metals. A composite, a conductive oxide such as indium tin oxide (ITO), or a conductive polymer such as polyethylenedioxythiophene (PEDOT) or polyparaphenylene vinylene (PPV) is applicable. Moreover, the laminated structure of multiple types of metals may be sufficient.
　有機半導体層６、ソース電極７、ドレイン電極８、ゲート絶縁層４の各上面は、保護膜１０によって覆われている。保護膜１０は、下側のフッ素樹脂層１１、中側の水溶性樹脂層１２及び上側のガラスコーティング層１３が積層されて構成されている。 Each upper surface of the organic semiconductor layer 6, the source electrode 7, the drain electrode 8, and the gate insulating layer 4 is covered with a protective film 10. The protective film 10 is configured by laminating a lower fluororesin layer 11, a middle water-soluble resin layer 12, and an upper glass coating layer 13.
　フッ素樹脂層１１の材質としては、ポリテトラフルオロエチレン（例えばフロロサーフＦＧ３０３０：フロロテクノロジー社製、サイトップ：旭硝子社製）、１，１，１，２，３，４，４，５，５，５－デカフルオロペンタン（例えばフッソプラコート：ファインケミカルジャパン社製）フルオロエチレンプロピレンコポリマー、ペルフルオロアルコキシフッ素、エチレン四フッ化エチレンなどが挙げられる。 Examples of the material of the fluororesin layer 11 include polytetrafluoroethylene (for example, fluorosurf FG3030: manufactured by Fluoro Technology, Cytop: manufactured by Asahi Glass), 1,1,1,2,3,4,4,5,5,5. -Decafluoropentane (for example, fluorine plastic coat: manufactured by Fine Chemical Japan Co.) fluoroethylene propylene copolymer, perfluoroalkoxy fluorine, ethylene tetrafluoride ethylene and the like.
　水溶性樹脂層１２の材質としては、ポリビニルアルコール（例えばポバール：クラレ社製）、ポリエチレンオキサイド（例えばアルコックス：明成化学工業社製）、ポリアクリル酸ナトリウム等の水溶性ポリマー、エチレン酢酸ビニルエマルジョン、アクリルエマルジョン、酢酸ビニルエマルジョン、アクリルスチレンエマルジョン等の水溶性エマルジョンが挙げられる。 As the material of the water-soluble resin layer 12, polyvinyl alcohol (for example, Poval: manufactured by Kuraray Co., Ltd.), polyethylene oxide (for example, Alcox: manufactured by Meisei Chemical Co., Ltd.), water-soluble polymers such as sodium polyacrylate, ethylene vinyl acetate emulsion, Water-soluble emulsions such as acrylic emulsion, vinyl acetate emulsion, and acrylic styrene emulsion are listed.
　ガラスコーティング層１３の材質としては、ポリシラザン（例えばアクアミカ：ＡＺエレクトロニックマテリアルズ社製）等が挙げられる。 Examples of the material of the glass coating layer 13 include polysilazane (for example, Aquamica: manufactured by AZ Electronic Materials).
　保護膜１０の上面には、画素電極２１が設けられている。画素電極２１は、ＩＴＯ（酸化インジウムスズ）により形成される。 A pixel electrode 21 is provided on the upper surface of the protective film 10. The pixel electrode 21 is made of ITO (indium tin oxide).
　次に、有機半導体素子１の製造工程について説明する。有機半導体素子１の製造工程は、図２に示すように、基板２の上面にゲート電極３を形成するゲート電極形成工程（Ｓ１）と、ゲート電極３、基板２の上面を覆うようにゲート絶縁層４を形成するゲート絶縁層形成工程（Ｓ２）と、ソース電極７及びドレイン電極８を、ゲート絶縁層４上面のゲート電極３と対向した箇所を挟む形で離間して形成するソース・ドレイン電極形成工程（Ｓ３）と、ゲート絶縁層４上面の、ゲート電極３と対向した箇所に有機半導体層６を、ソース電極７及びドレイン電極８と接触させて形成する有機半導体層形成工程（Ｓ４）と、有機半導体層６、ソース電極７及びドレイン電極８を覆うように保護膜を形成する保護膜形成工程（Ｓ５）と、保護膜１０にコンタクトホール３１を形成するコンタクトホール形成工程（Ｓ６）と、コンタクトホール３１と接続するように画素電極２１を形成する画素電極形成工程（Ｓ７）とから構成されている。保護膜形成工程（Ｓ５）は、フッ素樹脂層１１を形成するフッ素樹脂層形成工程（Ｓ５１）と、フッ素樹脂層１１の上面に水溶性樹脂層１２を形成する水溶性樹脂層形成工程（Ｓ５２）と、水溶性樹脂層１２の上面にガラスコーティング層１３を形成するガラスコーティング層形成工程（Ｓ５３）とから構成されている。以下、各工程について実施例を挙げて説明する。 Next, the manufacturing process of the organic semiconductor element 1 will be described. As shown in FIG. 2, the manufacturing process of the organic semiconductor element 1 includes a gate electrode forming step (S1) for forming the gate electrode 3 on the upper surface of the substrate 2, and gate insulation so as to cover the upper surface of the gate electrode 3 and the substrate 2. The gate insulating layer forming step (S2) for forming the layer 4 and the source / drain electrodes formed by separating the source electrode 7 and the drain electrode 8 so as to sandwich the portion facing the gate electrode 3 on the upper surface of the gate insulating layer 4 A forming step (S3), and an organic semiconductor layer forming step (S4) in which the organic semiconductor layer 6 is formed in contact with the source electrode 7 and the drain electrode 8 at a position on the upper surface of the gate insulating layer 4 facing the gate electrode 3; A protective film forming step (S5) for forming a protective film so as to cover the organic semiconductor layer 6, the source electrode 7 and the drain electrode 8, and a contact hole formation for forming the contact hole 31 in the protective film 10 Extent and (S6), and is configured from the pixel electrode forming step of forming a pixel electrode 21 so as to be connected to the contact hole 31 (S7). The protective film forming step (S5) includes a fluororesin layer forming step (S51) for forming the fluororesin layer 11, and a water soluble resin layer forming step (S52) for forming the water soluble resin layer 12 on the upper surface of the fluororesin layer 11. And a glass coating layer forming step (S53) for forming the glass coating layer 13 on the upper surface of the water-soluble resin layer 12. Hereinafter, each step will be described with reference to examples.
　はじめに、Ｓ１のゲート電極形成工程が行われる。この工程では、基板２の上面にゲート電極３が形成される。本実施形態では、ガラスにより構成される基板２を洗浄後、基板２の上面にＣｒ薄膜を形成した。そして、形成したＣｒ薄膜のパターニングを行い、不要部分を除去することにより、ゲート電極３を形成した。Ｃｒ薄膜の製膜は、スパッタリング法によって行った。このときのターゲットとしてはＣｒを使用し、装置としてはＤＣスパッタ装置を用いた。形成されたＣｒ薄膜の上面に、フォトリソグラフィ法を用いてレジストパターンを形成した後、エッチング法を用いてＣｒ薄膜をエッチングした。不要となったフォトレジストは、アセトン洗浄により除去した。 First, the gate electrode forming step of S1 is performed. In this step, the gate electrode 3 is formed on the upper surface of the substrate 2. In this embodiment, the Cr thin film is formed on the upper surface of the substrate 2 after cleaning the substrate 2 made of glass. And the gate electrode 3 was formed by patterning the formed Cr thin film and removing an unnecessary part. The Cr thin film was formed by a sputtering method. At this time, Cr was used as the target, and a DC sputtering apparatus was used as the apparatus. A resist pattern was formed on the upper surface of the formed Cr thin film using a photolithography method, and then the Cr thin film was etched using an etching method. The unnecessary photoresist was removed by washing with acetone.
　次に、Ｓ２のゲート絶縁層形成工程が行われる。この工程では、ポリビニルフェノールとメラミンホルムアルデヒドをポリエチレングリコールモノメチルエーテルアセテートに溶解させてできた混合液を、ゲート電極３を備えた基板２の上面を覆うように、スピンコート法により成膜した。その後、アニール処理を１８０℃環境下にて２時間行った。こうして、ゲート電極３を備えた基板２の上面に、メラミンホルムアルデヒドで架橋されたポリビニルフェノールにより構成されるゲート絶縁層４を形成させた。 Next, the step S2 of forming a gate insulating layer is performed. In this step, a mixed solution obtained by dissolving polyvinyl phenol and melamine formaldehyde in polyethylene glycol monomethyl ether acetate was formed by spin coating so as to cover the upper surface of the substrate 2 provided with the gate electrode 3. Thereafter, annealing treatment was performed in an environment of 180 ° C. for 2 hours. Thus, the gate insulating layer 4 composed of polyvinylphenol crosslinked with melamine formaldehyde was formed on the upper surface of the substrate 2 provided with the gate electrode 3.
　次に、Ｓ３のソース・ドレイン電極形成工程が行われる。この工程では、まず有機半導体層６、ゲート絶縁層４の上面にＣｒ積層薄膜を形成した。次いでＡｕ薄膜を形成し、最終的にはＡｕとＣｒが積層された薄膜（Ａｕ／Ｃｒ薄膜）を形成した。そして、形成したＡｕ／Ｃｒ薄膜のパターニングを行い、不要部分を除去することにより、ゲート絶縁層４上面のゲート電極３と対向した箇所を挟む形で離間した、ソース電極７及びドレイン電極８を形成した。Ａｕ／Ｃｒ薄膜の製膜は、スパッタリング法によって行った。このときのターゲットとしてはＡｕ、Ｃｒをそれぞれ使用し、装置としてはＤＣスパッタ装置を用いた。形成されたＡｕ／Ｃｒ薄膜の上面に、フォトリソグラフィ法を用いてレジストパターンを形成した後、エッチング法を用いてＡｕ／Ｃｒ薄膜をエッチングした。不要となったフォトレジストは、アセトン洗浄により除去した。 Next, the source / drain electrode forming step of S3 is performed. In this step, first, a Cr laminated thin film was formed on the upper surfaces of the organic semiconductor layer 6 and the gate insulating layer 4. Next, an Au thin film was formed, and finally a thin film (Au / Cr thin film) in which Au and Cr were laminated was formed. Then, by patterning the formed Au / Cr thin film and removing unnecessary portions, a source electrode 7 and a drain electrode 8 are formed that are separated from each other with a portion facing the gate electrode 3 on the upper surface of the gate insulating layer 4 interposed therebetween. did. The Au / Cr thin film was formed by a sputtering method. At this time, Au and Cr were respectively used as targets, and a DC sputtering apparatus was used as an apparatus. A resist pattern was formed on the upper surface of the formed Au / Cr thin film using a photolithography method, and then the Au / Cr thin film was etched using an etching method. The unnecessary photoresist was removed by washing with acetone.
　次に、Ｓ４の有機半導体層形成工程が行われる。この工程では、ゲート絶縁層４上のゲート電極３と対向した位置にソース電極７及びドレイン電極８と接触させて、有機半導体層６を形成した。有機半導体層６としては、トリイソプロピルシリルエチニルペンタセンをインクジェット法にて形成した。その後、アニール処理を１２０℃環境下で５分間行った。 Next, the organic semiconductor layer forming step of S4 is performed. In this step, the organic semiconductor layer 6 was formed in contact with the source electrode 7 and the drain electrode 8 at a position facing the gate electrode 3 on the gate insulating layer 4. As the organic semiconductor layer 6, triisopropylsilylethynylpentacene was formed by an inkjet method. Thereafter, annealing treatment was performed for 5 minutes in a 120 ° C. environment.
　次に、Ｓ５の保護膜形成工程が行われる。Ｓ５の保護膜形成工程は、フッ素樹脂層形成工程（Ｓ５１）と、水溶性樹脂層形成工程（Ｓ５２）と、ガラスコーティング層形成工程（Ｓ５３）とから構成されている。 Next, the protective film forming step of S5 is performed. The protective film forming step of S5 includes a fluororesin layer forming step (S51), a water-soluble resin layer forming step (S52), and a glass coating layer forming step (S53).
　Ｓ５１のフッ素樹脂層形成工程では、ソース電極７、ドレイン電極８、有機半導体層６の上面を覆うように、フッソプラコート（ファインケミカルジャパン社製）をスピンコート法にて成膜した。次いでアニール処理を１２０℃環境下で５分間行った。こうして、フッ素樹脂層１１を形成した。 In the fluororesin layer forming step of S51, a fluorine plastic coat (manufactured by Fine Chemical Japan) was formed by a spin coat method so as to cover the upper surfaces of the source electrode 7, the drain electrode 8, and the organic semiconductor layer 6. Next, annealing was performed for 5 minutes in a 120 ° C. environment. Thus, the fluororesin layer 11 was formed.
　次に、Ｓ５２の水溶性樹脂層形成工程が行われる。この工程では、まず、フッ素樹脂層１１の表面を、プラズマクリーナ（ｄｉｅｎｅｒ　ｅｌｅｃｔｒｏｎｉｃ社製低圧プラズマ装置「ＦＥＭＴＯ」）にて３秒間処理することで、フッ素樹脂層１１の表面を親水化処理した。次いで、ポバール（クラレ社製）５重量％水溶液をスピンコート法にて成膜した。さらにアニール処理を１２０℃環境下で５分間行った。こうして、水溶性樹脂層１２を形成した。 Next, the water-soluble resin layer forming step of S52 is performed. In this step, first, the surface of the fluororesin layer 11 was hydrophilized by treating the surface of the fluororesin layer 11 with a plasma cleaner (low pressure plasma apparatus “FEMTO” manufactured by diener electronic) for 3 seconds. Next, a 5% by weight aqueous solution of Poval (manufactured by Kuraray Co., Ltd.) was formed by spin coating. Furthermore, annealing treatment was performed for 5 minutes in 120 degreeC environment. Thus, the water-soluble resin layer 12 was formed.
　次に、Ｓ５３のガラスコーティング層形成工程が行われる。この工程では、アクアミカ（ＡＺエレクトロニックマテリアルズ社製）をスピンコート法にて成膜した。さらにアニール処理を１２０℃環境下で５分間行った。こうして、ガラスコーティング層１３を形成した。 Next, the glass coating layer forming step of S53 is performed. In this step, aquamica (manufactured by AZ Electronic Materials) was formed by spin coating. Furthermore, annealing treatment was performed for 5 minutes in 120 degreeC environment. In this way, the glass coating layer 13 was formed.
　次に、Ｓ６のコンタクトホール形成工程が行われる。この工程では、フッ素樹脂層１１と水溶性樹脂層１２とガラスコーティング層１３とを貫通するコンタクトホール３１が形成される。コンタクトホール形成工程（Ｓ６）では、初めに、コンタクトホール３１に対応する箇所に開口部を備えたレジストマスクを、ガラスコーティング層１３の上面にフォトリソグラフィ法にて形成させる。次に、バッファードフッ酸を使用して、ガラスコーティング層１３及び水溶性樹脂層１２の一部をエッチングする。ここでフォトレジストを、アセトンを使用して剥離する。そして、酸素プラズマにてドライエッチング法により、ガラスコーティング層１３をレジスト代わりとして、水溶性樹脂層１２の残りとフッ素樹脂層１１とをエッチングする。こうしてコンタクトホール３１が形成される。 Next, the contact hole forming step of S6 is performed. In this step, a contact hole 31 that penetrates the fluororesin layer 11, the water-soluble resin layer 12, and the glass coating layer 13 is formed. In the contact hole forming step (S 6), first, a resist mask having an opening at a location corresponding to the contact hole 31 is formed on the upper surface of the glass coating layer 13 by photolithography. Next, a part of the glass coating layer 13 and the water-soluble resin layer 12 is etched using buffered hydrofluoric acid. Here, the photoresist is stripped using acetone. Then, the remainder of the water-soluble resin layer 12 and the fluororesin layer 11 are etched by dry etching with oxygen plasma, using the glass coating layer 13 as a resist. A contact hole 31 is thus formed.
　次に、Ｓ７の画素電極形成工程が行われる。この工程では、ガラスコーティング層１３の上面に、ＩＴＯ薄膜が形成された後、パターニングして不要部分が除去されることにより、ＩＴＯにより構成される画素電極２１が形成した。ＩＴＯ膜の形成は、スパッタリング法によって行った。ＩＴＯ膜形成後、レジストパターンを形成し、ＩＴＯ膜をエッチングし、不要となったフォトレジストは、アセトン洗浄により除去した。 Next, the pixel electrode forming step of S7 is performed. In this step, after the ITO thin film was formed on the upper surface of the glass coating layer 13, the pixel electrode 21 composed of ITO was formed by patterning to remove unnecessary portions. The ITO film was formed by a sputtering method. After the ITO film was formed, a resist pattern was formed, the ITO film was etched, and unnecessary photoresist was removed by washing with acetone.
　また、各比較例の縦断面図を図３～５に図示した。 Also, longitudinal sectional views of each comparative example are shown in FIGS.
　なお、ガラスコーティング層１３がなく、保護膜１０の最上面をフッ素樹脂層１１、または水溶性樹脂層１２として、その上面に画素電極２１を形成するような有機半導体素子１を製造することは、コンタクトホール形成工程において、ドライエッチングを適用した場合にはそのレジストの変質によりレジストの除去が困難になってしまうこと、ウエットエッチングを適用した場合には、フッ素樹脂はエッチングが不能であり、水溶性樹脂は水溶性であるが故にエッチングのレジスト除去工程において溶出してしまう危険性があること、また、水溶性樹脂上にはＩＴＯ膜の付着が難しいこと、などの理由により、製造は困難であるので、比較例としては示さなかった。 Note that manufacturing the organic semiconductor element 1 without the glass coating layer 13 and forming the pixel electrode 21 on the upper surface of the protective film 10 with the uppermost surface of the protective film 10 as the fluororesin layer 11 or the water-soluble resin layer 12 In the contact hole formation process, when dry etching is applied, it becomes difficult to remove the resist due to the alteration of the resist, and when wet etching is applied, fluororesin cannot be etched and is water-soluble. Since the resin is water-soluble, there is a risk of elution in the resist removal process of etching, and it is difficult to produce an ITO film on the water-soluble resin because it is difficult to adhere to the ITO film. Therefore, it was not shown as a comparative example.
　次に、上述の製造方法によって形成された有機半導体素子１の効果を確認するため、有機半導体素子１の性能評価を行った。この性能評価では、比較例として、保護膜１０ａを水溶性樹脂層１２とガラスコーティング層１３とのみから形成した有機半導体素子１ａに関する比較例１、保護膜１０ｂをフッ素樹脂１１とガラスコーティング層１３とのみから形成した有機半導体素子１ｂに関する比較例２、及び、保護膜１０ｃをガラスコーティング層１３のみから形成した有機半導体素子１ｃに関する比較例３についても性能評価を行った。 Next, in order to confirm the effect of the organic semiconductor element 1 formed by the manufacturing method described above, performance evaluation of the organic semiconductor element 1 was performed. In this performance evaluation, as a comparative example, Comparative Example 1 relating to the organic semiconductor element 1a in which the protective film 10a is formed only from the water-soluble resin layer 12 and the glass coating layer 13, and the protective film 10b as the fluororesin 11 and the glass coating layer 13 are used. Performance evaluation was also performed for Comparative Example 2 related to the organic semiconductor element 1b formed only from the organic semiconductor element 1b and Comparative Example 3 related to the organic semiconductor element 1c formed only from the glass coating layer 13 of the protective film 10c.
　性能評価の方法および性能評価の結果について、図６乃至図９を参照して説明する。なお、図６乃至図９において、曲線ａは、保護膜１０、１０ａ、１０ｂ、１０ｃ形成前の有機半導体素子１、１ａ、１ｂ、１ｃの電圧－電流特性を示し、曲線ｂは、保護膜１０、１０ａ、１０ｂ、１０ｃ形成後の有機半導体素子１、１ａ、１ｂ、１ｃの電圧－電流特性を示す。また、縦軸がドレイン電流値、横軸がゲート電圧値を示し、これらの評価を行った際のドレイン電圧は３０Ｖであった。 The performance evaluation method and performance evaluation results will be described with reference to FIGS. 6 to 9, the curve a represents the voltage-current characteristics of the organic semiconductor elements 1, 1a, 1b, and 1c before the formation of the protective films 10, 10a, 10b, and 10c, and the curve b represents the protective film 10. The voltage-current characteristics of the organic semiconductor elements 1, 1a, 1b and 1c after the formation of 10a, 10b and 10c are shown. Further, the vertical axis represents the drain current value, and the horizontal axis represents the gate voltage value. When these evaluations were performed, the drain voltage was 30V.
　第１実施形態の有機半導体素子１は、図６に示した通り、保護膜１０の形成によってＴＦＴ特性が変化することがない（しきい値電圧：５Ｖのまま変化なし、オンオフ比：１０6を保持）。一方、比較例１の有機半導体素子１ａは、図７に示した通り、そのしきい値電圧が高くなって（５Ｖ→２０Ｖ）しまい、かつオンオフ比の低下（１０6→１０3）も見られ、トランジスタ特性は悪化している。また、比較例２乃至３の有機半導体素子１ｂ、１ｃは、図８、図９に示した通り、いずれも曲線ｂがほぼ平坦である。このことは、保護膜１０ｂ、１０ｃ形成により比較例２乃至３の有機半導体素子１ｂ、１ｃがトランジスタとして動作しなくなってしまったことを示している。 As shown in FIG. 6, the organic semiconductor element 1 of the first embodiment has no change in TFT characteristics due to the formation of the protective film 10 (threshold voltage: 5 V remains unchanged, on / off ratio: 10 6 . Retention). On the other hand, as shown in FIG. 7, the organic semiconductor element 1a of Comparative Example 1 has a high threshold voltage (5V → 20V) and a decrease in on / off ratio (10 6 → 10 3 ). The transistor characteristics are getting worse. Further, in the organic semiconductor elements 1b and 1c of Comparative Examples 2 to 3, the curve b is almost flat as shown in FIGS. This indicates that the organic semiconductor elements 1b and 1c of Comparative Examples 2 to 3 no longer operate as transistors due to the formation of the protective films 10b and 10c.
　第１実施形態の有機半導体素子１と比較して、比較例１の有機半導体素子１ａは、保護膜１０にフッ素樹脂層１１が欠けている構造となっている。極性を持つ水溶性樹脂層１２を有機半導体層６の直上に形成することで、有機半導体のしきい値電圧が高くなり、オンオフ比が低下してしまうものと推測される。 Compared with the organic semiconductor element 1 of the first embodiment, the organic semiconductor element 1 a of Comparative Example 1 has a structure in which the protective resin 10 is missing the fluororesin layer 11. By forming the water-soluble resin layer 12 having polarity directly on the organic semiconductor layer 6, it is presumed that the threshold voltage of the organic semiconductor increases and the on / off ratio decreases.
　また、水溶性樹脂層１２のない構造の保護膜を持つ比較例２乃至３の有機半導体素子１ｂ、１ｃは、ガラスコーティング層１３を形成する際に、その溶媒として使用する有機溶媒の影響で、有機半導体に対しダメージを与えてしまい、そのためにトランジスタとして動作しなくなってしまうものと推測される。 In addition, the organic semiconductor elements 1b and 1c of Comparative Examples 2 to 3 having a protective film having a structure without the water-soluble resin layer 12 are affected by the organic solvent used as the solvent when the glass coating layer 13 is formed. It is presumed that the organic semiconductor is damaged, and as a result, it does not operate as a transistor.
　以上説明したとおり、第１実施形態の有機半導体素子１は、その保護膜１０を、まずフッ素樹脂層１１から形成することにより、水溶性樹脂層１２、ガラスコーティング層１３を有機半導体層６上に直接形成するよりも有機半導体に対するダメージが少なく、また、ガラスコーティング層１３を形成することにより、水溶性樹脂層１２上に画素電極２１を形成する場合と比べて画素電極２１を容易に形成でき、また、フッ素樹脂層１１とガラスコーティング層１３の中間に水溶性樹脂層１２を形成することによりガラスコーティング層１３形成時の有機半導体層６へのダメージを軽減できるため、安定したＴＦＴ特性を持つ有機半導体素子を得ることができる。 As described above, in the organic semiconductor element 1 of the first embodiment, the protective film 10 is first formed from the fluororesin layer 11 so that the water-soluble resin layer 12 and the glass coating layer 13 are formed on the organic semiconductor layer 6. There is less damage to the organic semiconductor than directly forming, and by forming the glass coating layer 13, the pixel electrode 21 can be easily formed as compared with the case where the pixel electrode 21 is formed on the water-soluble resin layer 12, In addition, since the water-soluble resin layer 12 is formed between the fluororesin layer 11 and the glass coating layer 13, damage to the organic semiconductor layer 6 during the formation of the glass coating layer 13 can be reduced. A semiconductor element can be obtained.
＜第２実施形態＞
　次に、本発明の第２の実施形態の有機半導体素子について、図面を参照して説明する。 Second Embodiment
Next, the organic semiconductor element of the 2nd Embodiment of this invention is demonstrated with reference to drawings.
　第２実施形態の有機半導体素子１００は、ゲート電極１０３がソース電極１０７やドレイン電極１０８よりも上側に位置する、所謂「トップゲート型」の有機半導体素子である。第２実施形態の有機半導体素子１００は、フッ素樹脂層１１０、水溶性樹脂層１２０及び第１のガラスコーティング層１３０の３層構造により構成されるゲート絶縁積層１０４を持つことに特徴を有する。 The organic semiconductor element 100 of the second embodiment is a so-called “top gate type” organic semiconductor element in which the gate electrode 103 is located above the source electrode 107 and the drain electrode 108. The organic semiconductor device 100 according to the second embodiment is characterized by having a gate insulating laminate 104 constituted by a three-layer structure of a fluororesin layer 110, a water-soluble resin layer 120, and a first glass coating layer 130.
　初めに、有機半導体素子１００の断面構造について説明する。図１０に示す有機半導体素子１００は、板状の基板２を有する。基板２の上面にはソース電極１０７、ドレイン電極１０８が離間して設けられている。ソース電極１０７とドレイン電極１０８に挟まれる基板２の上面には有機半導体層１０６がソース電極１０７とドレイン電極１０８に接触するように設けられている。有機半導体層１０６、ソース電極１０７、ドレイン電極１０８の上面にはゲート絶縁積層１０４が設けられている。ゲート絶縁積層１０４は３層構造からなっており、下側のフッ素樹脂層１１０、中側の水溶性樹脂層１２０、上側の第１のガラスコーティング層１３０の順に積層されて設けられている。ゲート絶縁積層１０４を挟んで有機半導体層１０６と対向した、ゲート絶縁積層１０４の上面にはゲート電極１０３が設けられている。ゲート電極１０３、及びゲート電極１０３が設けられていないゲート絶縁積層１０４の上面には第２のガラスコーティング層１４０が設けられている。第２のガラスコーティング層１４０の上面には画素電極１２１が形成されており、この画素電極１２１は、コンタクトホール１３１により、ソース電極１０７と導通している。 First, the cross-sectional structure of the organic semiconductor element 100 will be described. An organic semiconductor element 100 shown in FIG. 10 has a plate-like substrate 2. A source electrode 107 and a drain electrode 108 are provided apart from each other on the upper surface of the substrate 2. An organic semiconductor layer 106 is provided on the upper surface of the substrate 2 between the source electrode 107 and the drain electrode 108 so as to be in contact with the source electrode 107 and the drain electrode 108. A gate insulating laminate 104 is provided on the top surfaces of the organic semiconductor layer 106, the source electrode 107, and the drain electrode 108. The gate insulating laminate 104 has a three-layer structure, and is provided by laminating a lower fluororesin layer 110, a middle water-soluble resin layer 120, and an upper first glass coating layer 130 in this order. A gate electrode 103 is provided on the upper surface of the gate insulating laminate 104 facing the organic semiconductor layer 106 with the gate insulating laminate 104 interposed therebetween. A second glass coating layer 140 is provided on the upper surface of the gate insulating laminate 104 where the gate electrode 103 and the gate electrode 103 are not provided. A pixel electrode 121 is formed on the upper surface of the second glass coating layer 140, and the pixel electrode 121 is electrically connected to the source electrode 107 through a contact hole 131.
　第２実施形態の有機半導体素子の構成要素である、ゲート電極１０３、有機半導体層１０６、ソース電極１０７、ドレイン電極１０８、フッ素樹脂層１１０、水溶性樹脂層１２０、ガラスコーティング層１３０、画素電極１２１の材質は、第１実施形態の有機半導体素子１の構成要素である、ゲート電極３、有機半導体層６、ソース電極７、ドレイン電極８、フッ素樹脂層１１、水溶性樹脂層１２、ガラスコーティング層１３、画素電極２１とそれぞれ同様である。第２のガラスコーティング層１４０の材質は、第１のガラスコーティング層１３０と同様の、ポリシラザン（例えばアクアミカ：ＡＺエレクトロニックマテリアルズ社製）等が挙げられる。 The gate electrode 103, the organic semiconductor layer 106, the source electrode 107, the drain electrode 108, the fluororesin layer 110, the water-soluble resin layer 120, the glass coating layer 130, and the pixel electrode 121, which are components of the organic semiconductor element of the second embodiment. The material is a component of the organic semiconductor element 1 of the first embodiment, which is the gate electrode 3, the organic semiconductor layer 6, the source electrode 7, the drain electrode 8, the fluororesin layer 11, the water-soluble resin layer 12, and the glass coating layer. 13 and the pixel electrode 21, respectively. Examples of the material of the second glass coating layer 140 include polysilazane (for example, Aquamica: manufactured by AZ Electronic Materials), which is the same as the first glass coating layer 130.
　次に、有機半導体素子１００の製造工程について説明する。有機半導体素子１００の製造工程は、図１１に示すように、基板２の上面にソース電極１０７及びドレイン電極１０８を離間して形成するソース・ドレイン電極形成工程（Ｓ１０１）と、ソース電極１０７とドレイン電極１０８の間に有機半導体層１０６をソース電極１０７とドレイン電極１０８に接触するように形成する有機半導体層形成工程（Ｓ１０２）と、有機半導体層１０６、ソース電極１０７及びドレイン電極１０８を覆うようにゲート絶縁積層１０４を形成するゲート絶縁積層形成工程（Ｓ１０３）と、ゲート絶縁積層１０４上面の、有機半導体層１０６と対向した箇所にゲート電極１０３を形成するゲート電極形成工程（Ｓ１０４）と、ゲート電極１０３及びゲート電極１０３の形成されていないゲート絶縁積層１０４とを覆うように第２のガラスコーティング層１４０を形成する第２のガラスコーティング層形成工程（Ｓ１０５）と、ゲート絶縁積層１０４及び第２のガラスコーティング層１４０にコンタクトホール１３１を形成するコンタクトホール形成工程（Ｓ１０６）と、コンタクトホール１３１と接続するように画素電極１２１を形成する画素電極形成工程（Ｓ１０７）とから構成されている。ゲート絶縁積層形成工程（Ｓ１０３）は、フッ素樹脂層１１０を形成するフッ素樹脂層形成工程（Ｓ１３１）と、フッ素樹脂層１１０の上面に水溶性樹脂層１２０を形成する水溶性樹脂層形成工程（Ｓ１３２）と、水溶性樹脂層１２０の上面に第１のガラスコーティング層１３０を形成する第１のガラスコーティング層形成工程（Ｓ１３３）とから構成されている。以下、各工程について実施例を挙げて説明する。 Next, the manufacturing process of the organic semiconductor element 100 will be described. As shown in FIG. 11, the manufacturing process of the organic semiconductor device 100 includes a source / drain electrode formation step (S101) in which the source electrode 107 and the drain electrode 108 are formed on the upper surface of the substrate 2 apart from each other, and the source electrode 107 and the drain electrode. An organic semiconductor layer forming step (S102) for forming the organic semiconductor layer 106 in contact with the source electrode 107 and the drain electrode 108 between the electrodes 108, and so as to cover the organic semiconductor layer 106, the source electrode 107, and the drain electrode 108. A gate insulating layer forming step (S103) for forming the gate insulating layer 104, a gate electrode forming step (S104) for forming the gate electrode 103 at a location facing the organic semiconductor layer 106 on the upper surface of the gate insulating layer 104, and a gate electrode 103 and the gate insulating laminate 104 where the gate electrode 103 is not formed. The second glass coating layer forming step (S105) for forming the second glass coating layer 140 and the contact hole forming step (S106) for forming the contact hole 131 in the gate insulating laminate 104 and the second glass coating layer 140. ) And a pixel electrode formation step (S107) for forming the pixel electrode 121 so as to be connected to the contact hole 131. The gate insulating layer forming step (S103) includes a fluororesin layer forming step (S131) for forming the fluororesin layer 110, and a water soluble resin layer forming step (S132) for forming the water soluble resin layer 120 on the upper surface of the fluororesin layer 110. ), And a first glass coating layer forming step (S133) for forming the first glass coating layer 130 on the upper surface of the water-soluble resin layer 120. Hereinafter, each step will be described with reference to examples.
　はじめに、Ｓ１０１のソース・ドレイン電極形成工程が行われる。この工程では、基板２の上面にソース電極１０７及びドレイン電極１０８が離間して形成される。本実施形態では、ガラスにより構成される基板２を洗浄後、基板２の上面にＡｕ／Ｃｒ薄膜を形成した。そして、形成したＡｕ／Ｃｒ薄膜のパターニングを行い、不要部分を除去することにより、ソース電極１０７及びドレイン電極１０８を形成した。詳細については第１実施形態におけるソース・ドレイン電極形成工程（Ｓ４）と同様であるため、説明は省略する。 First, the source / drain electrode forming step of S101 is performed. In this step, the source electrode 107 and the drain electrode 108 are formed apart from each other on the upper surface of the substrate 2. In this embodiment, the Au / Cr thin film is formed on the upper surface of the substrate 2 after cleaning the substrate 2 made of glass. Then, by patterning the formed Au / Cr thin film and removing unnecessary portions, the source electrode 107 and the drain electrode 108 were formed. Details are the same as in the source / drain electrode formation step (S4) in the first embodiment, and a description thereof will be omitted.
　次に、Ｓ１０２の有機半導体層形成工程が行われる。この工程は、第１実施形態における有機半導体層形成工程（Ｓ３）と同様であるため、説明は省略する。 Next, the organic semiconductor layer forming step of S102 is performed. Since this step is the same as the organic semiconductor layer forming step (S3) in the first embodiment, the description thereof is omitted.
　次に、Ｓ１０３のゲート絶縁積層形成工程が行われる。この工程は、フッ素樹脂層形成工程（Ｓ１３１）、水溶性樹脂層形成工程（Ｓ１３２）、第１のガラスコーティング層形成工程（Ｓ１３３）により構成される。フッ素樹脂層形成工程（Ｓ１３１）、水溶性樹脂層形成工程（Ｓ１３２）、第１のガラスコーティング層形成工程（Ｓ１３３）はそれぞれ、第１実施形態のフッ素樹脂層形成工程（Ｓ５１）、水溶性樹脂層形成工程（Ｓ５２）、ガラスコーティング層形成工程（Ｓ５３）と同様であるため、説明は省略する。 Next, the gate insulating layer forming step of S103 is performed. This step includes a fluororesin layer forming step (S131), a water-soluble resin layer forming step (S132), and a first glass coating layer forming step (S133). The fluororesin layer forming step (S131), the water-soluble resin layer forming step (S132), and the first glass coating layer forming step (S133) are respectively the fluororesin layer forming step (S51) and the water-soluble resin of the first embodiment. Since it is the same as the layer forming step (S52) and the glass coating layer forming step (S53), description thereof is omitted.
　次に、Ｓ１０４のゲート電極形成工程が行われる。この工程は、ゲート絶縁積層１０４の上面にＣｒ薄膜を形成した。そして、形成したＣｒ薄膜のパターニングを行い、不要部分を除去することにより、ゲート電極１０３を形成した。詳細については第１実施形態におけるゲート電極形成工程（Ｓ１）と同様であるため、説明は省略する。 Next, the gate electrode forming step of S104 is performed. In this step, a Cr thin film was formed on the upper surface of the gate insulating laminate 104. And the gate electrode 103 was formed by patterning the formed Cr thin film and removing an unnecessary part. Details are the same as those in the gate electrode formation step (S1) in the first embodiment, and thus the description thereof is omitted.
　次に、Ｓ１０５の第２のガラスコーティング層形成工程が行われる。Ｓ１０５の保護膜形成工程は、ゲート電極１０３及びゲート電極１０３の形成されていない第２実施形態のゲート絶縁層１０４を覆うように第２のガラスコーティング層１４０を形成した。具体的には、アクアミカ（ＡＺエレクトロニックマテリアルズ社製）をスピンコート法にて成膜し、その後アニール処理を１２０℃環境下で５分間実施することによって形成した。 Next, the second glass coating layer forming step of S105 is performed. In the protective film forming step of S105, the second glass coating layer 140 is formed so as to cover the gate electrode 103 and the gate insulating layer 104 of the second embodiment in which the gate electrode 103 is not formed. Specifically, aquamica (manufactured by AZ Electronic Materials) was formed by spin coating, and then annealed for 5 minutes in a 120 ° C. environment.
　次に、Ｓ１０６のコンタクトホール形成工程が行われ、次いでＳ１０７の画素電極形成工程が行われる。これらの工程は、それぞれ第１実施形態のコンタクトホール形成工程（Ｓ６）及び画素電極形成工程（Ｓ７）と同様であるため、説明は省略する。 Next, the contact hole forming step of S106 is performed, and then the pixel electrode forming step of S107 is performed. These steps are the same as the contact hole forming step (S6) and the pixel electrode forming step (S7) of the first embodiment, respectively, and thus description thereof is omitted.
　第２実施形態の有機半導体素子１００でも、第１実施形態の有機半導体素子１と同様の効果が得られる。第２実施形態の有機半導体素子１００は、そのゲート絶縁積層１０４を、まずフッ素樹脂層１１０から形成することにより、水溶性樹脂層１２０、ガラスコーティング層１３０を有機半導体層１０６上に直接形成するよりも有機半導体に対するダメージが少なく、また、第１のガラスコーティング層１３０を形成することにより、水溶性樹脂層１２０上に画素電極１２１を形成する場合と比べて画素電極１２１を容易に形成でき、また、フッ素樹脂層１１０と第１のガラスコーティング層１３０の中間に水溶性樹脂層１２０を形成することによりガラスコーティング層１３０形成時の有機半導体層１０６へのダメージを軽減できるため、安定したＴＦＴ特性を持つ有機半導体素子を得ることができる。 Also in the organic semiconductor element 100 of the second embodiment, the same effect as that of the organic semiconductor element 1 of the first embodiment can be obtained. In the organic semiconductor device 100 of the second embodiment, the gate insulating laminate 104 is first formed from the fluororesin layer 110, thereby forming the water-soluble resin layer 120 and the glass coating layer 130 directly on the organic semiconductor layer 106. In addition, there is little damage to the organic semiconductor, and by forming the first glass coating layer 130, the pixel electrode 121 can be easily formed as compared with the case where the pixel electrode 121 is formed on the water-soluble resin layer 120. Since the water-soluble resin layer 120 is formed between the fluororesin layer 110 and the first glass coating layer 130, damage to the organic semiconductor layer 106 when the glass coating layer 130 is formed can be reduced, so that stable TFT characteristics can be obtained. An organic semiconductor element can be obtained.
　なお、本発明は、詳述した実施形態に限定されるものではなく、本開示の要旨を逸脱しない範囲内において種々変更を加えてもよい。例えば、有機半導体素子を構成する基板、ゲート電極、ソース電極、ドレイン電極、ゲート絶縁層、有機半導体層の材料、大きさ、形状は実施形態の場合に限定されず、本開示の要旨を逸脱しない範囲内において適宜変更可能である。 Note that the present invention is not limited to the embodiments described in detail, and various modifications may be made without departing from the scope of the present disclosure. For example, the materials, sizes, and shapes of the substrate, the gate electrode, the source electrode, the drain electrode, the gate insulating layer, and the organic semiconductor layer that constitute the organic semiconductor element are not limited to the embodiment, and do not depart from the gist of the present disclosure. It can be changed as appropriate within the range.
　また、第１実施形態及び第２実施形態では、ソース電極とドレイン電極とを形成させた後に有機半導体層を形成させたが、有機半導体層を形成させた後にソース電極とドレイン電極とを形成させてもよい。 In the first and second embodiments, the organic semiconductor layer is formed after forming the source electrode and the drain electrode. However, after forming the organic semiconductor layer, the source electrode and the drain electrode are formed. May be.
　本発明の酸化物薄膜トランジスタ及び酸化物薄膜トランジスタの製造方法は、所謂ボトムゲート型またはトップゲート型の酸化物薄膜トランジスタ及びその製造方法に適用可能である。 The oxide thin film transistor and the method for manufacturing the oxide thin film transistor of the present invention can be applied to a so-called bottom gate type or top gate type oxide thin film transistor and a method for manufacturing the same.
１　　　第１実施形態の有機半導体素子
２　　　基板
３　　　ゲート電極
４　　　ゲート絶縁層
６　　　有機半導体層
７　　　ソース電極
８　　　ドレイン電極
１０　　保護膜
１１　　フッ素樹脂層
１２　　水溶性樹脂層
１３　　ガラスコーティング層
２１　　画素電極
３１　　スルーホール
１００　第２実施形態の有機半導体素子
１０３　ゲート電極
１０４　ゲート絶縁積層
１０６　有機半導体層
１０７　ソース電極
１０８　ドレイン電極
１１０　フッ素樹脂層
１２０　水溶性樹脂層
１３０　第１のガラスコーティング層
１４０　第２のガラスコーティング層 DESCRIPTION OF SYMBOLS 1 Organic-semiconductor element 2 of 1st Embodiment Substrate 3 Gate electrode 4 Gate insulating layer 6 Organic semiconductor layer 7 Source electrode 8 Drain electrode 10 Protective film 11 Fluororesin layer 12 Water-soluble resin layer 13 Glass coating layer 21 Pixel electrode 31 Through hole 100 Organic Semiconductor Element 103 of Second Embodiment Gate Electrode 104 Gate Insulating Stack 106 Organic Semiconductor Layer 107 Source Electrode 108 Drain Electrode 110 Fluoro Resin Layer 120 Water-soluble Resin Layer 130 First Glass Coating Layer 140 Second Glass Coating Layer

Claims (5)

  1. 　絶縁機能を有する絶縁層の上面に設けられた有機半導体層上に、
    　フッ素樹脂層と、水溶性樹脂層と、ガラスコーティング層とを順次積層して形成したことを特徴とする有機半導体素子。     On the organic semiconductor layer provided on the upper surface of the insulating layer having an insulating function,
    An organic semiconductor element characterized by being formed by sequentially laminating a fluororesin layer, a water-soluble resin layer, and a glass coating layer.
  2. 　基板上に設けられているゲート電極と、
    　前記ゲート電極を覆うように設けられた絶縁層であるゲート絶縁層と、
    　前記ゲート絶縁層の上面に設けられた有機半導体層と、
    　前記有機半導体層に接触するよう設けられると共に、互いに離間して配置されたソース電極及びドレイン電極とにより構成される有機半導体素子において、
    　前記有機半導体層、ソース電極及びドレイン電極の各上面を覆うようにして設けられたフッ素樹脂層と、
    　前記フッ素樹脂層上に設けられた水溶性樹脂層と、
    　前記水溶性樹脂層上に設けられたガラスコーティング層と、
    　前記ガラスコーティング層上に設けられた画素電極と
    　により構成されることを特徴とする有機半導体素子。     A gate electrode provided on the substrate;
    A gate insulating layer which is an insulating layer provided so as to cover the gate electrode;
    An organic semiconductor layer provided on an upper surface of the gate insulating layer;
    In the organic semiconductor element that is provided so as to be in contact with the organic semiconductor layer and includes a source electrode and a drain electrode that are arranged apart from each other,
    A fluororesin layer provided so as to cover each upper surface of the organic semiconductor layer, the source electrode and the drain electrode;
    A water-soluble resin layer provided on the fluororesin layer;
    A glass coating layer provided on the water-soluble resin layer;
    An organic semiconductor element comprising: a pixel electrode provided on the glass coating layer.
  3. 　絶縁機能を有する絶縁層である基板と、
    　前記基板上に設けられた有機半導体層と、
    　前記有機半導体層に接触するよう設けられると共に、互いに離間して配置されたソース電極及びドレイン電極と、
    　前記有機半導体層、ソース電極及びドレイン電極の各上面を覆うようにして設けられたフッ素樹脂層と、
    　前記フッ素樹脂層上に設けられた水溶性樹脂層と、
    　前記水溶性樹脂層上に設けられた第１のガラスコーティング層と、
    　前記フッ素樹脂層と前記水溶性樹脂層と前記第１のガラスコーティング層とが積層されて形成されるゲート絶縁積層上の、前記有機半導体層と相対する場所に設けられたゲート電極と、
    　前記第１のガラスコーティング層と前記ゲート電極の各上面を覆うように設けられた第２のガラスコーティング層と、
    　前記第２のガラスコーティング層上に設けられた画素電極と
    　により構成されることを特徴とする有機半導体素子。     A substrate which is an insulating layer having an insulating function;
    An organic semiconductor layer provided on the substrate;
    A source electrode and a drain electrode provided in contact with the organic semiconductor layer and spaced apart from each other;
    A fluororesin layer provided so as to cover each upper surface of the organic semiconductor layer, the source electrode and the drain electrode;
    A water-soluble resin layer provided on the fluororesin layer;
    A first glass coating layer provided on the water-soluble resin layer;
    A gate electrode provided at a location facing the organic semiconductor layer on a gate insulating laminate formed by laminating the fluororesin layer, the water-soluble resin layer, and the first glass coating layer;
    A second glass coating layer provided so as to cover each upper surface of the first glass coating layer and the gate electrode;
    An organic semiconductor element comprising: a pixel electrode provided on the second glass coating layer.
  4. 　基板上にゲート電極を形成させるゲート電極形成工程と、
    　前記ゲート電極を覆うようにゲート絶縁層を形成させるゲート絶縁層形成工程と、
    　前記ゲート絶縁層上に有機半導体層を形成させる有機半導体層形成工程と、
    　前記有機半導体層に接触するよう設けられると共に、互いに離間して配置されているソース電極及びドレイン電極を形成させるソース・ドレイン電極形成工程と、
    　前記有機半導体層、ソース電極及びドレイン電極の各上面を覆うようにしてフッ素樹脂層を形成させるフッ素樹脂層形成工程と、
    　前記フッ素樹脂層の露出面に親水化処理を施すフッ素樹脂層表面親水化処理工程と、
    　露出面に親水化処理を施された前記フッ素樹脂層上に水溶性樹脂層を形成させる水溶性樹脂層形成工程と、
    　前記水溶性樹脂層上にガラスコーティング層を形成させるガラスコーティング層形成工程と、
    　前記ガラスコーティング層上に画素電極を形成させる画素電極形成工程と、
    　により構成されることを特徴とする有機半導体素子の製造方法。     A gate electrode forming step of forming a gate electrode on the substrate;
    A gate insulating layer forming step of forming a gate insulating layer so as to cover the gate electrode;
    An organic semiconductor layer forming step of forming an organic semiconductor layer on the gate insulating layer;
    A source / drain electrode forming step of forming a source electrode and a drain electrode provided in contact with the organic semiconductor layer and spaced apart from each other;
    A fluororesin layer forming step of forming a fluororesin layer so as to cover each upper surface of the organic semiconductor layer, the source electrode and the drain electrode;
    A fluororesin layer surface hydrophilization treatment step of hydrophilizing the exposed surface of the fluororesin layer;
    A water-soluble resin layer forming step of forming a water-soluble resin layer on the fluororesin layer subjected to hydrophilic treatment on the exposed surface;
    A glass coating layer forming step of forming a glass coating layer on the water-soluble resin layer;
    A pixel electrode forming step of forming a pixel electrode on the glass coating layer;
    The manufacturing method of the organic-semiconductor element characterized by these.
  5. 　基板上に、有機半導体層を形成させる有機半導体層形成工程と、
    　前記有機半導体層に接触するよう設けられると共に、互いに離間して配置されているソース電極及びドレイン電極を形成させるソース・ドレイン電極形成工程と、
    　前記有機半導体層、ソース電極及びドレイン電極の各上面を覆うようにしてフッ素樹脂層を形成させるフッ素樹脂層形成工程と、
    　前記フッ素樹脂層の露出面に親水化処理を施すフッ素樹脂層表面親水化処理工程と、
    　露出面に親水化処理を施された前記フッ素樹脂層の上面に水溶性樹脂層を形成させる水溶性樹脂層形成工程と、
    　前記水溶性樹脂層の上面に第１のガラスコーティング層を形成させる第１のガラスコーティング層形成工程と、
    　前記第１のガラスコーティング層上の、前記有機半導体層と相対する場所にゲート電極を形成させるゲート電極形成工程と、
    　前記第１のガラスコーティング層と前記ゲート電極の各上面を覆うように第２のガラスコーティング層を形成させる第２のガラスコーティング層形成工程と、
    　前記第２のガラスコーティング層上面に画素電極を形成する画素電極形成工程と、
    　により構成されることを特徴とする有機半導体素子の製造方法。     An organic semiconductor layer forming step of forming an organic semiconductor layer on the substrate;
    A source / drain electrode forming step of forming a source electrode and a drain electrode provided in contact with the organic semiconductor layer and spaced apart from each other;
    A fluororesin layer forming step of forming a fluororesin layer so as to cover each upper surface of the organic semiconductor layer, the source electrode and the drain electrode;
    A fluororesin layer surface hydrophilization treatment step of hydrophilizing the exposed surface of the fluororesin layer;
    A water-soluble resin layer forming step of forming a water-soluble resin layer on the upper surface of the fluororesin layer subjected to hydrophilization treatment on the exposed surface;
    A first glass coating layer forming step of forming a first glass coating layer on the upper surface of the water-soluble resin layer;
    A gate electrode formation step of forming a gate electrode on the first glass coating layer at a location facing the organic semiconductor layer;
    A second glass coating layer forming step of forming a second glass coating layer so as to cover each upper surface of the first glass coating layer and the gate electrode;
    Forming a pixel electrode on the upper surface of the second glass coating layer; and
    The manufacturing method of the organic-semiconductor element characterized by these.
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