WO2010026798A1

WO2010026798A1 - Oxide thin film transistor and method for manufacturing the same

Info

Publication number: WO2010026798A1
Application number: PCT/JP2009/056593
Authority: WO
Inventors: 竜太飯島; 徳子美浦; 元士板垣
Original assignee: ブラザー工業株式会社
Priority date: 2008-09-03
Filing date: 2009-03-31
Publication date: 2010-03-11
Also published as: JP2010062276A

Abstract

An oxide thin film transistor (1) is provided with a first insulating layer (2); an oxide semiconductor layer (9) which forms a channel section on an upper surface of the first insulating layer (2); a source electrode (3) and a drain electrode (4) arranged by being spaced apart with a channel section therebetween; and a second insulating layer (5) arranged on an upper surface of the oxide semiconductor layer (9). The second insulating layer (5) is provided with a non-fluoric organic polymer layer (51) composed of non-fluoric organic polymer molecules, and an amorphous perfluoro resin layer (52) composed of an amorphous perfluoro resin.

Description

Oxide thin film transistor and manufacturing method thereof

The present invention relates to an oxide thin film transistor and a method for manufacturing the same.

Conventionally, an active drive circuit including a thin film transistor is embedded in each pixel of a flexible display such as an organic EL, a film liquid crystal, and electronic paper. In recent years, an oxide thin film transistor using an oxide as a material of a semiconductor layer of a thin film transistor has been developed. It is known that an oxide semiconductor layer can be formed at a low temperature and has high field-effect mobility. In addition, some oxide semiconductors include transparent oxide semiconductors. If a transparent oxide semiconductor and a known transparent substrate material are selected as materials, a transparent thin film transistor can be formed. Can be expected.

Incidentally, the insulating layer formed on the upper surface of the oxide semiconductor layer is generally formed by a vacuum process such as a sputtering method or a plasma CVD method. However, these methods have a problem that the apparatus becomes large and costs increase, and the process is complicated. In addition, when an insulating layer is formed by these methods, there is a problem that plasma ions generated from the apparatus in the forming process damage the oxide semiconductor layer and the like.

Thus, for example, a semiconductor device has been proposed that employs an organic polymer such as polyimide or polyamide as the material of the insulating layer on the top surface of the oxide semiconductor layer (see, for example, Patent Document 1). In this semiconductor device (oxide thin film transistor in the present application), a polymer resin is used as the material of the insulating layer on the top surface of the oxide semiconductor layer, and therefore the insulating layer can be formed by a coating method. Thus, the insulating layer can be formed without damaging the oxide semiconductor layer.
JP 2007-158147 A

However, this semiconductor device has the following problems. A gate electrode and a pixel electrode are formed on the upper surface of the insulating layer, and cleaning with pure water is performed in the formation process. When the insulating layer is composed of only an organic polymer resin layer such as polyimide or polyamide as in this semiconductor device, pure water passes through the insulating layer and reaches the oxide semiconductor layer during the cleaning process. There is a risk that. When the oxide semiconductor layer takes in moisture, the oxide thin film transistor has a problem that it is difficult to stabilize the characteristics. In order to stabilize characteristics of an oxide thin film transistor, heat treatment is generally performed after formation to remove moisture from the oxide semiconductor layer. However, when the insulating layer is made of only an organic polymer resin layer such as polyimide or polyamide as in the semiconductor device described above, the oxide semiconductor layer may be damaged during this heat treatment. Therefore, the heat treatment results in a problem that the semiconductor characteristics of the oxide semiconductor layer are deteriorated and the transistor characteristics are deteriorated.

The present invention has been made to solve the above-described problems, and an object thereof is to provide an oxide thin film transistor having stable characteristics and a method for manufacturing the same.

According to the present disclosure, the first insulating layer, the oxide semiconductor layer that forms the channel portion on the upper surface of the first insulating layer, the source electrode that is provided apart from each other via the channel portion, and A drain electrode; and a second insulating layer provided on an upper surface of the oxide semiconductor layer, wherein the second insulating layer includes a non-fluorine organic polymer layer made of a non-fluorine organic polymer, an amorphous material An oxide thin film transistor including an amorphous perfluoro resin layer made of a perfluoro resin is provided.

According to the present disclosure, the oxide semiconductor layer forming step of forming the oxide semiconductor layer on the upper surface of the first insulating layer, and the source electrodes separated from each other via the channel portion formed by the oxide semiconductor layer And a source / drain electrode forming step for forming a drain electrode, and a second insulating layer forming step for forming a second insulating layer on the top surface of the oxide semiconductor layer, wherein the second insulating layer forming step includes: A non-fluorine organic polymer layer forming step for forming a non-fluorine organic polymer layer composed of a fluorine-based organic polymer; and an amorphous perfluoro resin layer forming step for forming an amorphous perfluoro resin layer composed of an amorphous perfluoro resin. There is provided a method for manufacturing an oxide thin film transistor comprising:

1 is a longitudinal sectional view of an oxide thin film transistor 1 of a first embodiment. It is a flowchart which shows the manufacturing process of the oxide thin-film transistor 1 of 1st embodiment. 2 is a longitudinal sectional view of a state in which a source electrode 3 and a drain electrode 4 are formed on the upper surface of a substrate 2. FIG. FIG. 4 is a longitudinal sectional view showing a state where an oxide semiconductor layer 9 is formed between a source electrode 3 and a drain electrode 4 shown in FIG. 3. 2 is a longitudinal sectional view showing a state in which a non-fluorine organic resin layer 51 is formed on the top surfaces of a substrate 2, a source electrode 3, a drain electrode 4, and an oxide semiconductor layer 9. FIG. 2 is a longitudinal sectional view showing a state in which an amorphous perfluoro resin layer 52 is formed on the upper surface of a non-fluorine organic resin layer 51. FIG. 6 is a longitudinal sectional view of an oxide thin film transistor 1a of Comparative Example 1. FIG. 6 is a longitudinal sectional view of an oxide thin film transistor 1b of Comparative Example 2. FIG. 3 is a voltage-current characteristic of the oxide thin film transistor 1. This is a voltage-current characteristic of the oxide thin film transistor 1a. This is a voltage-current characteristic of the oxide thin film transistor 1b. It is a longitudinal cross-sectional view of the oxide thin-film transistor 12 of 2nd embodiment. It is a flowchart which shows the manufacturing process of the oxide thin-film transistor 12 of 2nd embodiment. It is a longitudinal cross-sectional view of the oxide thin film transistor 100 of 3rd embodiment. 3 is a flowchart showing manufacturing steps of the oxide thin film transistor 100. 2 is a longitudinal sectional view of a state where a gate electrode 106 is formed on the upper surface of a substrate 102. FIG. It is a longitudinal cross-sectional view of a state in which the gate insulating layer 110 according to the third embodiment is formed on the upper surfaces of the substrate 102 and the gate electrode 106. It is a longitudinal cross-sectional view in the state in which the source electrode 103 and the drain electrode 104 were formed on the upper surface of the gate insulating layer 110 in 3rd embodiment. FIG. 10 is a longitudinal sectional view of a state in which an oxide semiconductor layer 109 is formed between a source electrode 103 and a drain electrode 104. It is a longitudinal cross-sectional view in the state in which the non-fluorine type organic resin layer 151 was formed on the upper surface of the source electrode 103, the drain electrode 104, the oxide semiconductor layer 109, and the gate insulating layer 110 in 3rd embodiment. FIG. 6 is a longitudinal sectional view showing a state in which an amorphous perfluoro resin layer 152 is formed on the upper surface of a non-fluorine organic resin layer 151. It is a longitudinal cross-sectional view of a state in which a contact hole 111 penetrating the non-fluorine organic resin layer 151 and the amorphous perfluororesin layer 152 is formed.

Hereinafter, the oxide thin film transistor 1 according to the first embodiment of the present disclosure will be described. First, a cross-sectional structure of the oxide thin film transistor 1 will be described with reference to FIG.

The oxide thin film transistor 1 of the first embodiment is a so-called “top gate type” oxide thin film transistor in which the gate electrode 6 is located above the source electrode 3 and the drain electrode 4. The oxide thin film transistor 1 of this embodiment is characterized in that, in addition to being a top gate type, the gate insulating layer 5 is formed of two layers of a non-fluorine organic resin layer 51 and an amorphous perfluoro resin layer 52. Have. In the following description, the lower side of FIG. 1 (substrate 2 side) is described as the lower side of the oxide thin film transistor 1, and the upper side of FIG.

The oxide thin film transistor 1 has a plate-like substrate 2, and a source electrode 3 and a drain electrode 4 are provided on the upper surface of the substrate 2 so as to be separated from each other. An oxide semiconductor layer 9 is continuously provided on the upper surface of the source electrode 3 and the drain electrode 4 and the upper surface of the substrate 2 sandwiched between the source electrode 3 and the drain electrode 4. A gate insulating layer 5 is provided so as to cover the oxide semiconductor layer 9, the source electrode 3, the drain electrode 4, and the substrate 2. The gate insulating layer 5 includes a lower non-fluorine organic resin layer 51 covering at least the oxide semiconductor layer 9 and an upper amorphous perfluoro resin layer 52 covering the upper surface of the non-fluorine organic resin layer 51. Yes. A gate electrode 6 is provided on the upper surface of the amorphous perfluororesin layer 52 at a position facing the oxide semiconductor layer 9.

The substrate 2 is a plate-like member having a flat surface. Various materials are applicable as the material of the substrate 2, but when a conductive material is employed, an insulating film needs to be provided on the surface of the substrate 2. When an insulating material is used as the material of the substrate 2, a plastic substrate is used in addition to a glass substrate and a silicon substrate with a thermal oxide film. When it is desired to impart flexibility to the substrate 2, plastic is particularly used as the material of the substrate 2. Examples of plastic materials include polyethersulfone (PES), polyethylene terephthalate (PET), polyimide (PI), polyethylene naphthalate (PEN), polyetherimide (PEI), polystyrene (PS), and polyvinyl chloride (PVC). ), Polyethylene (PE), polypropylene (PP) and the like. In order to improve the water resistance of the substrate 2, a glass barrier film made of SiO ₂ or SiNx is formed on the surface of the substrate 2. In the present embodiment, a glass substrate is used as the substrate 2.

On the upper surface of the substrate 2, a source electrode 3 and a drain electrode 4 are provided with a separation width of a predetermined channel length. The material of the source electrode 3 and the drain electrode 4 is a single metal such as Au, Ag, Ni, Cu, Pd, Al, Mo, Cr, Ti, Ta, Pt, W (tungsten), or at least one of the metals. A composite containing a conductive oxide such as indium tin oxide (ITO) or a conductive polymer such as polyethylenedioxythiophene (PEDOT) is applicable. The source electrode 3 and the drain electrode 4 of this embodiment are made of Ni.

An oxide semiconductor layer 9 is continuously provided on each upper surface of the source electrode 3 and the drain electrode 4 and an upper surface of the substrate 2 sandwiched between the source electrode 3 and the drain electrode 4. A known oxide semiconductor material can be used as the material of the oxide semiconductor layer 9. Preferably, an oxide semiconductor material containing at least one element of In, Ga, and Zn is employed. Specific examples of the oxide semiconductor material containing at least one element of In, Ga, and Zn include InGaZnO ₄ , ZnO, ZnInO, and In ₂ O ₃ . The oxide semiconductor layer 9 of this embodiment is made of InGaZnO ₄ .

Each upper surface of the oxide semiconductor layer 9, the source electrode 3, the drain electrode 4, and the substrate 2 is covered with a gate insulating layer 5. The gate insulating layer 5 includes a lower non-fluorine organic resin layer 51 covering at least the oxide semiconductor layer 9 and an upper amorphous perfluoro resin layer 52 covering the upper surface of the non-fluorine organic resin layer 51. Yes.

The material of the non-fluorine organic resin layer 51 may be any non-fluorine organic polymer having insulating properties. Specifically, polyimide (PI), polyamide (PA), polyester (PE), polyvinylphenol (PVP), polyvinyl alcohol (PVA), polyvinyl acetate (PVAC), polymethyl methacrylate (PMMA), polyurethane (PUR) Polysulfone (PSF), cyanoethyl pullulan, epoxy resin, phenol resin, benzocyclobutene resin, acrylic resin, polymer alloy of the above resin, or copolymer resin can be used. The non-fluorinated organic resin layer 51 of the present embodiment is formed by cross-linked PVP in which polyvinyl phenol (PVP) is cross-linked by melanin resin.

The upper surface of the non-fluorine organic resin layer 51 is covered with an amorphous perfluoro resin layer 52. The amorphous perfluoro resin layer 52 is made of an amorphous perfluoro resin, and specifically, for example, Cytop (registered trademark) manufactured by Asahi Glass Co., Ltd. is used.

Here, the amorphous perfluoro resin will be described. Perfluororesin is a fluororesin composed of a carbon skeleton, fluorine, and a small amount of oxygen. Its structure is amorphous. Amorphous perfluororesin has properties as a fluororesin such as fire resistance, chemical resistance, and water repellency, and is very transparent due to its amorphous structure (visible light transmittance of 95% or more). The amorphous perfluoro resin can be handled as a liquid material by dissolving it in a predetermined fluorine-based solvent. Therefore, an amorphous perfluoro resin thin film can be formed by a coating method.

On the upper surface of the amorphous perfluoro resin layer 52, a gate electrode 6 is provided at a position facing the oxide semiconductor layer 9. The material of the gate electrode 6 includes a single metal such as Au, Ag, Cu, Pd, Ni, Al, Mo, Cr, Ti, Ta, Pt, W (tungsten), or a composite containing at least one metal, A conductive oxide such as indium tin oxide (ITO) or a conductive polymer such as polyethylenedioxythiophene (PEDOT) is applicable. The gate electrode 6 of this embodiment is made of Ni.

Next, a manufacturing process of the oxide thin film transistor 1 having the above structure will be described with reference to FIGS.

As shown in FIG. 2, the manufacturing process of the oxide thin film transistor 1 includes a source / drain electrode formation step (S1) in which the source electrode 3 and the drain electrode 4 are formed on the upper surface of the substrate 2, and the source electrode 3 and the drain electrode, respectively. The semiconductor layer forming step (S2) in which the oxide semiconductor layer 9 is formed on the upper surface of the substrate 2 between 4, and the gate insulating layer forming step (S3) in which the gate insulating layer 5 is formed at least on the upper surface of the oxide semiconductor layer 9 ) And a gate electrode forming step (S4) in which the gate electrode 6 is formed on the upper surface of the gate insulating layer 5. The gate insulating layer forming step (S3) includes a non-fluorinated organic resin layer forming step (S31) in which the non-fluorinated organic resin layer 51 is formed so as to cover at least the upper surface of the oxide semiconductor layer 9, and a non-fluorinated organic resin. This includes an amorphous perfluoro resin layer forming step (S32) in which the amorphous perfluoro resin layer 52 is formed so as to cover the upper surface of the resin layer 51.

First, the source / drain electrode forming step of S1 is performed. In this source / drain electrode formation step (S1), the source electrode 3 and the drain electrode 4 are formed on the upper surface of the substrate 2 as shown in FIG. The method for forming the source electrode 3 and the drain electrode 4 is not particularly limited. In general, a thin film made of a material for forming electrodes is formed on the upper surface of the substrate 2 and then unnecessary portions are removed by patterning. Here, various methods can be applied to the film forming method and the patterning method. Specifically, as a film forming method, a sputtering method, a vacuum evaporation method, a CVD method, a plating method, or the like can be applied. As the patterning method, a photolithography method, a screen printing method, or the like can be applied.

In this embodiment, after cleaning the substrate 2 made of glass, a Ni thin film was formed on the upper surface of the substrate 2. And the formed Ni thin film was patterned and the unnecessary part was removed, and the source electrode 3 and the drain electrode 4 were formed. The Ni thin film was formed by a sputtering method. At this time, Ni was used as the target, and a DC sputtering apparatus was used as the apparatus. A resist pattern was formed on the upper surface of the formed Ni thin film using a photolithography method, and then the Ni thin film was etched using an etching method. The unnecessary photoresist was removed by washing with acetone. Thus, as shown in FIG. 3, the source electrode 3 and the drain electrode 4 made of Ni were formed on the upper surface of the substrate 2. The formed source electrode 3 and drain electrode 4 had a thickness of 150 nm.

Next, the semiconductor layer forming step of S2 is performed. In the semiconductor layer forming step (S2), as shown in FIG. 4, the oxide semiconductor layer 9 is continuous with the upper surface of the substrate 2 between the source electrode 3 and the drain electrode 4 and the upper surface of the source electrode 3 and the drain electrode 4. Formed. A method of forming the oxide semiconductor layer 9 is generally a method of removing unnecessary portions by patterning after forming a semiconductor thin film. A sputtering method is suitable as the film forming method, but is not limited thereto. As the patterning method, a photolithography method, a screen printing method, or the like can be used.

In the present embodiment, the InGaZnO ₄ film covers the upper surface of the source electrode 3, the upper surface of the drain electrode 4, and the upper surface of the substrate 2 shown in FIG. 3 so as to cover the portion where the source electrode 3 and drain electrode 4 are not provided. Is formed. Thereafter, the InGaZnO ₄ film is patterned to remove unnecessary portions, whereby the oxide semiconductor layer 9 made of InGaZnO ₄ is formed. The InGaZnO ₄ film is formed by a sputtering method. InGaZnO ₄ is used as a target, and a mixed gas of Ar and O ₂ is flowed. After forming the InGaZnO ₄ film, a resist pattern is formed by a photolithography method, and the InGaZnO ₄ film is etched by an etching method using an organic acid-based ITO etchant. The unnecessary photoresist is removed by washing with acetone. Thus, as illustrated in FIG. 4, the oxide semiconductor layer 9 made of InGaZnO ₄ is continuously formed on the upper surface of the substrate 2 between the source electrode 3 and the drain electrode 4, the upper surface of the source electrode 3, and the upper surface of the drain electrode 4. Can be made. The thickness of the formed oxide semiconductor layer 9 was 30 nm.

Next, the gate insulating layer forming step of S3 is performed. In the gate insulating layer forming step (S3), as shown in FIG. 2, the non-fluorine organic resin layer 51 is formed so as to cover the upper surface of the source electrode 3, the drain electrode 4, the oxide semiconductor layer 9, and the substrate 2. The non-fluorinated organic resin layer forming step (S31) and the amorphous perfluororesin layer forming step (S32) in which the amorphous perfluororesin layer 52 is formed on the upper surface of the non-fluorinated organic resin layer 51.

In the non-fluorine-based organic resin layer forming step (S31), as shown in FIG. 5, the source electrode 3 and the drain among the upper surfaces of the source electrode 3, the drain electrode 4, and the oxide semiconductor layer 9 and the upper surface of the substrate 2 are formed. A non-fluorine organic resin layer 51 is formed so as to cover a portion where the electrode 4 and the oxide semiconductor layer 9 are not provided. The method for forming the non-fluorine organic resin layer 51 is not particularly limited, but it is preferable to use a coating method from the viewpoint of cost. Various methods can be applied as the coating method. Specifically, any of spin coating, slit coating, dip coating, spraying, roll coating, curtain coating, printing, droplet discharge, and the like can be used.

In the present embodiment, a non-fluorine organic resin layer forming solution containing polyvinylphenol is formed by spin coating on the upper surfaces of the oxide semiconductor layer 9, the source electrode 3, and the drain electrode 4 shown in FIG. Then, the oxide semiconductor layer 9, the source electrode 3, and the drain electrode 4 were coated so as to cover a portion where the oxide semiconductor layer 9, the source electrode 3, and the drain electrode 4 were not provided, and then heat treatment was performed. The non-fluorine organic resin layer forming solution is a mixed solution of PVP, melamine-formaldehyde, and propylene glycol monomethyl ether acetate. The weight ratio of each material is PVP: melamine-formaldehyde: propylene glycol monomethyl ether acetate = 1: 2: 10. The heat treatment was performed by using a hot plate, heating at 70 ° C. for 10 minutes, heating at 150 ° C. for 10 minutes, and finally heating at 200 ° C. for 30 minutes. The thickness of the non-fluorine organic resin layer 51 after the heat treatment was 700 nm.

In the amorphous perfluoro resin layer forming step (S32), the amorphous perfluoro resin layer 52 is formed so as to cover the non-fluorine organic resin layer 51 as shown in FIG. The formation of the amorphous perfluororesin layer 52 is performed using a coating method.

In this embodiment, the amorphous perfluororesin layer forming solution was applied by spin coating so as to cover the upper surface of the non-fluorine organic resin layer 51 shown in FIG. As a solution for forming an amorphous perfluoro resin layer, “Cytop (registered trademark) solution” manufactured by Asahi Glass Co., Ltd., prepared for the spin coating method was used. The heat treatment was performed using a hot plate. As an example, heating was performed at 70 ° C. for 10 minutes, followed by heating at 120 ° C. for 10 minutes, and finally heating at 200 ° C. for 10 minutes. The thickness of the amorphous perfluororesin layer 52 after the heat treatment was 100 nm.

Next, the gate electrode forming step of S4 is performed. In the gate electrode formation step (S4), the gate electrode 6 is formed on the upper surface of the amorphous perfluororesin layer 52 as shown in FIG. The method for forming the gate electrode 6 is not particularly limited. In general, after forming a thin film of a material for forming the gate electrode 6, patterning is performed to remove unnecessary portions. However, various methods can be applied to the film forming method and the patterning method. Specifically, as a film forming method, a sputtering method, a vacuum evaporation method, a CVD method, a plating method, or the like can be applied. As the patterning method, a photolithography method, a screen printing method, or the like can be applied.

In this embodiment, after forming the Ni thin film, the Ni thin film is patterned to remove unnecessary portions, thereby forming the gate electrode 6 made of Ni. The Ni thin film was formed by a vacuum deposition method. After the Ni thin film was formed, a resist pattern was formed by photolithography, and the Ni thin film was etched by etching. The unnecessary photoresist was removed by washing with acetone. Thus, as shown in FIG. 1, the gate electrode 6 made of Ni was formed on the upper surface of the amorphous perfluoro resin layer 52. The formed gate electrode 6 had a thickness of 200 nm.

Next, in order to confirm the effect of the oxide thin film transistor 1 formed by the above-described manufacturing method, the performance of the oxide thin film transistor 1 was evaluated. In this performance evaluation, as Comparative Example 1, the oxide thin film transistor 1a in which the gate insulating layer 5 is composed of only one non-fluorine organic resin layer 51, and as Comparative Example 2, the gate insulating layer 5 is an amorphous perfluoro resin layer. The performance evaluation was also performed on the oxide thin film transistor 1b composed of only one layer. Hereinafter, this performance evaluation will be described.

First, cross-sectional structures of the oxide thin film transistor 1a of the comparative example 1 and the oxide thin film transistor 1b of the comparative example 2 will be described with reference to FIGS.

The configuration of the oxide thin film transistor 1a of Comparative Example 1 shown in FIG. 7 is the same as that of the oxide thin film transistor 1 except that the gate insulating layer 5 is composed of only one non-fluorine organic resin layer 51 having a thickness of 800 nm. . The oxide thin film transistor 1a is obtained by omitting only the amorphous perfluororesin layer forming step (S32) in the manufacturing process of the oxide thin film transistor 1 of the first embodiment.

Further, the oxide thin film transistor 1b of Comparative Example 2 shown in FIG. 8 is the oxide thin film transistor 1 of the first embodiment except that the gate insulating layer 5 is composed of only one layer of an amorphous perfluoro resin layer 52 having a thickness of 800 nm. It is the same. Moreover, the oxide thin film transistor 1b is obtained by omitting only the non-fluorine-based organic resin layer forming step (S31) in the manufacturing process of the oxide thin film transistor 1 of the first embodiment.

Next, a performance evaluation method and performance evaluation results will be described with reference to FIGS. 9 to 11, the curve a shows the voltage-current characteristics of the oxide

thin film transistors

1, 1a, 1b before the heat treatment, and the curve b shows the voltage-current of the oxide

thin film transistors

1, 1a, 1b after the heat treatment. Show the characteristics.

The performance evaluation was performed using the field effect mobility of the oxide thin film transistor and the turn-on voltage obtained from the voltage-current characteristics shown in FIGS. 9 to 11 as indices. The field effect mobility is calculated using the following formula.
I _ds = μC _in W (V _g −V _th ) ² / 2L
Where μ is the field effect mobility, I _ds is the current flowing between the source and drain in the saturation region (hereinafter referred to as drain current), C _in is the capacitance per unit area of the gate insulating film, W is the channel width, and V _g is The gate voltage, _Vth is the threshold voltage, and L is the channel length. The turn-on voltage is a gate voltage that becomes a boundary when the oxide thin film transistor is turned on from the off state. When a predetermined voltage is applied between the source electrode 3 and the drain electrode 4 to change the gate voltage, the current flowing between the source electrode 3 and the drain electrode 4 is measured, and the field effect mobility is calculated from the obtained value. And turn-on voltage were calculated.

Further, the performance evaluation was performed on the oxide

thin film transistors

1, 1a, and 1b after the formation and the oxide

thin film transistors

1, 1a, and 1b on which the heat treatment was further performed after the formation. The heat treatment was performed by heating the formed oxide

thin film transistors

1, 1a, and 1b at 200 ° C. for 5 minutes using a hot plate. In an oxide thin film transistor including an oxide semiconductor layer, characteristics may be unstable when moisture is taken into the oxide semiconductor layer. Therefore, in order to stabilize transistor characteristics, heat treatment is generally performed after formation to remove moisture in the oxide semiconductor layer.

First, the field effect mobility before and after the heat treatment in the oxide thin film transistor 1 and the turn-on voltage were evaluated. Based on the voltage-current characteristics of the oxide thin film transistor 1 shown in FIG. 9, the field-effect mobility and the turn-on voltage were determined to be 7.2 cm ² / Vs and the turn-on voltage was −10 V before the heat treatment. (Curve a). Further, after the heat treatment, the field effect mobility was 7.6 cm ² / Vs, and the turn-on voltage was −10 V (curve b). Thereby, in the oxide thin-film transistor 1 of 1st embodiment, it turned out that field effect mobility improves a little by heat processing. It was also found that the turn-on voltage hardly changed before and after the heat treatment. Thus, it was shown that the oxide thin film transistor 1 having high field effect mobility and having stable characteristics without fluctuation of turn-on voltage due to heat treatment can be obtained.

The oxide thin film transistor 1 was subjected to the same experiment a plurality of times, and the field effect mobility and the turn-on voltage were obtained. As a result, a reproducible result was obtained. Thereby, it was confirmed that the oxide thin film transistor 1 has stable transistor characteristics.

Next, the field effect mobility and the turn-on voltage before and after the heat treatment in the oxide thin film transistor 1a were evaluated. Based on the voltage-current characteristics of the oxide thin film transistor 1a shown in FIG. 10, the field-effect mobility and the turn-on voltage are determined. The field-effect mobility is 4.9 cm ² / Vs and the turn-on voltage is −7.5 V before the heat treatment. (Curve a). Further, after the heat treatment, the field effect mobility was 5.2 cm ² / Vs, and the turn-on voltage was −50 V or less (curve b). Thereby, in the oxide thin film transistor 1a of the comparative example 1, it was shown that the turn-on voltage is significantly shifted negatively by the heat treatment. In order to reduce the drive voltage of the transistor, it is necessary to reduce the absolute value of the turn-on voltage. However, in the oxide thin film transistor 1a, it has been shown that the absolute value of the turn-on voltage may increase due to heat treatment.

It should be noted that the same experiment was performed a plurality of times for the oxide thin film transistor 1a, and the field effect mobility and the turn-on voltage were determined. As a result, reproducibility was not obtained before and after the heat treatment. Thereby, it was confirmed that the transistor characteristics of the oxide thin film transistor 1a were not stable.

Next, the field effect mobility and the turn-on voltage before and after the heat treatment in the oxide thin film transistor 1b were evaluated. Based on the voltage-current characteristics of the oxide thin film transistor 1b shown in FIG. 11, the field-effect mobility and the turn-on voltage were determined to be 0.32 cm ² / Vs and the turn-on voltage was −20 V before the heat treatment. (Curve a). Further, after the heat treatment, the field effect mobility was 0.31 cm ² / Vs, and the turn-on voltage was −20 V (curve b). Thereby, in the oxide thin-film transistor 1b of the comparative example 2, it was shown that the field effect mobility is low and the absolute value of the turn-on voltage is large compared with the oxide thin-film transistor 1 of the first embodiment. It is known that the turn-on voltage of a thin film transistor approximates the inverse proportion of the capacitance of the gate insulating layer. The capacitance of the gate insulating layer is proportional to the relative dielectric constant of the material forming the gate insulating layer. In the oxide thin film transistor 1b of Comparative Example 2, the gate insulating layer 5 is formed only from the amorphous perfluoro resin layer 52 having a low dielectric constant. For this reason, it is presumed that the absolute value of the turn-on voltage has increased.

On the other hand, in the oxide thin film transistor 1 of the first embodiment, the gate insulating layer 5 includes a non-fluorine-based organic resin layer 51 made of a crosslinked PVP having a higher dielectric constant than the amorphous perfluoro resin, an amorphous perfluoro resin layer 52, and This is a laminated structure. For this reason, it is presumed that the absolute value of the turn-on voltage could be reduced.

As described above, in the oxide thin film transistor 1 according to the first embodiment, the gate insulating layer 5 stacked on the upper surface of the oxide semiconductor layer 9 includes the non-fluorine organic resin layer 51 covering the oxide semiconductor layer 9 and the non-fluorine. And an amorphous perfluoro resin layer 52 covering the organic resin layer 51. By using the amorphous perfluoro resin layer 52 as a constituent element of the gate insulating layer 5, good and stable characteristics are obtained. In addition, even when heat treatment is performed, the oxide thin film transistor 1 with almost no change in characteristics can be obtained.

The gate insulating layer 5 includes a water-repellent amorphous perfluoro resin layer 52. Therefore, in the cleaning process during patterning performed when the gate electrode 6 is formed on the upper surface of the gate insulating layer 5, the cleaning water passes through the gate insulating layer 5 and the oxide semiconductor layer on the lower surface of the gate insulating layer 5. Never reach 9. It is known that the characteristics of the oxide thin film transistor 1 become unstable when moisture is adsorbed on the oxide semiconductor layer 9. In the oxide thin film transistor 1, the cleaning water can be prevented from reaching the oxide semiconductor layer 9, and the characteristics of the oxide thin film transistor 1 can be stabilized.

Further, since polyvinylphenol (PVP) having a high dielectric constant is adopted as the material of the non-fluorine organic resin layer 51, the dielectric constant of the gate insulating layer 5 is improved and the absolute value of the turn-on voltage of the oxide thin film transistor 1 is reduced. be able to. Therefore, the oxide thin film transistor 1 having a low driving voltage can be obtained.

Further, both the non-fluorine organic resin layer 51 and the amorphous perfluoro resin layer 52 can be formed at a low temperature by a coating method. Therefore, the gate insulating layer 5 can be formed easily and inexpensively without using a large-scale apparatus. In addition, the gate insulating layer 5 can be formed without damaging the oxide semiconductor layer 9 formed on the lower surface side. Furthermore, a flexible plastic substrate with low heat resistance can be used as the substrate, and in that case, an oxide thin film transistor having flexibility can be manufactured.

Further, only the non-fluorine organic resin layer 51 is in contact with the upper surface of the oxide semiconductor layer 9, and the material of the non-fluorine organic resin layer 51 is polyvinyl phenol (PVP) having low reactivity with respect to the oxide semiconductor. It was adopted. Therefore, the oxide semiconductor layer 9 is not damaged in the process of forming the gate insulating layer 5. Therefore, the semiconductor characteristics of the oxide semiconductor layer 9 can be maintained, and the oxide thin film transistor 1 having favorable characteristics can be formed.

In addition, after the source electrode 3 and the drain electrode 4 are formed, the oxide semiconductor layer 9 is formed. Therefore, the oxide semiconductor layer 9 is not damaged when the source electrode 3 and the drain electrode 4 are formed.

In addition, since InGaZnO ₄ is employed as the material of the oxide semiconductor layer 9, film formation in the semiconductor layer formation step (S2) can be performed at room temperature. Therefore, a flexible plastic substrate can be used as the substrate. In that case, a flexible oxide thin film transistor can be manufactured. In addition, an oxide thin film transistor having high field effect mobility can be realized.

Next, the oxide thin film transistor 12 of the second embodiment will be described with reference to FIG. 12 and FIG. In the oxide thin film transistor 12 of the second embodiment, the non-fluorine organic resin layer 51 is formed above the amorphous perfluororesin layer 52 in the gate insulating layer 50. Other configurations are the same as those of the oxide thin film transistor 1 of the first embodiment. Therefore, only the stacking order of the non-fluorinated organic resin layer 51 and the amorphous perfluororesin layer 52 in the gate insulating layer 50 will be described mainly. Other configurations are denoted by the same reference numerals, and detailed description thereof is omitted.

First, the cross-sectional structure of the oxide thin film transistor 12 of the second embodiment will be described. In the oxide thin film transistor 12, as shown in FIG. 12, the source electrode 3 and the drain electrode 4 are provided apart from each other on the upper surface of the substrate 2. An oxide semiconductor layer 9 is continuously provided on the upper surface of the source electrode 3 and the drain electrode 4 and the upper surface of the substrate 2 sandwiched between the source electrode 3 and the drain electrode 4. A gate insulating layer 50 is provided so as to cover the oxide semiconductor layer 9, the source electrode 3, the drain electrode 4, and the upper surface of the substrate 2. The gate insulating layer 50 includes a lower amorphous perfluoro resin layer 52 covering at least the oxide semiconductor layer 9 and an upper non-fluorine organic resin layer 51 covering the amorphous perfluoro resin layer 52. A gate electrode 6 is provided on the top surface of the non-fluorine organic resin layer 51 at a position facing the oxide semiconductor layer 9. The material of each component of the oxide thin film transistor 12 is the same as that of the oxide thin film transistor 1 of the first embodiment.

Next, the manufacturing process of the oxide thin film transistor 12 of the second embodiment will be described. As shown in FIG. 13, the manufacturing process of the oxide thin film transistor 12 of the second embodiment includes a source / drain electrode forming step (S1) in which the source electrode 3 and the drain electrode 4 are formed on the upper surface of the substrate 2, respectively, A semiconductor layer forming step (S2) in which the oxide semiconductor layer 9 is formed on the upper surface of the substrate 2 between the electrode 3 and the drain electrode 4, and gate insulation in which the gate insulating layer 5 is formed on at least the upper surface of the oxide semiconductor layer 9 The layer forming step (S30) and the gate electrode forming step (S4) in which the gate electrode 6 is formed on the upper surface of the gate insulating layer 5 are configured. Since the source / drain electrode forming step (S1), the semiconductor layer forming step (S2), and the gate electrode forming step (S4) are the same as those in the first embodiment, description thereof is omitted. Only the gate insulating layer forming step (S30) will be described.

The gate insulating layer forming step (S30) in the second embodiment includes an amorphous perfluoro resin layer forming step (S301) in which an amorphous perfluoro resin layer 52 is formed so as to cover at least the upper surface of the oxide semiconductor layer 9, and an amorphous state. This includes a non-fluorinated organic resin layer forming step (S302) in which the non-fluorinated organic resin layer 51 is formed so as to cover the upper surface of the perfluororesin layer 52.

The amorphous perfluoro resin layer forming step (S301) will be described. In the amorphous perfluoro resin layer forming step (S301), first, an amorphous perfluoro resin layer forming solution is applied to the upper surfaces of the oxide semiconductor layer 9, the source electrode 3, the drain electrode 4 and the substrate 2 by spin coating. After coating so as to cover a portion of the upper surface where the oxide semiconductor layer 9, the source electrode 3, and the drain electrode 4 are not provided, heat treatment was performed. As the amorphous perfluoro resin layer forming solution, “Cytop (registered trademark) solution” manufactured by Asahi Glass Co., Ltd., prepared for the spin coating method was used. The heat treatment was performed using a hot plate, heated at 70 ° C. for 10 minutes, then heated at 120 ° C. for 10 minutes, and finally heated at 200 ° C. for 10 minutes. After the heat treatment, the upper surface of the amorphous perfluororesin layer 52 was hydrophilized by plasma treatment with oxygen, argon, nitrogen or the like. In the amorphous perfluoro resin layer forming step (S301) of the second embodiment, after the heat treatment, the amorphous perfluoro resin layer forming step (S32) in the first embodiment is performed in that plasma treatment is performed to make the upper surface hydrophilic. Is different.

Next, the non-fluorine organic resin layer forming step (S302) will be described. In the non-fluorine-based organic resin layer forming step (S302), a non-fluorine-based organic resin layer-forming solution containing polyvinylphenol was applied to the upper surface of the amorphous perfluororesin layer by spin coating, and then heat-treated. . The non-fluorine organic resin layer forming solution is a mixed solution of PVP, melamine-formaldehyde, and propylene glycol monomethyl ether acetate. The weight ratio of each material is PVP: melamine-formaldehyde: propylene glycol monomethyl ether acetate = 1: 2: 10. The heat treatment was performed by using a hot plate, heating at 70 ° C. for 10 minutes, heating at 150 ° C. for 10 minutes, and finally heating at 200 ° C. for 30 minutes.

Also in the oxide thin film transistor 12 of the second embodiment, the same effect as the oxide thin film transistor 1 of the first embodiment can be obtained. Further, in the oxide thin film transistor 12 of the second embodiment, the amorphous perfluoro resin layer 52 is covered with the non-fluorine organic resin layer 51 and is not exposed to the outside. Since the cross-linked PVP forming the non-fluorine organic resin layer 51 has higher hardness than the amorphous perfluoro resin, the physical resistance of the gate insulating layer 50 can be improved. Thereby, deterioration of the characteristics of the oxide thin film transistor 12 due to damage to the gate insulating layer 50 can be suppressed. In particular, damage to the gate insulating layer 50 in the gate electrode formation step (S4) performed after forming the gate insulating layer 50 can be reduced, and the oxide thin film transistor 12 having favorable characteristics can be obtained.

Next, the oxide thin film transistor 100 of the third embodiment will be described with reference to FIG. Unlike the first and second embodiments, the oxide thin film transistor 100 of the third embodiment is a so-called “bottom gate type” oxidation in which the gate electrode 106 is located below the source electrode 103 and the drain electrode 104. Thin film transistor. The oxide thin film transistor 100 according to the third embodiment is characterized in that, in addition to being a bottom gate type, the interlayer insulating layer 105 is formed of two layers of a non-fluorine organic resin layer 151 and an amorphous perfluoro resin layer 152. Have. Further, the second embodiment is different from the first embodiment in that a contact hole 111 penetrating the interlayer insulating layer 105 is provided and a pixel electrode 112 is provided. Note that description of the same parts as those in the first embodiment is omitted.

First, a cross-sectional structure of the oxide thin film transistor 100 will be described. The oxide thin film transistor 100 includes a plate-like substrate 102, and a gate electrode 106 is provided over the substrate 102. The gate insulating layer 110 in the third embodiment is provided so as to cover the substrate 102 and the gate electrode 106. A source electrode 103 and a drain electrode 104 are provided apart from each other on the upper surface of the gate insulating layer 110 in the third embodiment. In addition, the oxide semiconductor layer 109 is continuously provided on the upper surface of the gate insulating layer 110, the upper surface of the source electrode 103, and the upper surface of the drain electrode 104 in the third embodiment between the source electrode 103 and the drain electrode 104. ing.

The upper surface of the oxide semiconductor layer 109, the upper surfaces of the source electrode 103 and the drain electrode 104, and the upper surface of the gate insulating layer 110 in the third embodiment are covered with an interlayer insulating layer 105. The interlayer insulating layer 105 includes a lower non-fluorine organic resin layer 151 and an upper amorphous perfluoro resin layer 152. A pixel electrode 112 is provided on the upper surface of the interlayer insulating layer 105. A contact hole 111 that penetrates the interlayer insulating layer 105 is provided between the pixel electrode 112 and the drain electrode 104.

The material of the substrate 102 is the same as the material of the substrate 2 of the first embodiment. The material of the gate electrode 106 formed on the upper surface of the substrate 102 is the same as the material of the gate electrode 6 of the first embodiment.

The gate insulating layer 110 in the third embodiment provided so as to cover the upper surface of the substrate 102 and the upper surface of the gate electrode 106 is composed of a single layer and is formed of an insulating material. In the case where an inorganic insulating material is employed as the insulating material, Al ₂ O ₃ , SiO ₂ , SiN, TiO ₂ or the like can be applied. When an organic insulating material is employed as the insulating material, PI (polyimide), PMMA (polymethyl methacrylate), PVP (polyparavinylphenol), or the like can be applied. In addition, as a material of the gate insulating layer 110 in 3rd embodiment, it is more preferable to employ | adopt an inorganic insulating material from a viewpoint of insulation performance and tolerance.

The materials of the source electrode 103 and the drain electrode 104 provided on the upper surface of the gate insulating layer 110 in the third embodiment are the same as the materials of the source electrode 3 and the drain electrode 4 in the first embodiment. The material of the oxide semiconductor layer 109 provided on the upper surface of the gate insulating layer 110, the upper surface of the source electrode 103, and the upper surface of the drain electrode 104 in the third embodiment between the source electrode 103 and the drain electrode 104 is the first embodiment. The form is the same as the material of the oxide semiconductor layer 9 of the second embodiment.

The interlayer insulating layer 105 provided on the upper surface of the substrate 102, the source electrode 103, the drain electrode 104, and the oxide semiconductor layer 109 has the same configuration as the gate insulating layer 5 in the first embodiment. The interlayer insulating layer 105 includes a lower non-fluorine organic resin layer 151 and an upper amorphous perfluoro resin layer 152. The materials of the non-fluorine organic resin layer 151 and the amorphous perfluoro resin layer 152 forming the interlayer insulating layer 105 in the third embodiment are the non-fluorine organic materials forming the gate insulating layer 5 in the first embodiment. This is the same as the resin layer 51 and the amorphous perfluoro resin layer 52.

The pixel electrode 112 formed on the upper surface of the interlayer insulating layer 105 is formed of ITO (indium tin oxide).

Next, a method for manufacturing the oxide thin film transistor 100 according to the third embodiment will be described with reference to FIGS.

As shown in FIG. 15, the manufacturing process of the oxide thin film transistor 100 of the third embodiment includes a gate electrode formation step (S101), a gate insulating layer formation step (S102), a source / drain electrode formation step (S103), The semiconductor layer forming step (S104), the interlayer insulating layer forming step (S105), the contact hole forming step (S106), and the pixel electrode forming step (S107) are provided. The interlayer insulating layer forming step (S105) includes a non-fluorinated organic resin layer forming step (S151) and an amorphous perfluoro resin layer forming step (S152). Hereinafter, each step will be specifically described.

First, a gate electrode formation step (S101) is performed. In the gate electrode formation step (S101), the gate electrode 106 is formed on the upper surface of the substrate 102. Specifically, first, the substrate 102 is cleaned, and a Ni thin film is formed on the upper surface of the substrate 102. The Ni thin film is formed by a sputtering method. At this time, Ni is used as the target, and a DC sputtering apparatus is used as the apparatus. A resist pattern is formed on the upper surface of the formed Ni thin film by a photolithography method, and the Ni thin film is etched by an etching method. Finally, the unnecessary photoresist is removed by acetone cleaning. Thus, as shown in FIG. 16, the gate electrode 106 made of Ni can be formed on the upper surface of the substrate 102.

Next, a gate insulating layer forming step is performed (S102). In the gate insulating layer forming step (S102), an SiO ₂ film is formed on the upper surface of the gate electrode 106 and the upper surface of the substrate 102 shown in FIG. The SiO ₂ film is formed by a sputtering method, and SiO ₂ is used as a target while flowing a mixed gas of Ar and O ₂ . Thus, as shown in FIG. 17, the gate insulating layer 110 of the third embodiment made of SiO ₂ is formed on the upper surface of the gate electrode 106 and the portion of the upper surface of the substrate 102 where the gate electrode 106 is not provided. The

Next, a source / drain electrode formation step (S103) is performed. In the source / drain electrode formation step (S103), an Ni thin film is formed on the upper surface of the gate insulating layer 110 in the third embodiment shown in FIG. As shown, a source electrode 103 and a drain electrode 104 are formed. Since the formation conditions are the same as those of the gate electrode 106, description thereof is omitted.

Next, a semiconductor layer forming step (S104) is performed. In the semiconductor layer forming step (S104), as shown in FIG. 19, the upper surface of the gate insulating layer 110, the upper surface of the source electrode 103, and the upper surface of the drain electrode 104 between the source electrode 103 and the drain electrode 104 in the third embodiment. In addition, the oxide semiconductor layer 109 is continuously formed. In the semiconductor layer forming step (S104), first, the source electrode 103 and the drain electrode among the upper surface of the source electrode 103, the upper surface of the drain electrode 104, and the upper surface of the gate insulating layer 110 in the third embodiment shown in FIG. An InGaZnO ₄ film is formed so as to cover a portion where 104 is not provided. After that, the InGaZnO ₄ film is patterned to remove unnecessary portions, whereby the oxide semiconductor layer 109 made of InGaZnO ₄ is formed. The InGaZnO ₄ film is formed by a sputtering method, and InGaZnO ₄ is used as a target and a mixed gas of Ar and O ₂ is supplied. After the InGaZnO ₄ film is formed, a resist pattern is formed using a photolithography method, and the InGaZnO ₄ film is etched. Finally, the unnecessary photoresist is removed by acetone cleaning. Thus, as shown in FIG. 19, an oxide made of InGaZnO _{4 is} formed on the upper surface of the gate insulating layer 110, the upper surface of the source electrode 103, and the upper surface of the drain electrode 104 in the third embodiment between the source electrode 103 and the drain electrode 104. The semiconductor layer 109 can be formed continuously.

Next, an interlayer insulating layer forming step (S105) is performed. As shown in FIG. 15, the interlayer insulating layer forming step (S105) includes a non-fluorine organic resin layer forming step (S151) for forming the lower non-fluorine organic resin layer 151, and an upper amorphous perfluoro resin layer. And an amorphous perfluoro resin layer forming step (S152) for forming 152.

In the non-fluorine organic resin layer forming step (S151), as shown in FIG. 20, the upper surfaces of the oxide semiconductor layer 109, the source electrode 103, and the drain electrode 104, and the upper surface of the gate insulating layer 110 in the third embodiment. Among these, the non-fluorine organic resin layer 151 is formed so as to cover a portion where the oxide semiconductor layer 109, the source electrode 103, and the drain electrode 104 are not provided. In the non-fluorine-based organic resin layer forming step (S151), the non-fluorine-based organic resin layer forming solution containing PVP is spin-coated with the oxide semiconductor layer 109, the source electrode 103, and the drain electrode 104 shown in FIG. Each of these upper surfaces and the upper surface of the gate insulating layer 110 in the third embodiment are applied to a portion where the oxide semiconductor layer 109, the source electrode 103, and the drain electrode 104 are not provided, and then heat treatment is performed. The non-fluorine organic resin layer forming solution is a mixed solution of PVP, melamine-formaldehyde, and propylene glycol monomethyl ether acetate. The weight ratio of each material is PVP: melamine-formaldehyde: propylene glycol monomethyl ether acetate = 1: 2: 10. The heat treatment is performed using a hot plate, and is performed by heating at 70 ° C. for 10 minutes, then heating at 150 ° C. for 10 minutes, and finally heating at 200 ° C. for 30 minutes.

In the amorphous perfluoro resin layer forming step (S152), as shown in FIG. 21, the amorphous perfluoro resin layer 152 is formed so as to cover the upper surface of the non-fluorine organic resin layer 151. In the amorphous perfluoro resin layer forming step (S152), after applying the amorphous perfluoro resin layer forming solution on the top surface of the substrate 2, the source electrode 3, the drain electrode 4, and the oxide semiconductor layer 9 by spin coating, Heat treatment was performed. As the amorphous perfluoro resin layer forming solution, “Cytop (registered trademark) solution” manufactured by Asahi Glass Co., Ltd., prepared for the spin coating method was used. The heat treatment was performed using a hot plate, heated at 70 ° C. for 10 minutes, then heated at 120 ° C. for 10 minutes, and finally heated at 200 ° C. for 10 minutes.

Next, a contact hole forming step (S106) is performed. In the contact hole forming step (S106), a contact hole 111 penetrating the non-fluorine organic resin layer 151 and the amorphous perfluororesin layer 152 is formed. In the contact hole forming step (S106), first, a resist mask having openings at locations corresponding to the contact holes 111 is formed on the upper surface of the amorphous perfluororesin layer 152 shown in FIG. Then, the amorphous perfluoro resin layer 152 and the non-fluorine organic resin layer 151 are etched by a dry etching method. Oxygen is used as the etching gas. In this way, the contact hole 111 can be formed as shown in FIG.

Next, a pixel electrode forming step is performed (S107). In the pixel electrode formation step (S107), an ITO thin film is formed on the upper surface of the amorphous perfluoro resin layer 152. Thereafter, unnecessary portions are removed by patterning to form pixel electrodes 112 made of ITO. The ITO film is formed by a sputtering method. After forming the ITO film, a resist pattern is formed and the ITO film is etched. Then, the unnecessary photoresist is removed by acetone cleaning. Thus, the pixel electrode 112 can be formed on the upper surface of the amorphous perfluororesin layer 152 as shown in FIG.

According to the manufacturing method of the oxide thin film transistor 100 of the third embodiment described in detail above, the interlayer insulating layer 105 laminated on the upper surface of the oxide semiconductor layer 109 is a non-fluorine organic resin layer covering the oxide semiconductor layer 109. 151 and an amorphous perfluororesin layer 152 covering the non-fluorine organic resin layer 151. By using the amorphous perfluoro resin layer 152 as a constituent element of the interlayer insulating layer 105, a change in characteristics of the oxide thin film transistor 100 when heat treatment is performed after the formation of the interlayer insulating layer 105 can be suppressed.

Further, the non-fluorine organic resin layer 151 and the amorphous perfluoro resin layer 152 are formed at a low temperature by a coating method. Therefore, the interlayer insulating layer 105 can be formed easily and inexpensively without using a large-scale apparatus. In addition, the interlayer insulating layer 105 can be formed without damaging the oxide semiconductor layer 109 formed on the lower surface side of the interlayer insulating layer 105. Furthermore, a flexible plastic substrate having low heat resistance can be employed as the substrate. In that case, a flexible oxide thin film transistor can be manufactured.

Further, only the non-fluorine organic resin layer 151 is in contact with the upper surface of the oxide semiconductor layer 109, and the material of the non-fluorine organic resin layer 151 is polyvinyl phenol (PVP) having low reactivity with respect to the oxide semiconductor. It was adopted. Therefore, the oxide semiconductor layer 109 is not damaged in the formation process of the interlayer insulating layer 105. Therefore, the semiconductor characteristics of the oxide semiconductor layer 109 can be maintained, and the oxide thin film transistor 100 having favorable characteristics can be formed.

Further, after the source electrode 103 and the drain electrode 104 are formed, the oxide semiconductor layer 109 is formed. Therefore, the oxide semiconductor layer 109 is not damaged when the source electrode 103 and the drain electrode 104 are formed.

In addition, since InGaZnO ₄ is used as a material for the oxide semiconductor layer 109, film formation in the semiconductor layer formation step (S104) can be performed at room temperature. Therefore, a flexible plastic substrate can be used as the substrate. In that case, a flexible oxide thin film transistor can be manufactured. In addition, an oxide thin film transistor having high field effect mobility can be realized.

Note that the present disclosure is not limited to the embodiments described in detail, and various modifications may be made without departing from the scope of the present disclosure. For example, the materials, sizes, and shapes of the substrate, the gate electrode, the source electrode, the drain electrode, the gate insulating layer, and the oxide semiconductor layer included in the oxide thin film transistor are not limited to those in the embodiment and depart from the gist of the present disclosure. It can be appropriately changed within the range not to be.

In the first to third embodiments, the oxide semiconductor layer is formed after the source electrode and the drain electrode are formed. However, the source electrode and the drain electrode may be formed after the oxide semiconductor layer is formed. In this case, since the source electrode and the drain electrode are not oxidized in the formation process of the oxide semiconductor layer, the selection range when selecting the material of the source electrode and the drain electrode can be widened.

In the interlayer insulating layer forming step (S105) in the third embodiment, first, the non-fluorine organic resin layer 151 is formed on the top surface of the oxide semiconductor layer 109, and the amorphous perfluororesin layer 152 is formed on the top surface. . However, similarly to the gate insulating layer forming step (S30) of the second embodiment, first, the amorphous perfluoro resin layer 152 is formed on the upper surface of the oxide semiconductor layer 109, and the non-fluorine-based organic resin layer 151 is formed on the upper surface. You may form. In this case, the amorphous perfluoro resin layer 152 having low hardness is covered with the non-fluorine organic resin layer 151 and is not exposed to the outside. If a material having high hardness is selected as the material of the non-fluorine organic resin layer 151, the physical resistance of the interlayer insulating layer 105 can be improved. Thus, deterioration of the characteristics of the oxide thin film transistor 100 due to damage to the interlayer insulating layer 105 can be suppressed. In particular, damage to the interlayer insulating layer 105 in the pixel electrode formation step (S107) performed after forming the interlayer insulating layer 105 can be reduced, and the oxide thin film transistor 100 having favorable characteristics can be obtained.

The oxide thin film transistor and the manufacturing method of the oxide thin film transistor of the present disclosure can be applied to a so-called bottom gate type or top gate type oxide thin film transistor and a manufacturing method thereof.

Claims

A first insulating layer;
An oxide semiconductor layer forming a channel portion on the top surface of the first insulating layer;
A source electrode and a drain electrode provided apart from each other through the channel portion;
A second insulating layer provided on an upper surface of the oxide semiconductor layer,
The oxide thin film transistor, wherein the second insulating layer includes a non-fluorine organic polymer layer made of a non-fluorine organic polymer and an amorphous perfluoro resin layer made of an amorphous perfluoro resin.
2. The oxide thin film transistor according to claim 1, wherein the non-fluorine organic polymer layer contains polyvinylphenol.
3. The oxide thin film transistor according to claim 1, wherein the oxide semiconductor layer is formed of an oxide containing at least one element of In, Ga, and Zn.
The second insulating layer is
The non-fluorine organic polymer layer comprising the non-fluorine organic polymer provided on the oxide semiconductor layer;
4. The oxide thin film transistor according to claim 1, further comprising the amorphous perfluororesin layer made of the amorphous perfluororesin and provided on an upper surface of the non-fluorine organic polymer layer. 5. .
The second insulating layer is
The amorphous perfluoro resin layer provided on the top surface of the oxide semiconductor layer and made of the amorphous perfluoro resin;
The oxidation according to any one of claims 1 to 3, further comprising: the non-fluorine organic polymer layer made of the non-fluorine organic polymer provided on an upper surface of the amorphous perfluoro resin layer. Thin film transistor.
The oxide thin film transistor is a top gate type,
6. The oxide thin film transistor according to claim 1, wherein the first insulating layer is a substrate, and a gate electrode is provided on an upper surface of the second insulating layer.
The oxide thin film transistor is a bottom gate type,
The oxide thin film transistor according to claim 1, wherein the first insulating layer is a gate insulating layer, and a pixel electrode is provided on an upper surface of the second insulating layer.
An oxide semiconductor layer forming step of forming an oxide semiconductor layer on the upper surface of the first insulating layer;
A source / drain electrode forming step of forming a source electrode and a drain electrode separated from each other through a channel portion formed by the oxide semiconductor layer;
A second insulating layer forming step of forming a second insulating layer on the upper surface of the oxide semiconductor layer,
The second insulating layer forming step includes
A non-fluorine organic polymer layer forming step of forming a non-fluorine organic polymer layer comprising a non-fluorine organic polymer;
An oxide thin film transistor manufacturing method, comprising: an amorphous perfluoro resin layer forming step of forming an amorphous perfluoro resin layer made of an amorphous perfluoro resin.
9. The oxide thin film transistor manufacturing method according to claim 8, wherein in the non-fluorine organic polymer layer forming step, the non-fluorine organic polymer layer is formed by applying a solution containing polyvinylphenol. Method.
The second insulating layer forming step includes
The non-fluorine organic polymer layer forming step of forming the non-fluorine organic polymer layer made of the non-fluorine organic polymer on the top surface of the oxide semiconductor layer;
The amorphous perfluoro resin layer forming step of forming the amorphous perfluoro resin layer made of the amorphous perfluoro resin on an upper surface of the non-fluorine organic polymer layer. The manufacturing method of the oxide thin-film transistor of description.
The second insulating layer forming step includes
The amorphous perfluoro resin layer forming step of forming the amorphous perfluoro resin layer made of the amorphous perfluoro resin on the upper surface of the oxide semiconductor layer;
The non-fluorine organic polymer layer forming step of forming the non-fluorine organic polymer layer made of the non-fluorine organic polymer on an upper surface of the amorphous perfluoro resin layer. Item 10. A method for producing an oxide thin film transistor according to Item 8 or 9.
The oxide thin film transistor is a top gate type,
The first insulating layer is a substrate;
12. The method of manufacturing an oxide thin film transistor according to claim 8, further comprising a gate electrode forming step of forming a gate electrode on the upper surface of the second insulating layer.
The oxide thin film transistor is a bottom gate type,
A gate electrode forming step of forming a gate electrode on the substrate;
A first insulating layer forming step of forming the first insulating layer on the gate electrode;
The method for manufacturing an oxide thin film transistor according to claim 8, further comprising a pixel electrode forming step of forming a pixel electrode on the upper surface of the second insulating layer.