JP2003198521A5 - - Google Patents

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Publication number
JP2003198521A5
JP2003198521A5 JP2002273199A JP2002273199A JP2003198521A5 JP 2003198521 A5 JP2003198521 A5 JP 2003198521A5 JP 2002273199 A JP2002273199 A JP 2002273199A JP 2002273199 A JP2002273199 A JP 2002273199A JP 2003198521 A5 JP2003198521 A5 JP 2003198521A5
Authority
JP
Japan
Prior art keywords
input
circuit
data
clock skew
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002273199A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003198521A (ja
Filing date
Publication date
Priority claimed from US09/967,443 external-priority patent/US6823466B2/en
Application filed filed Critical
Publication of JP2003198521A publication Critical patent/JP2003198521A/ja
Publication of JP2003198521A5 publication Critical patent/JP2003198521A5/ja
Pending legal-status Critical Current

Links

JP2002273199A 2001-09-28 2002-09-19 通信システムにおけるクロック・スキューの調整回路及び方法 Pending JP2003198521A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/967,443 2001-09-28
US09/967,443 US6823466B2 (en) 2001-09-28 2001-09-28 Circuit and method for adjusting the clock skew in a communications system

Publications (2)

Publication Number Publication Date
JP2003198521A JP2003198521A (ja) 2003-07-11
JP2003198521A5 true JP2003198521A5 (https=) 2005-11-04

Family

ID=25512800

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002273199A Pending JP2003198521A (ja) 2001-09-28 2002-09-19 通信システムにおけるクロック・スキューの調整回路及び方法

Country Status (4)

Country Link
US (1) US6823466B2 (https=)
EP (1) EP1298443B1 (https=)
JP (1) JP2003198521A (https=)
DE (1) DE60206232T2 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6823466B2 (en) * 2001-09-28 2004-11-23 Agilent Technologies, Inc. Circuit and method for adjusting the clock skew in a communications system
US6973603B2 (en) * 2002-06-28 2005-12-06 Intel Corporation Method and apparatus for optimizing timing for a multi-drop bus
ES2551427T3 (es) 2012-02-06 2015-11-19 William L. Pridgen Combinación de famciclovir y celecoxib para síndromes somáticos funcionales
CN104243222A (zh) * 2013-06-06 2014-12-24 鸿富锦精密工业（深圳）有限公司 网络设备性能测试方法及测试装置和测试系统

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4550405A (en) * 1982-12-23 1985-10-29 Fairchild Camera And Instrument Corporation Deskew circuit for automatic test equipment
US4546269A (en) * 1983-12-01 1985-10-08 Control Data Corporation Method and apparatus for optimally tuning clock signals for digital computers
US5157277A (en) * 1990-12-28 1992-10-20 Compaq Computer Corporation Clock buffer with adjustable delay and fixed duty cycle output
JPH0832425A (ja) * 1994-07-18 1996-02-02 Fujitsu Ltd データ読み取りタイミング可変回路
US5856753A (en) * 1996-03-29 1999-01-05 Cypress Semiconductor Corp. Output circuit for 3V/5V clock chip duty cycle adjustments
US6108794A (en) * 1998-02-24 2000-08-22 Agilent Technologies Signal comparison system and method for improving data analysis by determining transitions of a data signal with respect to a clock signal
US6239629B1 (en) * 1999-04-29 2001-05-29 Agilent Technologies, Inc. Signal comparison system and method for detecting and correcting timing errors
US6687844B1 (en) * 2000-09-28 2004-02-03 Intel Corporation Method for correcting clock duty cycle skew by adjusting a delayed clock signal according to measured differences in time intervals between phases of original clock signal
US6823466B2 (en) * 2001-09-28 2004-11-23 Agilent Technologies, Inc. Circuit and method for adjusting the clock skew in a communications system

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