WO2008120322A1 - 信号遅延評価プログラム、信号遅延評価方法、および信号遅延評価装置 - Google Patents

信号遅延評価プログラム、信号遅延評価方法、および信号遅延評価装置 Download PDF

Info

Publication number
WO2008120322A1
WO2008120322A1 PCT/JP2007/056688 JP2007056688W WO2008120322A1 WO 2008120322 A1 WO2008120322 A1 WO 2008120322A1 JP 2007056688 W JP2007056688 W JP 2007056688W WO 2008120322 A1 WO2008120322 A1 WO 2008120322A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal delay
slew rate
delay assessment
signal
circuit block
Prior art date
Application number
PCT/JP2007/056688
Other languages
English (en)
French (fr)
Inventor
Mitsuru Onodera
Original Assignee
Fujitsu Microelectronics Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Microelectronics Limited filed Critical Fujitsu Microelectronics Limited
Priority to JP2009507314A priority Critical patent/JP4526596B2/ja
Priority to PCT/JP2007/056688 priority patent/WO2008120322A1/ja
Publication of WO2008120322A1 publication Critical patent/WO2008120322A1/ja
Priority to US12/552,015 priority patent/US8713500B2/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/3312—Timing analysis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/12—Timing analysis or timing optimisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

　それぞれ異なるプラットフォーム上で設計された複数の回路ブロックが搭載された半導体装置において、システム全体の信号遅延を正確に評価できるようにする。 　信号遅延評価プログラム（１）において、プラットフォーム判別工程（ステップＳ１）では、第１の回路ブロックのスルーレートと、この第１の回路ブロックからの出力信号の供給を受ける第２の回路ブロックのスルーレートとが、伝送される信号レベルに対する異なるレベル基準値により定義されたものか否かを判別する。スルーレート補正工程（ステップＳ２）では、プラットフォーム判別工程（ステップＳ１）で各レベル基準値が異なると判別された場合に、これらのレベル基準値の差に応じたスルーレート誤差に基づいて、第１の回路ブロックからの出力信号における出力スルーレートを補正する。
PCT/JP2007/056688 2007-03-28 2007-03-28 信号遅延評価プログラム、信号遅延評価方法、および信号遅延評価装置 WO2008120322A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2009507314A JP4526596B2 (ja) 2007-03-28 2007-03-28 信号遅延評価プログラム、信号遅延評価方法、および信号遅延評価装置
PCT/JP2007/056688 WO2008120322A1 (ja) 2007-03-28 2007-03-28 信号遅延評価プログラム、信号遅延評価方法、および信号遅延評価装置
US12/552,015 US8713500B2 (en) 2007-03-28 2009-09-01 Computer program and apparatus for evaluating signal propagation delays

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/056688 WO2008120322A1 (ja) 2007-03-28 2007-03-28 信号遅延評価プログラム、信号遅延評価方法、および信号遅延評価装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/552,015 Continuation US8713500B2 (en) 2007-03-28 2009-09-01 Computer program and apparatus for evaluating signal propagation delays

Publications (1)

Publication Number Publication Date
WO2008120322A1 true WO2008120322A1 (ja) 2008-10-09

Family

ID=39807915

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/056688 WO2008120322A1 (ja) 2007-03-28 2007-03-28 信号遅延評価プログラム、信号遅延評価方法、および信号遅延評価装置

Country Status (3)

Country Link
US (1) US8713500B2 (ja)
JP (1) JP4526596B2 (ja)
WO (1) WO2008120322A1 (ja)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5117170B2 (ja) * 2007-11-20 2013-01-09 株式会社リコー 回路設計支援装置、回路設計支援方法、回路設計支援プログラム及び記録媒体
JP5569237B2 (ja) * 2010-08-06 2014-08-13 富士通セミコンダクター株式会社 情報処理装置、プログラム、および設計支援方法
US8997031B2 (en) * 2013-03-13 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Timing delay characterization method, memory compiler and computer program product
US10984165B1 (en) * 2020-01-29 2021-04-20 International Business Machines Corporation Digital Rights Management for printed circuit boards
CN116822450A (zh) * 2023-06-27 2023-09-29 上海奎芯集成电路设计有限公司 在验证训练流程时制造线上延迟的方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0863509A (ja) * 1994-08-24 1996-03-08 Oki Electric Ind Co Ltd シミュレーション方法
JPH10162040A (ja) * 1996-11-29 1998-06-19 Fujitsu Ltd 大規模集積回路装置の製造方法及び大規模集積回路装置
JPH10270564A (ja) * 1997-03-27 1998-10-09 Fujitsu Ltd 半導体集積回路装置の製造方法

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4306194A (en) * 1979-10-11 1981-12-15 International Business Machines Corporation Data signal detection circuit
US4641246A (en) * 1983-10-20 1987-02-03 Burr-Brown Corporation Sampling waveform digitizer for dynamic testing of high speed data conversion components
US4513207A (en) * 1983-12-27 1985-04-23 General Electric Company Alternating comparator circuitry for improved discrete sampling resistance control
US5369309A (en) * 1991-10-30 1994-11-29 Harris Corporation Analog-to-digital converter and method of fabrication
US5481129A (en) * 1991-10-30 1996-01-02 Harris Corporation Analog-to-digital converter
US5377202A (en) * 1993-05-03 1994-12-27 Raytheon Company Method and apparatus for limiting pin driver offset voltages
JPH0765041A (ja) 1993-08-25 1995-03-10 Hitachi Ltd 信号遅延評価方法
JP3351651B2 (ja) * 1995-04-07 2002-12-03 富士通株式会社 会話型回路設計装置
US6304998B1 (en) 1997-03-27 2001-10-16 Fujitsu Limited Method of manufacturing integrated circuit device
US6432731B1 (en) * 1998-07-09 2002-08-13 Seiko Epson Corporation Method and apparatus for verifying semiconductor integrated circuit
JP2000286342A (ja) 1999-03-30 2000-10-13 Hitachi Ltd コンピュータ読み取り可能な記憶媒体、半導体集積回路の設計方法、ならびに半導体装置の設計方法
JP4087572B2 (ja) * 2001-01-24 2008-05-21 富士通株式会社 カスタムｌｓｉにおける遅延特性解析方法
JP2002232271A (ja) * 2001-02-01 2002-08-16 Fujitsu Ltd Ｄｃオフセットキャンセル回路、光−電気パルス変換回路、及びパルス整形回路
US6571376B1 (en) * 2002-01-03 2003-05-27 Intel Corporation Method and apparatus for analog compensation of driver output signal slew rate against device impedance variation
WO2004075414A1 (en) * 2003-02-14 2004-09-02 Mcdonald James J Iii Circuitry to reduce pll lock acquisition time
US7215274B2 (en) * 2005-07-29 2007-05-08 Agere Systems Inc. Reference voltage pre-charge in a multi-step sub-ranging analog-to-digital converter
GB2429351B (en) * 2005-08-17 2009-07-08 Wolfson Microelectronics Plc Feedback controller for PWM amplifier
US7523430B1 (en) * 2005-09-09 2009-04-21 Altera Corporation Programmable logic device design tool with simultaneous switching noise awareness
US20070136705A1 (en) * 2005-12-09 2007-06-14 Fujitsu Limited Timing analysis method and device
US8115508B2 (en) * 2007-01-09 2012-02-14 International Business Machines Corporation Structure for time based driver output transition (slew) rate compensation
US7992119B1 (en) * 2008-06-06 2011-08-02 Altera Corporation Real-time background legality verification of pin placement

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0863509A (ja) * 1994-08-24 1996-03-08 Oki Electric Ind Co Ltd シミュレーション方法
JPH10162040A (ja) * 1996-11-29 1998-06-19 Fujitsu Ltd 大規模集積回路装置の製造方法及び大規模集積回路装置
JPH10270564A (ja) * 1997-03-27 1998-10-09 Fujitsu Ltd 半導体集積回路装置の製造方法

Also Published As

Publication number Publication date
JP4526596B2 (ja) 2010-08-18
US20090319972A1 (en) 2009-12-24
JPWO2008120322A1 (ja) 2010-07-15
US8713500B2 (en) 2014-04-29

Similar Documents

Publication Publication Date Title
TW200802823A (en) Method for forming bit line contacts and bit lines during the formation of a semiconductor device, and devices and systems including the bit lines and bit line contacts
TW200943300A (en) Memory system and method for providing error correction
WO2009000639A3 (en) System and method for error correction and detection in a memory system
TW200742028A (en) On-die calibration system and calibration method
TW200629365A (en) Substrate transfer and processing apparatus, obstacle measure method in substrate transfer and processing apparatus and program for an obstacle measure in the substrate transfer and processing apparatus
WO2009105204A3 (en) Memory device with network on chip methods, apparatus, and systems
WO2011016934A3 (en) Method and system for synchronizing address and control signals in threaded memory modules
GB0705327D0 (en) Method of transmitting data in a commumication system
WO2008120322A1 (ja) 信号遅延評価プログラム、信号遅延評価方法、および信号遅延評価装置
TW200713761A (en) Circuit and method for a soft-start with residual voltage
WO2007031908A3 (en) Improved device, system and method for determining authenticity of an item
WO2007062358A3 (en) Methods and apparatus to detect and correct integrity failures in satellite positioning system receivers
WO2006069040A3 (en) Method and apparatus for adjusting relative disposition of projection optics based on operating conditions
WO2009040143A3 (en) Controlling quality of video data by a user
WO2007112032A3 (en) Fpga routing with reservation for long lines and sharing long lines
TW200943154A (en) Capacitor-type touch device and method for data transmission applied to the capacitor-type touch device
ATE531131T1 (de) Verfahren und vorrichtung zum verteilen mehrerer signaleingänge an mehrere integrierte schaltungen
WO2009069184A1 (ja) 音処理装置、補正装置、補正方法及びコンピュータプログラム
WO2011109487A8 (en) Method and apparatus for testing a memory device
WO2009016837A1 (ja) 無線通信装置および再送判定方法
WO2011100491A3 (en) Adaptive systems using correntropy
WO2009095546A3 (en) A method for controlling a process and for monitoring the condition of process equipment, and an automation system
TW200618153A (en) Method and system for calibrating integrated metrology systems and stand-alone metrology systems that acquire wafer state data
WO2009128786A3 (en) A system and process for dicing integrated circuits
ATE458333T1 (de) Routing-einrichtung für ein unterseeisches elektronikmodul

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07740126

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2009507314

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 07740126

Country of ref document: EP

Kind code of ref document: A1