JP2003188193A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the number of times of registering reference pattern data (template pattern) used to position a die bonded semiconductor chip. <P>SOLUTION: A method for manufacturing a semiconductor device comprises the steps of housing the semiconductor chips divided into individual pieces and a pattern state of its periphery as image data D1 in a die bonder, processing the image data D1 by cutting off a desired region of the image data D2 or masking a region except a desired region, thereby forming a reference pattern data D2, and aligning the chip intended to be picked up by using the data D2. As a result, even when the pattern shape of the surface of the chip is slightly different according to the component to be processed, the previous process is conducted to form the reference pattern data, and its surface state can be confirmed at each component, and hence a work of re-registering the reference pattern data can be omitted. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, it is applied to positioning when a die (semiconductor chip) obtained by scribing a wafer is mounted on an upper portion of a lead frame or the like. It is related to effective technology.

[0002]

2. Description of the Related Art MISFET (Metal Insulator Semico)
A semiconductor substrate (wafer) on which semiconductor elements such as nductor field effect transistors) and wiring are formed is diced into substantially rectangular dies (semiconductor chips), and is fixed onto, for example, a lead frame. After that, for example, the bonding pad exposed on the surface of the semiconductor chip and the lead frame are connected with a wire, and the wire, the semiconductor chip, and the like are sealed with resin.

[0003]

The step of fixing the above-mentioned individualized die (semiconductor chip) to the upper portion of a lead frame or the like is called die bonding, and the device used in this step is called a die bonder.

Some of the die bonders have an adsorption mechanism for adsorbing and conveying the die, as will be described later in detail. That is, the die separated from the wafer state is held on the adhesive sheet on the back surface of the wafer, and the die is adsorbed by the adsorption mechanism from the upper part of the adhesive sheet and peeled from the adhesive sheet to obtain the desired die. It is transported to a position, for example, a lead frame and fixed.

At this time, it is necessary to position the die in order to suck and convey the desired position of the die.

For example, for this positioning, the pattern of the die surface is registered as a template pattern in the die bonder in advance, and the positioning can be performed by comparing the template pattern with the pattern of the die surface to be processed. .

However, in such a positioning method,
When the position or shape of the pattern on the die surface differs depending on the product, it was necessary to re-register the template pattern each time.

An object of the present invention is to reduce the number of template pattern registrations. It is also an object of the present invention to reduce the number of registrations to improve the operating rate of the device and shorten the time required for manufacturing a product.

Another object of the present invention is to improve the positioning accuracy of the die.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0011]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

The method of manufacturing a semiconductor device according to the present invention comprises (a)
A step of preparing a plurality of individualized semiconductor chips,
(B) a step of creating reference pattern data by taking in any one surface of the plurality of semiconductor chips as image data and masking an area other than a desired area of the image data; Aligning the surfaces of the plurality of semiconductor chips with the reference pattern data.

The method of manufacturing a semiconductor device according to the present invention comprises (a)
A step of installing a plurality of semiconductor chips each of which has a plurality of patterns on its surface into an apparatus, and (b) capturing any one surface of the plurality of semiconductor chips as image data, A step of creating reference pattern data by masking a pattern other than a desired pattern among the plurality of patterns and registering it in the device,
(C) recognizing the surfaces of the plurality of semiconductor chips, performing alignment by comparing with the reference pattern data, and processing the semiconductor chips.
The device is, for example, a die bonder, and the process is, for example, picking up a semiconductor chip.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

First, a die bonder (die bonding apparatus) used in the method of manufacturing a semiconductor device according to this embodiment will be described. FIG. 1 shows a partial top view of the die bonder.

First, as shown in FIG. 1, a cassette lifter 2 is provided on the front left side. This cassette lifter 2
A semiconductor wafer W is stored inside. The semiconductor wafer W is adhered on a tape attached to a wafer ring (frame) R, and is already diced (individualized) into rectangular semiconductor chips CH.

A wafer correction chute 3 is provided on the right side of the cassette lifter 2, and a ring transfer section 5 is provided behind it. The semiconductor wafer W is transferred to the wafer holder 7 via the wafer correction chute 3 and the ring transfer unit 5.
Be transported to.

On the right side of the wafer correction chute 3,
An operation control unit 6 is provided. The operation controller 6 controls the die bonder.

The above-mentioned wafer holder 7 is located behind the ring transfer unit 5, and the wafer holder 7 mounts and fixes the semiconductor wafer W transferred by the ring transfer unit 5.

A loader 8 is provided inside the cassette lifter 2. This loader 8 is a semiconductor chip C
A lead frame F to which H is attached is stored.

A frame feeder 9 is provided behind the loader 8 from the left side to the right side. The lead frame F is conveyed by the frame feeder 9. Above the frame feeder 9, the preform head 10
Is provided. The preform head 10 has a lead frame F conveyed by the frame feeder 9.
An adhesive material such as a silver paste for joining the semiconductor chip CH is applied to a predetermined position of.

Further, a position where the semiconductor chip CH is picked up (pickup position PP) and a position where the semiconductor chip CH is bonded on the lead frame (bonding position Bo).
A bonding head 11 is provided above P). As will be described later, after the semiconductor chip CH on the semiconductor wafer W is picked up by the suction mechanism (pickup mechanism) 11a in the bonding head 11 and transferred to the upper portion of the lead frame F, the semiconductor chip CH is placed on the lead frame F. Stick to it.

On the pickup position PP of the semiconductor wafer W, a chip recognition camera 12 is provided. The surface state of the chip is recognized by the chip recognition camera 12, and the monitor 15 at the back of the die bonder 1 is recognized.
The situation is displayed in.

A magazine rack 13 is provided at the right end of the frame feeder 9, and an unloader 14 is provided in front of the magazine rack 13. The lead frame F to which the semiconductor chip CH is bonded is stored in the magazine rack 13 and then stored in the unloader 14.

Next, a method of bonding the semiconductor chip CH onto the lead frame F using such a die bonder will be described. FIG. 2 is an explanatory diagram of a main part of the die bonder 1. FIG. 2 schematically shows a mechanism particularly necessary for explaining the flow of the bonding method.

First, as shown in FIG. 2, the semiconductor wafer W stored in the cassette lifter 2 reaches a desired position (pickup position) via the wafer correction chute 3 and the ring transfer unit 5 described in FIG. Be transported.

This semiconductor wafer W is, as described above,
Tape T attached to wafer ring (frame) R
It is adhered to the top in the state of being singulated. That is, the semiconductor wafer W has the tape adhered to its back surface,
The semiconductor wafer W is diced into individual pieces. At this time, for example, the semiconductor wafer W is cut into a rectangular shape, but the tape is diced so as not to be cut so that the individual semiconductor chips CH are not separated (see FIG. 3).

Semiconductor wafer W carried to a desired position
The semiconductor chip CH is peeled from the tape T on the back surface of the semiconductor chip CH by moving the suction mechanism (pickup mechanism) 11a constituting the bonding head 11 and lowering the suction mechanism 11a to suction the semiconductor chip CH. After that, the suction mechanism 11a is raised. This series of operations is called a pickup operation.

Further, while holding the semiconductor chip CH, the semiconductor chip CH is fixed (bonded) on the lead frame F by being conveyed to the lead frame F and lowered. An adhesive material Bo such as silver paste is already applied on the lead frame. FIG. 3 shows how the semiconductor chip CH is picked up and fixed.

As shown in FIG. 3, the adsorption mechanism 11a has a hollow portion inside, and a decompression (V
AC) to adsorb and hold the semiconductor chip CH.

The suction mechanism 11a is a semiconductor chip CH.
Can be moved in the vertical direction (Z direction) to fix the semiconductor chip CH to a desired position and to be fixed on the lead frame F. In addition, the semiconductor chip CH can be moved in the XY direction (the extending direction of the wafer W). ) Is also available. The semiconductor wafer W can also be moved in the XY directions (the extending direction of the wafer W).

At the time of this pickup, the semiconductor chip CH
In order to accurately adsorb the desired position, for example, the central portion thereof, the pattern formed on the surface of the semiconductor chip CH is compared with the reference pattern data registered in the die bonder 1 in advance to perform the alignment. The method of this alignment will be described below.

In this embodiment, of the camera images taken by the wafer recognition camera shown in FIG. 4, the pattern state of the semiconductor chip CH and its periphery is represented by image data D.
It is stored in the device as 1. Next, this image data D
The image data (D2) corresponding to one semiconductor chip CH out of 1 is cut out and stored in the device in advance as reference pattern data (template). The reference pattern data may be created by selecting a characteristic pattern or a pattern common to a plurality of products to be processed and masking other patterns.

Therefore, the die bonder used in this embodiment has a place for storing the image data D1, and further the reference pattern data D processed from the image data D1.
It has a place to store 2 (template).

Then, at the time of pickup, the image of the surface of the semiconductor chip CH to be picked up taken by the wafer recognition camera above the pickup position PP is compared with the reference pattern data to perform the alignment. To do. Then, the pickup operation as described above is performed.

As described above, in this embodiment, for example, the pattern state of the semiconductor chip CH and its periphery is stored in the apparatus as image data, and the image data is processed to form the reference pattern data. The re-registration work of pattern data can be simplified. Further, erroneous recognition can be prevented and the pickup operation can be performed accurately.

For example, as shown in FIGS. 5A and 5B, the pattern on the surface of the semiconductor chip CH may differ depending on the product. In this case, the pattern Pa on the upper right of the semiconductor chip CH has a characteristic pattern shape, and the shapes of the pattern Pa are different between FIGS. 5A and 5B. If this pattern Pa is used as the reference pattern data, it must be registered for each product. At the time of this registration, it takes time for the work such as extracting a product (good product) in which the pattern is accurately formed.

Further, in the manufacture of the product having the patterns shown in FIGS. 5A and 5B, the pattern in the vicinity of the characteristic pattern Pa, for example, the rectangular bonding pad BP, etc. of the chip is also included. The reference pattern data D21 (FIG. 5 (c)) is data obtained by applying mask M to the image data of one corner on different parts of the pattern in advance.
It is also possible to use In this case, it is sufficient to register one reference pattern data for these two types of products, but for example, for the product of the third type, as shown in FIG. 6, a certain characteristic pattern Pa appears at different positions. Cannot use this reference pattern data D21 (FIG. 5C), and must re-register the reference pattern data.

On the other hand, according to the present embodiment, since the image data of a wide area is stored in the apparatus in advance, the reference pattern data is created only by appropriately processing the image data according to the product. Therefore, the work efficiency can be improved as compared with the re-registration described above. As a result, the product manufacturing period can be shortened.

Further, since the reference pattern data can be created simply by appropriately processing the image data according to the product, the degree of coincidence between the reference pattern data and the pattern of the product to be processed can be improved. In addition, it is possible to prevent erroneous recognition and improve the operating rate of the device.

In particular, the semiconductor chip C on the semiconductor wafer W
For H, for example, a probe test is performed before dicing, and the quality is judged. At this time, as shown in FIG. 7, the defective semiconductor chip is provided with a defective mark FM on the surface of the semiconductor chip CH.

Such defective marks FM often have different attachment positions for each processing unit (lot) even if they are the same product. For example, as shown in FIG. 8, the defective mark FM is formed on a comparatively lower portion of the semiconductor chip CH (FIG. 8B), or is formed slightly in the center (FIG. 8A). ).

Even in such a case, for example, as shown in FIG.
For the lot in which the defective mark FM is formed at the position shown in (a), the image data D1 shown in FIG. 4 is processed and the area Ma is masked to be the reference pattern data, and then the FIG. With respect to the lot in which the defective mark is formed at the position indicated by, it is possible to perform the alignment by using the masked area Mb as the reference pattern data.

The defective chip is fixed on the defective lead frame, and alignment is required when securing the continuity of processing. Also, whether or not the chip is defective
This is determined by scanning the inside of the semiconductor chip and inspecting for the presence or absence of defective marks, but alignment is necessary before this scanning.

As described above, according to the present embodiment, the image of the surface of the semiconductor chip stored in advance is processed by, for example, appropriately changing the masking place, and the reference pattern data suitable for each lot is created. be able to.

As a result, the number of times the reference pattern data is registered can be reduced and the operating rate of the device can be improved. In addition, it is possible to reduce the time required to manufacture the product. Furthermore, the positioning accuracy of the semiconductor chip can be improved.

Next, the subsequent processing steps of the semiconductor chip CH (see FIG. 3) fixed on the lead frame F will be described.

As shown in FIG. 9, the semiconductor chip CH fixed to the lead frame F is prepared, and the electrode portion (bonding pad portion) exposed on the surface and the lead portion of the lead frame F are gold wire or the like. Connection using the conductive wire 27. The connection between the electrode portion on the semiconductor chip CH and the external lead-out terminal of the package by a wire is called wire bonding, and the device used for this connection is called a wire bonder.

Also during this wire bonding, it is necessary to align the semiconductor chips in order to accurately fix the lead frame and the semiconductor chips. Also in this case, the above-mentioned effect can be obtained by using the above-mentioned reference pattern data.

Next, as shown in FIG. 10, the lead frame F is sandwiched by the molding dies (28a, 28b). This mold includes an upper mold 28a and a lower mold 2.
8b, and the molten resin 30 is injected from a resin introduction hole (resin introduction portion) 29 provided in the lower mold 28b to fill the recess (cavity) of the molding mold with the molten resin. Next, the peripheral portion of the semiconductor chip CH is covered with the sealing resin 30a by curing the molten resin.

Next, the lead portion (external lead) protruding from the sealing resin 30a is shaped into a desired shape, for example, a gull wing shape (FIG. 11).

In this embodiment, the semiconductor chip CH is fixed (die bonded) on the lead frame F. However, as shown in FIG. 12A, the solder ball HB is formed on the back surface of the semiconductor chip CH. The semiconductor chip CH may be fixed on the substrate JK. Even in the die bonder used in such a process, the alignment can be performed using the reference pattern data described in the present embodiment when the semiconductor chip CH is picked up.

In the semiconductor chip CH fixed to the mounting board JK, as shown in FIG. 12B, the electrode portion on the surface and the electrode formed on the surface of the mounting board are connected by wires 27, and The periphery is covered with the sealing resin 30a. A package having a size substantially the same as or slightly larger than the semiconductor chip CH is called a CSP (chip size package).

In addition, the CS shown in FIGS.
P is so-called face-up mounting in which the back surface of the semiconductor chip CH (the surface opposite to the element formation surface) is fixed to the mounting board JK. As shown in FIG. 13, the element formation surface of the semiconductor chip is mounted on the mounting board. The present embodiment can also be applied to the case of so-called face-down mounting, which is fixed to the.

In this case, as shown in FIG. 13A, the bump electrode B is formed on the element formation surface of the semiconductor chip CH, and the back surface of the bump electrode B is picked up and mounted on the mounting board J.
Stick to K. Positioning can be performed at the time of this pickup using the reference pattern described in the present embodiment.

That is, in this case, for example, the alignment can be performed based on various marks formed on the back surface of the semiconductor chip CH and the shapes of the corners, but in this case also, the semiconductor chip is aligned. The image data of the entire back surface of the CH is stored in the device in advance, and the reference pattern data is created by processing the image data by appropriately masking it and the semiconductor chip CH to be processed.
Alignment is performed by comparing with the image on the back side of.

After positioning, picking up is performed and the bump electrodes B of the semiconductor chip CH are fixed so as to be positioned on electrodes (not shown) formed on the surface of the mounting substrate. After that, as shown in FIG. 13B, the periphery of the semiconductor chip CH is covered with the sealing resin 30a.

The so-called LOC (le
The present embodiment can be applied to a product having an ad on chip structure. As shown in FIG. 14C, this LOC structure is a structure in which a lead frame F is arranged on a semiconductor chip CH and the surface of the semiconductor chip CH (element formation surface) and the lead frame F are connected by wire bonding. is there.

Also in this case, as shown in FIG.
In order to bond the element formation surface of the semiconductor chip CH to the lead frame, the back surface is picked up and bonded to the lead frame F. At the time of this pickup, the reference pattern data described in the present embodiment can be used for alignment. That is, the image data of the entire back surface of the semiconductor chip CH is stored in the device in advance, the reference pattern data is created by processing the image data by appropriately masking, and this and the semiconductor chip to be processed. Positioning is performed by comparing the image on the back surface of the CH. After that, as shown in FIG. 14B, the electrode portion on the surface of the semiconductor chip CH and the lead portion of the lead frame F are connected by the wire 27. Next, as shown in FIG. 14C, the periphery of the semiconductor chip CH is covered with the sealing resin 30a, and the lead portion protruding from the sealing resin 30a is shaped into a desired shape.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

Particularly, in the present embodiment, the alignment of the die bonder has been mainly described, but the invention is not limited to such an apparatus, and for example, a chip mounter, a wire bonder, or the like can be used.
It is widely applicable when using a device having a function of performing alignment based on a mark or pattern formed on the surface of a semiconductor chip (whether or not it is an element formation surface).

Further, in the present embodiment, the data corresponding to one semiconductor chip CH is used as the reference pattern data, but it is not the size corresponding to one semiconductor chip CH but a part thereof, for example, the semiconductor. 1 / chip CH
The part corresponding to the area of the four corners may be the reference pattern data.

[0063]

The effects obtained by the typical ones of the inventions disclosed in this application will be briefly described as follows.
It is as follows.

The individual semiconductor chips and the pattern state around the semiconductor chips are stored as image data in a die bonder, and a desired region of this image data is cut out or masked in a region other than the desired region. By processing, the reference pattern data was created and the position of the semiconductor chip to be processed was aligned using this reference pattern data.Therefore, when the pattern shape of the surface of the semiconductor chip differs slightly depending on the product. Even if there is, the reference pattern data can be created by performing the above-mentioned processing, and the work of confirming the surface state of each product and re-registering the reference pattern data can be omitted.

That is, the number of times the reference pattern data (template pattern) is registered can be reduced, and
By reducing the number of registrations, the operating rate of the device can be improved. As a result, the time required to manufacture the product can be shortened.

Further, the positioning accuracy of the semiconductor chip can be improved.

[Brief description of drawings]

FIG. 1 is a plan view showing a die bonder used in this embodiment of the present invention.

FIG. 2 is a perspective view schematically showing the mechanism of the die bonder for explaining the flow of the bonding method according to the embodiment of the present invention.

FIG. 3 is a diagram showing how a semiconductor chip according to an embodiment of the present invention is picked up and fixed.

FIG. 4 is a diagram showing a pattern state of a semiconductor chip and its periphery.

FIG. 5 is a diagram showing a pattern of a semiconductor chip for explaining the effect of the embodiment of the present invention.

FIG. 6 is a diagram showing a pattern of a semiconductor chip for explaining the effect of the embodiment of the present invention.

FIG. 7 is a plan view showing a state where a defect mark is attached to the surface of a semiconductor chip of a semiconductor wafer.

8A and 8B are diagrams showing the surface state of a semiconductor chip having a defective mark.

FIG. 9 is a cross-sectional view of an essential part of a device showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 10 is a main-portion cross-sectional view of the device showing the manufacturing method of the semiconductor device which is the embodiment of the present invention;

FIG. 11 is a main-portion cross-sectional view of the device showing the manufacturing method of the semiconductor device which is the embodiment of the present invention;

12A and 12B are cross-sectional views of a main part of an apparatus showing an example of another semiconductor device in which the embodiment of the present invention is used and a manufacturing method thereof.

13A and 13B are cross-sectional views of a main part of the device showing an example of another semiconductor device in which the embodiment of the present invention is used and a manufacturing method thereof.

14A to 14C are main-portion cross-sectional views of an example of another semiconductor device in which the embodiment of the present invention is used and a manufacturing method thereof.

[Explanation of symbols]

1 die bonder 2 cassette lifters 3 Wafer correction chute 5 ring conveyor 6 Operation control unit 7 Wafer holder 8 loader 9 frame feeder 10 preform head 11 Bonding head 11a Adsorption mechanism (pickup mechanism) 12 chip recognition camera 13 magazine rack 14 Unloader 15 monitors 27 wires 28a Mold die (upper die) 28b Mold die (lower die) 30 molten resin 30a sealing resin B bump electrode Bo adhesive BoP bonding position BP bonding pad CH semiconductor chip D1 image data D2 standard pattern data D21 standard pattern data F lead frame FM defective mark HB solder ball JK mounting board M mask Ma, Mb mask area PP pickup position Pa pattern T tape W semiconductor wafer

Continued front page    F-term (reference) 5F047 AA11 BA21 BA53 BB11 BB18                       FA08 FA15 FA16 FA22 FA32                       FA36 FA73 FA75 FA79

Claims (5)

[Claims] 1. A step of: (a) preparing a plurality of individual semiconductor chips; and (b) taking in one of the surfaces of the plurality of semiconductor chips as image data to obtain a desired image data. A semiconductor having a step of creating reference pattern data by masking an area other than the area, and (c) aligning the surfaces of the plurality of semiconductor chips with the reference pattern data. Device manufacturing method. 2. A step of: (a) installing a plurality of semiconductor chips, each of which is divided into individual pieces and having a plurality of patterns on a surface thereof, in an apparatus; and (b) any one of the plurality of semiconductor chips. Taking in one surface as image data and masking other than the desired pattern among the plurality of patterns to create reference pattern data, and registering the reference pattern data in the device; (c) surfaces of the plurality of semiconductor chips And aligning by comparing with the reference pattern data to process the semiconductor chip, the method for manufacturing a semiconductor device. 3. A step of: (a) installing a sheet, which is divided into individual pieces, on the surface of which a plurality of semiconductor chips having a plurality of patterns are fixed, in a die bonder; and (b) among the plurality of semiconductor chips. Capturing any one surface as image data, masking other than the desired pattern of the plurality of patterns to create reference pattern data, and registering the reference pattern data in the die bonder; (c) on the sheet Recognizing the surface of the semiconductor chip, performing alignment by comparing with the reference pattern data, and picking up the semiconductor chip. 4. The method for manufacturing a semiconductor device according to claim 3, further comprising: (d) fixing the picked-up semiconductor chip onto a mounting substrate after the step (c). A method for manufacturing a semiconductor device as described above. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the area used as the reference pattern data is smaller than the area captured as the image data.