JPH06244245A - Semiconductor device bonding device - Google Patents

Semiconductor device bonding device

Info

Publication number
JPH06244245A
JPH06244245A JP2787093A JP2787093A JPH06244245A JP H06244245 A JPH06244245 A JP H06244245A JP 2787093 A JP2787093 A JP 2787093A JP 2787093 A JP2787093 A JP 2787093A JP H06244245 A JPH06244245 A JP H06244245A
Authority
JP
Japan
Prior art keywords
semiconductor element
data
semiconductor
wafer
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2787093A
Other languages
Japanese (ja)
Other versions
JP2849519B2 (en
Inventor
Noriki Iwasaki
岩▲崎▼範樹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP2787093A priority Critical patent/JP2849519B2/en
Publication of JPH06244245A publication Critical patent/JPH06244245A/en
Application granted granted Critical
Publication of JP2849519B2 publication Critical patent/JP2849519B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To obtain a face down bonding device, which facilitates control of the characteristics of a semiconductor device by the slight improvement to a conventional die bonding device, by a method wherein the face down bonding device is constituted of a first transfer means, a first recognition means, a second transfer means, a second recognition means, a collating means and a bonding means, which are respectively specified. CONSTITUTION:A face down bonding device is constituted of a first transfer means, which turns an active element surface 2 of a semiconductor element 1 down ward and transfers the element 1, a first recognition means, which recognizes data on a pattern on the surface 2 of the element 1 and consists of an infrared camera 4 and an infrared microscope 3, a second transfer means, which sucks the element 1 from over and transfers the element 1 to a material 7 to be mounted, a second recognition means (a camera) 8 to recognize data on a pattern on the surface of the material 7 to be mounted, a collating means to collate the data on the pattern on the surface 2 of the element 1 with the data on the patter on the surface of the material 7 and a bonding means to bond the element 1 to the material 7 to be mounted on the basis of the collated result.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体素子接合装置に
関し、更に詳しくは、半導体素子の組み立て工程のう
ち、リードフレームや回路基板等の被搭載物に半導体素
子の能動素子面を対向させて接合する、フェイスダウン
接合装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element bonding apparatus, and more specifically, in the process of assembling a semiconductor element, the active element surface of the semiconductor element is made to face a mounted object such as a lead frame or a circuit board. The present invention relates to a face-down joining device for joining.

【0002】[0002]

【従来の技術】図4の従来のフェイスダウン接合の工程
図を用いて、従来のフェイスダウン接合工程を説明す
る。
2. Description of the Related Art A conventional face-down joining process will be described with reference to a conventional face-down joining process diagram of FIG.

【0003】まず、ウエハー20の裏面にテープを貼
り、このテープの周囲を専用リングで保持した状態で、
カメラ22aを用いてウエハー20の能動素子面21か
らダイシングラインを認識し、該ラインに沿って切断す
る(図4(a)、ダイシング工程)。
First, a tape is attached to the back surface of the wafer 20, and the periphery of the tape is held by a dedicated ring.
The camera 22a is used to recognize the dicing line from the active element surface 21 of the wafer 20 and cut along the line (FIG. 4A, dicing step).

【0004】次に、ダイシングされた半導体素子23の
能動素子面21を認識し、コレット24aを用いて、良
品をトレイ25aに治具詰めする(図4(b)、チップ
選別工程)。その後、治具詰めしたトレイ25aに空の
トレイ25bをかぶせて反転させ、半導体素子23の能
動素子面21が下を向くようにする(図4(c)、反転
工程)。
Next, the active element surface 21 of the diced semiconductor element 23 is recognized, and non-defective products are jig-filled in the tray 25a using the collet 24a (FIG. 4B, chip selection step). After that, the jig-filled tray 25a is covered with an empty tray 25b and inverted so that the active element surface 21 of the semiconductor element 23 faces downward (FIG. 4C, inversion step).

【0005】次に、反転した半導体素子23を上方から
コレット24bを用いて真空吸着してピックアップし、
能動素子面21のパターンと電極とを下方に設けたカメ
ラ22bによって認識し、被搭載物26の表面パターン
をカメラ22cによって認識して得た搭載位置まで被搭
載物26の表面に対向させてフェイスダウン接合を行う
(図4(d)、接合工程)。
Next, the inverted semiconductor element 23 is vacuum-adsorbed and picked up from above using a collet 24b,
The pattern of the active element surface 21 and the electrodes are recognized by the camera 22b provided below, and the surface pattern of the mounted object 26 is recognized by the camera 22c to face the surface of the mounted object 26 up to the mounting position obtained. Down joining is performed (FIG. 4D, joining step).

【0006】尚、ウエハーの能動素子面を保護するため
に、能動素子面にテープを貼り付け、半導体素子を単体
に切断する方法はこれまでにも報告されているが(特開
昭55−53437号公報、特開昭60−4010号公
報等)、この状態で直接フェイスダウン接合をする方法
はなかった。
A method of attaching a tape to the active element surface to protect the active element surface of the wafer and cutting the semiconductor element into individual pieces has been reported up to now (Japanese Patent Laid-Open No. 55-53437). JP-A-60-4010, etc.), there was no method of directly performing face-down bonding in this state.

【0007】[0007]

【発明が解決しようとする課題】しかしながら、上記従
来のフェイスダウン接合方法を用いた場合、以下の問題
点がある。
However, when the above-mentioned conventional face-down joining method is used, there are the following problems.

【0008】まず、第1にワイヤーボンディング等の半
導体素子の組み立て工程ではテープ上で、ダイシングさ
れた半導体素子23を直接ピックアップして被搭載物2
6に接合し、チップ選別工程は省略されることが多い。
したがって、フェイスダウン接合の場合には、ワイヤー
ボンディング等を用いた半導体素子23の組み立てと比
較して、チップ選別や反転等の工程が多い。
First, in a semiconductor element assembling process such as wire bonding, the dicing semiconductor element 23 is directly picked up on the tape to be mounted 2
6 and the chip selection step is often omitted.
Therefore, in the case of face-down bonding, as compared with the assembly of the semiconductor element 23 using wire bonding or the like, there are many steps such as chip selection and reversal.

【0009】また、第2にフェイスダウン接合する場合
は1枚の被搭載物26に複数の半導体素子23をウエハ
ーテストの特性によって選別して搭載することがある。
更に、組み立て後のテストによって、搭載した不良半導
体素子23を取り除き、別の半導体素子23を搭載する
リペア作業を行うが、この場合もウエハーテストの同特
性のものを搭載する。しかしながら、半導体素子23を
トレイ25aに移し替えるため、トレイ25a上に選別
された半導体素子23の個々の特性はウエハー形態の半
導体素子23の個々の座標とウエハーテスト結果を記録
したマッピングデータでは管理できず、トレイ25aに
移し替えた時にシートに記録しておく等、管理が面倒で
ある。
Secondly, in the case of face-down bonding, a plurality of semiconductor elements 23 may be mounted on one mounted object 26 by selecting them according to the characteristics of the wafer test.
Further, a defective semiconductor element 23 mounted is removed by a test after assembling and another semiconductor element 23 is mounted to perform repair work. In this case as well, a wafer having the same characteristics as the wafer test is mounted. However, since the semiconductor elements 23 are transferred to the tray 25a, individual characteristics of the semiconductor elements 23 selected on the tray 25a can be managed by the individual coordinates of the semiconductor elements 23 in a wafer form and the mapping data in which the wafer test results are recorded. Instead, it is troublesome to manage, such as recording on a sheet when the sheet is transferred to the tray 25a.

【0010】更に、第3に従来のフェイスダウン接合装
置は、ピックアップした半導体素子23の能動素子面2
1を搬送途中で下方から認識し、このデータと被搭載物
26の位置データとを照合して搭載位置を決める機構が
必要で構造が複雑になる。
Thirdly, in the conventional face-down bonding apparatus, the active element surface 2 of the semiconductor element 23 picked up is used.
1 is recognized from the lower side during conveyance, and a mechanism for deciding the mounting position by collating this data with the position data of the mounted object 26 is required, which complicates the structure.

【0011】本発明は、従来のダイボンド装置の僅かな
改良で、半導体素子の特性管理が容易なフェイスダウン
接合装置を提供することを目的とする。
It is an object of the present invention to provide a face-down bonding apparatus in which characteristics of semiconductor elements can be easily controlled by slightly improving the conventional die bonding apparatus.

【0012】[0012]

【課題を解決するための手段】本発明の半導体素子接合
装置は、半導体素子の能動素子面を下側にし、前記半導
体素子を搬送する第1搬送手段と、前記半導体素子の能
動素子面のパターンデータを認識する、赤外線カメラ及
び赤外線顕微鏡から成る第1認識手段と、前記半導体素
子を上方から真空吸着し、被搭載物へ搬送する第2搬送
手段と、前記被搭載物表面のパターンデータを認識する
第2認識手段と、前記半導体素子の能動素子面のパター
ンデータと前記被搭載物表面のパターンデータとを照合
する照合手段と、前記照合した結果に基づいて、前記半
導体素子と被搭載物とを接合する接合手段とを有するこ
とを特徴とするものである。
A semiconductor element bonding apparatus according to the present invention comprises a first transfer means for transferring the semiconductor element with the active element surface of the semiconductor element facing downward and a pattern of the active element surface of the semiconductor element. A first recognizing means for recognizing data, which includes an infrared camera and an infrared microscope, a second conveying means for vacuum-sucking the semiconductor element from above and conveying it to a mounting object, and recognizing pattern data on the surface of the mounting object. Second recognizing means, collating means for collating the pattern data of the active element surface of the semiconductor element with the pattern data of the surface of the mounted object, and the semiconductor element and the mounted object based on the collated result. It has a joining means for joining.

【0013】[0013]

【作用】上記本発明を用いることによって、チップ選別
工程と反転工程を省略することができるので、組み立て
工程が簡単になる。また、ウエハーテスト結果のマッピ
ングデータに基づいて接合できるため、半導体素子を特
性選別して実装及びリペアすることが容易になる。更
に、ダイシングした状態でテープに貼り付けたままで半
導体素子をフェイスダウン接合装置に供給し、ダイレク
トに搭載でき、フェイスダウン接合装置の機構が簡略化
される。
By using the present invention, the chip selecting step and the reversing step can be omitted, so that the assembling step is simplified. Further, since the bonding can be performed based on the mapping data of the wafer test result, it becomes easy to select the characteristics of the semiconductor element and mount and repair it. Further, the semiconductor element can be supplied to the face-down joining apparatus while being attached to the tape in a dicing state and directly mounted, and the mechanism of the face-down joining apparatus can be simplified.

【0014】[0014]

【実施例】以下、実施例に基づいて、本発明を詳細に説
明する。図1は本発明の一実施例のフェイスダウン接合
装置の構成図、図2は本発明の一実施例のフェイスダウ
ン接合装置の外観図、図3(a)は表面用のマッピング
図、図3(b)は裏面用に座標変換したマッピング図で
ある。図1において、1は半導体素子、2は能動素子
面、3は赤外線顕微鏡、4は赤外線カメラであり、赤外
線はシリコンを透過しメタル成分には反射するため、赤
外線顕微鏡3及び赤外線カメラ4を用いて、ダイシング
されたウエハーの能動素子面2のメタル配線部や電極パ
ッド等のパターン認識を行う。また、5は能動素子面2
を傷つけないように先端が球状又は平面状になってお
り、下方から半導体素子1を押し上げる押し上げ針、6
は半導体素子1を上方から真空吸着するコレット、7は
半導体素子1を搭載する被搭載物、8は上方から被搭載
物7のパターンデータを認識するためのカメラを示す。
また、図2において、9はウエハーマガジン、10は被
搭載物用マガジン、11はボールネジをモータで駆動さ
せ、2本のガイドポストで直線案内し上下に動かし、ウ
エハーマガジン9の各溝で停止するウエハーローダ、1
2は直線案内されたアームの中央部にチャックツメ13
が設けられているウエハー搬送ユニット、14はピック
アップする半導体素子の位置決めを行う、X−Y−θの
3軸テーブルであるウエハーテーブル、15はX−Y−
Zの3軸テーブルで構成され、先端に吸着機能を有する
コレット6が設けられたボンディングヘッドを示す。
EXAMPLES The present invention will be described in detail below based on examples. FIG. 1 is a configuration diagram of a face-down joining device according to an embodiment of the present invention, FIG. 2 is an external view of a face-down joining device according to an embodiment of the present invention, FIG. 3A is a mapping diagram for a surface, and FIG. (B) is a mapping diagram in which coordinates are converted for the back surface. In FIG. 1, reference numeral 1 is a semiconductor element, 2 is an active element surface, 3 is an infrared microscope, 4 is an infrared camera. Since infrared rays pass through silicon and are reflected by metal components, the infrared microscope 3 and the infrared camera 4 are used. Then, the pattern of the metal wiring portion, the electrode pad, etc. of the active element surface 2 of the diced wafer is recognized. Further, 5 is an active element surface 2
The tip has a spherical shape or a flat shape so as not to damage it, and pushes up the semiconductor element 1 from below.
Is a collet for vacuum-sucking the semiconductor element 1 from above, 7 is a mounted object on which the semiconductor element 1 is mounted, and 8 is a camera for recognizing pattern data of the mounted object 7 from above.
In FIG. 2, 9 is a wafer magazine, 10 is a mounted magazine, 11 is a ball screw driven by a motor, and is linearly guided by two guide posts to move up and down, and stopped at each groove of the wafer magazine 9. Wafer loader, 1
2 is a chuck claw 13 at the center of the linearly guided arm.
, A wafer transfer unit 14 is provided, 14 is a wafer table which is a three-axis table of XY-θ for positioning a semiconductor element to be picked up, and 15 is an XY-
1 shows a bonding head which is composed of a Z triaxial table and has a collet 6 having a suction function at its tip.

【0015】次に、本発明の一実施例のフェイスダウン
接合装置を用いたフェイスダウン接合工程を説明する。
Next, a face-down joining process using the face-down joining apparatus according to one embodiment of the present invention will be described.

【0016】まず、ウエハーマガジン9に収納された、
ダイシング済みで能動素子面2を下にしてテープに貼り
付け、専用リングに保持されたウエハー(図示せず。)
はウエハーローダ11で高さの位置決めが行われ、チャ
ックツメ13で専用リングをつかみ、1枚ずつ引き出
し、レールに沿って搬送した後、専用リングの後部を押
し込み、ウエハーテーブル14に供給される。
First, stored in the wafer magazine 9,
A wafer (not shown) that has been diced and is attached to a tape with the active element surface 2 facing down and held in a dedicated ring.
The wafer loader 11 performs height positioning, the chuck claws 13 grab the dedicated rings, pull them one by one, carry them along the rails, and then push in the rear part of the dedicated rings to supply them to the wafer table 14.

【0017】次に、赤外線顕微鏡3及び赤外線カメラ4
を用いて半導体素子1の能動素子面2のアルミ配線や電
極部等のパターンを上側から認識し、このデータに基づ
いてウエハーテーブル14を位置決めし、半導体素子1
を下方から押し上げ針5を用いて突き上げながら、コレ
ット6で半導体素子1を上方から真空吸着する。
Next, the infrared microscope 3 and the infrared camera 4
The pattern of the aluminum wiring or the electrode portion of the active element surface 2 of the semiconductor element 1 is recognized from the upper side by using, and the wafer table 14 is positioned based on this data.
While pushing up from below using the push-up needle 5, the semiconductor element 1 is vacuum-sucked from above by the collet 6.

【0018】次に、実装前の被搭載物7に対して、ロー
ダ(図示せず。)で高さの位置決めを行い、例えば、上
下駆動機構付の専用ピンを被搭載物7に設けられた穴
(図示せず。)に挿入し、1軸テーブルによって、ガイ
ドレールに沿って搭載位置まで搬送し、カメラ8で被搭
載物7の搭載部分の詳細パターンを認識し、該パターン
データと赤外線顕微鏡3及び赤外線カメラ4で認識した
半導体素子1の能動素子面2のパターンデータとを照合
し、ボンディングヘッド15で所定の位置にフェイスダ
ウン接合を行う。
Next, the loader (not shown) is used to perform height positioning with respect to the mounted object 7 before mounting, and for example, a dedicated pin with a vertical drive mechanism is provided on the mounted object 7. It is inserted into a hole (not shown) and conveyed by a uniaxial table along the guide rail to the mounting position, and the camera 8 recognizes the detailed pattern of the mounted portion of the mounted object 7, and the pattern data and the infrared microscope. 3 and the pattern data of the active element surface 2 of the semiconductor element 1 recognized by the infrared camera 4 are collated, and the bonding head 15 performs face-down bonding at a predetermined position.

【0019】その後、半導体素子1が搭載された被搭載
物7はガイドレールに沿って更に搬送されアンローダの
被搭載物マガジン10bに収納される。
Thereafter, the mounted object 7 on which the semiconductor element 1 is mounted is further transported along the guide rails and stored in the mounted object magazine 10b of the unloader.

【0020】また、ピックアップする半導体素子1の良
品/不良品の判別は、ウエハーテスト時に不良半導体素
子に塗布するインクにメタル成分を含有することによっ
て、赤外線顕微鏡3及び赤外線カメラ4によって、良品
/不良品を認識し、良品のみを選別して搭載することが
できる。
In order to determine whether the semiconductor device 1 to be picked up is a good product or a defective product, the infrared microscope 3 and the infrared camera 4 determine whether the semiconductor device 1 is a good product or a defective product by including a metal component in the ink applied to the defective semiconductor device during the wafer test. It is possible to recognize good products and select and install only good products.

【0021】更に、半導体素子の特性を判断して搭載す
る場合には、図3に示すように、ウエハーテストの特性
データを示す、マッピングデータ(図3(a))を例え
ばオリフラを基準として列データ(X座標)を反転した
裏面用のマッピングデータ(図3(b))に変換し、こ
のデータに基づいて指定する特性データの半導体素子1
を選別して搭載することができる。
Further, when the characteristics of the semiconductor element are judged and mounted, as shown in FIG. 3, the mapping data (FIG. 3A) showing the characteristic data of the wafer test is arranged on the basis of, for example, the orientation flat. The data (X coordinate) is converted into the reverse mapping data (FIG. 3B), and the semiconductor device 1 having the characteristic data specified based on this data is converted.
Can be selected and mounted.

【0022】なお、上述の実施例の被搭載物は回路基板
の他に、ガラス、フィルム、リードフレーム等の半導体
素子1の能動素子面2と接合する全ての材料で適用可能
であり、その供給方法や搬送方法は被搭載物によって異
なる。
In addition to the circuit board, the mounted object of the above-described embodiment is applicable to all materials such as glass, film, and lead frame that are bonded to the active element surface 2 of the semiconductor element 1, and supply thereof. The method and transfer method differ depending on the mounted object.

【0023】[0023]

【発明の効果】以上、詳細に説明した様に、本発明を用
いることによって、従来複雑な接合装置を用いて行って
いたフェイスダウン接合が既存のダイボンダに赤外線顕
微鏡及び赤外線カメラを用いることによって簡単にでき
る。また、選別工程や反転工程を省略することができ、
ウエハー状態で半導体素子を供給し、マッピングデータ
に基づいて接合するため、半導体素子管理が容易で、リ
ペア作業も簡単に行うことができる。更に半導体素子の
能動素子面をテープに貼り付けて供給し、裏面をコレッ
トで真空吸着するため、能動素子面の汚染や傷がなく、
品質不良がない。
As described above in detail, by using the present invention, the face-down joining which has been conventionally performed by using the complicated joining apparatus can be easily performed by using the infrared microscope and the infrared camera in the existing die bonder. You can Also, the sorting process and the reversing process can be omitted,
Since semiconductor elements are supplied in a wafer state and bonded based on mapping data, semiconductor element management is easy and repair work can be performed easily. Furthermore, the active element surface of the semiconductor element is attached to the tape and supplied, and the back surface is vacuum-adsorbed by the collet, so there is no contamination or scratch on the active element surface.
There is no quality defect.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例のフェイスダウン接合装置の
構成図である。
FIG. 1 is a configuration diagram of a face-down joining device according to an embodiment of the present invention.

【図2】同フェイスダウン接合装置の外観図である。FIG. 2 is an external view of the face-down joining device.

【図3】(a)は表面用マッピング図であり、(b)は
裏面用に変換したマッピング図である。
FIG. 3A is a front surface mapping diagram, and FIG. 3B is a back surface mapping diagram.

【図4】従来のフェイスダウン接合装置の構成図であ
る。
FIG. 4 is a configuration diagram of a conventional face-down joining device.

【符号の説明】 1 半導体素子 2 能動素子面 3 赤外線顕微鏡 4 赤外線カメラ 5 押し上げ針 6 コレット 7 被搭載物 8 カメラ 9 ウエハーマガジン 10 被搭載物マガジン 11 ウエハーローダ 12 ウエハー搬送ユニット 13 チャックツメ 14 ウエハーテーブル 15 ボンディングヘッド[Explanation of symbols] 1 semiconductor element 2 active element surface 3 infrared microscope 4 infrared camera 5 push-up needle 6 collet 7 mounted object 8 camera 9 wafer magazine 10 mounted object magazine 11 wafer loader 12 wafer transfer unit 13 chuck claw 14 wafer table 15 Bonding head

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子の能動素子面を下側にし、前
記半導体素子を搬送する第1搬送手段と、 前記半導体素子の能動素子面のパターンデータを認識す
る、赤外線カメラ及び赤外線顕微鏡から成る第1認識手
段と、 前記半導体素子を上方から真空吸着し、被搭載物へ搬送
する第2搬送手段と、 前記被搭載物表面のパターンデータを認識する第2認識
手段と、 前記半導体素子の能動素子面のパターンデータと前記被
搭載物表面のパターンデータとを照合する照合手段と、 前記照合した結果に基づいて、前記半導体素子と被搭載
物とを接合する接合手段とを有することを特徴とする半
導体素子接合装置。
1. A first transport means for transporting the semiconductor element with the active element surface of the semiconductor element facing downward, and an infrared camera and an infrared microscope for recognizing pattern data of the active element surface of the semiconductor element. 1 recognition means, second transfer means for vacuum-sucking the semiconductor element from above and transferring it to the mounted object, second recognition means for recognizing pattern data on the surface of the mounted object, and active element of the semiconductor element It is characterized by having a collating means for collating the pattern data of the surface and the pattern data of the surface of the mounted object, and a joining means for joining the semiconductor element and the mounted object based on the collated result. Semiconductor element bonding equipment.
JP2787093A 1993-02-17 1993-02-17 Semiconductor device bonding equipment Expired - Fee Related JP2849519B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2787093A JP2849519B2 (en) 1993-02-17 1993-02-17 Semiconductor device bonding equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2787093A JP2849519B2 (en) 1993-02-17 1993-02-17 Semiconductor device bonding equipment

Publications (2)

Publication Number Publication Date
JPH06244245A true JPH06244245A (en) 1994-09-02
JP2849519B2 JP2849519B2 (en) 1999-01-20

Family

ID=12232938

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2787093A Expired - Fee Related JP2849519B2 (en) 1993-02-17 1993-02-17 Semiconductor device bonding equipment

Country Status (1)

Country Link
JP (1) JP2849519B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6869819B2 (en) 2002-05-28 2005-03-22 Fujitsu Limited Recognition method of a mark provided on a semiconductor device
KR100709006B1 (en) * 2001-04-13 2007-04-18 앰코 테크놀로지 코리아 주식회사 Method for manufacturing semiconductor package
JP2019145692A (en) * 2018-02-22 2019-08-29 東レエンジニアリング株式会社 Mounting device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100709006B1 (en) * 2001-04-13 2007-04-18 앰코 테크놀로지 코리아 주식회사 Method for manufacturing semiconductor package
US6869819B2 (en) 2002-05-28 2005-03-22 Fujitsu Limited Recognition method of a mark provided on a semiconductor device
JP2019145692A (en) * 2018-02-22 2019-08-29 東レエンジニアリング株式会社 Mounting device

Also Published As

Publication number Publication date
JP2849519B2 (en) 1999-01-20

Similar Documents

Publication Publication Date Title
US7568606B2 (en) Electronic device handler for a bonding apparatus
TWI552250B (en) Collet cleaning method and the use of its grain adapter
CN108346585B (en) Semiconductor manufacturing apparatus and method for manufacturing semiconductor device
JP2000012568A (en) Die bonder
JP4233705B2 (en) Die bonding method and die bonding equipment
KR20200034600A (en) Semiconductor manufacturing apparatus, push-up jig and method for manufacturing semiconductor device
KR20190042419A (en) Semiconductor manufacturing device and manufacturing method of semiconductor device
KR100395981B1 (en) Die bonding method and apparatus
KR20040071590A (en) Die bonding method and apparatus
KR20080041471A (en) A die bonder
US4913335A (en) Method and apparatus for die bonding
TW201742179A (en) Bonding device and bonding method
JPH06244245A (en) Semiconductor device bonding device
KR100312743B1 (en) Semiconductor die bonder position recognizing and testing apparatus and method thereof
JP2000012571A (en) Method for positioning in die bonder of semiconductor chip
US6787374B2 (en) Semiconductor device manufacturing method and semiconductor device sorting system to be used with the same
TWI645496B (en) Substrate supply unit and bonding device
JP2001250834A (en) Method of manufacturing semiconductor device
JP4800076B2 (en) Component mounting method and apparatus
JP2746989B2 (en) Chip positioning method and device, inner lead bonding apparatus, and inner lead bonding method
JP7328848B2 (en) Die bonding apparatus and semiconductor device manufacturing method
WO2011007398A1 (en) Pickup apparatus
JPWO2005013351A1 (en) Work recognition method and die bonder in die bonder
JP2002164361A (en) Semiconductor manufacturing apparatus and method of manufacturing the same
JPH0575299A (en) Chip mounting device

Legal Events

Date Code Title Description
FPAY Renewal fee payment (prs date is renewal date of database)

Year of fee payment: 10

Free format text: PAYMENT UNTIL: 20081106

LAPS Cancellation because of no payment of annual fees