JP2003169464A - Controller for voltage-driven semiconductor devices connected in series - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent an overvoltage from being applied to specific one of a plurality of voltage-driven semiconductor devices connected in series by equalizing the timing of switching in turning on and off the devices, monitoring the overvoltage in the individual devices after turn-off, and turning on the device again. <P>SOLUTION: The gate wire or emitter wire of the voltage-driven semiconductor device at each stage is magnetically coupled with the gate wire or emitter wire of the device at the next stage. The overvoltage in the individual devices after turn-off is monitored through gate drive circuits. The device to which the overvoltage is applied is subjected to gate voltage control, and the device is turned on again in an active region. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control device for overvoltage suppression and switching timing when a plurality of voltage-driven semiconductor elements connected in series are simultaneously turned on / off.

[0002]

2. Description of the Related Art In a power converter having semiconductor switching elements connected in series, many problems and solutions are known for turning on / off each switching element at the same time. In particular, a problem in the case where voltage-driven semiconductor switching elements are connected in series will be described by taking one phase of an inverter circuit in which two semiconductor switching elements are connected in series in each arm as shown in FIG. .

In FIG. 11, Q1 to Q4 are IGBTs (insulated gate bipolar transistors) as voltage drive type semiconductor elements, and a circuit consisting of a resistor R, a capacitor C and a diode D connected in parallel to each other is a snubber circuit. Is. Further, GDU1 to GDU4 are gate drive circuits, and the power supply voltage is Ed.

In this inverter circuit, the upper arm,
That is, when Q1 and Q2 shift from on-operation to off-operation, behavior when Q1 turns off at a timing earlier than Q2 (mode 1: switching transient state) and Q1
12 (a) regarding the behavior after the turn-off when the current after the turn-off, which is referred to as the tail current of (1), is smaller than Q2 (Mode 2: switching transient state to steady state).
Shows an operation waveform when there is no snubber circuit, and FIG. 12B shows an operation waveform when there is a snubber circuit.

That is, as shown in FIG.
Starts the turn-off operation first, and from this start time Δt
Since Q2 is still in the ON state during the period of, the element voltage VCE (Q1) of Q1 rises, voltage imbalance occurs, and the difference in tail current becomes the charging current, and the element of Q1 with less tail current The voltage VCE (Q1) is further increased. However, as shown in FIG. 12B, when the snubber circuit is connected, the increase rate dv / dt of the element voltage and the voltage imbalance can be reduced as compared with the case where the snubber circuit is not connected. These reductions depend on the capacitance of C of the snubber circuit, and the larger the capacitance, the greater the reduction effect.

[0006]

As described above, by connecting the snubber circuit in parallel with the element, the dv / dt of the element voltage is increased.
Although it is possible to reduce the unbalance, it is attempted to allow the switching time difference and the tail current difference of the elements to be larger, which causes a problem that the circuit becomes larger and the circuit loss increases.

Therefore, an object of the present invention is to unbalance the element voltage distribution in all the periods from the switching transient state of the elements connected in series to the steady state without inviting an increase in circuit size and an increase in circuit loss. To prevent the application of overvoltage to the element and the destruction of the element due to the overvoltage.

[0008]

In order to solve the above-mentioned problems, according to the present invention, a plurality of voltage-driven semiconductor elements connected in series and for turning on / off these voltage-driven semiconductor elements are provided. In a semiconductor switch circuit consisting of a gate drive circuit that supplies a gate signal to the gate terminal of the voltage-driven semiconductor element, in order to match the current values flowing in the gate lines of the voltage-driven semiconductor elements of each stage, The gate line and the gate line of the next stage are magnetically coupled, and the gate lines of each stage except the first stage magnetically couple the gate line of the previous stage and the gate line of the next stage, and are applied to these voltage-driven semiconductor elements. When the voltage becomes an overvoltage, the gate voltage of the voltage-driven semiconductor element is controlled in order to suppress the application of the overvoltage, so that the gate currents are matched and the switching current is controlled. While suppressing the variation of the timing, (the invention according to claim 1) to suppress the unbalance of the voltage distribution of elements of each stage are.

Further, in the semiconductor switch circuit according to claim 1, by magnetically coupling the emitter lines connecting the gate drive circuit and the emitter terminals of the voltage drive type semiconductor elements, or by magnetically coupling the gate line and the emitter line. The same effect can be exhibited (the invention according to claim 2).

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION A first embodiment of the present invention will be described by taking as an example a circuit constituted by two IGBTs connected in series.

FIG. 1 shows an example of a circuit configuration using the semiconductor switch circuit of the present invention. This circuit corresponds to one phase of an inverter circuit as in FIG.

That is, in the circuit configuration shown in FIG.
The snubber circuit is omitted from the circuit configuration shown in FIG. 1, and the gate drive circuits GDU1 to GDU4 are replaced with GDU.
1a to GDU4a, and voltage dividing resistors Rb1 to Rb
b4 and magnetic circuits MC1 and MC2 are added.

The feature of the circuit configuration of FIG. 1 is that the gate line of the upper arm is magnetically coupled by a magnetic circuit MC1.
Similarly, the gate line of the lower arm is magnetically coupled by the magnetic circuit MC2. When magnetically coupling, each gate line is wound around the same magnetic substance as shown in FIG. 2, for example. Thereby, for example, the gate current Ig (Q
When 1) flows, a magnetic flux of Φ1 is generated in the magnetic circuit, which crosses the gate line of GDU2a. Similarly, Ig (Q2)
Flows, a magnetic flux of Φ2 is generated, which crosses the gate line of GDU1a. As a result, each gate line is magnetically coupled. At this time, by setting the numbers of turns N1 and N2 around the magnetic body to be the same, when Ig (Q1) = Ig (Q2), |
Φ1 | = | Φ2 | so that Ig (Q1) and Ig
When (Q2) has opposite polarities, Φ1 and Φ2 have opposite polarities.

FIG. 3 shows the gate drive circuit GD shown in FIG.
It is a detailed circuit configuration example of each U1a ~ GDU4a,
As shown in the figure, an overvoltage determination circuit OV and a gate voltage control circuit RO are added to each of the conventional GDU1 to GDU4. The overvoltage determination circuit OV determines whether or not the voltage detected by the voltage dividing resistor Rb shown in FIG. 1 is an overvoltage, and the gate voltage control circuit RO is
An IGBT that is determined to be an overvoltage when the IGBT is turned off
To turn it on again.

The operation of the inverter circuit shown in FIG. 1 when Q and Q2 are turned off will be described below with reference to FIGS.

FIG. 4A and FIG. 4B show operating waveforms during the above-mentioned mode 1 (switching transient state). First, as shown in FIG. 4A, when the turn-off timings of Q1 and Q2 are the same. , The gate (G) -emitter (E) voltages VGE (Q1) and VGE (Q2) are substantially equal to each other. That is, the IG that constitutes Q1 and Q2
Between G and E of BT can be regarded equivalently as the capacitor Cies as shown in FIG. 5, so that as shown in FIG. 4A, Ig (Q1) and Ig (Q2) have the same waveform transient. Purposely C
A discharge current flows to ies. At this time, the magnetic circuit MC1
Since the polarities of Ig (Q1) and Ig (Q2) flowing through are opposite, and therefore Φ1 and Φ2 have opposite polarities at the same level, the magnetic fluxes generated in MC1 cancel each other out to “0”.
Becomes As a result, the respective gate lines are not magnetically coupled, and Ig (Q1) and Ig (Q2) are different from each Cies.
Continues to flow as discharge current from.

Next, as shown in FIG. 4B, Q1 and Q2
If the turn-off timing of is unbalanced,
For example, when Q1 is turned off first, that is, Ig
When (Q1) flows out before Ig (Q2),
Since Φ1 ≠ Φ2, | Φ1-Φ in the magnetic circuit MC1
A magnetic flux of 2 | is generated, and each gate line is magnetically coupled by this magnetic flux. At this time, inductance components L1 and L2 are generated in each gate line, and these are | Φ
There is a characteristic proportional to 1-Φ2 |. That is, Ig (Q
The larger the imbalance between 1) and Ig (Q2), the more L1
L2 also becomes large. Further, as L1 and L2 increase, the impedance of the gate line increases, so that Ig (Q1)
And Ig (Q2) becomes difficult to flow. As a result of this operation, as shown in FIG. 6, the impedance of the gate line is automatically changed according to the unbalanced amount of Ig (Q1) and Ig (Q2), and Ig (Q1) is decreased, Ig (Q2) Acts in an increasing direction, and can be operated so that Ig (Q1) and Ig (Q2) match.

As described above, by providing the magnetic circuit MC1, it is possible to suppress variations in turn-off timing of Q1 and Q2 without delay. This also works effectively for suppressing variation in the turn-on timing.

FIG. 7 shows operation waveforms after turn-off when the current after turn-off, which is called the tail current of Q1, is smaller than Q2 during the period of mode 2 (switching transient state to steady state) described above. , At this time, Q1
Collector-emitter voltage VCE (Q1) starts rising and is detected via the voltage dividing resistor Rb1.
Reaches the overvoltage detection level, the overvoltage determination circuit OV of the gate drive circuit GDU1a having the circuit configuration shown in FIG. As a result, the normal on / off drive circuit shown in FIG. 3 stops its operation (specifically, TR2
Is turned on → off), and the gate voltage control circuit RO of the same circuit as TR1 and Rg (on) operates to set the gate-emitter voltage VGE (Q1) of Q1 to a voltage near the threshold value. Turn Q1 back on in the active region. Q1
Is turned on, the collector-emitter voltage VCE (Q
It is possible to prevent 1) from dropping and applying an overvoltage to Q1.

Further, FIG. 8 showing the circuit configuration of the Q1 and Q2 parts shown in FIG. 1 has the gate drive circuit GDU as described above.
The path of the current Ig (Q1) of the gate line when the gate voltage control circuit RO of 1a operates is shown. As is apparent from this figure, the Ig (Q1) at this time does not flow in the path of the magnetic circuit MC1 and only the gate voltage of Q1 to which the overvoltage is applied can be set to a predetermined value. Has become.

FIG. 9 shows a second embodiment of the present invention and shows a circuit configuration when n elements are connected in series. As is apparent from the figure, the gate lines of Q1 and Q2 are magnetically coupled by the magnetic circuit MC1 to match the gate current values, and in order to match the gate currents of Q3 with these current values as a reference, By magnetically coupling the gate lines subordinately by magnetically coupling the gate lines with the magnetic circuit MC2, it becomes possible to suppress the switching imbalance of all the elements in an instant.
Further, since it is only necessary to attach one magnetic circuit to two gate lines, the wiring can be simplified.

Further, as shown in FIG. 1, since the gate current flows through a round route, the current values flowing through the gate line and the emitter line are the same. Therefore, even if the gate line and the emitter line or the emitter line and the emitter line are magnetically coupled as shown in FIG. 10 as the third embodiment of the present invention,
The same principle as described with reference to FIG. 1 effectively operates to suppress variation in switching timing.

Further, in the circuit configurations of FIG. 9 and FIG. 10, in the above-mentioned mode 2, the current of the gate line when the gate voltage control circuit RO operates does not flow in the path of each magnetic circuit, It is possible to turn on only the element to which the overvoltage is applied.

[0024]

According to the present invention, when a plurality of voltage-driven semiconductor elements are connected in series, the gate lines of the respective elements are magnetically coupled and the gate current values are made equal to each other, thereby suppressing the switching time difference, and When an imbalance occurs in the voltage applied to each element, the gate voltage control of the voltage-driven semiconductor element to which the overvoltage is applied prevents the overvoltage from being applied to the voltage-driven semiconductor element and the element breakdown due to the overvoltage. be able to.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a wiring diagram for explaining the principle of FIG.

FIG. 3 is a partial detailed circuit configuration diagram of FIG.

FIG. 4 is a waveform diagram illustrating the operation of FIG.

5 is a circuit configuration diagram for explaining the operation of FIG.

FIG. 6 is a circuit configuration diagram for explaining the operation of FIG.

FIG. 7 is a waveform diagram for explaining the operation of FIG.

FIG. 8 is a circuit configuration diagram for explaining the operation of FIG.

FIG. 9 is a circuit configuration diagram showing a second embodiment of the present invention.

FIG. 10 is a circuit configuration diagram showing a third embodiment of the present invention.

FIG. 11 is a circuit configuration diagram showing a conventional example.

FIG. 12 is a waveform diagram illustrating the operation of FIG.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Kiyoaki Sasakawa             1-1 Tanabe Nitta, Kawasaki-ku, Kawasaki-shi, Kanagawa             Within Fuji Electric Co., Ltd. F-term (reference) 5H740 BA11 BB01 KK01 KK03 MM01                       MM05                 5J050 AA34 BB24 CC01 DD00 EE03                       EE18 EE22 FF22                 5J055 AX32 BX16 CX19 DX09 EX07                       EY01 EY07 EY10 EY12 EZ00                       EZ12 FX03 GX01 GX02 GX05                       GX08

Claims (2)

[Claims] 1. A plurality of voltage-driven semiconductor elements connected in series, and a gate drive for supplying a gate signal to a gate terminal of the voltage-driven semiconductor elements for turning on / off these voltage-driven semiconductor elements. In the semiconductor switch circuit including the circuit, in order to match the current value flowing in the gate line of the voltage-driven semiconductor element in each stage, the gate line of the first stage and the gate line of the next stage are magnetically coupled to each other except the first stage. The gate line of the stage magnetically couples the gate line of the previous stage and the gate line of the next stage, and when the voltage applied to these voltage-driven semiconductor elements becomes an overvoltage, in order to suppress the overvoltage application, A controller for controlling voltage-driven semiconductor elements connected in series, which controls the gate voltage of the voltage-driven semiconductor elements. 2. The semiconductor switch circuit according to claim 1, wherein emitter lines connecting the gate drive circuit and the emitter terminals of the voltage-driven semiconductor element are magnetically coupled to each other or the gate line and the emitter line are magnetically coupled to each other. 2. A control device for voltage-driven semiconductor elements connected in series, which is characterized in that.