JP2005167535A - Semiconductor switching circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the size and loss in a suppression circuit for suppressing each element voltage unbalance in switching, in a semiconductor switching circuit comprising connection of a plurality of voltage drive type semiconductor devices (semiconductor devices) in series. <P>SOLUTION: A transition voltage balance circuit B1 is connected to the semiconductor devices Q1, Q2 with the shortest distance, and a steady voltage balance circuit B2 is connected to a position that is apart form the semiconductor devices Q1, Q2 and is structurally optimum. In this case, the reason why the distance is made shortest is that it is required that the capacity of a capacitor in the circuit B1 should be increased further, since the time constant of voltage unbalance is very small in a mode, immediately after switching in transition and hence parasitic inductance becomes large, when wiring length is lengthened. Voltage balance results in terms of DC in the unbalance mode of a leakage current, which is not related to the inductance, so that connection is made to an optimum arbitrary position. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a circuit system for reducing variations in voltage sharing among elements when a plurality of voltage-driven semiconductor elements connected in series (hereinafter also simply referred to as elements) are simultaneously turned on and off.

FIG. 6 shows a conventional example disclosed in Patent Document 1 and Non-Patent Document 1, for example.
In the figure, Q1 to Q4 are IGBTs (insulated gate bipolar transistors) as voltage-driven semiconductor elements, and Q1 and Q2 and Q3 and Q4 are connected in series. A circuit including a resistor R, a capacitor C, and a diode D connected in parallel to each element is an example of a transient voltage balance circuit, and the capacitor operates so as to suppress the element voltage imbalance. Rd1 to Rd4 are steady voltage balance circuits, GDU1 to GDU4 are gate drive circuits, and Ed is a DC power supply voltage.

In the above circuit, when the upper arm, that is, Q1 and Q2 perform the turn-off operation, the operation waveform when each voltage balance circuit is not present when Q1 is turned off earlier than Q2 is shown in FIG. FIG. 7B shows an operation waveform when there is a voltage balance circuit.
In these waveforms, mode 1 is a period immediately after switching, which is a very fast unbalance mode, mode 2 is a tail current flow period, unbalance mode is slower than mode 1, and mode 3 is leakage current in the steady state of the element. Shows the unbalanced mode.

  As shown in the waveform of the mode 1 period, Q1 starts the turn-off operation first, and since Q2 is still in the on state during the period Δt from the start time, only the element voltage VCE (Q1) of Q1 rises. Voltage imbalance occurs. However, when the transient voltage balance circuit is connected, the increase rate dv / dt of the element voltage can be reduced as compared with the case where the transient voltage balance circuit is not connected, so that the voltage imbalance amount is suppressed. This dv / dt depends on the capacity of C of the transient voltage balance circuit, and the effect of reducing the transient voltage imbalance can be increased as this is increased.

In addition, if the tail current unbalance of the element is large as in the waveform of the mode 2 period, the element voltage of Q1 having a small tail current is increased, but the capacitance of C of the transient voltage balance circuit is increased as described above. Thus, this voltage imbalance amount can be suppressed. Since the voltage unbalance in mode 3 is unbalanced by the leakage current of the element, for example, by connecting resistors rd1 to Rd4 as shown in FIG. 6, the apparent leakage current is balanced and the element voltage is balanced. it can.
Japanese Patent Laid-Open No. 04-125071 (page 2-3, FIG. 1) 1999 IEEJ Industrial Application Division Conference Paper “Switching Test with Flat IGBT Series Connection”

As described above, the increase rate dv / dt of the element voltage is reduced by connecting two kinds of voltage balance circuits in parallel with the element, and as a result, the element voltage is unbalanced due to the switching difference or the element due to the tail current difference. The voltage imbalance can be suppressed, and the effect of suppressing the imbalance can be further increased by increasing the capacitor capacity of the circuit.
However, when the voltage imbalance of mode 2 is superimposed on the voltage imbalance of mode 1, a capacitor with a large capacity is required to suppress this, and the power consumption at the resistor R increases accordingly. Therefore, there is a problem that the transient voltage balance circuit becomes large.
Therefore, the problem to be solved by the present invention is to reduce the size and the loss of the transient voltage balance circuit while suppressing the device voltage imbalance during switching.

  In order to solve such a problem, according to the first aspect of the present invention, a plurality of voltage-driven semiconductor elements (semiconductor elements) connected in series and a control signal is supplied to the gate terminal to turn on and off the semiconductor elements. A gate drive circuit, a transient voltage balance circuit that suppresses voltage imbalance that occurs during the transient operation of each semiconductor element, and a steady voltage balance circuit that suppresses voltage imbalance that occurs during the steady operation of each semiconductor element, The transient voltage balance circuit is connected to each semiconductor element by the shortest wiring, and the steady voltage balance circuit is arranged at an arbitrary position away from each semiconductor element.

  In the invention of claim 1, the transient voltage balance circuit can suppress voltage imbalance caused by variations in tail current of the semiconductor element (invention of claim 2), or the claim. In the invention of 1 or 2, the gate lines connecting the output terminal of the gate drive circuit and the gate terminal of the semiconductor element can be magnetically coupled to each other (invention of claim 3). In this invention of Claim 3, the said transient voltage balance circuit can be arrange | positioned in arbitrary positions from the said semiconductor element by matching with wiring inductance (Invention of Claim 4).

  According to the present invention, when a plurality of semiconductor elements are connected in series, a semiconductor element is connected to the entire region by connecting a core that magnetically couples each gate line, a transient voltage balance circuit, and a steady voltage balance circuit. Can be balanced. Also, with this circuit configuration, the transient voltage balance circuit and the steady voltage balance circuit can be connected to any position as long as they are equivalently connected in parallel with the semiconductor element, and the structure can be simplified. .

FIG. 1 is a block diagram showing a first embodiment of the present invention.
As shown in the figure, this is a semiconductor switch circuit in which two IGBTs Q1 and Q2 are connected in series, and GDU1 and GDU2 are gate drive circuits for Q1 and Q2, respectively. Here, the transient voltage balance circuit B1 is disposed as short as possible between the elements so that the wiring inductance is minimized, and the steady voltage balance circuit B2 is disposed at an arbitrary position regardless of the wiring length. This is because the time constant of voltage imbalance in transition, especially in mode 1, is very small. Therefore, if the wiring is long, the parasitic inductance increases, and if the capacitance of the transient voltage balance circuit B1 is not increased further, the imbalance suppression effect can be obtained. This is because it becomes smaller. Further, in mode 3, since it is balanced in direct current and the inductance is not particularly affected, it is installed at an arbitrary position structurally.

FIG. 2 is a block diagram showing a second embodiment of the present invention.
The core Tc, the transient voltage balance circuit B1, and the steady voltage balance circuit B2 are circuits for suppressing the device voltage unbalance in the mode 1, mode 2, and mode 3 described with reference to FIG. Also in this circuit, the steady voltage balance circuit B2 can be arranged at an arbitrary position as in the case of FIG. Input signal 1 and input signal 2 are on / off signals of each IGBT from the control circuit, and are input to the gate drive circuits GDU 1 and 2.

The operation at turn-off will be described with reference to FIG.
Assume that Q1 is turned off earlier than Q2 due to the transmission time variation of the gate drive circuit in mode 1, that is, in the turn-off transient operation. Here, when the core Tc, the transient voltage balance circuit B1, and the steady voltage balance circuit B2 are not connected, the element voltage VCE (Q1) of Q1 is equal to the element voltage VCE (Q2) of Q2, as indicated by a broken line in FIG. ) Begins to rise before these voltages become unbalanced. In mode 2, it is assumed that the tail current of Q2 is larger than Q1 in the turn-off tail current region.

An equivalent circuit at this time is shown in FIG.
In the figure, Ic (Q1) and Ic (Q2) indicate tail currents of Q1 and Q2, and Coes1 and Coes2 indicate output capacities of Q1 and Q2. In the circuit of FIG. 4, when Ic (Q1) <Ic (Q2), the difference current flows to Coes1, so that VCE (Q1) rises above VCE (Q2) and is superimposed on the variation in mode 1. As a result, under the above circuit conditions, VCE (Q1) and VCE (Q2) may be greatly unbalanced and VCE (Q1) may be overvoltage.

  Next, when the core Tc, the transient voltage balance circuit B1, and the steady voltage balance circuit B2 are connected, as shown by a solid line in FIG. 3, first, the gate currents coincide with each other by the core Tc, and Q1 and Q2 Since the switching timings coincide, variation in element voltage is suppressed. Regarding the balancing effect of the element voltage by the core, refer to Japanese Patent Application Laid-Open No. 2002-204578 if necessary. In the mode 2 period, the voltage imbalance due to the tail current can be suppressed by the transient voltage balance circuit B1 of each IGBT. At this time, the time constants Cs and Rs are set to be smaller than the time constant τ when the voltage is unbalanced so that the operation of the transient voltage balance circuit B1 follows the voltage unbalance in mode 2.

Further, Rs is set to a condition value that does not generate vibration so that vibration does not occur and the effective current of Cs and Rs does not increase in the charge / discharge path of the transient voltage balance circuit B1.
FIG. 5 shows an equivalent circuit of the transient voltage balance circuit. As shown in the figure, the circuit is composed of the wiring inductance Ls, Cs, Rs, and IGBT. In this circuit, when the IGBT is turned on, the charge of Cs is discharged through the illustrated arrow path. If the vibration coefficient ζ of this path is 1 or more, the current is discharged without oscillating. That is, the following equation should be satisfied.
ζ = Rs√ (Cs / Ls) / 2 ≧ 1
Therefore,
Rs ≧ 2√ (Ls / Cs)
If this condition is satisfied, the transient voltage balance circuit can be arranged at an arbitrary position, and the structure can be simplified.

The block diagram which shows 1st Embodiment of this invention The block diagram which shows 2nd Embodiment of this invention Waveform diagram of each part for explaining the operation of FIG. Circuit diagram showing the equivalent circuit of the element Circuit diagram showing equivalent circuit of transient voltage balance circuit Configuration diagram showing a conventional example Waveform diagram of each part for explaining the operation of FIG.

Explanation of symbols

Q1, Q2 ... IGBT (voltage driven semiconductor element), Tc ... core, GDU1, GDU2 ... gate drive circuit, B1 ... transient voltage balance circuit, B2 ... steady voltage balance circuit, Cs1, CS2 ... capacitor, Rd1, Rd2, Rs1 , Rs2... Resistance.

Claims (4)

A plurality of voltage-driven semiconductor elements (semiconductor elements) connected in series, a gate drive circuit that supplies a control signal to the gate terminal to turn on and off the semiconductor elements, and a voltage amplifier generated during the transient operation of each semiconductor element A transient voltage balance circuit that suppresses the balance, and a steady voltage balance circuit that suppresses voltage imbalance that occurs during the steady operation of each semiconductor element;
A semiconductor switching circuit, wherein the transient voltage balance circuit is connected to each semiconductor element by a shortest wiring, and the steady voltage balance circuit is arranged at an arbitrary position away from each semiconductor element.   The semiconductor switching circuit according to claim 1, wherein the transient voltage balance circuit suppresses voltage imbalance caused by variation in tail current of the semiconductor element.   3. The semiconductor switching circuit according to claim 1, further comprising a core that magnetically couples a gate line connecting the output terminal of the gate drive circuit and the gate terminal of the semiconductor element. 4. The semiconductor switching circuit according to claim 3, wherein the transient voltage balance circuit is arranged at an arbitrary position from the semiconductor element by matching with wiring inductance.

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