JP2003163496A - 位置決め手段および方法 - Google Patents

位置決め手段および方法

Info

Publication number
JP2003163496A
JP2003163496A JP2002305332A JP2002305332A JP2003163496A JP 2003163496 A JP2003163496 A JP 2003163496A JP 2002305332 A JP2002305332 A JP 2002305332A JP 2002305332 A JP2002305332 A JP 2002305332A JP 2003163496 A JP2003163496 A JP 2003163496A
Authority
JP
Japan
Prior art keywords
pattern
component
axis
along
tracks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2002305332A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003163496A5 (enExample
Inventor
Libero Zucchelli
リベロ・ツッケッリ
Luigi Gastaldi
ルイジ・ガスタルディ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agilent Technologies Inc
Original Assignee
Agilent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agilent Technologies Inc filed Critical Agilent Technologies Inc
Publication of JP2003163496A publication Critical patent/JP2003163496A/ja
Publication of JP2003163496A5 publication Critical patent/JP2003163496A5/ja
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/27—Structural arrangements therefor
    • H10P74/277—Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/303—Assembling printed circuits with electric components, e.g. with resistors with surface mounted components
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4219—Mechanical fixtures for holding or positioning the elements relative to each other in the couplings; Alignment methods for the elements, e.g. measuring or observing methods especially used therefor
    • G02B6/422—Active alignment, i.e. moving the elements in response to the detected degree of coupling or position of the elements
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0266—Marks, test patterns or identification means
    • H05K1/0268—Marks, test patterns or identification means for electrical inspection or testing
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/16—Inspection; Monitoring; Aligning
    • H05K2203/166—Alignment or registration; Control of registration
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Supply And Installment Of Electrical Components (AREA)
JP2002305332A 2001-10-22 2002-10-21 位置決め手段および方法 Withdrawn JP2003163496A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP01308967:7 2001-10-22
EP01308967A EP1304543B1 (en) 2001-10-22 2001-10-22 Positioning with conductive indicia ( silicon optical bench )

Publications (2)

Publication Number Publication Date
JP2003163496A true JP2003163496A (ja) 2003-06-06
JP2003163496A5 JP2003163496A5 (enExample) 2005-12-02

Family

ID=8182383

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002305332A Withdrawn JP2003163496A (ja) 2001-10-22 2002-10-21 位置決め手段および方法

Country Status (4)

Country Link
US (1) US6647619B2 (enExample)
EP (1) EP1304543B1 (enExample)
JP (1) JP2003163496A (enExample)
DE (1) DE60109937T2 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6959134B2 (en) * 2003-06-30 2005-10-25 Intel Corporation Measuring the position of passively aligned optical components
US9985158B2 (en) 2012-06-13 2018-05-29 Massachusetts Institute Of Technology Visibly transparent, luminescent solar concentrator
CN113423170B (zh) * 2021-06-17 2024-09-17 北京京东方光电科技有限公司 线路母板、线路板的制备方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5337398A (en) * 1992-11-30 1994-08-09 At&T Bell Laboratories Single in-line optical package
US6237218B1 (en) * 1997-01-29 2001-05-29 Kabushiki Kaisha Toshiba Method and apparatus for manufacturing multilayered wiring board and multi-layered wiring board
US6188028B1 (en) * 1997-06-09 2001-02-13 Tessera, Inc. Multilayer structure with interlocking protrusions
DE69833087T2 (de) * 1997-10-08 2006-07-20 Delphi Technologies, Inc., Troy Verfahren zur Herstellung von Dickfilmschaltungen

Also Published As

Publication number Publication date
DE60109937T2 (de) 2006-02-23
DE60109937D1 (de) 2005-05-12
US20030077846A1 (en) 2003-04-24
US6647619B2 (en) 2003-11-18
EP1304543A1 (en) 2003-04-23
EP1304543B1 (en) 2005-04-06

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