JP2003156545A - Inspection method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily detect leakage failure in a digital circuit after packaging chips in a semiconductor device where an analog circuit and a digital circuit are integrated into one chip and at the same time a power supply terminal is shared while chips have been packaged. SOLUTION: In inspection, a transistor 17 that is arranged in a power supply line from a power supply terminal 13 to a digital circuit 11 is turned off for breaking, at the same time a supply voltage is applied to the power supply terminal 13 while the digital circuit 11 is being set to a test mode, and current leakage in the digital circuit 11 is detected by potential difference that is generated in a detection resistor 28 that is connected in parallel with a break section at the power supply line from the power supply terminal 13 to the digital circuit 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device inspection method.

[0002]

2. Description of the Related Art For example, an automobile ECU (electronic control unit) may be equipped with a constant current circuit for supplying a constant current to a peripheral circuit connected to the outside in order to further integrate the functions. An analog circuit may be configured in addition to the A / D converter. Conventionally, in such a configuration in which an analog circuit and a digital circuit are mixed in one chip in the ECU, both power supply terminals may be shared for the purpose of reducing the mounting area, for example.

By the way, regarding the digital circuit, by measuring the leakage current (leakage current) in a steady state in which the signal of each part is continuously at a constant level, it is confirmed that each element constituting the digital circuit is normal. There is a request to confirm.

However, in the case where the analog circuit and the digital circuit are mixed in one chip as described above, it becomes extremely difficult to directly measure the leak current. Therefore, conventionally, for example, an indirect method such as estimating a leak current by a difference between a total current consumption value in an operating state in which a signal level of a digital circuit is actively changed and the current consumption value in the steady state is used. However, there was a problem with the measurement accuracy.

As a method for solving this problem, Japanese Unexamined Patent Application Publication No.
Japanese Patent Laid-Open No. 0-147073 proposes a method of measuring leak in the state of an IC chip. In FIG. 5, a digital circuit 101 and an analog circuit 102 are formed in the IC chip 100, the power source of the digital circuit 101 is connected to the digital pad 103, and the power source of the analog circuit 102 is connected to the analog pad 104. Therefore, by connecting the power supply 106 and the ammeter 107 between the digital pad 103 and the GND pad 105 in the state of the IC chip 100, the leak of the digital circuit 101 can be measured by the ammeter 107.

The inspected IC chip 100, as shown in FIG.
03 and the analog pad 104 are connected to the power supply pin 151 and assembled as an IC package 160.

As a problem in this case, even after the power source pin 151 and the GND pin 152 are connected to the power source 106 and the ammeter 107 after the IC package 160 is assembled, the current value measured by the ammeter 107 is an analog circuit. It was not possible to accurately measure a minute leak including the current consumption of 102 and flowing to the digital circuit 101.

[0008]

The present invention has been made under such a background, and an object thereof is to integrate an analog circuit and a digital circuit in one chip and to provide a state after the chip is mounted. In a semiconductor device having a common power supply terminal, it is possible to easily detect a leak defect of a digital circuit after chip mounting.

[0009]

According to the invention described in claim 1, a semiconductor device in which an analog circuit and a digital circuit are integrated in one chip and a power supply terminal is made common after the chip is mounted. In, it is possible to easily detect a leak defect of the digital circuit after the chip is mounted.

According to the invention described in claim 2, in the semiconductor device in which the analog circuit and the digital circuit are integrated in one chip and the power supply terminals are made common after the chip is mounted, the power supply dedicated to the test is used. It is possible to easily detect a leak defect of a digital circuit after mounting a chip without providing a terminal.

According to the third aspect of the invention, the power supply line is cut off by turning off the transistor,
It is practically preferable. According to the invention described in claim 6, it is possible to inspect the current leakage when the clock is stopped.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. In this embodiment, the semiconductor device is applied to an automobile ECU (electronic control unit).

FIG. 1 shows the electrical construction of the ECU. More specifically, it is a functional block diagram showing a state in which a standby leak current is measured for a digital circuit. The IC package 10 is composed of a semiconductor chip in which a digital circuit 11 and an analog circuit 12 are integrated, the chip and the lead frame are bonded by wires, and the chip and the wires are molded. The chip is mounted in this way. For details, IC package 1
0 is an LSI (Large Scale) formed in one chip.
The digital circuit 11 and the analog circuit 12 are integrated. The digital circuit 11 includes a microcomputer and other logic circuits. The analog circuit 12 includes an A / D converter, a constant current circuit, an analog comparator and the like.

In an IC package 10 in which chips are packaged, external connection pins (terminals) 1 and 1 are provided.
4, 15 and 16, the pin 13 is a power supply pin, the pin 14 is a GND pin (ground pin), the pin 15 is a test input shared pin, and the pin 16 is a test output shared pin. A power supply 50 is connected to the power supply pin 13 outside the IC package 10. Also, the GND pin 14 is an IC
It is grounded outside the package 10. Further, with respect to the pin 15 also serving as a test input, a low voltage power source is normally connected outside the IC package 10, and
A high-voltage test power supply 51 is connected during the test. Further, to the test output / combined pin 16, a digital signal is normally output, and a test result is output during a test.

On the other hand, in the IC package 10, the analog circuit 12 is connected to the GND pin 14 and the power supply pin 13. Also, the digital circuit 1
1 is connected to the GND pin 14 and also connected to the power supply pin 13 via the power supply transistor 17. In this way, the power supply pin (power supply terminal) 13 is connected to the digital circuit 11
And the analog circuit 12 has a common pin, and this pin 1
3 can be used to supply a power supply voltage to the analog circuit 12 and the digital circuit 11. Here, by disposing the transistor 17 in the power supply line from the power supply pin 13 to the digital circuit 11 and turning off the transistor 17 at the time of inspection, the power supply line can be cut off. The base terminal of the power transistor 17 is the internal power generation circuit 18
Connected with. Normally, the power supply transistor 17 is turned on by the voltage from the internal power supply generation circuit 18.

In the IC package 10, resistors 19 and 2 are provided between the pin 15 also serving as a test input and the GND pin 14.
0 are connected in series, and the point α1, between the resistors 19 and 20 is
α2 is connected to the + input terminals of the comparators 21 and 22, respectively. In addition, the power supply pin 13 and the GND pin 14
The resistors 23 and 24 are connected in series between
The point β between 24 is connected to the minus input terminal of the comparator 21. Similarly, resistors 25 and 26 are connected in series between the power supply pin 13 and the GND pin 14, and the point γ between the resistors 25 and 26 is − of the comparator 22.
It is connected to the input terminal. The output terminal of the comparator 22 is connected to the digital circuit 11. Then, in the normal state (when a low power supply voltage is applied to the pin 15), the comparator 22 has the potential of the point γ higher than the potential of the point α2 and the output becomes the L level. On the other hand, high voltage power supply 5
By connecting 1 to the pin 15, the potential at the point α2 rises, and when the potential at the point α2 becomes higher than the potential at the point γ in the comparator 22, the output becomes H level. As a result, the digital circuit 11 is set to the test mode.

A transistor 27 is arranged between the base terminal of the transistor 17 and the GND pin 14, and the base terminal of the transistor 27 is connected to the output terminal of the comparator 21 via the buffer B1. Then, by connecting the high-voltage power supply 51 to the pin 15, the potential at the point α1 rises, and when the potential at the point α1 becomes higher than the potential at the point β in the comparator 21, the output becomes H level. As a result, the transistor 27 is turned on in the test mode.

A detection resistor 28 is connected in parallel with the transistor 17 in a power supply line from the power supply pin 13 to the digital circuit 11. Also, power supply pin 13 and G
The resistors 29 and 30 are connected in series with the ND pin 14, and the point δ between the resistors 29 and 30 is connected to the + input terminal of the leak determination comparator 31. The negative input terminal of the comparator 31 is the digital circuit 11 with the detection resistor 28.
It is connected to the side (the emitter terminal of the transistor 17). The output terminal of the comparator 31 is connected to the AND gate 32. Then, the comparator 31 compares the potential at the point δ with the potential of the detection resistor 28 on the digital circuit 11 side, and when the transistor 17 is off (during a test).
When the potential of the detection resistor 28 on the digital circuit 11 side is lower than the potential at the point δ, an H level signal is output.

An AND gate 33 is connected to the signal output side (signal output port) of the digital circuit 11. In addition, the above-mentioned comparator (inspection input comparator) 21
The output terminal of is connected to the AND gate 32 and the AND gate 33 via the buffer B2. The signal to the AND gate 33 is inverted and input. AND gate 3
2 and the output terminal of the AND gate 33 are connected to the test output / purpose pin 16 through the OR gate 34.

Next, the semiconductor device (I
The inspection method for the C package will be described. Normally (non-test, normal time), a low voltage power supply is connected to pin 15. The power supply transistor 17 is turned on by the voltage generated by the internal power supply generation circuit 18, and the power supply voltage is supplied to the digital circuit 11 through the power supply pin 13. The output of the digital circuit 11 is output from the pin 16 via the AND gate 33 and the OR gate 34.

At the time of the test (at the time of measuring the standby leak), the power source 51 is connected to the pin 15 also serving as the test input and a high voltage which is not normally used is applied. Then, the output of the comparator 21 is inverted and the transistor 27 is turned on,
As a result, the transistor 17 is turned off. Further, the output of the comparator 22 is inverted to put the digital circuit 11 in the test mode.

In this state (the state where the power supply line from the power supply terminal 13 to the digital circuit 11 is cut off and the digital circuit 11 is in the test mode at the time of inspection), the voltage from the power supply 50 is applied to the power supply pin 13, Power pin 13
The current leak in the digital circuit 11 is inspected by the potential difference generated in the detection resistor 28 connected in parallel to the interruption part in the power supply line from the to the digital circuit 11. Specifically, when the leak current flowing through the detection resistor 28 is large, the voltage drop generated across the detection resistor 28 also becomes large, and the output terminal of the leak determination comparator 31 becomes H level,
The output of the AND gate 32 becomes H level and O
The pin 16 becomes H level via the R gate 34. Therefore, by monitoring the output of the pin 16, it is detected that the leak current is large.

In this way, at the time of test, a high voltage is input to the test input / use pin 15 and the test output / use pin 16 is set to H level.
The leakage current abnormality of the digital circuit 11 can be easily determined only by measuring the / L level. That is, in a semiconductor device in which the analog circuit 12 and the digital circuit 11 are integrated in one chip and the power supply terminal 13 is shared after the chip is mounted, the digital circuit is mounted after the chip is mounted without providing a power supply terminal dedicated to the test. A leak failure in the circuit 11 can be easily detected.

Modifications and extensions of the above embodiment will be described below. The digital circuit 11 in FIG.
It may be composed of CMOSFETs or other materials. For example, bipolar transistor or B
You may comprise i-CMOS etc.

Further, as shown in FIG. 2, by providing the input pin 35 and the check pin 36 exclusively for the test, the inspection input comparator 21 and the leak judgment comparator 31 of FIG. 1 are not required and the input pin 35 is set to the H level. The potential difference between the power supply pin 13 and the check pin 36 may be directly measured by the voltmeter 37. That is, in the configuration of FIG. 1, the potential difference generated in the detection resistor 28 in the device is compared with the reference value to inspect the current leak in the digital circuit 11 based on the magnitude relationship, but as shown in FIG. To
The voltage between the power supply terminal 13 connected to both terminals of the detection resistor 28 and the check terminal 36 is measured outside the device by a voltmeter 37.
The current leak in the digital circuit 11 may be inspected by measuring with.

FIG. 3 shows a case where the detection resistor 28 of FIG. 1 is further omitted. At this time, check pin 38 is connected to power source 5
By connecting 0 and the ammeter 39, the leak of the digital circuit 11 is directly measured. That is, at the time of inspection, the current leak in the digital circuit 11 is measured by measuring the current flowing in the digital circuit 11 while the power supply line from the power supply terminal 13 to the digital circuit 11 is cut off and the digital circuit 11 is in the test mode. To inspect. As a result, it is possible to easily detect a leak defect of the digital circuit 11 after the chip is mounted.

FIG. 4 shows the digital circuit 11 with higher accuracy.
It is an example of a circuit when detecting the leak of. In FIG. 4, when a voltage higher than that in the state where the output of the test input comparator 21 becomes H level is applied to the test input / combined pin 15 by the power supply 51a, the clock stop comparator 40 outputs H level, and the digital circuit 11 outputs. Fix dynamic circuits such as clocks. Then, the terminal voltage of the detection resistor 28 is judged by the standby leak judging comparator 41 having a threshold voltage higher than that of the standby leak judging comparator 31, and when the standby leak is larger than the standard value, the AND gate 42 (43) and the OR gate. Four
An H level is output to the test output dual-purpose pin 45 via 4. The reference voltage (-input terminal voltage) at the comparators 40 and 21 is generated by the resistors 23, 46 and 24 connected in series between the power supply pin 13 and the GND pin 14, and at the comparators 41 and 31. The reference voltage (+ input terminal voltage) is generated by resistors 29, 47 and 30 connected in series between the power supply pin 13 and the GND pin 14.

In this way, the clock of the digital circuit 11 is stopped at the time of inspection, and the current flowing in the digital circuit 11 is measured in this state to inspect the current leak in the digital circuit 11. As a result, it is possible to check the current leak when the clock is stopped.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a semiconductor device according to an embodiment.

FIG. 2 is a configuration diagram of another example of a semiconductor device.

FIG. 3 is a configuration diagram of another example of a semiconductor device.

FIG. 4 is a configuration diagram of a semiconductor device according to another example.

FIG. 5 is a configuration diagram of a semiconductor device for explaining a conventional technique.

FIG. 6 is a configuration diagram of a semiconductor device for explaining a conventional technique.

[Explanation of symbols]

11 ... Digital circuit, 12 ... Analog circuit, 13 ... Power supply pin, 17 ... Transistor, 28 ... Detection resistor, 31 ... Comparator, 36 ... Check pin, 39 ... Ammeter, 41
…comparator.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 27/04 H01L 27/04 TUF term (reference) 2G035 AA01 AB02 AC02 AC16 AD02 AD10 AD23 AD27 AD28 AD56 2G132 AA00 AA11 AC03 AD01 AE10 AE14 AE27 AK07 AK09 AK15 AL11 5F038 DF12 DT04 DT09 DT10 EZ20

Claims (6)

[Claims] 1. A semiconductor chip in which an analog circuit and a digital circuit are integrated is mounted, and a common power supply terminal is used to inspect a semiconductor device that supplies a power supply voltage to the analog circuit and the digital circuit for a current leak in the digital circuit. The method is to cut the power supply line from the power supply terminal to the digital circuit at the time of inspection and put the digital circuit in the test mode. A method for inspecting a semiconductor device, characterized in that a leak is inspected. 2. A semiconductor chip having an analog circuit and a digital circuit integrated therein is mounted, and a common power supply terminal is used to inspect a semiconductor device that supplies a power supply voltage to the analog circuit and the digital circuit for current leakage in the digital circuit. A method of applying a power supply voltage to the power supply terminal in a state where the power supply line from the power supply terminal to the digital circuit is cut off and the digital circuit is in a test mode during inspection.
A method for inspecting a semiconductor device, wherein a current leak in a digital circuit is inspected by a potential difference generated in a detection resistor connected in parallel to a cutoff portion in a power supply line from the power supply terminal to the digital circuit. 3. The power supply line from the power supply terminal to the digital circuit is provided with a transistor, and the power supply line is cut off by turning off the transistor at the time of inspection. 2. The method for inspecting a semiconductor device according to 2. 4. The current leak in a digital circuit is inspected by comparing the potential difference generated in the detection resistor with a reference value in the device, and comparing the magnitude of the difference. A method for inspecting a semiconductor device as described above. 5. A current leak in a digital circuit is inspected by measuring a voltage between a power supply terminal connected to both terminals of the detection resistor and a check terminal with a voltmeter outside the device. The method for inspecting a semiconductor device according to claim 2. 6. The current leak in the digital circuit is inspected by stopping the clock of the digital circuit during the inspection and measuring the current flowing through the digital circuit in this state. Any one of 5
Item 6. A method for inspecting a semiconductor device according to item.