JP2003172763A - Inspection device and inspection method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform accurate measurement by removing the influence of a parasitic resistance in inspection of a semiconductor device. <P>SOLUTION: This inspection device 1 is equipped with a power source part 3 capable of supplying a test signal variably, a theoretical resistance value storage part 13 for storing a theoretical resistance value between two terminals of the semiconductor device, a parasitic resistance value calculation part 11 for calculating a parasitic resistance value based on a current value measured by a measuring part 9 and the theoretical resistance value stored in the theoretical resistance value storage part 13, when a voltage value is specified by the power source part 3 and a preliminary test signal is supplied in the state where measuring terminals 7a, 7b are brought into contact with the two terminals of the semiconductor device, a correction value calculation part 15 for calculating a correction value of the test signal so that the test signal having the prescribed size is supplied between the two terminals of the semiconductor device based on the parasitic resistance value calculated by the parasitic resistance value calculation part 11, and a control part 17 for controlling the power source part 3 based on the correction value calculated by the correction value calculation part 15. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inspection device and an inspection method for inspecting the operation of a semiconductor device.

[0002]

2. Description of the Related Art One of the inspection items for semiconductor devices is to apply a constant voltage to a specific terminal and determine the value of the current flowing at that time in order to determine whether the product is a good product or a defective product. Such inspection includes a wafer test performed on a wafer using a probe card having needle-shaped terminals and a final test performed using a test jig after package sealing.

In any of the tests, accurate measurement cannot be performed if there is contact resistance between the terminals of the semiconductor device and the measurement terminals of the test board. Therefore, it has been dealt with by polishing the tip of the needle terminal of the probe card or periodically replacing the socket terminal. When replacing the socket terminal, the socket body is replaced with a socket for QFP (quad flat package), and the pogo pin (socket terminal) is replaced with a socket for BGA (ball grid array) (for example, Japanese Patent Laid-Open No. 5-1
9014).

[0004]

FIG. 6 shows an example of a circuit configuration when a semiconductor device is inspected. A constant voltage is applied to the semiconductor device 21 from the measurement unit 25 of the inspection device 27 via the test board 5, and the current flowing between the semiconductor device 21 and the ground is measured at that time. In the semiconductor device 21, a current flows from the terminal A to the terminal B via the internal circuit 23. In this circuit, it is assumed that a current of 50 mA is detected when 3 V is applied, for example.

However, from this result, it cannot be said that the actual power of the semiconductor device 21 is 50 mA at 3 V operation. Influenced by parasitic resistances R1 and R2 existing on the test board 5,
This is because the voltage applied to the semiconductor device 21 has dropped to (3V− (R1 + R2) × 50 mA).

Of the parasitic resistances on the test board, the resistance value due to the wiring can be measured and removed in advance when the test board is prepared. However, the contact resistance between the terminal of the semiconductor device and the measuring terminal of the test board changes with time, which causes a measurement error and hinders accurate inspection. Here, the contact resistance between the terminal of the semiconductor device and the measurement terminal of the test board is the contact resistance between the pad electrode of the semiconductor device and the needle terminal of the probe card in the wafer test, and the contact resistance of the semiconductor device package in the final test. This is the contact resistance of the socket terminal.

The cause of the contact resistance changing with time may be abrasion of the needle terminals of the probe card or adhesion of foreign matter to the needle terminals in the wafer test, and deterioration or deterioration of the socket terminals in the final test. For example, foreign matter may be attached to the socket terminals.

In many cases, a voltage drop due to contact resistance is not a problem. However, in power supply devices and analog devices that pass relatively large currents and have severe current specifications, even if the contact resistance increases slightly, it will be a fatal inspection obstacle, so the contact resistance cannot be ignored. ing. In particular, in the BGA package which has been frequently used recently, the contact between the ball portion, which is the terminal of the semiconductor device, and the socket terminal is close to point contact, and the ball material is transferred to the socket terminal to cause oxide. Therefore, the fluctuation of the contact resistance is large.

Further, in recent years, the terminal material of the semiconductor device package has become lead-free without using lead. With such a material, it is difficult to obtain a stable contact because tin in the terminal material is transferred to the socket terminal and oxidized.

As described above, in the inspection, there is a problem that the current value cannot be accurately measured due to the contact resistance existing between the terminal of the semiconductor device and the measuring terminal of the test board. Therefore, even if the current value guarantee accuracy of the semiconductor device is improved, the guarantee range of the product standard is unavoidably narrowed due to restrictions on the measurement side.

Therefore, the present invention can eliminate the influence of the parasitic resistance on the test board including the contact resistance existing between the terminal of the semiconductor device and the measurement terminal of the test board to perform accurate measurement. It is an object of the present invention to provide an inspection device and an inspection method.

[0012]

A semiconductor device inspection apparatus according to the present invention provides a test signal by prescribing one of a voltage and a current with two terminals of the semiconductor device in contact with a measuring terminal. A power supply unit for supplying a power supply unit and a measuring unit for measuring the other, and a power supply unit capable of variably supplying a test signal, and a theoretical resistance value storage for storing a theoretical resistance value between two terminals in a semiconductor device. Section and the measurement terminal in contact with the two terminals of the semiconductor device, the power source section regulates one of voltage and current to supply a preliminary test signal and measures the other, and Based on the parasitic resistance value calculation unit for calculating the parasitic resistance value based on the theoretical resistance value stored in the theoretical resistance value storage unit, and the parasitic resistance value calculated by the parasitic resistance value calculation unit, the semiconductor device Between the two terminals A correction value calculation unit for calculating a correction value of the test signal so that a test signal of a constant magnitude is supplied, and for controlling the power supply unit based on the correction value calculated by the correction value calculation unit. And a control unit of.

A method of inspecting a semiconductor device according to the present invention is
A first step in which a measuring terminal is brought into contact with two terminals of a semiconductor device whose theoretical resistance value between the two terminals is known, and one of voltage and current is defined to supply a preliminary test signal and the other is measured; The second step of calculating the parasitic resistance value based on the measurement result in the first step and the logical resistance value, and the two terminals of the semiconductor device based on the parasitic resistance value calculated in the second step A third step of calculating a correction value of the test signal so that a test signal having a predetermined magnitude is supplied between the two steps, and between the two terminals of the semiconductor device based on the correction value calculated in the third step. A fourth step of providing a test signal.

Here, the theoretical resistance value between the two terminals in the semiconductor device is obtained by simulation or actual measurement, and the parasitic resistance value is the parasitic resistance existing between the terminal of the semiconductor device and the inspection device. Is the resistance value of.

According to the inspection apparatus and the inspection method of the present invention, in the inspection of the semiconductor device, either the voltage or the current is defined, the preliminary test signal is supplied, and the other is measured. Thereby, the resistance value of the entire preliminary test signal path at the time of inspection can be known. By subtracting the theoretical resistance value between the two terminals in the semiconductor device from the resistance value, the parasitic resistance value existing between the terminals of the semiconductor device and the inspection device is calculated. Semiconductor device 2
The correction value of the test signal is calculated so that the test signal of a predetermined magnitude is supplied between the terminals. By supplying a test signal based on the correction value, the influence of parasitic resistance existing between the terminals of the semiconductor device and the inspection device, including the contact resistance existing between the terminals for measurement and the terminals of the semiconductor device, is eliminated. Accurate measurement can be performed.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION In a semiconductor device inspection apparatus of the present invention, the power supply unit supplies the preliminary test signal so that a current flows in a forward direction of a parasitic diode existing between two terminals in the semiconductor device. It is preferable.

In the semiconductor device inspection method of the present invention,
In the first step, it is preferable to supply the preliminary test signal so that a current flows in the forward direction of a parasitic diode existing between two terminals in the semiconductor device.

Generally, a parasitic diode exists between two terminals in a semiconductor device. The forward resistance value of this parasitic diode can be made sufficiently small, and the error in the forward resistance value of the parasitic diode in a plurality of semiconductor devices can be made negligible. By using, as the theoretical resistance value, a resistance value when a current flows in the forward direction of a parasitic diode existing between two terminals in the semiconductor device, it is possible to obtain the theoretical resistance value for each semiconductor device in advance. , Can be used as a common theoretical resistance value in the inspection of a plurality of semiconductor devices.

[0019]

1 is a block diagram showing an embodiment of a semiconductor device inspection apparatus. The inspection device 1 is provided with a power supply unit 3 for supplying a test signal by defining one of voltage and current, for example, voltage. The power supply unit 3 can set the supplied voltage variably. The output of the power supply unit 3 is connected to the measuring terminal 7a via the wiring 5a provided on the test board 5. A measurement terminal 7b is provided in pair with the measurement terminal 7a. Measurement terminal 7b
Is grounded via a wiring 5b provided on the test board 5. A measuring unit 9 including, for example, an ammeter is provided between the wiring 5a and the wiring 5b.

A parasitic resistance value calculation unit 11 for calculating a resistance value based on the voltage supplied by the power supply unit 3 and the current value measured by the measurement unit 9 is provided. The parasitic resistance value calculation unit 11 is connected to a theoretical resistance value storage unit 13 for storing a theoretical resistance value between two terminals to be measured in the semiconductor device.

A correction value calculation unit 15 for calculating the correction value of the test signal based on the parasitic resistance value calculated by the parasitic resistance value calculation unit 11 is provided. A control unit 17 for controlling the power supply unit 3 is provided. The control unit 17 controls the power supply unit 3 based on the correction value calculated by the correction value calculation unit 15. The control unit 17 is also connected to the parasitic resistance value calculation unit 11, and sends the voltage value information supplied by the power supply unit 3 to the parasitic resistance value calculation unit 11.

FIG. 2 shows a circuit diagram for measuring a theoretical resistance value between two terminals in the semiconductor device. When measuring the theoretical resistance value, the wirings 19a, 1 whose resistance values RR1, RR2 are known are used.
9b is directly connected to the terminals A and B of the semiconductor device 21 by soldering or the like so as not to have a contact resistance. Semiconductor device 21
Inside, an internal circuit 23 is provided between terminals A and B.
A parasitic diode D1 also exists between the terminals A and B.

A voltage having a magnitude VR is applied by the power supply unit 3. Here, for example, a voltage value VR lower than the ground potential is applied to the terminal A so that the diode D1 is connected in the forward direction and a current flows through the diode D1. The current flowing at that time is measured by the measuring unit 9. The current value measured by the measuring unit 9 is AR.

Since the resistance values RR1 and RR2 are known, the applied voltage value is VR, and the measured current value is AR, the internal resistance (theoretical resistance value) between the terminals A and B of the semiconductor device 21 is RD. Then, RD = VR / AR- (RR1 + RR2).

The theoretical resistance value RD is calculated by the parasitic resistance value calculation unit 11 and stored in the theoretical resistance value storage unit 13 (see also FIG. 1). For the measurement of the theoretical resistance value RD, the inspection device shown in FIG. 1 may be used, or another measuring device may be used. Here, the theoretical resistance value RD is obtained by the actual measurement value, but the present invention is not limited to this, and the resistance value between two terminals in the semiconductor device obtained by simulation may be used as the theoretical resistance value. .

Here, the forward resistance value of the parasitic diode D1 is designed to be sufficiently smaller than the resistance value of the internal circuit 23. Further, the forward resistance value of the parasitic diode D1 is designed so that the amount of change due to process variation is sufficiently smaller than the amount of change in contact resistance between the measurement terminal and the terminal of the semiconductor device during inspection. As a result, the error that the theoretical resistance value RD itself has in a plurality of semiconductor devices can be made negligible, and the theoretical resistance value RD can be used in the calculation of the contact resistance of the plurality of semiconductor devices during the inspection of the semiconductor device described later. Can be used.

FIG. 3 shows a circuit diagram when the semiconductor device is inspected. FIG. 4 is a flowchart showing an embodiment of a semiconductor device inspection method. An example of the inspection method will be described with reference to FIGS. 3 and 4. The controller 17 sets the value of the preliminary test voltage (preliminary test signal) to VM. The preliminary test voltage value VM is set to the same magnitude as the voltage value VR lower than the ground potential used when measuring the theoretical resistance value RD, for example (step S1).

As shown in FIG. 3, a measuring terminal (not shown) is brought into contact with the terminals A and B of the semiconductor device 21 (step S2). At this time, the sum of the contact resistance value at the terminal A and the resistance value of the wiring 5a is R1, and the sum of the contact resistance value at the terminal B and the resistance value of the wiring 5b is R2.

The control unit 17 controls the power supply unit 3 to supply the preliminary test voltage value VM lower than the ground potential (step S3). The current flowing at this time is measured by the measuring unit 9 (step S4). The current value measured at this time is AM. Then, the voltage application by the power supply unit 3 is stopped (step S5).

The parasitic resistance value calculation unit 11 calculates the preliminary test voltage value VM supplied by the power supply unit 3, the current value AM measured by the measurement unit 9 and the theoretical resistance value RD stored in the theoretical resistance value storage unit 13. Based on the parasitic resistance value (R1 +
Calculate R2). The parasitic resistance value R1 + R2 is calculated by (R1 + R2) = VM / AM-RD.

The correction value calculation unit 15 calculates the correction value (test signal) of the voltage applied at the time of inspection based on the parasitic resistance value (R1 + R2) calculated by the parasitic resistance value calculation unit 11 (step S6).

At the time of inspection, the expected current value is AS
Then, the voltage drop due to the parasitic resistances R1 and R2 is (R1 + R2) × AS = (VM / AM-RD) × AS.

When the voltage value of the voltage (test signal) supplied from the power supply unit 3 is VT without considering the parasitic resistance value (R1 + R2) at the time of inspection, the parasitic resistance value (R1 + R2) is taken into consideration for actual application. If the voltage (correction value) to be applied is VT + (VM / AM-RD) × AS, the influence of the parasitic resistances R1 and R2 can be removed and the inspection can be performed.

The control unit 17 sets the test voltage (test signal) supplied by the power supply unit 3 based on the correction value calculated by the correction value calculation unit 15 (step S7). A test voltage is supplied by the power supply unit 3 (step S8). By supplying the test voltage based on the correction value calculated by the correction value calculation unit 15, the terminals A and B of the semiconductor device including the contact resistance existing between the terminals A and B of the semiconductor device and the measuring terminal are supplied. Accurate measurement can be performed by removing the influence of the parasitic resistance existing between the inspection device 1 and the inspection device 1.

When the test voltage is supplied, the current value measured by the measuring unit 9 is compared with the standard value, and if it is within the specified range, it is judged as a good product (Pass), and if it is outside the specified range, it is a defective product (Fail).
(Step S9).

Depending on the inspection method, contact resistance may be required for each terminal. In this case, as shown in FIG. 5, at least three terminals having a known theoretical resistance value in the semiconductor device are prepared. 4, C, D and E are terminals of the semiconductor device 21a, RD34 is a theoretical resistance value between the terminals C and D, RD35 is a theoretical resistance value between the terminals C and E, and RD45.
Is a theoretical resistance value between the terminals D and E, R3 is a parasitic resistance on the test board 5 including a contact resistance with the terminal C, and R4 is a terminal D.
Parasitic resistance on test board 5, including contact resistance with R
Reference numeral 5 is a parasitic resistance on the test board 5 including contact resistance with the terminal E, P3 is an input terminal to the terminal C, P4 is an input terminal to the terminal D, and P5 is an input terminal to the terminal E.

A preliminary test voltage value V34 is applied between the input terminals P3 and P4, and the current value A34 is measured. Similarly, the preliminary test voltage value V45 is applied between the input terminals P4 and P5 to measure the current value A45, and the preliminary test voltage value V35 is applied between the input terminals P3 and P5 to measure the current value A35. .

From these results, the parasitic resistances R3, R4,
For R5, the resistance value of each is R3 = ((V34 / A34 + V35 / A35-V45 / A45)-(R34 + R35-R45)) / 2 R4 = ((V34 / A34 + V45 / A45-V35 / A35 )-(R34 + R45-R35)) / 2 R5 = ((V35 / A35 + V45 / A45-V34 / A34)-(R35 + R45-R34)) / 2. After that, the correction value is calculated in the same manner as step S6 and subsequent steps of the flowchart shown in FIG.
An inspection is performed by supplying a test signal based on the correction value.

In the embodiments described with reference to FIGS. 1 to 4, the case where the voltage is applied and the current is measured has been described as the inspection method of the semiconductor device, but the present invention is not limited to this. Obviously, the inspection apparatus and the inspection method of the present invention can be applied to the case where the current is applied and the voltage is measured. In FIG. 1, each unit in the inspection apparatus 1 can be realized as hardware, or the parasitic resistance value calculation unit 11, the correction value calculation unit 15, and the control unit 1 can be implemented.
7 can also be realized by a central processing unit (CPU) and software.

Although the embodiment of the present invention has been described above, the present invention is not limited to this, and various modifications can be made within the scope of the present invention described in the claims.

[0041]

According to the semiconductor device inspecting apparatus of the present invention, a power supply unit capable of variably supplying a test signal and a theoretical resistance value storage unit for storing a theoretical resistance value between two terminals in the semiconductor device. And a parasitic resistance value calculation unit for calculating the parasitic resistance value based on the measurement result and the theoretical resistance value when the preliminary test signal is supplied, and for calculating the correction value of the test signal based on the parasitic resistance value. The semiconductor device inspection method according to claim 2, further comprising a correction value calculation unit and a control unit for controlling the power supply unit based on the correction value, and the theoretical resistance value between the two terminals is known. Measuring terminals are brought into contact with the two terminals of the semiconductor device of 1), and one of voltage and current is defined to supply a preliminary test signal and the other is measured.
Step, a second step of calculating a parasitic resistance value based on the measurement result and the logical resistance value in the first step, and a third step of calculating a correction value of the test signal based on the parasitic resistance value. , 2 of the semiconductor device based on the correction value
Since the fourth step of supplying the test signal between the terminals is included, it exists between the terminals of the semiconductor device and the inspection device including the contact resistance existing between the terminals for measurement and the terminals of the semiconductor device. Accurate measurement can be performed by removing the influence of parasitic resistance.

According to another aspect of the semiconductor device inspection apparatus of the present invention, the power supply unit supplies the preliminary test signal so that a current flows in the forward direction of the parasitic diode existing between the two terminals in the semiconductor device. In the semiconductor device inspecting method according to claim 4, in the first step, the preliminary test signal is supplied so that a current flows in the forward direction of a parasitic diode existing between two terminals in the semiconductor device. By using the resistance value when a current flows in the forward direction of the parasitic diode as the theoretical resistance value between two terminals in the semiconductor device, a plurality of semiconductors can be obtained without obtaining the theoretical resistance value for each semiconductor device in advance. It can be used as a common theoretical resistance value in device inspection.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a semiconductor device inspection apparatus.

FIG. 2 is a circuit diagram showing a connection state when measuring a theoretical resistance value between two terminals in a semiconductor device.

FIG. 3 is a circuit diagram showing a connection state when a semiconductor device is inspected.

FIG. 4 is a flowchart showing an embodiment of a semiconductor device inspection method.

FIG. 5 is a circuit diagram for explaining a method for measuring the contact resistance of each terminal of the semiconductor device.

FIG. 6 is a circuit diagram showing a circuit configuration example when a semiconductor device is inspected.

[Explanation of symbols]

1 Inspection device 3 power supply 5 test board 5a, 5b wiring 7a, 7b Measuring terminal 9 Measuring section 11 Parasitic resistance value calculation unit 13 Theoretical resistance value storage 15 Correction value calculation unit 17 Control unit 19a, 19b wiring 21 Semiconductor device 23 Internal circuit A and B terminals R1, R2 Parasitic resistance including contact resistance RR1, RR2 Parasitic resistance of wiring only

Claims (4)

[Claims] 1. A semiconductor device comprising a power supply unit for supplying a test signal by defining one of a voltage and a current and a measuring unit for measuring the other in a state in which a measuring terminal is in contact with two terminals of a semiconductor device. In a device inspection device, a power supply unit that can variably supply a test signal, a theoretical resistance value storage unit that stores a theoretical resistance value between two terminals in a semiconductor device, and a measurement terminal at two terminals of the semiconductor device. In the contacted state,
Parasitic resistance value based on the theoretical resistance value stored in the theoretical resistance value storage section and the measurement result when supplying the preliminary test signal by defining one of voltage and current by the power supply section and measuring the other Based on the parasitic resistance value calculated by the parasitic resistance value calculating section, and a test is performed so that a test signal of a predetermined magnitude is supplied between two terminals of the semiconductor device. An inspection apparatus comprising: a correction value calculation unit for calculating a correction value of a signal; and a control unit for controlling the power supply unit based on the correction value calculated by the correction value calculation unit. . 2. The inspection apparatus according to claim 1, wherein the power supply unit supplies the preliminary test signal so that a current flows in a forward direction of a parasitic diode existing between two terminals in the semiconductor device. 3. A semiconductor device in which a theoretical resistance value between two terminals is known, and a measurement terminal is brought into contact with the two terminals to supply one of a voltage and a current to supply a preliminary test signal and measure the other. 1 step, a second step of calculating a parasitic resistance value based on the measurement result and the logical resistance value in the first step, and based on the parasitic resistance value calculated in the second step, A third method of calculating a correction value of a test signal so that a test signal having a predetermined magnitude is supplied between two terminals of a semiconductor device.
And a fourth step of supplying a test signal between two terminals of the semiconductor device based on the correction value calculated in the third step. 4. The inspection method according to claim 3, wherein, in the first step, the preliminary test signal is supplied so that a current flows in a forward direction of a parasitic diode existing between two terminals in a semiconductor device.