JP2003131634A - Lcd controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an LCD controller which can easily be adaptive to an LCD model of various display modes, in which a chip area is not increased also when the models to be adapted to are increased, and which can be adaptive to a newly and commercially produced LCD model. SOLUTION: A pulse width setting signal generation part 24 inputs frequency data FDp and generates shift-processed frequency data which are obtained by performing bit shift of the inputted data FDp, calculates the detection count values N1, N2,...Nk by the addition and subtraction of shift-processed frequency data, and outputs, whenever it detects the coincidence of a count value CN of a counter 23 and the detection count value Ni, a pulse width setting signal Dni which corresponds to the coincident count value. Each of set reset latches 25-1 to 25-j outputs a high-level driver control signal during the period from falling of the signal inputted into a set terminal to falling of the signal inputted in a reset terminal.

Description

Detailed Description of the Invention

[0001]

The present invention relates to an LCD (Liquid Crys).
The present invention relates to an LCD controller that controls the display of a tal display).

[0002]

2. Description of the Related Art LC for controlling display timing of LCD
The D controller receives a display mode setting signal as a serial signal from the system controller that controls the entire video display system, and generates and outputs a driver control signal corresponding to the LCD to be controlled. In recent years, LCD display modes have changed from VGA to high-definition SVGA, XGA, SXG
Rapid expansion to A, UXGA and increasing variety,
Since many models have different frequencies such as the dot clock DCK and the horizontal synchronizing signal Hsync even in the same display mode, the number of types of LCD models that the LCD controller is required to handle is extremely large. FIG. 10 shows
It is a list of LCD models described in Japanese Patent Publication No. 000-89740. It is desired that the LCD controller supplies driver control signals corresponding to such various LCD models to the horizontal driver and the vertical driver that directly drive the LCD.

The LCD controller generates a driver control signal from a dot clock DCK, a horizontal synchronizing signal Hsync, etc. However, since the display modes are diverse, the driver control signal is also diverse accordingly, and one LC is used.
It is difficult to make a D controller compatible with all LCD models. For this reason, the conventional LCD controller has dealt with by limiting the LCD model types that one LCD controller can deal with. That is, the LCD controller is configured to include a decoder unit that selects and outputs the start position and the required pulse width of the driver control signal corresponding to the LCD model according to the mode selection signal input from the system controller.

FIG. 11A is a block diagram showing the structure of a conventional LCD controller. The LCD controller 82 includes a serial / parallel conversion circuit 91, a counter load signal generation circuit 22, a counter 23, a decoder unit including decoders 92, 93 and 94, and a driver including set / reset latches 25-1 and 25-2. And a control signal generator. Counter load signal generation circuit 22
Is loaded with a change in the horizontal synchronizing signal Hsync sent from the system controller 81 to the low level in synchronization with the rising edge of the dot clock DCK, and the load signal L
Output S. The counter 23 detects the load signal LS, starts counting the pulses of the dot clock DCK by the counter 23, updates the count value CN in synchronization with the dot clock DCK, and outputs it. The serial-parallel conversion circuit 91 receives the mode setting signal MODs as serial data from the system controller 81, converts it into a parallel mode setting signal MODp, and outputs it. Generally, the mode setting signal MODs is included in the serial signal transmitted from the system controller 81 to the LCD controller.
Not only the portion but also data indicating the VALID position which is the horizontal and vertical effective display range of the data are included, but in the following description, these data are omitted for simplification.

Decoders 92 and 9 constituting the decoder section
In 3 and 94, when the detection count value corresponding to the LCD model selected by the mode setting signal MODp and the count value CN match, the pulse width setting signals Dn1 and Dn.
2 and Dn3 are output respectively. FIG. 11B is a diagram showing the configuration of the decoder 92. For example, when the 4-bit mode setting signal MODp is (0011), the count value CN of the counter 23 becomes the count value detection circuit for SVGA (1). The pulse width setting signal Dn1 is output upon detecting that the detection count value N1 is set. The decoder 92 and the decoder 93 are similarly configured. Since each count value detection circuit in the decoder requires a register for storing the detection count value and a comparison circuit for comparing the count value CN with the detection count value, the area occupied by the decoder section including a plurality of decoders is required. Will be big.

FIG. 11C shows the LCD controller 82.
3 is an operation timing chart of FIG. The change of the horizontal synchronizing signal Hsync to the low level is detected in synchronization with the rising edge of the dot clock DCK, the load signal LS is generated, and the counter 23 starts counting. At the same time, the set / reset latch 25-1 is set and the driver control signal DC1 changes to high level.

When the count value CN of the counter 23 matches the SVGA (1) detection count value N1 selected by the mode setting signal MODp in the decoder 92, the pulse width setting signal Dn1 is generated. As a result, the set / reset latch 25-1 is reset, and the driver control signal DC1 changes to low level.

Similarly, the count value CN of the counter 23
Is the SVGA (1) detection count value N selected by the decoder 93 by the mode setting signal MODp.
When it matches 2, the pulse width setting signal Dn2 is generated, whereby the set / reset latch 25-2 is set and the driver control signal DC2 changes to the high level. Further, when the count value CN of the counter 23 matches the SVGA (1) detection count value N3 selected by the mode setting signal MODp in the decoder 94, the pulse width setting signal Dn3 is generated, and the pulse width setting signal Dn3 is set. The reset latch 25-2 is reset and the driver control signal DC2 changes to low level. In this way, the LCD controller 82 can generate and output the driver control signal corresponding to the LCD model.

By receiving serially the mode setting signal MODs sent from the system controller 81 and converting it into parallel data of M (M is a positive integer) bits by the LCD controller 82, 2 ^M kinds of mode setting can be performed. .

[0010]

However, as shown in FIG.
In order to support various LCD models as shown in (1), each decoder needs to have a large number of count value detection circuits, and the decoder becomes large in size and the occupied area increases. As the display modes such as QXGA (2048 x 1536) will continue to be made finer, the number of LCD models that should be supported should increase accordingly.
In the conventional LCD controller, the area of the decoder section becomes more and more remarkable. Further, since the decoder is preset according to the corresponding model, it is not possible to deal with a new model or the like that is not set in the decoder.

As a technique for supporting a variety of display modes with a single LCD controller, Japanese Patent Laid-Open No. 2001-2001
In Japanese Patent No. 92423, a dot clock DC from the outside
A technique of generating a driver control signal using an internal clock generated using an oscillator and an oscillation circuit instead of K is disclosed. However, this known technique requires an oscillator and an oscillation circuit as external parts of the LCD controller, which leads to an increase in cost.

In view of the above situation, an object of the present invention is to support LCD models of various display modes,
It is an object of the present invention to provide an LCD controller that does not increase the chip area even when the number of models to be supported increases and that can easily correspond to a newly commercialized LCD model.

[0013]

An LCD controller according to the present invention comprises a load signal generating circuit for detecting a level change of a predetermined signal and outputting a load signal in synchronization with a dot clock, and a dot signal in response to the load signal. A counter that starts counting the clock and frequency data that represents the frequency of the dot clock are input, and a plurality of detection count values are calculated based on the frequency data, and the count value of the counter matches each of the detection count values. A pulse width setting signal generator for outputting a corresponding pulse width setting signal, and a plurality of the pulse width setting signals that are input to respond to one of the pulse width setting signal signals from the first signal level to the second signal level. Changes to a signal level and changes from a second signal level to a first signal level in response to another one of the pulse width setting signals. Constructed and a driver control signal generator for outputting a driver control signal more generated and.

Alternatively, the LCD controller of the present invention is
A load signal generation circuit that detects a level change of a predetermined signal and outputs a load signal in synchronization with the dot clock, a counter that starts counting the dot clock in response to the load signal, and a frequency that represents the frequency of the dot clock. A detection count value that is input by inputting a plurality of different processed frequency data and calculates and outputs a plurality of detection count values by performing addition, subtraction, or both of the processed frequency data. A pulse width setting signal generation unit having setting means and count value comparing means for comparing the count value of the counter with each of the plurality of detection count values and outputting a corresponding pulse width setting signal when they match. A plurality of pulse width setting signals are input, and in response to one of the pulse width setting signal signals, a first
Driver for generating and outputting a plurality of driver control signals that change from the second signal level to the second signal level and that change from the second signal level to the first signal level in response to another one of the pulse width setting signals. And a control signal generator.

Alternatively, the LCD controller of the present invention is
When a dot clock is input and a dot clock selection bit is input and the dot clock selection bit has a predetermined value, a signal obtained by dividing the dot clock by m (a positive integer of m ≧ 2) is used as an internal dot clock, and when it is not the predetermined value. An internal dot clock generation circuit that outputs the dot clock as it is as an internal dot clock, a load signal generation circuit that detects a level change of a predetermined signal and outputs a load signal in synchronization with the internal dot clock, and a response to the load signal A counter for starting counting of the internal dot clock and frequency data representing the frequency of the dot clock or the frequency of 1 / m of the dot clock are input, and a plurality of detection count values are calculated based on the frequency data. The count value of the counter is the detected count value. And a pulse width setting signal generator that outputs a corresponding pulse width setting signal when a plurality of the pulse width setting signals are input and responds to one of the pulse width setting signal signals from the first signal level. A driver control signal generation unit that generates and outputs a plurality of driver control signals that change to a second signal level and that change from a second signal level to a first signal level in response to another one of the pulse width setting signals. And is configured.

Alternatively, the LCD controller of the present invention is
When a dot clock is input and a dot clock selection bit is input and the dot clock selection bit has a predetermined value, a signal obtained by dividing the dot clock by m (a positive integer of m ≧ 2) is used as an internal dot clock, and when it is not the predetermined value. An internal dot clock generation circuit that outputs the dot clock as it is as an internal dot clock, a load signal generation circuit that detects a level change of a predetermined signal and outputs a load signal in synchronization with the internal dot clock, and a response to the load signal Then, the counter for starting the counting of the internal dot clock and the frequency data representing the frequency of the dot clock or the frequency of 1 / m of the dot clock are input to generate a plurality of different processed frequency data, and the processed frequency is generated. Performs addition and / or subtraction processing between data And a detection count value setting means for calculating and outputting a plurality of detection count values, and a pulse width setting signal corresponding to the count value of the counter and each of the plurality of detection count values when they match each other. A pulse width setting signal generator having a count value comparing means for inputting the plurality of pulse width setting signals and responding to one of the pulse width setting signal signals from the first signal level to the second signal level. And a driver control signal generation unit that generates and outputs a plurality of driver control signals that change and change from the second signal level to the first signal level in response to another one of the pulse width setting signals. It

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION The LCD controller of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram of a first embodiment of the LCD controller of the present invention. The LCD controller 2 includes a serial / parallel conversion circuit 21, a counter load signal generation circuit 22, a counter 23, a pulse width setting signal generation unit 24, and a driver control signal generation including set / reset latches 25-1 to 25-k. And a section. The LCD controller of the present invention is characterized in that it has a pulse width setting signal generator 24 in place of the decoder in the conventional LCD controller of FIG.

The load signal generating circuit 22 of the counter is used for the horizontal synchronizing signal Hs transmitted from the system controller 1.
The change of sync to low level is captured in synchronization with the rising edge of the dot clock DCK, and the load signal LS is output. The counter 23 detects the load signal LS, starts counting the pulses of the dot clock DCK by the counter 23, updates the count value CN in synchronization with the dot clock DCK, and outputs it.

The serial-parallel conversion circuit 21 receives the frequency data signal FDs as serial data from the system controller 1 and outputs the parallel frequency data signal F.
Convert to Dp and output. As in the conventional example of FIG. 11, the system controller 1 to the LCD controller 2
The serial signal transmitted to the VAL is not only the frequency data part but also the horizontal and vertical effective display range of VAL.
A series of serial data may be added by adding data indicating the ID position, etc., but in the following description, these data are omitted for simplification.

The pulse width setting signal generator 24 inputs the frequency data FDp, bit-shifts the frequency data FDp, creates shift processed frequency data, and performs addition and subtraction of the shift processed frequency data to generate k (k is a positive integer). Detection count value N
1, N2, ... Nk are calculated, and each time a match between the count value CN of the counter 23 and the detected count value Ni (i is 1, 2, ..., K) is detected, the corresponding pulse width setting signal Dni (i
Outputs 1, 2, ... K).

Each of the j number of set / reset latches 25-1 to 25-j included in the driver control signal generation section inputs the load signal LS or one of the pulse width setting signals to the set input terminal to set the pulse width. The other one of the signals is input to the reset input terminal, and the driver control signal is output as a high level during the period from the fall of the signal input to the set terminal to the fall of the signal input to the reset terminal. In the embodiment of FIG. 1, the set / reset latch 25-1 is set by the load signal LS, reset by the pulse width setting signal Dn1 and outputs the driver control signal DC1. The set / reset latch 25-2 is configured to be set by the pulse width setting signal Dn2, reset by the pulse width setting signal Dn3, and output the driver control signal DC2.

In the frequency data generator 11 in the system control 1, the frequency data FD is the vertical synchronizing frequency fV shown in FIG. 10, the total number of samples H in the horizontal direction,
It is calculated by the following equation using the data of the total number of lines V.
Frequency data FD = fV × H × V × 10 ⁻⁶ That is, in the present embodiment, the frequency data FD is the dot clock DC.
It is a binary representation of K in MHz units. Therefore, when the dot clock DCK frequency up to 255 MHz is supported, the frequency data FD becomes 8 bits,
When the dot clock DCK frequency up to 511 MHz is supported, the frequency data FD is 9 bits.

FIG. 2 is a block diagram showing a pulse width setting signal generator in the first example of the first embodiment. In the first example of the first embodiment, the pulse width setting signal generator 24a includes a detection count value setting means 30 and a count value comparing means 31.

The detection count value setting means 30 inputs the frequency data FDp after being converted into parallel data, bit shifts the frequency data to create a plurality of shift processed frequency data, and executes a preset calculation procedure. The detection count values CKn1, CKn2, ... CKnk are calculated and output. The count value comparison means 31 includes k comparators 61-1, 61-2, ... 61-k in the same number as the detected count values CKn1, CKn2, ... CKnk, and the comparator 61-
Each i (i is 1, 2, ... K) compares the corresponding detection count value CKni (i is 1, 2, ... K) with the count value CN of the counter, and when they match, a pulse width setting signal Dni (i is 1, 2, ... K) is output.

By configuring the pulse width setting signal generator 24a in this way, the input frequency data FDp
It is possible to prevent the output time of the pulse width setting signal from changing even when the values are different. In the first embodiment, the detection count value setting means 30 is configured to include a shift data creation circuit 32 and a detection count value calculation circuit 33, and the calculation procedure for calculating the detection count value is hardware. .

The shift data generation circuit 32 inputs the frequency data FDp, frequency data FD (0) without shift (that is, the same numerical value as FDp), 1-bit left shift (that is, a value that is twice the numerical value of FDp) frequency. Data FD
(+1), 2-bit left shift (that is, a value of 4 times FDp) frequency data FD (+2), 3-bit left shift (that is, a value of 8 times FDp) frequency data FD
(+3) 1 bit right shift (ie 0.5 of FDp
Frequency data FD (−1) and the like (having a doubled numerical value) are generated by the bit shift processing and output.

The detection count value calculation circuit 33 inputs the plurality of shift processed frequency data output from the shift data generation circuit 32, and based on the driver control signal standard of the horizontal driver and the vertical driver connected to the LCD controller. Preset adder (or adder and subtractor)
Detection count values CKn1, CKn2, ... CKn are added and subtracted by the internal circuit including
Calculate and output k.

FIG. 3 is a circuit diagram showing an example of a concrete configuration of the pulse width setting signal generator of the first embodiment. In FIG. 3, the pulse width setting signal generating circuit 24 a is provided with the counter 23.
Outputs a pulse width setting signal Dn1 after 3 μs has elapsed from the start of counting, outputs a pulse width setting signal Dn2 after 5 μs has elapsed, and outputs a pulse width setting signal Dn after 7 μs has elapsed.
3 is output, the pulse width setting signal Dn4 is output when 1 μs has passed, the pulse width setting signal Dn5 is output when 1.5 μs has passed, and the pulse width setting signal Dn6 is output when 2 μs has passed.

The detection count value setting means 30a inputs the frequency data FDp, and the frequency data FD (0) without shift and the frequency data left-shifted by 1 bit by the bit shift circuit 41 in the shift data generation circuit 32a. 2 by FD (+1) and the bit shift circuit 42
Frequency data FD (+2) left-shifted by bits, frequency data FD (+3) left-shifted by 3 bits by the bit shift circuit 43, and frequency data FD (-1) right-shifted by 1 bit by the bit shift circuit 44.
Produces and. Further, the detection count value setting means 30a
In the detection count value calculation circuit 33a, the adder 51 calculates FD (0) + FD (+1) and outputs it as the detection count value CKn1, and the adder 52 outputs FD (0).
+ FD (+2) is calculated and output as the detection count value CKn2, and the subtracter 53 calculates FD (+3) -FD (0).
Is calculated and output as the detection count value CKn3, and FD
(0) is output as the detection count value CKn4, FD (0) + FD (-1) is calculated by the adder 54 and output as the detection count value CKn5, and FD (+1) is output as the detection count value CKn6.

In the count value comparing means 31a, the comparator 6
1-1 outputs the pulse width setting signal Dn1 when the count value CN of the counter 23 matches the detection count value CKn1, and the comparator 61-2 outputs the pulse width when the count value CN matches the detection count value CKn2. Setting signal Dn2
The comparator 61-3 outputs the pulse width setting signal Dn when the count value CN matches the detected count value CKn3.
3, the comparator 61-4 outputs the pulse width setting signal D when the count value CN matches the detection count value CKn4.
n4 is output, the comparator 61-5 outputs the pulse width setting signal Dn5 when the count value CN matches the detected count value CKn5, and the comparator 61-6 has the count value CN matched with the detected count value CKn6. At this time, the pulse width setting signal Dn6 is output.

FIG. 4 shows the pulse width setting signal generator 2 of FIG.
4A is a diagram for explaining the operation of FIG. 4A, FIG. 4A shows the relationship between the pulse width setting signal and the count value when the frequency of the dot clock DCK is 108 MHz, and FIG. 4B shows the frequency of the dot clock DCK. FIG. 4C shows the relationship between the pulse width setting signal and the count value in the case of 50 MHz.
It is an operation timing chart.

The operation of the pulse width setting signal generator will be described in detail with reference to FIGS. 1 and 3. In the case of supporting the SXGA-compatible (1) LCD described in FIG. 10, the frequency of the dot clock DCK supplied from the system controller 1 to the LCD controller 2 is 108 MHz. The frequency data FD is calculated by the frequency data generator 11 as FD = fV × H × V × 10 ⁻⁶ . For SXGA compatible (1), fV = 60, H = 180
Since 0 and V = 1000, FD = 108. Serial data (0110) in binary notation of frequency data FD
1100) is transmitted to the LCD controller 2 as frequency data FDs, and the frequency information of the dot clock DCK is transmitted to the LCD controller. In the case of the dot clock 108 MHz, the period of the dot clock DCK is 9.259 ns, so the frequency data FDs (10
FD with 108) as a base number without bit shift
When counting (0) dot clocks, 1 μs (= 10
00 ns) has passed. Similarly, counting FD (+1) (binary (11011000), decimal 216) dot clocks obtained by shifting the frequency data FDs to the left by 1 bit indicates that 2 μs has elapsed. Therefore, the number calculated by FD (0) + FD (+1) (binary number (101000100), decimal number 32)
When the dot clock of 4) is counted, 3 μs has elapsed. That is, in the case of SXGA compatible (1) in which the frequency of the dot clock DCK is 108 MHz, C in FIG.
Kn1 is a binary number (101000100) and is a decimal number of 324.
It is possible to detect that 3 μs has elapsed from the start of counting by the counter 23 by detecting the coincidence between the count number CN and CKn1.

Next, in the case of supporting the SVGA compatible (3) LCD, the frequency of the dot clock DCK is 50M.
The frequency data FD is fV = 72.18.
Since 8, H = 1040 and V = 666, the frequency data generator 11 calculates FD = 50. In this case, serial data (00110010) is transmitted as frequency data FDs to the LCD controller 2 as a binary representation of the frequency data FD, and the frequency information of the dot clock DCK is transmitted to the LCD controller. When the dot clock is 50 MHz, the dot clock DCK has a period of 20 ns, so the frequency data F
When the number of FD (0) dot clocks in which Ds (decimal number 50) is directly used without bit shift is counted, in this case as well, as in the case of the dot clock 108 MHz,
It means that 1 μs has elapsed. Similarly, frequency data FD
FD (+1) obtained by shifting s by 1 bit to the left ((0 in binary)
When 1100100) and 100) decimal dot clocks are counted, it means that 2 μs has elapsed, as in the case of the dot clock of 108 MHz. Therefore, F
Even when the number of dot clocks calculated by D (0) + FD (+1) (binary number (10010110), decimal number 150) is counted, the dot clock 108MH
As with z, 3 μs has elapsed. That is, an SV whose dot clock DCK frequency is 50 MHz
In the GA compatible (3), CKn1 in FIG. 3 is binary (10010110) and decimal 150.
The count number CN of the counter 23 in the comparator 61-1
By detecting the coincidence between CKn1 and CKn1, it is possible to detect that 3 μs has elapsed from the start of counting by the counter 23, as in the case of the dot clock of 108 MHz.

The operation timing chart of FIG. 4C is for a dot clock of 50 MHz. Horizontal sync signal Hsy
The change of nc to the low level is detected in synchronization with the rising edge of the dot clock DCK, the load signal LS is generated, and the counter 23 starts counting. At the same time, the set / reset latch 25-1 is set and the driver control signal DC
1 changes to high level.

3 when the count value CN of the counter 23 matches the detected count value CK1 (150 in decimal).
A pulse width setting signal Dn1 indicating the passage of μs is generated. As a result, the set / reset latch 25-1 is reset, and the driver control signal DC1 changes to low level.

Similarly, when the count value CN of the counter 23 matches the detection count value CK2 (decimal number 250), a pulse width setting signal Dn2 indicating the passage of 5 μs is generated, whereby the set / reset latch 25-2 is activated. The driver control signal DC2 is set to high level. When the count value CN of the counter 23 matches the detection count value CK3 (350 in decimal), 7 μ
A pulse width setting signal Dn3 indicating the progress of s is generated, whereby the set / reset latch 25-2 is reset, and the driver control signal DC2 changes to low level. When the frequency of the dot clock DCK is different and the dot clock is 108 MHz, the detection count value CK in FIG.
1 is changed from 150 to 324 (both are decimal numbers),
The detection count value CK2 is 250 to 540 (= 108 ×
5), and the detection count value CK1 changes from 350 to 75
6 (= 108 × 7), but otherwise the same.

As described above, the LCD controller 2 of the present invention appropriately configures the internal circuits of the shift data creation circuit 32 and the detection count value calculation circuit 33,
It is possible to generate a plurality of driver control signals set to arbitrary signal start times and arbitrary signal time widths. Further, since the signal start time and the signal time width of the set driver control signal do not change even if the frequency of the dot clock changes, it is possible to change various dot clock frequencies without changing or adding the components of the LCD controller. Since it is possible to correspond to the LCD model, the more kinds of the corresponding LCD model, the more the occupied area becomes superior to the conventional example. Figure 5 (a) shows
FIG. 12 is a comparison of the occupied area of the pulse setting signal section in the first example of the first embodiment of the present invention and the occupied area of the decoder section in the conventional example of FIG. 11 with the number of occupied grids independent of the design rule. FIG. 5B is a graph, and in the conventional example, the number of occupied grids in the decoder section increases almost in proportion to the number of display modes, whereas in the pulse width setting signal generation section of the present invention, Since the number of occupied grids is constant regardless of the number of display modes, the number of display modes or the corresponding LC
The advantage of the present invention becomes more remarkable as the number of types of D models increases.

FIG. 6 is a block diagram of a pulse width setting signal generator in the LCD controller of the second example of the first embodiment of the present invention. In the LCD controller of the second embodiment, the pulse width setting signal generator 2 of the first embodiment is used.
4a is the same as that of the first embodiment except that the pulse width setting signal generating section 24b is changed to 4a.

The pulse width setting signal generating section 24b is provided with the parallel frequency data FDp and the count value C of the counter 23.
Input N and pulse width setting signals Dn1, Dn2, Dn
Outputs 3, Dn4, Dn5, Dn6. The pulse width setting signal generation unit 24b includes a detection count value setting unit 30b.
And a count value comparison means 31a. In the detection count value setting means 30b, the shift data creation procedure and the detection count value calculation procedure are stored as software in the memory 77, the arithmetic circuit (ALU) 73 is controlled to create the shift processed frequency data, and the detection count value is detected. Calculate the value. The count value comparison means 31a is the same as the count value comparison means 31 of the first embodiment.

The parallel frequency data FDp is stored in the frequency data register 71, and the frequency data FDp is read from the frequency data register 71 under the control of the control circuit 78 in accordance with the shift data creation procedure stored in the memory 77. The arithmetic circuit 73 executes a bit shift process and stores it in the shift data storage register 75. After execution of the shift data creation procedure is completed, the memory 7
According to the detection count value calculation procedure stored in 7,
Under the control of the control circuit 78, the shift processed frequency data is read from the shift data storage register 75, added or subtracted by the arithmetic circuit 73, the detection count value is calculated and stored in the detection count value storage register 76. These operations are executed when the LCD controller is started up.
The detection count value storage register 76 stores the detection count value C
Kn1, CKn2, CKn3, CKn4, CKn5, C
Kn6 is stored when the LCD controller 2 is started up. That is, the shift data creation procedure, the arithmetic circuit 73, and the shift data storage register 75 replace the shift data creation circuit 32a in FIG. 3, and the detection count value calculation procedure, the arithmetic circuit 73, and the detection count value storage register 76 detect counts. It replaces the value calculation circuit 33a. Subsequent operations are similar to those of the pulse width setting signal generator 24a in FIG.

In the second embodiment including the pulse width setting signal generator 24b of FIG. 6, the larger the type of the corresponding LCD model, the more the occupied area becomes superior to the conventional example.
In addition to the effect similar to that of the embodiment, by changing the shift data creation procedure and the detection count value calculation procedure stored in the memory 77, it is possible to cope with drivers having different driver control signals. The effect occurs. The memory 77 for storing the shift data creation procedure and the detection count value calculation procedure is preferably configured by a mask ROM or EPROM so as to retain the shift data creation procedure and the detection count value calculation procedure even when the power is cut off.

In the above, the frequency data FD is MH.
Although it is described as the z unit, the frequency data may be in the 10 MHz unit or the 100 MHz unit. In this case, the frequency data generator 1 in the system controller 1
1, the frequency data FD in 10 MHz units is FD = fV × H × V × 10 ⁻⁵ , and the frequency data FD in 100 MHz units is calculated as FD = fV × H × V × 10 ⁻⁴ . The pulse width setting signal is generated by adding / subtracting the shift-processed frequency data based on 1 μs in the unit of 1 MHz.
In the case of the MHz unit, 100 ns is basically used, so that the setting becomes easy when the change of the driver control signal changes at a time that is a multiple of 100 ns. Similarly, when the frequency data FD is in the unit of 100 MHz, 10 ns is basically used, so that the setting becomes easy when the change in the driver control signal changes at a time that is a multiple of 10 ns.

Next, a second embodiment of the present invention will be described. FIG. 7 is a block diagram of the second embodiment of the present invention. The LCD controller 2a of FIG. 7 is different from the LCD controller 2 of the first embodiment of FIG. 1 in that the LCD controller 2a inputs the dot clock DCK and the dot clock selection bit SDCK, and the dot clock selection bit SDCK is, for example, 1. Dot clock m when
Having an internal dot clock generation circuit 26 that divides and outputs as an internal dot clock, and outputs the dot clock as an internal dot clock as it is when the dot clock selection bit SDCK is 0, and an internal dot clock instead of a dot clock. Is a load signal generation circuit 22, a counter 23 and a set / reset latch 25-
1 to 25-j. The other configuration of the LCD controller 2a is the same as that of the LCD controller 2 of FIG.

When the frequency of the dot clock DCK is high, the LCD controller 2a causes the dot clock DCK to
In some cases, it may not be possible to operate at high speed following the above. In the second embodiment, when the frequency of the dot clock DCK is high, the frequency data generator 1 of the system controller 1a
The frequency of 1 / m of the dot clock is selected by the selector 12 from the first frequency data representing the frequency of the dot clock created in 1a and the second frequency data representing the frequency of 1 / m of the dot clock. Select the frequency data to represent and select serial frequency data FDs
To the LCD controller 2a. At this time,
When the frequency data represents the frequency of 1 / m of the dot clock, the dot clock selection bit SDCK is set to 1. When the frequency data represents the frequency of the dot clock itself, the dot clock selection bit SDCK is set to 0, and the dot clock is added to the frequency data FDs. Select bit SDCK is added and transmitted.

In the LCD controller 2a, if the dot clock selection bit SDCK is 1, the dot clock is divided by m in the internal dot clock generation circuit 26 and output as the internal dot clock to output the load signal generation circuit 2
2, counter 23 and set / reset latch 25-1
~ 25-j. Dot clock selection bit SD
If CK is 0, the internal dot clock generation circuit 26 outputs the dot clock as it is as an internal dot clock and supplies it to the load signal generation circuit 22, the counter 23, and the set / reset latches 25-1 to 25-j.

In the second embodiment, in addition to the effect similar to that of the first embodiment in that the occupied area becomes superior to the conventional example as the number of types of corresponding LCD models increases, also in the case where the dot clock has a high frequency. There is a new effect that the LCD controller can follow the operation. In the second embodiment, as in the first embodiment, the pulse width generation unit 24 may be either the first embodiment shown in FIG. 2 or the second embodiment shown in FIG.

In FIGS. 1 and 7, the horizontal synchronizing signal Hsyn is used.
Although the LCD controller is configured to input c to the load signal generation circuit, the horizontal synchronization signal Hsync
Alternatively, the data enable signal DE indicating the period during which the image data transmitted to the driver is valid may be input to the load signal generation circuit. FIG. 8 is a block diagram of an LCD controller using the data enable signal DE. Instead of changing the horizontal synchronizing signal Hsync to the low level in the timing chart of FIG. 4C, the VALID end timing of the data enable signal DE (for example, if the image data is valid when DE is high level, DE Change to a low level), except that the counter load signal is generated, the same operation as in FIG.

The detection count value setting means 30, 30
In a and 30b, various combinations are allowed for the selection of the shift processed frequency data and the selection of addition and subtraction.
For example, to calculate the detection count value CKn3 in FIG. 3, FD (+3) −FD (0) as shown in FIG. 9A.
Alternatively, as shown in FIG. 9 (b), FD (0) + F
It may be D (+1) + FD (+2), and as shown in FIG. 9C, {FD (0) + FD (1)} × 2 + FD
It may be (0), and there are many other than these, but it goes without saying that the calculation by any of these is within the scope of the present invention.

[0049]

As described above, the LCD of the present invention.
The controller calculates the number of dot clocks required for the pulse width specified for driver control based on the frequency data transmitted from the system controller, and uses it as the detection count value to detect a match with the dot clock count number. Since the driver control signal is generated by the method, compared to the conventional driver control signal generation by the mode setting, it can support LCD models of various display modes, and the chip area does not increase even when the models to be supported increase. Moreover, it is possible to provide an LCD controller that can easily cope with a newly commercialized LCD model. As a result, the development cost can be reduced, and the manufacturing cost of the LCD controller chip can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a block diagram of a pulse width setting signal generator of the first embodiment.

FIG. 3 is a circuit diagram of a specific example of a pulse width setting signal generator of the first embodiment.

FIG. 4 is a diagram illustrating an operation of a pulse width setting signal generation unit according to the first embodiment.

FIG. 5 is a diagram showing a result of comparison of an occupied area of a pulse width setting signal generation unit of the first embodiment with a conventional example.

FIG. 6 is a block diagram of a pulse width setting signal generator of the second embodiment.

FIG. 7 is a block diagram of a second embodiment of the present invention.

FIG. 8 is a block diagram of an LCD controller using a data enable signal.

FIG. 9 is a diagram showing an example of different calculation formulas for calculating the same detection count value.

FIG. 10 is a list of LCD models.

FIG. 11 is a diagram showing a configuration and operation of a conventional LCD controller.

[Explanation of symbols]

1,1a System controller 2,2a LCD controller 11, 11a Frequency data generator 21 Serial-parallel conversion circuit 22 Load signal generation circuit 23 counter 24, 24a, 24b Pulse width setting signal generator 25 set reset latch 26 Internal dot clock generation circuit 30, 30a, 30b Detection count value setting means 31, 31a Count value comparison means 32, 32a shift data generation circuit 33, 33a Detection count value calculation circuit DCK dot clock DE data enable signal DC1, DC2 driver control signal FDs, FDp frequency data Hsync horizontal sync signal

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 2H093 NA06 NC41 ND50 ND60 NF03                 5C006 AF51 AF52 AF53 AF61 AF71                       BB11 BC16 BF04 BF14 BF16                       BF22 BF24 BF26 BF28 FA08                 5C058 AA06 BA01 BA35 BB06 BB11                 5C080 AA10 BB05 DD21 DD27 DD28                       JJ02 JJ04 JJ05

Claims (12)

[Claims] 1. A load signal generation circuit that detects a level change of a predetermined signal and outputs a load signal in synchronization with a dot clock; a counter that starts counting dot clocks in response to the load signal; Inputting frequency data representing the frequency of the above, calculating a plurality of detection count values based on the frequency data, and outputting a corresponding pulse width setting signal when the count value of the counter matches each of the detection count values. A pulse width setting signal generator, which receives a plurality of the pulse width setting signals and responds to one of the pulse width setting signal signals from the first signal level to the second signal level.
And a driver control signal generation unit that generates and outputs a plurality of driver control signals that change from the second signal level to the first signal level in response to another one of the pulse width setting signals. LCD comprising
controller. 2. A load signal generation circuit that detects a level change of a predetermined signal and outputs a load signal in synchronization with a dot clock; a counter that starts counting dot clocks in response to the load signal; and a dot clock. Frequency detection data is input, bit shift processing is performed to create a plurality of different processed frequency data, and a plurality of detection counts are obtained by performing addition or subtraction processing or both processing between the processed frequency data. A detection count value setting means for calculating and outputting a value, and a count value comparing means for comparing the count value of the counter with each of the plurality of detection count values and outputting a corresponding pulse width setting signal when they match. And a pulse width setting signal generator that receives a plurality of the pulse width setting signals. In response to the first signal level from the second
And a driver control signal generation unit that generates and outputs a plurality of driver control signals that change from the second signal level to the first signal level in response to another one of the pulse width setting signals. LCD comprising
controller. 3. The detection count value setting means has a plurality of bit shift circuits, inputs frequency data, performs preset bit shift processing, and creates and outputs a plurality of processed frequency data different from each other. A shift data generation circuit for performing the above operation, and one or both of an adder and a subtractor are input, and the plurality of processed frequency data are input to perform one or both of the preset addition and subtraction processes to perform a plurality of detections. The LCD controller according to claim 2, further comprising a detection count value calculation circuit that calculates and outputs a count value. 4. The detection count value setting means includes a procedure of bit-shifting frequency data to generate a plurality of different processed frequency data, and one or both of addition and subtraction between the plurality of processed frequency data. Memory for storing a procedure for performing a process of calculating a plurality of detection count values, an arithmetic circuit having a bit shift function and an addition / subtraction function, a procedure for creating the processed frequency data, and calculating a detection count value. 3. The LCD controller according to claim 2, further comprising: a control circuit that controls the arithmetic circuit according to a procedure, and that inputs the frequency data and outputs the detection count value. 5. The LCD controller according to claim 2, 3 or 4, wherein the predetermined signal is a horizontal synchronizing signal. 6. The LCD controller according to claim 2, 3 or 4, wherein the predetermined signal is a data enable signal. 7. A dot clock input and a dot clock selection bit are input, and when the dot clock selection bit has a predetermined value, a signal obtained by dividing the dot clock by m (a positive integer of m ≧ 2) is used as an internal dot clock. An internal dot clock generation circuit that outputs the dot clock as an internal dot clock when it is not a predetermined value, and a load signal generation circuit that detects a level change of a predetermined signal and outputs a load signal in synchronization with the internal dot clock. A counter that starts counting the internal dot clock in response to the load signal, and frequency data that represents the frequency of the dot clock or the frequency of 1 / m of the dot clock, and a plurality of detection counts based on the frequency data. The value of the counter is calculated while the value is calculated. A pulse width setting signal generator that outputs a pulse width setting signal corresponding to each of the pulse width setting values, and a plurality of the pulse width setting signals that are input in response to one of the pulse width setting signal signals. Second from the signal level of
And a driver control signal generation unit that generates and outputs a plurality of driver control signals that change from the second signal level to the first signal level in response to another one of the pulse width setting signals. LCD comprising
controller. 8. A signal obtained by dividing the dot clock by m (a positive integer of m ≧ 2) when the dot clock is input and the dot clock selection bit is input and the dot clock selection bit has a predetermined value is defined as the internal dot clock. An internal dot clock generation circuit that outputs the dot clock as an internal dot clock when it is not a predetermined value, and a load signal generation circuit that detects a level change of a predetermined signal and outputs a load signal in synchronization with the internal dot clock. A counter that starts counting the internal dot clocks in response to the load signal, and bit shifts that represent the frequency of the dot clocks or the frequency of 1 / m of the dot clocks, and the frequency data is input to perform a plurality of different processings. Create frequency data and add or subtract between the processed frequency data When a detection count value setting means for calculating and outputting a plurality of detection count values by performing one or both of the processes and the count value of the counter and each of the plurality of detection count values are compared and coincident with each other, A pulse width setting signal generator having count value comparing means for outputting a corresponding pulse width setting signal, and a first signal in response to one of the pulse width setting signal signals inputted with a plurality of the pulse width setting signals Second from level
And a driver control signal generation unit that generates and outputs a plurality of driver control signals that change from the second signal level to the first signal level in response to another one of the pulse width setting signals. LCD comprising
controller. 9. The detection count value setting means has a plurality of bit shift circuits, inputs frequency data, performs preset bit shift processing, and creates and outputs a plurality of different processed frequency data. A shift data generation circuit for performing the above operation, and one or both of an adder and a subtractor are input, and the plurality of processed frequency data are input to perform one or both of the preset addition and subtraction processes to perform a plurality of detections. 9. The LCD controller according to claim 8, further comprising a detection count value calculation circuit that calculates and outputs a count value. 10. The detection count value setting means includes a step of bit-shifting frequency data to create a plurality of different processed frequency data, and one or both of addition and subtraction between the plurality of processed frequency data. Memory for storing a procedure for performing a process of calculating a plurality of detection count values, an arithmetic circuit having a bit shift function and an addition / subtraction function, a procedure for creating the processed frequency data, and calculating a detection count value. 9. The LCD controller according to claim 8, further comprising: a control circuit that controls the arithmetic circuit according to the procedure, wherein the frequency data is input and the detection count value is output. 11. The LCD controller according to claim 8, 9 or 10, wherein the predetermined signal is a horizontal synchronizing signal. 12. The LCD controller according to claim 8, 9 or 10, wherein the predetermined signal is a data enable signal.